2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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26 * THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __NLM_MIPS_EXTNS_H__
33 #define __NLM_MIPS_EXTNS_H__
35 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
36 static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val)
40 __asm__ __volatile__ (
45 ".word 0x71280014\n" /* "swapw $8, $9\n" */
48 : "+m" (*loc), "=r" (oldval)
49 : "r" (loc), "r" (val)
55 static __inline__ uint32_t nlm_swapwu(int32_t *loc, uint32_t val)
59 __asm__ __volatile__ (
64 ".word 0x71280015\n" /* "swapwu $8, $9\n" */
67 : "+m" (*loc), "=r" (oldval)
68 : "r" (loc), "r" (val)
75 static __inline__ uint64_t nlm_swapd(int32_t *loc, uint64_t val)
79 __asm__ __volatile__ (
84 ".word 0x71280014\n" /* "swapw $8, $9\n" */
87 : "+m" (*loc), "=r" (oldval)
88 : "r" (loc), "r" (val)
96 * Atomic increment a unsigned int
98 static __inline unsigned int
99 nlm_ldaddwu(unsigned int value, unsigned int *addr)
101 __asm__ __volatile__(
106 ".word 0x71280011\n" /* ldaddwu $8, $9 */
109 : "=&r"(value), "+m"(*addr)
110 : "0"(value), "r" ((unsigned long)addr)
116 * 32 bit read write for c0
118 #define read_c0_register32(reg, sel) \
121 __asm__ __volatile__( \
124 "mfc0 %0, $%1, %2\n\t" \
126 : "=r" (__rv) : "i" (reg), "i" (sel) ); \
130 #define write_c0_register32(reg, sel, value) \
131 __asm__ __volatile__( \
134 "mtc0 %0, $%1, %2\n\t" \
136 : : "r" (value), "i" (reg), "i" (sel) );
138 #if defined(__mips_n64) || defined(__mips_n32)
140 * On 64 bit compilation, the operations are simple
142 #define read_c0_register64(reg, sel) \
145 __asm__ __volatile__( \
148 "dmfc0 %0, $%1, %2\n\t" \
150 : "=r" (__rv) : "i" (reg), "i" (sel) ); \
154 #define write_c0_register64(reg, sel, value) \
155 __asm__ __volatile__( \
158 "dmtc0 %0, $%1, %2\n\t" \
160 : : "r" (value), "i" (reg), "i" (sel) );
161 #else /* ! (defined(__mips_n64) || defined(__mips_n32)) */
164 * 32 bit compilation, 64 bit values has to split
166 #define read_c0_register64(reg, sel) \
168 uint32_t __high, __low; \
169 __asm__ __volatile__( \
171 ".set noreorder\n\t" \
173 "dmfc0 $8, $%2, %3\n\t" \
174 "dsra32 %0, $8, 0\n\t" \
175 "sll %1, $8, 0\n\t" \
177 : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
179 ((uint64_t)__high << 32) | __low; \
182 #define write_c0_register64(reg, sel, value) \
184 uint32_t __high = value >> 32; \
185 uint32_t __low = value & 0xffffffff; \
186 __asm__ __volatile__( \
188 ".set noreorder\n\t" \
190 "dsll32 $8, %1, 0\n\t" \
191 "dsll32 $9, %0, 0\n\t" \
192 "dsrl32 $8, $8, 0\n\t" \
193 "or $8, $8, $9\n\t" \
194 "dmtc0 $8, $%2, %3\n\t" \
196 :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
201 /* functions to write to and read from the extended
203 * EIRR : Extended Interrupt Request Register
204 * cp0 register 9 sel 6
205 * bits 0...7 are same as cause register 8...15
206 * EIMR : Extended Interrupt Mask Register
207 * cp0 register 9 sel 7
208 * bits 0...7 are same as status register 8...15
210 static __inline uint64_t
211 nlm_read_c0_eirr(void)
214 return (read_c0_register64(9, 6));
218 nlm_write_c0_eirr(uint64_t val)
221 write_c0_register64(9, 6, val);
224 static __inline uint64_t
225 nlm_read_c0_eimr(void)
228 return (read_c0_register64(9, 7));
232 nlm_write_c0_eimr(uint64_t val)
235 write_c0_register64(9, 7, val);
238 static __inline__ uint32_t
239 nlm_read_c0_ebase(void)
242 return (read_c0_register32(15, 1));
245 static __inline__ int
248 return (nlm_read_c0_ebase() >> 5) & 0x3;
251 static __inline__ int
254 return nlm_read_c0_ebase() & 0x1f;
257 static __inline__ int
260 return nlm_read_c0_ebase() & 0x3;
263 static __inline__ int
266 return (nlm_read_c0_ebase() >> 2) & 0x7;
270 #define XLP_MAX_NODES 4
271 #define XLP_MAX_CORES 8
272 #define XLP_MAX_THREADS 4