2 * Copyright 2006-2007 by Juniper Networks.
3 * Copyright 2008 Semihalf.
4 * Copyright 2010 The FreeBSD Foundation
7 * Portions of this software were developed by Semihalf
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/sockio.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
51 #include <sys/mutex.h>
53 #include <sys/endian.h>
58 #include <dev/fdt/fdt_common.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcib_private.h>
65 #include "ofw_bus_if.h"
68 #include <machine/resource.h>
69 #include <machine/bus.h>
70 #include <machine/intr_machdep.h>
72 #include <powerpc/mpc85xx/mpc85xx.h>
74 #define REG_CFG_ADDR 0x0000
75 #define CONFIG_ACCESS_ENABLE 0x80000000
77 #define REG_CFG_DATA 0x0004
78 #define REG_INT_ACK 0x0008
80 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
81 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
82 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
83 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
85 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
86 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
87 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
88 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
90 #define REG_PEX_MES_DR 0x0020
91 #define REG_PEX_MES_IER 0x0028
92 #define REG_PEX_ERR_DR 0x0e00
93 #define REG_PEX_ERR_EN 0x0e08
95 #define PCIR_LTSSM 0x404
96 #define LTSSM_STAT_L0 0x16
98 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
100 struct fsl_pcib_softc {
103 struct rman sc_iomem;
104 bus_addr_t sc_iomem_va; /* Virtual mapping. */
105 bus_addr_t sc_iomem_size;
106 bus_addr_t sc_iomem_alloc; /* Next allocation. */
108 struct rman sc_ioport;
109 bus_addr_t sc_ioport_va; /* Virtual mapping. */
110 bus_addr_t sc_ioport_size;
111 bus_addr_t sc_ioport_alloc; /* Next allocation. */
112 int sc_ioport_target;
114 struct resource *sc_res;
115 bus_space_handle_t sc_bsh;
116 bus_space_tag_t sc_bst;
121 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
123 /* Devices that need special attention. */
125 int sc_devfn_via_ide;
127 struct fdt_pci_intr sc_intr_info;
130 /* Local forward declerations. */
131 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
133 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
134 u_int, uint32_t, int);
135 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
136 static void fsl_pcib_err_init(device_t);
137 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long,
139 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
140 static int fsl_pcib_intr_info(phandle_t, struct fsl_pcib_softc *);
141 static int fsl_pcib_set_range(struct fsl_pcib_softc *, int, int, u_long,
143 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long,
146 /* Forward declerations. */
147 static int fsl_pcib_attach(device_t);
148 static int fsl_pcib_detach(device_t);
149 static int fsl_pcib_probe(device_t);
151 static struct resource *fsl_pcib_alloc_resource(device_t, device_t, int, int *,
152 u_long, u_long, u_long, u_int);
153 static int fsl_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
154 static int fsl_pcib_release_resource(device_t, device_t, int, int,
156 static int fsl_pcib_write_ivar(device_t, device_t, int, uintptr_t);
158 static int fsl_pcib_maxslots(device_t);
159 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
160 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
163 /* Configuration r/w mutex. */
164 struct mtx pcicfg_mtx;
165 static int mtx_initialized = 0;
168 * Bus interface definitions.
170 static device_method_t fsl_pcib_methods[] = {
171 /* Device interface */
172 DEVMETHOD(device_probe, fsl_pcib_probe),
173 DEVMETHOD(device_attach, fsl_pcib_attach),
174 DEVMETHOD(device_detach, fsl_pcib_detach),
177 DEVMETHOD(bus_read_ivar, fsl_pcib_read_ivar),
178 DEVMETHOD(bus_write_ivar, fsl_pcib_write_ivar),
179 DEVMETHOD(bus_alloc_resource, fsl_pcib_alloc_resource),
180 DEVMETHOD(bus_release_resource, fsl_pcib_release_resource),
181 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
182 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
183 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
184 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
187 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
188 DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
189 DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
190 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
192 /* OFW bus interface */
193 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
194 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
195 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
196 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
197 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
202 static driver_t fsl_pcib_driver = {
205 sizeof(struct fsl_pcib_softc),
208 devclass_t pcib_devclass;
210 DRIVER_MODULE(pcib, fdtbus, fsl_pcib_driver, pcib_devclass, 0, 0);
213 fsl_pcib_probe(device_t dev)
217 node = ofw_bus_get_node(dev);
218 if (!fdt_is_type(node, "pci"))
221 if (!(fdt_is_compatible(node, "fsl,mpc8540-pci") ||
222 fdt_is_compatible(node, "fsl,mpc8548-pcie")))
225 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
226 return (BUS_PROBE_DEFAULT);
230 fsl_pcib_attach(device_t dev)
232 struct fsl_pcib_softc *sc;
236 uint8_t ltssm, capptr;
238 sc = device_get_softc(dev);
242 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
244 if (sc->sc_res == NULL) {
245 device_printf(dev, "could not map I/O memory\n");
248 sc->sc_bst = rman_get_bustag(sc->sc_res);
249 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
252 if (!mtx_initialized) {
253 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
257 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
258 if (cfgreg != 0x1057 && cfgreg != 0x1957)
261 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
262 while (capptr != 0) {
263 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
264 switch (cfgreg & 0xff) {
269 sc->sc_pcie_capreg = capptr;
272 capptr = (cfgreg >> 8) & 0xff;
275 node = ofw_bus_get_node(dev);
277 * Get PCI interrupt info.
279 if (fsl_pcib_intr_info(node, sc) != 0) {
280 device_printf(dev, "could not retrieve interrupt info\n");
285 * Configure decode windows for PCI(E) access.
287 if (fsl_pcib_decode_win(node, sc) != 0)
290 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
291 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
293 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
295 sc->sc_devfn_tundra = -1;
296 sc->sc_devfn_via_ide = -1;
300 * Scan bus using firmware configured, 0 based bus numbering.
303 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
304 fsl_pcib_init(sc, sc->sc_busnr, maxslot);
307 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
308 if (ltssm < LTSSM_STAT_L0) {
310 printf("PCI %d: no PCIE link, skipping\n",
311 device_get_unit(dev));
316 fsl_pcib_err_init(dev);
318 device_add_child(dev, "pci", -1);
319 return (bus_generic_attach(dev));
322 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
327 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
328 u_int reg, int bytes)
332 if (bus == sc->sc_busnr - 1)
335 addr = CONFIG_ACCESS_ENABLE;
336 addr |= (bus & 0xff) << 16;
337 addr |= (slot & 0x1f) << 11;
338 addr |= (func & 0x7) << 8;
341 addr |= (reg & 0xf00) << 16;
343 mtx_lock_spin(&pcicfg_mtx);
344 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
348 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
349 REG_CFG_DATA + (reg & 3));
352 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
353 REG_CFG_DATA + (reg & 2)));
356 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
363 mtx_unlock_spin(&pcicfg_mtx);
368 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
369 u_int reg, uint32_t data, int bytes)
373 if (bus == sc->sc_busnr - 1)
376 addr = CONFIG_ACCESS_ENABLE;
377 addr |= (bus & 0xff) << 16;
378 addr |= (slot & 0x1f) << 11;
379 addr |= (func & 0x7) << 8;
382 addr |= (reg & 0xf00) << 16;
384 mtx_lock_spin(&pcicfg_mtx);
385 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
389 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
390 REG_CFG_DATA + (reg & 3), data);
393 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
394 REG_CFG_DATA + (reg & 2), htole16(data));
397 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
398 REG_CFG_DATA, htole32(data));
401 mtx_unlock_spin(&pcicfg_mtx);
406 dump(struct fsl_pcib_softc *sc)
410 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
411 for (i = 0; i < 5; i++) {
412 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
413 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
414 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
415 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
418 for (i = 1; i < 4; i++) {
419 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
420 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
421 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
422 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
427 for (i = 0; i < 0x48; i += 4) {
428 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
435 fsl_pcib_maxslots(device_t dev)
437 struct fsl_pcib_softc *sc = device_get_softc(dev);
439 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
443 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
444 u_int reg, int bytes)
446 struct fsl_pcib_softc *sc = device_get_softc(dev);
449 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
451 devfn = DEVFN(bus, slot, func);
452 if (devfn == sc->sc_devfn_tundra)
454 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
456 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
460 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
461 u_int reg, uint32_t val, int bytes)
463 struct fsl_pcib_softc *sc = device_get_softc(dev);
465 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
467 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
471 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus,
475 if (device == 0x0686) {
476 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
477 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
478 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
479 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
480 } else if (device == 0x0571) {
481 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
482 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
487 fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func,
491 uint32_t addr, mask, size;
494 reg = PCIR_BAR(barno);
496 if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
498 case 0: addr = 0x1f0; break;
499 case 1: addr = 0x3f4; break;
500 case 2: addr = 0x170; break;
501 case 3: addr = 0x374; break;
502 case 4: addr = 0xcc0; break;
505 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
509 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
510 size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
513 width = ((size & 7) == 4) ? 2 : 1;
515 if (size & 1) { /* I/O port */
516 allocp = &sc->sc_ioport_alloc;
518 if ((size & 0xffff0000) == 0)
520 } else { /* memory */
521 allocp = &sc->sc_iomem_alloc;
526 /* Sanity check (must be a power of 2). */
530 addr = (*allocp + mask) & ~mask;
531 *allocp = addr + size;
534 printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n",
535 device_get_unit(sc->sc_dev), bus, slot, func, reg,
538 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
540 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
546 fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
550 u_int devfn, intline;
552 unit = device_get_unit(sc->sc_dev);
554 devfn = DEVFN(bus, slot, func);
555 if (devfn == sc->sc_devfn_via_ide)
556 intline = MAP_IRQ(0, 14);
557 else if (devfn == sc->sc_devfn_via_ide + 1)
558 intline = MAP_IRQ(0, 10);
559 else if (devfn == sc->sc_devfn_via_ide + 2)
560 intline = MAP_IRQ(0, 10);
563 err = fdt_pci_route_intr(bus, slot, func, intpin,
564 &sc->sc_intr_info, &intline);
570 printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n",
571 unit, bus, slot, func, intpin, intline);
577 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
580 int old_pribus, old_secbus, old_subbus;
581 int new_pribus, new_secbus, new_subbus;
582 int slot, func, maxfunc;
584 uint16_t vendor, device;
585 uint8_t command, hdrtype, class, subclass;
586 uint8_t intline, intpin;
589 for (slot = 0; slot <= maxslot; slot++) {
591 for (func = 0; func <= maxfunc; func++) {
592 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
593 func, PCIR_HDRTYPE, 1);
595 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
598 if (func == 0 && (hdrtype & PCIM_MFDEV))
599 maxfunc = PCI_FUNCMAX;
601 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot,
602 func, PCIR_VENDOR, 2);
603 device = fsl_pcib_read_config(sc->sc_dev, bus, slot,
604 func, PCIR_DEVICE, 2);
606 if (vendor == 0x1957 && device == 0x3fff) {
607 sc->sc_devfn_tundra = DEVFN(bus, slot, func);
611 command = fsl_pcib_read_config(sc->sc_dev, bus, slot,
612 func, PCIR_COMMAND, 1);
613 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
614 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
615 PCIR_COMMAND, command, 1);
617 if (vendor == 0x1106)
618 fsl_pcib_init_via(sc, device, bus, slot, func);
620 /* Program the base address registers. */
621 maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
624 bar += fsl_pcib_init_bar(sc, bus, slot, func,
627 /* Perform interrupt routing. */
628 intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot,
629 func, PCIR_INTPIN, 1);
630 intline = fsl_pcib_route_int(sc, bus, slot, func,
632 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
633 PCIR_INTLINE, intline, 1);
635 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
636 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
637 PCIR_COMMAND, command, 1);
640 * Handle PCI-PCI bridges
642 class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
643 func, PCIR_CLASS, 1);
644 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
645 func, PCIR_SUBCLASS, 1);
647 /* Allow only proper PCI-PCI briges */
648 if (class != PCIC_BRIDGE)
650 if (subclass != PCIS_BRIDGE_PCI)
655 /* Program I/O decoder. */
656 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
657 PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1);
658 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
659 PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1);
660 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
661 PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2);
662 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
663 PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2);
665 /* Program (non-prefetchable) memory decoder. */
666 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
667 PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2);
668 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
669 PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2);
671 /* Program prefetchable memory decoder. */
672 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
673 PCIR_PMBASEL_1, 0x0010, 2);
674 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
675 PCIR_PMLIMITL_1, 0x000f, 2);
676 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
677 PCIR_PMBASEH_1, 0x00000000, 4);
678 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
679 PCIR_PMLIMITH_1, 0x00000000, 4);
681 /* Read currect bus register configuration */
682 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
683 slot, func, PCIR_PRIBUS_1, 1);
684 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
685 slot, func, PCIR_SECBUS_1, 1);
686 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
687 slot, func, PCIR_SUBBUS_1, 1);
690 printf("PCI: reading firmware bus numbers for "
691 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
692 secbus, old_pribus, old_secbus, old_subbus);
697 secbus = fsl_pcib_init(sc, secbus,
698 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
703 printf("PCI: translate firmware bus numbers "
704 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
705 secbus, old_pribus, old_secbus, old_subbus,
706 new_pribus, new_secbus, new_subbus);
708 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
709 PCIR_PRIBUS_1, new_pribus, 1);
710 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
711 PCIR_SECBUS_1, new_secbus, 1);
712 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
713 PCIR_SUBBUS_1, new_subbus, 1);
721 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, u_long start,
722 u_long size, u_long pci_start)
724 uint32_t attr, bar, tar;
726 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
729 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
730 case OCP85XX_TGTIF_RAM1:
731 attr = 0xa0f55000 | (ffsl(size) - 2);
738 bar = pci_start >> 12;
740 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
741 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
742 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
743 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
747 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start,
748 u_long size, u_long pci_start)
750 uint32_t attr, bar, tar;
754 attr = 0x80044000 | (ffsl(size) - 2);
757 attr = 0x80088000 | (ffsl(size) - 2);
764 tar = pci_start >> 12;
766 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
767 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
768 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
769 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
773 fsl_pcib_set_range(struct fsl_pcib_softc *sc, int type, int wnd, u_long start,
778 bus_addr_t pci_start, pci_end;
779 bus_addr_t *vap, *allocp;
782 end = start + size - 1;
790 vap = &sc->sc_ioport_va;
791 allocp = &sc->sc_ioport_alloc;
798 vap = &sc->sc_iomem_va;
799 allocp = &sc->sc_iomem_alloc;
805 rm->rm_type = RMAN_ARRAY;
806 rm->rm_start = pci_start;
807 rm->rm_end = pci_end;
808 error = rman_init(rm);
812 error = rman_manage_region(rm, pci_start, pci_end);
818 *allocp = pci_start + alloc;
819 *vap = (uintptr_t)pmap_mapdev(start, size);
820 fsl_pcib_outbound(sc, wnd, type, start, size, pci_start);
825 fsl_pcib_err_init(device_t dev)
827 struct fsl_pcib_softc *sc;
828 uint16_t sec_stat, dsr;
829 uint32_t dcr, err_en;
831 sc = device_get_softc(dev);
833 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
835 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
837 /* Clear error bits */
838 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
840 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
842 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
845 dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
846 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
848 fsl_pcib_cfgwrite(sc, 0, 0, 0,
849 sc->sc_pcie_capreg + PCIER_DEVICE_STA,
852 /* Enable all errors reporting */
854 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
857 /* Enable error reporting: URR, FER, NFER */
858 dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
859 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
860 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
861 PCIEM_CTL_NFER_ENABLE;
862 fsl_pcib_cfgwrite(sc, 0, 0, 0,
863 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
868 fsl_pcib_detach(device_t dev)
871 if (mtx_initialized) {
872 mtx_destroy(&pcicfg_mtx);
875 return (bus_generic_detach(dev));
878 static struct resource *
879 fsl_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
880 u_long start, u_long end, u_long count, u_int flags)
882 struct fsl_pcib_softc *sc = device_get_softc(dev);
884 struct resource *res;
890 va = sc->sc_ioport_va;
894 va = sc->sc_iomem_va;
898 device_printf(dev, "%s requested ISA interrupt %lu\n",
899 device_get_nameunit(child), start);
901 flags |= RF_SHAREABLE;
902 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
903 type, rid, start, end, count, flags));
908 res = rman_reserve_resource(rm, start, end, count, flags, child);
912 rman_set_bustag(res, &bs_le_tag);
913 rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start);
918 fsl_pcib_release_resource(device_t dev, device_t child, int type, int rid,
919 struct resource *res)
922 return (rman_release_resource(res));
926 fsl_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
928 struct fsl_pcib_softc *sc = device_get_softc(dev);
932 *result = sc->sc_busnr;
934 case PCIB_IVAR_DOMAIN:
935 *result = device_get_unit(dev);
942 fsl_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
944 struct fsl_pcib_softc *sc = device_get_softc(dev);
948 sc->sc_busnr = value;
955 fsl_pcib_intr_info(phandle_t node, struct fsl_pcib_softc *sc)
959 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
966 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
968 struct fdt_pci_range io_space, mem_space;
974 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) {
975 device_printf(dev, "could not retrieve 'ranges' data\n");
980 * Configure LAW decode windows.
982 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
983 &sc->sc_ioport_target);
985 device_printf(dev, "could not retrieve PCI LAW target info\n");
988 error = law_enable(sc->sc_iomem_target, mem_space.base_parent,
991 device_printf(dev, "could not program LAW for PCI MEM range\n");
994 error = law_enable(sc->sc_ioport_target, io_space.base_parent,
997 device_printf(dev, "could not program LAW for PCI IO range\n");
1002 * Set outbout and inbound windows.
1004 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
1005 if ((error = fsl_pcib_set_range(sc, SYS_RES_MEMORY, 1,
1006 mem_space.base_parent, mem_space.len)) != 0)
1008 if ((error = fsl_pcib_set_range(sc, SYS_RES_IOPORT, 2,
1009 io_space.base_parent, io_space.len)) != 0)
1012 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
1013 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
1015 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
1016 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
1017 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0,
1018 2U * 1024U * 1024U * 1024U, 0);