2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
72 #include <dev/ale/if_alereg.h>
73 #include <dev/ale/if_alevar.h>
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 /* For more information about Tx checksum offload issues see ale_encap(). */
79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
81 MODULE_DEPEND(ale, pci, 1, 1, 1);
82 MODULE_DEPEND(ale, ether, 1, 1, 1);
83 MODULE_DEPEND(ale, miibus, 1, 1, 1);
86 static int msi_disable = 0;
87 static int msix_disable = 0;
88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
92 * Devices supported by this driver.
94 static const struct ale_dev {
95 uint16_t ale_vendorid;
96 uint16_t ale_deviceid;
99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
103 static int ale_attach(device_t);
104 static int ale_check_boundary(struct ale_softc *);
105 static int ale_detach(device_t);
106 static int ale_dma_alloc(struct ale_softc *);
107 static void ale_dma_free(struct ale_softc *);
108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
109 static int ale_encap(struct ale_softc *, struct mbuf **);
110 static void ale_get_macaddr(struct ale_softc *);
111 static void ale_init(void *);
112 static void ale_init_locked(struct ale_softc *);
113 static void ale_init_rx_pages(struct ale_softc *);
114 static void ale_init_tx_ring(struct ale_softc *);
115 static void ale_int_task(void *, int);
116 static int ale_intr(void *);
117 static int ale_ioctl(struct ifnet *, u_long, caddr_t);
118 static void ale_mac_config(struct ale_softc *);
119 static int ale_miibus_readreg(device_t, int, int);
120 static void ale_miibus_statchg(device_t);
121 static int ale_miibus_writereg(device_t, int, int, int);
122 static int ale_mediachange(struct ifnet *);
123 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
124 static void ale_phy_reset(struct ale_softc *);
125 static int ale_probe(device_t);
126 static void ale_reset(struct ale_softc *);
127 static int ale_resume(device_t);
128 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
129 uint32_t, uint32_t *);
130 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
131 static int ale_rxeof(struct ale_softc *sc, int);
132 static void ale_rxfilter(struct ale_softc *);
133 static void ale_rxvlan(struct ale_softc *);
134 static void ale_setlinkspeed(struct ale_softc *);
135 static void ale_setwol(struct ale_softc *);
136 static int ale_shutdown(device_t);
137 static void ale_start(struct ifnet *);
138 static void ale_start_locked(struct ifnet *);
139 static void ale_stats_clear(struct ale_softc *);
140 static void ale_stats_update(struct ale_softc *);
141 static void ale_stop(struct ale_softc *);
142 static void ale_stop_mac(struct ale_softc *);
143 static int ale_suspend(device_t);
144 static void ale_sysctl_node(struct ale_softc *);
145 static void ale_tick(void *);
146 static void ale_txeof(struct ale_softc *);
147 static void ale_watchdog(struct ale_softc *);
148 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
149 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
150 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
152 static device_method_t ale_methods[] = {
153 /* Device interface. */
154 DEVMETHOD(device_probe, ale_probe),
155 DEVMETHOD(device_attach, ale_attach),
156 DEVMETHOD(device_detach, ale_detach),
157 DEVMETHOD(device_shutdown, ale_shutdown),
158 DEVMETHOD(device_suspend, ale_suspend),
159 DEVMETHOD(device_resume, ale_resume),
162 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
163 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
164 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
169 static driver_t ale_driver = {
172 sizeof(struct ale_softc)
175 static devclass_t ale_devclass;
177 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL);
178 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL);
180 static struct resource_spec ale_res_spec_mem[] = {
181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
185 static struct resource_spec ale_irq_spec_legacy[] = {
186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
190 static struct resource_spec ale_irq_spec_msi[] = {
191 { SYS_RES_IRQ, 1, RF_ACTIVE },
195 static struct resource_spec ale_irq_spec_msix[] = {
196 { SYS_RES_IRQ, 1, RF_ACTIVE },
201 ale_miibus_readreg(device_t dev, int phy, int reg)
203 struct ale_softc *sc;
207 sc = device_get_softc(dev);
209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
213 v = CSR_READ_4(sc, ALE_MDIO);
214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
227 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
229 struct ale_softc *sc;
233 sc = device_get_softc(dev);
235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
240 v = CSR_READ_4(sc, ALE_MDIO);
241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
252 ale_miibus_statchg(device_t dev)
254 struct ale_softc *sc;
255 struct mii_data *mii;
259 sc = device_get_softc(dev);
260 mii = device_get_softc(sc->ale_miibus);
262 if (mii == NULL || ifp == NULL ||
263 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
266 sc->ale_flags &= ~ALE_FLAG_LINK;
267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
268 (IFM_ACTIVE | IFM_AVALID)) {
269 switch (IFM_SUBTYPE(mii->mii_media_active)) {
272 sc->ale_flags |= ALE_FLAG_LINK;
275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
276 sc->ale_flags |= ALE_FLAG_LINK;
283 /* Stop Rx/Tx MACs. */
286 /* Program MACs with resolved speed/duplex/flow-control. */
287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
289 /* Reenable Tx/Rx MACs. */
290 reg = CSR_READ_4(sc, ALE_MAC_CFG);
291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
297 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
299 struct ale_softc *sc;
300 struct mii_data *mii;
304 if ((ifp->if_flags & IFF_UP) == 0) {
308 mii = device_get_softc(sc->ale_miibus);
311 ifmr->ifm_status = mii->mii_media_status;
312 ifmr->ifm_active = mii->mii_media_active;
317 ale_mediachange(struct ifnet *ifp)
319 struct ale_softc *sc;
320 struct mii_data *mii;
321 struct mii_softc *miisc;
326 mii = device_get_softc(sc->ale_miibus);
327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
329 error = mii_mediachg(mii);
336 ale_probe(device_t dev)
338 const struct ale_dev *sp;
340 uint16_t vendor, devid;
342 vendor = pci_get_vendor(dev);
343 devid = pci_get_device(dev);
345 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
346 if (vendor == sp->ale_vendorid &&
347 devid == sp->ale_deviceid) {
348 device_set_desc(dev, sp->ale_name);
349 return (BUS_PROBE_DEFAULT);
358 ale_get_macaddr(struct ale_softc *sc)
363 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
364 if ((reg & SPI_VPD_ENB) != 0) {
366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
369 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
371 * PCI VPD capability found, let TWSI reload EEPROM.
372 * This will set ethernet address of controller.
374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
375 TWSI_CTRL_SW_LD_START);
376 for (i = 100; i > 0; i--) {
378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
379 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
383 device_printf(sc->ale_dev,
384 "reloading EEPROM timeout!\n");
387 device_printf(sc->ale_dev,
388 "PCI VPD capability not found!\n");
391 ea[0] = CSR_READ_4(sc, ALE_PAR0);
392 ea[1] = CSR_READ_4(sc, ALE_PAR1);
393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
402 ale_phy_reset(struct ale_softc *sc)
405 /* Reset magic from Linux. */
406 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
408 GPHY_CTRL_PHY_PLL_ON);
410 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
415 #define ATPHY_DBG_ADDR 0x1D
416 #define ATPHY_DBG_DATA 0x1E
418 /* Enable hibernation mode. */
419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
420 ATPHY_DBG_ADDR, 0x0B);
421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
422 ATPHY_DBG_DATA, 0xBC00);
423 /* Set Class A/B for all modes. */
424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
425 ATPHY_DBG_ADDR, 0x00);
426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
427 ATPHY_DBG_DATA, 0x02EF);
428 /* Enable 10BT power saving. */
429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
430 ATPHY_DBG_ADDR, 0x12);
431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
432 ATPHY_DBG_DATA, 0x4C04);
433 /* Adjust 1000T power. */
434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
435 ATPHY_DBG_ADDR, 0x04);
436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
437 ATPHY_DBG_ADDR, 0x8BBB);
438 /* 10BT center tap voltage. */
439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
440 ATPHY_DBG_ADDR, 0x05);
441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
442 ATPHY_DBG_ADDR, 0x2C46);
444 #undef ATPHY_DBG_ADDR
445 #undef ATPHY_DBG_DATA
450 ale_attach(device_t dev)
452 struct ale_softc *sc;
455 int error, i, msic, msixc, pmc;
456 uint32_t rxf_len, txf_len;
459 sc = device_get_softc(dev);
462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
465 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
467 /* Map the device. */
468 pci_enable_busmaster(dev);
469 sc->ale_res_spec = ale_res_spec_mem;
470 sc->ale_irq_spec = ale_irq_spec_legacy;
471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
473 device_printf(dev, "cannot allocate memory resources.\n");
477 /* Set PHY address. */
478 sc->ale_phyaddr = ALE_PHY_ADDR;
483 /* Reset the ethernet controller. */
486 /* Get PCI and chip id/revision. */
487 sc->ale_rev = pci_get_revid(dev);
488 if (sc->ale_rev >= 0xF0) {
489 /* L2E Rev. B. AR8114 */
490 sc->ale_flags |= ALE_FLAG_FASTETHER;
492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
494 sc->ale_flags |= ALE_FLAG_JUMBO;
496 /* L2E Rev. A. AR8113 */
497 sc->ale_flags |= ALE_FLAG_FASTETHER;
501 * All known controllers seems to require 4 bytes alignment
502 * of Tx buffers to make Tx checksum offload with custom
503 * checksum generation method work.
505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
507 * All known controllers seems to have issues on Rx checksum
508 * offload for fragmented IP datagrams.
510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
512 * Don't use Tx CMB. It is known to cause RRS update failure
513 * under certain circumstances. Typical phenomenon of the
514 * issue would be unexpected sequence number encountered in
517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
519 MASTER_CHIP_REV_SHIFT;
521 device_printf(dev, "PCI device revision : 0x%04x\n",
523 device_printf(dev, "Chip id/revision : 0x%04x\n",
526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
529 * Uninitialized hardware returns an invalid chip id/revision
530 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
533 rxf_len == 0xFFFFFFF) {
534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
542 /* Allocate IRQ resources. */
543 msixc = pci_msix_count(dev);
544 msic = pci_msi_count(dev);
546 device_printf(dev, "MSIX count : %d\n", msixc);
547 device_printf(dev, "MSI count : %d\n", msic);
550 /* Prefer MSIX over MSI. */
551 if (msix_disable == 0 || msi_disable == 0) {
552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
553 pci_alloc_msix(dev, &msixc) == 0) {
554 if (msixc == ALE_MSIX_MESSAGES) {
555 device_printf(dev, "Using %d MSIX messages.\n",
557 sc->ale_flags |= ALE_FLAG_MSIX;
558 sc->ale_irq_spec = ale_irq_spec_msix;
560 pci_release_msi(dev);
562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
563 msic == ALE_MSI_MESSAGES &&
564 pci_alloc_msi(dev, &msic) == 0) {
565 if (msic == ALE_MSI_MESSAGES) {
566 device_printf(dev, "Using %d MSI messages.\n",
568 sc->ale_flags |= ALE_FLAG_MSI;
569 sc->ale_irq_spec = ale_irq_spec_msi;
571 pci_release_msi(dev);
575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
577 device_printf(dev, "cannot allocate IRQ resources.\n");
581 /* Get DMA parameters from PCIe device control register. */
582 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
583 sc->ale_flags |= ALE_FLAG_PCIE;
584 burst = pci_read_config(dev, i + 0x08, 2);
585 /* Max read request size. */
586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
587 DMA_CFG_RD_BURST_SHIFT;
588 /* Max payload size. */
589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
590 DMA_CFG_WR_BURST_SHIFT;
592 device_printf(dev, "Read request size : %d bytes.\n",
593 128 << ((burst >> 12) & 0x07));
594 device_printf(dev, "TLP payload size : %d bytes.\n",
595 128 << ((burst >> 5) & 0x07));
598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
602 /* Create device sysctl node. */
605 if ((error = ale_dma_alloc(sc) != 0))
608 /* Load station address. */
611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
613 device_printf(dev, "cannot allocate ifnet structure.\n");
619 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
621 ifp->if_ioctl = ale_ioctl;
622 ifp->if_start = ale_start;
623 ifp->if_init = ale_init;
624 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
625 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
626 IFQ_SET_READY(&ifp->if_snd);
627 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
628 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
629 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
630 sc->ale_flags |= ALE_FLAG_PMCAP;
631 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
633 ifp->if_capenable = ifp->if_capabilities;
635 /* Set up MII bus. */
636 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
637 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
640 device_printf(dev, "attaching PHYs failed\n");
644 ether_ifattach(ifp, sc->ale_eaddr);
646 /* VLAN capability setup. */
647 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
648 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
649 ifp->if_capenable = ifp->if_capabilities;
651 * Even though controllers supported by ale(3) have Rx checksum
652 * offload bug the workaround for fragmented frames seemed to
653 * work so far. However it seems Rx checksum offload does not
654 * work under certain conditions. So disable Rx checksum offload
655 * until I find more clue about it but allow users to override it.
657 ifp->if_capenable &= ~IFCAP_RXCSUM;
659 /* Tell the upper layer(s) we support long frames. */
660 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
662 /* Create local taskq. */
663 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
664 taskqueue_thread_enqueue, &sc->ale_tq);
665 if (sc->ale_tq == NULL) {
666 device_printf(dev, "could not create taskqueue.\n");
671 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
672 device_get_nameunit(sc->ale_dev));
674 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
675 msic = ALE_MSIX_MESSAGES;
676 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
677 msic = ALE_MSI_MESSAGES;
680 for (i = 0; i < msic; i++) {
681 error = bus_setup_intr(dev, sc->ale_irq[i],
682 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
683 &sc->ale_intrhand[i]);
688 device_printf(dev, "could not set up interrupt handler.\n");
689 taskqueue_free(sc->ale_tq);
703 ale_detach(device_t dev)
705 struct ale_softc *sc;
709 sc = device_get_softc(dev);
712 if (device_is_attached(dev)) {
717 callout_drain(&sc->ale_tick_ch);
718 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
721 if (sc->ale_tq != NULL) {
722 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
723 taskqueue_free(sc->ale_tq);
727 if (sc->ale_miibus != NULL) {
728 device_delete_child(dev, sc->ale_miibus);
729 sc->ale_miibus = NULL;
731 bus_generic_detach(dev);
739 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
740 msic = ALE_MSIX_MESSAGES;
741 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
742 msic = ALE_MSI_MESSAGES;
745 for (i = 0; i < msic; i++) {
746 if (sc->ale_intrhand[i] != NULL) {
747 bus_teardown_intr(dev, sc->ale_irq[i],
748 sc->ale_intrhand[i]);
749 sc->ale_intrhand[i] = NULL;
753 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
754 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
755 pci_release_msi(dev);
756 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
757 mtx_destroy(&sc->ale_mtx);
762 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
763 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
765 #if __FreeBSD_version >= 900030
766 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
767 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
768 #elif __FreeBSD_version > 800000
769 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
770 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
772 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
773 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
777 ale_sysctl_node(struct ale_softc *sc)
779 struct sysctl_ctx_list *ctx;
780 struct sysctl_oid_list *child, *parent;
781 struct sysctl_oid *tree;
782 struct ale_hw_stats *stats;
785 stats = &sc->ale_stats;
786 ctx = device_get_sysctl_ctx(sc->ale_dev);
787 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
789 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
790 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
791 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
792 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
793 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
794 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
795 /* Pull in device tunables. */
796 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
797 error = resource_int_value(device_get_name(sc->ale_dev),
798 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
800 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
801 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
802 device_printf(sc->ale_dev, "int_rx_mod value out of "
803 "range; using default: %d\n",
804 ALE_IM_RX_TIMER_DEFAULT);
805 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
808 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
809 error = resource_int_value(device_get_name(sc->ale_dev),
810 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
812 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
813 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
814 device_printf(sc->ale_dev, "int_tx_mod value out of "
815 "range; using default: %d\n",
816 ALE_IM_TX_TIMER_DEFAULT);
817 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
820 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
821 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0,
822 sysctl_hw_ale_proc_limit, "I",
823 "max number of Rx events to process");
824 /* Pull in device tunables. */
825 sc->ale_process_limit = ALE_PROC_DEFAULT;
826 error = resource_int_value(device_get_name(sc->ale_dev),
827 device_get_unit(sc->ale_dev), "process_limit",
828 &sc->ale_process_limit);
830 if (sc->ale_process_limit < ALE_PROC_MIN ||
831 sc->ale_process_limit > ALE_PROC_MAX) {
832 device_printf(sc->ale_dev,
833 "process_limit value out of range; "
834 "using default: %d\n", ALE_PROC_DEFAULT);
835 sc->ale_process_limit = ALE_PROC_DEFAULT;
839 /* Misc statistics. */
840 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
841 &stats->reset_brk_seq,
842 "Controller resets due to broken Rx sequnce number");
844 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
845 NULL, "ATE statistics");
846 parent = SYSCTL_CHILDREN(tree);
849 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
850 NULL, "Rx MAC statistics");
851 child = SYSCTL_CHILDREN(tree);
852 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
853 &stats->rx_frames, "Good frames");
854 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
855 &stats->rx_bcast_frames, "Good broadcast frames");
856 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
857 &stats->rx_mcast_frames, "Good multicast frames");
858 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
859 &stats->rx_pause_frames, "Pause control frames");
860 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
861 &stats->rx_control_frames, "Control frames");
862 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
863 &stats->rx_crcerrs, "CRC errors");
864 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
865 &stats->rx_lenerrs, "Frames with length mismatched");
866 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
867 &stats->rx_bytes, "Good octets");
868 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
869 &stats->rx_bcast_bytes, "Good broadcast octets");
870 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
871 &stats->rx_mcast_bytes, "Good multicast octets");
872 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
873 &stats->rx_runts, "Too short frames");
874 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
875 &stats->rx_fragments, "Fragmented frames");
876 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
877 &stats->rx_pkts_64, "64 bytes frames");
878 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
879 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
880 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
881 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
882 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
883 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
884 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
885 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
886 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
887 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
888 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
889 &stats->rx_pkts_1519_max, "1519 to max frames");
890 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
891 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
892 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
893 &stats->rx_fifo_oflows, "FIFO overflows");
894 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
895 &stats->rx_rrs_errs, "Return status write-back errors");
896 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
897 &stats->rx_alignerrs, "Alignment errors");
898 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
899 &stats->rx_pkts_filtered,
900 "Frames dropped due to address filtering");
903 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
904 NULL, "Tx MAC statistics");
905 child = SYSCTL_CHILDREN(tree);
906 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
907 &stats->tx_frames, "Good frames");
908 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
909 &stats->tx_bcast_frames, "Good broadcast frames");
910 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
911 &stats->tx_mcast_frames, "Good multicast frames");
912 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
913 &stats->tx_pause_frames, "Pause control frames");
914 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
915 &stats->tx_control_frames, "Control frames");
916 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
917 &stats->tx_excess_defer, "Frames with excessive derferrals");
918 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
919 &stats->tx_excess_defer, "Frames with derferrals");
920 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
921 &stats->tx_bytes, "Good octets");
922 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
923 &stats->tx_bcast_bytes, "Good broadcast octets");
924 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
925 &stats->tx_mcast_bytes, "Good multicast octets");
926 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
927 &stats->tx_pkts_64, "64 bytes frames");
928 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
929 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
930 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
931 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
932 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
933 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
934 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
935 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
936 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
937 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
938 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
939 &stats->tx_pkts_1519_max, "1519 to max frames");
940 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
941 &stats->tx_single_colls, "Single collisions");
942 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
943 &stats->tx_multi_colls, "Multiple collisions");
944 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
945 &stats->tx_late_colls, "Late collisions");
946 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
947 &stats->tx_excess_colls, "Excessive collisions");
948 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
949 &stats->tx_abort, "Aborted frames due to Excessive collisions");
950 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
951 &stats->tx_underrun, "FIFO underruns");
952 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
953 &stats->tx_desc_underrun, "Descriptor write-back errors");
954 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
955 &stats->tx_lenerrs, "Frames with length mismatched");
956 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
957 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
960 #undef ALE_SYSCTL_STAT_ADD32
961 #undef ALE_SYSCTL_STAT_ADD64
963 struct ale_dmamap_arg {
964 bus_addr_t ale_busaddr;
968 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
970 struct ale_dmamap_arg *ctx;
975 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
977 ctx = (struct ale_dmamap_arg *)arg;
978 ctx->ale_busaddr = segs[0].ds_addr;
982 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
983 * which specifies high address region of DMA blocks. Therefore these
984 * blocks should have the same high address of given 4GB address
985 * space(i.e. crossing 4GB boundary is not allowed).
988 ale_check_boundary(struct ale_softc *sc)
990 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
991 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
993 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
995 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
997 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
998 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
999 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
1000 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
1002 if ((ALE_ADDR_HI(tx_ring_end) !=
1003 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
1004 (ALE_ADDR_HI(rx_page_end[0]) !=
1005 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
1006 (ALE_ADDR_HI(rx_page_end[1]) !=
1007 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
1008 (ALE_ADDR_HI(tx_cmb_end) !=
1009 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
1010 (ALE_ADDR_HI(rx_cmb_end[0]) !=
1011 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
1012 (ALE_ADDR_HI(rx_cmb_end[1]) !=
1013 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
1016 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
1017 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
1018 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
1019 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
1020 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
1027 ale_dma_alloc(struct ale_softc *sc)
1029 struct ale_txdesc *txd;
1031 struct ale_dmamap_arg ctx;
1032 int error, guard_size, i;
1034 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1035 guard_size = ALE_JUMBO_FRAMELEN;
1037 guard_size = ALE_MAX_FRAMELEN;
1038 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1040 lowaddr = BUS_SPACE_MAXADDR;
1042 /* Create parent DMA tag. */
1043 error = bus_dma_tag_create(
1044 bus_get_dma_tag(sc->ale_dev), /* parent */
1045 1, 0, /* alignment, boundary */
1046 lowaddr, /* lowaddr */
1047 BUS_SPACE_MAXADDR, /* highaddr */
1048 NULL, NULL, /* filter, filterarg */
1049 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1051 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1053 NULL, NULL, /* lockfunc, lockarg */
1054 &sc->ale_cdata.ale_parent_tag);
1056 device_printf(sc->ale_dev,
1057 "could not create parent DMA tag.\n");
1061 /* Create DMA tag for Tx descriptor ring. */
1062 error = bus_dma_tag_create(
1063 sc->ale_cdata.ale_parent_tag, /* parent */
1064 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1065 BUS_SPACE_MAXADDR, /* lowaddr */
1066 BUS_SPACE_MAXADDR, /* highaddr */
1067 NULL, NULL, /* filter, filterarg */
1068 ALE_TX_RING_SZ, /* maxsize */
1070 ALE_TX_RING_SZ, /* maxsegsize */
1072 NULL, NULL, /* lockfunc, lockarg */
1073 &sc->ale_cdata.ale_tx_ring_tag);
1075 device_printf(sc->ale_dev,
1076 "could not create Tx ring DMA tag.\n");
1080 /* Create DMA tag for Rx pages. */
1081 for (i = 0; i < ALE_RX_PAGES; i++) {
1082 error = bus_dma_tag_create(
1083 sc->ale_cdata.ale_parent_tag, /* parent */
1084 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1085 BUS_SPACE_MAXADDR, /* lowaddr */
1086 BUS_SPACE_MAXADDR, /* highaddr */
1087 NULL, NULL, /* filter, filterarg */
1088 sc->ale_pagesize, /* maxsize */
1090 sc->ale_pagesize, /* maxsegsize */
1092 NULL, NULL, /* lockfunc, lockarg */
1093 &sc->ale_cdata.ale_rx_page[i].page_tag);
1095 device_printf(sc->ale_dev,
1096 "could not create Rx page %d DMA tag.\n", i);
1101 /* Create DMA tag for Tx coalescing message block. */
1102 error = bus_dma_tag_create(
1103 sc->ale_cdata.ale_parent_tag, /* parent */
1104 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1105 BUS_SPACE_MAXADDR, /* lowaddr */
1106 BUS_SPACE_MAXADDR, /* highaddr */
1107 NULL, NULL, /* filter, filterarg */
1108 ALE_TX_CMB_SZ, /* maxsize */
1110 ALE_TX_CMB_SZ, /* maxsegsize */
1112 NULL, NULL, /* lockfunc, lockarg */
1113 &sc->ale_cdata.ale_tx_cmb_tag);
1115 device_printf(sc->ale_dev,
1116 "could not create Tx CMB DMA tag.\n");
1120 /* Create DMA tag for Rx coalescing message block. */
1121 for (i = 0; i < ALE_RX_PAGES; i++) {
1122 error = bus_dma_tag_create(
1123 sc->ale_cdata.ale_parent_tag, /* parent */
1124 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1125 BUS_SPACE_MAXADDR, /* lowaddr */
1126 BUS_SPACE_MAXADDR, /* highaddr */
1127 NULL, NULL, /* filter, filterarg */
1128 ALE_RX_CMB_SZ, /* maxsize */
1130 ALE_RX_CMB_SZ, /* maxsegsize */
1132 NULL, NULL, /* lockfunc, lockarg */
1133 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1135 device_printf(sc->ale_dev,
1136 "could not create Rx page %d CMB DMA tag.\n", i);
1141 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1142 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1143 (void **)&sc->ale_cdata.ale_tx_ring,
1144 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1145 &sc->ale_cdata.ale_tx_ring_map);
1147 device_printf(sc->ale_dev,
1148 "could not allocate DMA'able memory for Tx ring.\n");
1151 ctx.ale_busaddr = 0;
1152 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1153 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1154 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1155 if (error != 0 || ctx.ale_busaddr == 0) {
1156 device_printf(sc->ale_dev,
1157 "could not load DMA'able memory for Tx ring.\n");
1160 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1163 for (i = 0; i < ALE_RX_PAGES; i++) {
1164 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1165 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1166 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1167 &sc->ale_cdata.ale_rx_page[i].page_map);
1169 device_printf(sc->ale_dev,
1170 "could not allocate DMA'able memory for "
1171 "Rx page %d.\n", i);
1174 ctx.ale_busaddr = 0;
1175 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1176 sc->ale_cdata.ale_rx_page[i].page_map,
1177 sc->ale_cdata.ale_rx_page[i].page_addr,
1178 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1179 if (error != 0 || ctx.ale_busaddr == 0) {
1180 device_printf(sc->ale_dev,
1181 "could not load DMA'able memory for "
1182 "Rx page %d.\n", i);
1185 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1189 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1190 (void **)&sc->ale_cdata.ale_tx_cmb,
1191 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1192 &sc->ale_cdata.ale_tx_cmb_map);
1194 device_printf(sc->ale_dev,
1195 "could not allocate DMA'able memory for Tx CMB.\n");
1198 ctx.ale_busaddr = 0;
1199 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1200 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1201 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1202 if (error != 0 || ctx.ale_busaddr == 0) {
1203 device_printf(sc->ale_dev,
1204 "could not load DMA'able memory for Tx CMB.\n");
1207 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1210 for (i = 0; i < ALE_RX_PAGES; i++) {
1211 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1212 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1213 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1214 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1216 device_printf(sc->ale_dev, "could not allocate "
1217 "DMA'able memory for Rx page %d CMB.\n", i);
1220 ctx.ale_busaddr = 0;
1221 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1222 sc->ale_cdata.ale_rx_page[i].cmb_map,
1223 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1224 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1225 if (error != 0 || ctx.ale_busaddr == 0) {
1226 device_printf(sc->ale_dev, "could not load DMA'able "
1227 "memory for Rx page %d CMB.\n", i);
1230 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1234 * Tx descriptors/RXF0/CMB DMA blocks share the same
1235 * high address region of 64bit DMA address space.
1237 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1238 (error = ale_check_boundary(sc)) != 0) {
1239 device_printf(sc->ale_dev, "4GB boundary crossed, "
1240 "switching to 32bit DMA addressing mode.\n");
1243 * Limit max allowable DMA address space to 32bit
1246 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1251 * Create Tx buffer parent tag.
1252 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1253 * needs separate parent DMA tag as parent DMA address space
1254 * could be restricted to be within 32bit address space by
1255 * 4GB boundary crossing.
1257 error = bus_dma_tag_create(
1258 bus_get_dma_tag(sc->ale_dev), /* parent */
1259 1, 0, /* alignment, boundary */
1260 BUS_SPACE_MAXADDR, /* lowaddr */
1261 BUS_SPACE_MAXADDR, /* highaddr */
1262 NULL, NULL, /* filter, filterarg */
1263 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1265 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1267 NULL, NULL, /* lockfunc, lockarg */
1268 &sc->ale_cdata.ale_buffer_tag);
1270 device_printf(sc->ale_dev,
1271 "could not create parent buffer DMA tag.\n");
1275 /* Create DMA tag for Tx buffers. */
1276 error = bus_dma_tag_create(
1277 sc->ale_cdata.ale_buffer_tag, /* parent */
1278 1, 0, /* alignment, boundary */
1279 BUS_SPACE_MAXADDR, /* lowaddr */
1280 BUS_SPACE_MAXADDR, /* highaddr */
1281 NULL, NULL, /* filter, filterarg */
1282 ALE_TSO_MAXSIZE, /* maxsize */
1283 ALE_MAXTXSEGS, /* nsegments */
1284 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1286 NULL, NULL, /* lockfunc, lockarg */
1287 &sc->ale_cdata.ale_tx_tag);
1289 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1293 /* Create DMA maps for Tx buffers. */
1294 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1295 txd = &sc->ale_cdata.ale_txdesc[i];
1297 txd->tx_dmamap = NULL;
1298 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1301 device_printf(sc->ale_dev,
1302 "could not create Tx dmamap.\n");
1312 ale_dma_free(struct ale_softc *sc)
1314 struct ale_txdesc *txd;
1318 if (sc->ale_cdata.ale_tx_tag != NULL) {
1319 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1320 txd = &sc->ale_cdata.ale_txdesc[i];
1321 if (txd->tx_dmamap != NULL) {
1322 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1324 txd->tx_dmamap = NULL;
1327 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1328 sc->ale_cdata.ale_tx_tag = NULL;
1330 /* Tx descriptor ring. */
1331 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1332 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1333 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1334 sc->ale_cdata.ale_tx_ring_map);
1335 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1336 sc->ale_cdata.ale_tx_ring != NULL)
1337 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1338 sc->ale_cdata.ale_tx_ring,
1339 sc->ale_cdata.ale_tx_ring_map);
1340 sc->ale_cdata.ale_tx_ring = NULL;
1341 sc->ale_cdata.ale_tx_ring_map = NULL;
1342 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1343 sc->ale_cdata.ale_tx_ring_tag = NULL;
1345 /* Rx page block. */
1346 for (i = 0; i < ALE_RX_PAGES; i++) {
1347 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1348 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1350 sc->ale_cdata.ale_rx_page[i].page_tag,
1351 sc->ale_cdata.ale_rx_page[i].page_map);
1352 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1353 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1355 sc->ale_cdata.ale_rx_page[i].page_tag,
1356 sc->ale_cdata.ale_rx_page[i].page_addr,
1357 sc->ale_cdata.ale_rx_page[i].page_map);
1358 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1359 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1360 bus_dma_tag_destroy(
1361 sc->ale_cdata.ale_rx_page[i].page_tag);
1362 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1366 for (i = 0; i < ALE_RX_PAGES; i++) {
1367 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1368 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1370 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1371 sc->ale_cdata.ale_rx_page[i].cmb_map);
1372 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1373 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1375 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1376 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1377 sc->ale_cdata.ale_rx_page[i].cmb_map);
1378 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1379 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1380 bus_dma_tag_destroy(
1381 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1382 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1386 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1387 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1388 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1389 sc->ale_cdata.ale_tx_cmb_map);
1390 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1391 sc->ale_cdata.ale_tx_cmb != NULL)
1392 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1393 sc->ale_cdata.ale_tx_cmb,
1394 sc->ale_cdata.ale_tx_cmb_map);
1395 sc->ale_cdata.ale_tx_cmb = NULL;
1396 sc->ale_cdata.ale_tx_cmb_map = NULL;
1397 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1398 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1400 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1401 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1402 sc->ale_cdata.ale_buffer_tag = NULL;
1404 if (sc->ale_cdata.ale_parent_tag != NULL) {
1405 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1406 sc->ale_cdata.ale_parent_tag = NULL;
1411 ale_shutdown(device_t dev)
1414 return (ale_suspend(dev));
1418 * Note, this driver resets the link speed to 10/100Mbps by
1419 * restarting auto-negotiation in suspend/shutdown phase but we
1420 * don't know whether that auto-negotiation would succeed or not
1421 * as driver has no control after powering off/suspend operation.
1422 * If the renegotiation fail WOL may not work. Running at 1Gbps
1423 * will draw more power than 375mA at 3.3V which is specified in
1424 * PCI specification and that would result in complete
1425 * shutdowning power to ethernet controller.
1428 * Save current negotiated media speed/duplex/flow-control to
1429 * softc and restore the same link again after resuming. PHY
1430 * handling such as power down/resetting to 100Mbps may be better
1431 * handled in suspend method in phy driver.
1434 ale_setlinkspeed(struct ale_softc *sc)
1436 struct mii_data *mii;
1439 mii = device_get_softc(sc->ale_miibus);
1442 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1443 (IFM_ACTIVE | IFM_AVALID)) {
1444 switch IFM_SUBTYPE(mii->mii_media_active) {
1455 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1456 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1457 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1458 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1459 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1463 * Poll link state until ale(4) get a 10/100Mbps link.
1465 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1467 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1468 == (IFM_ACTIVE | IFM_AVALID)) {
1469 switch (IFM_SUBTYPE(
1470 mii->mii_media_active)) {
1480 pause("alelnk", hz);
1483 if (i == MII_ANEGTICKS_GIGE)
1484 device_printf(sc->ale_dev,
1485 "establishing a link failed, WOL may not work!");
1488 * No link, force MAC to have 100Mbps, full-duplex link.
1489 * This is the last resort and may/may not work.
1491 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1492 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1497 ale_setwol(struct ale_softc *sc)
1504 ALE_LOCK_ASSERT(sc);
1506 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1508 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1509 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1510 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1511 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1512 /* Force PHY power down. */
1513 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1514 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1515 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1516 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1517 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1522 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1523 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1524 ale_setlinkspeed(sc);
1528 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1529 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1530 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1531 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1532 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1534 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1535 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1536 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1537 reg |= MAC_CFG_RX_ENB;
1538 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1540 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1541 /* WOL disabled, PHY power down. */
1542 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1543 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1544 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1545 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1546 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1547 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1548 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1549 GPHY_CTRL_PWDOWN_HW);
1552 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1553 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1554 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1555 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1556 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1560 ale_suspend(device_t dev)
1562 struct ale_softc *sc;
1564 sc = device_get_softc(dev);
1575 ale_resume(device_t dev)
1577 struct ale_softc *sc;
1582 sc = device_get_softc(dev);
1585 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1586 /* Disable PME and clear PME status. */
1587 pmstat = pci_read_config(sc->ale_dev,
1588 pmc + PCIR_POWER_STATUS, 2);
1589 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1590 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1591 pci_write_config(sc->ale_dev,
1592 pmc + PCIR_POWER_STATUS, pmstat, 2);
1598 if ((ifp->if_flags & IFF_UP) != 0) {
1599 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1600 ale_init_locked(sc);
1608 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1610 struct ale_txdesc *txd, *txd_last;
1611 struct tx_desc *desc;
1615 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1617 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1618 int error, i, nsegs, prod, si;
1620 ALE_LOCK_ASSERT(sc);
1622 M_ASSERTPKTHDR((*m_head));
1629 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1631 * AR81xx requires offset of TCP/UDP payload in its Tx
1632 * descriptor to perform hardware Tx checksum offload.
1633 * Additionally, TSO requires IP/TCP header size and
1634 * modification of IP/TCP header in order to make TSO
1635 * engine work. This kind of operation takes many CPU
1636 * cycles on FreeBSD so fast host CPU is required to
1637 * get smooth TSO performance.
1639 struct ether_header *eh;
1641 if (M_WRITABLE(m) == 0) {
1642 /* Get a writable copy. */
1643 m = m_dup(*m_head, M_NOWAIT);
1644 /* Release original mbufs. */
1654 * Buggy-controller requires 4 byte aligned Tx buffer
1655 * to make custom checksum offload work.
1657 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1658 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1659 (mtod(m, intptr_t) & 3) != 0) {
1660 m = m_defrag(*m_head, M_NOWAIT);
1669 ip_off = sizeof(struct ether_header);
1670 m = m_pullup(m, ip_off);
1675 eh = mtod(m, struct ether_header *);
1677 * Check if hardware VLAN insertion is off.
1678 * Additional check for LLC/SNAP frame?
1680 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1681 ip_off = sizeof(struct ether_vlan_header);
1682 m = m_pullup(m, ip_off);
1688 m = m_pullup(m, ip_off + sizeof(struct ip));
1693 ip = (struct ip *)(mtod(m, char *) + ip_off);
1694 poff = ip_off + (ip->ip_hl << 2);
1695 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1698 * AR81xx requires the first descriptor should
1699 * not include any TCP playload for TSO case.
1700 * (i.e. ethernet header + IP + TCP header only)
1701 * m_pullup(9) above will ensure this too.
1702 * However it's not correct if the first mbuf
1703 * of the chain does not use cluster.
1705 m = m_pullup(m, poff + sizeof(struct tcphdr));
1710 ip = (struct ip *)(mtod(m, char *) + ip_off);
1711 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1712 m = m_pullup(m, poff + (tcp->th_off << 2));
1718 * AR81xx requires IP/TCP header size and offset as
1719 * well as TCP pseudo checksum which complicates
1720 * TSO configuration. I guess this comes from the
1721 * adherence to Microsoft NDIS Large Send
1722 * specification which requires insertion of
1723 * pseudo checksum by upper stack. The pseudo
1724 * checksum that NDIS refers to doesn't include
1725 * TCP payload length so ale(4) should recompute
1726 * the pseudo checksum here. Hopefully this wouldn't
1727 * be much burden on modern CPUs.
1728 * Reset IP checksum and recompute TCP pseudo
1729 * checksum as NDIS specification said.
1732 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1733 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1738 si = prod = sc->ale_cdata.ale_tx_prod;
1739 txd = &sc->ale_cdata.ale_txdesc[prod];
1741 map = txd->tx_dmamap;
1743 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1744 *m_head, txsegs, &nsegs, 0);
1745 if (error == EFBIG) {
1746 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS);
1753 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1754 *m_head, txsegs, &nsegs, 0);
1760 } else if (error != 0)
1768 /* Check descriptor overrun. */
1769 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1770 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1773 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1776 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1777 /* Request TSO and set MSS. */
1778 cflags |= ALE_TD_TSO;
1779 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1780 /* Set IP/TCP header size. */
1781 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1782 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1783 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1785 * AR81xx supports Tx custom checksum offload feature
1786 * that offloads single 16bit checksum computation.
1787 * So you can choose one among IP, TCP and UDP.
1788 * Normally driver sets checksum start/insertion
1789 * position from the information of TCP/UDP frame as
1790 * TCP/UDP checksum takes more time than that of IP.
1791 * However it seems that custom checksum offload
1792 * requires 4 bytes aligned Tx buffers due to hardware
1794 * AR81xx also supports explicit Tx checksum computation
1795 * if it is told that the size of IP header and TCP
1796 * header(for UDP, the header size does not matter
1797 * because it's fixed length). However with this scheme
1798 * TSO does not work so you have to choose one either
1799 * TSO or explicit Tx checksum offload. I chosen TSO
1800 * plus custom checksum offload with work-around which
1801 * will cover most common usage for this consumer
1802 * ethernet controller. The work-around takes a lot of
1803 * CPU cycles if Tx buffer is not aligned on 4 bytes
1806 cflags |= ALE_TD_CXSUM;
1807 /* Set checksum start offset. */
1808 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1809 /* Set checksum insertion position of TCP/UDP. */
1810 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1811 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1814 /* Configure VLAN hardware tag insertion. */
1815 if ((m->m_flags & M_VLANTAG) != 0) {
1816 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1817 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1818 cflags |= ALE_TD_INSERT_VLAN_TAG;
1822 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1824 * Make sure the first fragment contains
1825 * only ethernet and IP/TCP header with options.
1827 hdrlen = poff + (tcp->th_off << 2);
1828 desc = &sc->ale_cdata.ale_tx_ring[prod];
1829 desc->addr = htole64(txsegs[i].ds_addr);
1830 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1831 desc->flags = htole32(cflags);
1832 sc->ale_cdata.ale_tx_cnt++;
1833 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1834 if (m->m_len - hdrlen > 0) {
1835 /* Handle remaining payload of the first fragment. */
1836 desc = &sc->ale_cdata.ale_tx_ring[prod];
1837 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1838 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1840 desc->flags = htole32(cflags);
1841 sc->ale_cdata.ale_tx_cnt++;
1842 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1846 for (; i < nsegs; i++) {
1847 desc = &sc->ale_cdata.ale_tx_ring[prod];
1848 desc->addr = htole64(txsegs[i].ds_addr);
1849 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1850 desc->flags = htole32(cflags);
1851 sc->ale_cdata.ale_tx_cnt++;
1852 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1854 /* Update producer index. */
1855 sc->ale_cdata.ale_tx_prod = prod;
1856 /* Set TSO header on the first descriptor. */
1857 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1858 desc = &sc->ale_cdata.ale_tx_ring[si];
1859 desc->flags |= htole32(ALE_TD_TSO_HDR);
1862 /* Finally set EOP on the last descriptor. */
1863 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1864 desc = &sc->ale_cdata.ale_tx_ring[prod];
1865 desc->flags |= htole32(ALE_TD_EOP);
1867 /* Swap dmamap of the first and the last. */
1868 txd = &sc->ale_cdata.ale_txdesc[prod];
1869 map = txd_last->tx_dmamap;
1870 txd_last->tx_dmamap = txd->tx_dmamap;
1871 txd->tx_dmamap = map;
1874 /* Sync descriptors. */
1875 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1876 sc->ale_cdata.ale_tx_ring_map,
1877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1883 ale_start(struct ifnet *ifp)
1885 struct ale_softc *sc;
1889 ale_start_locked(ifp);
1894 ale_start_locked(struct ifnet *ifp)
1896 struct ale_softc *sc;
1897 struct mbuf *m_head;
1902 ALE_LOCK_ASSERT(sc);
1904 /* Reclaim transmitted frames. */
1905 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1908 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1909 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1912 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1913 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1917 * Pack the data into the transmit ring. If we
1918 * don't have room, set the OACTIVE flag and wait
1919 * for the NIC to drain the ring.
1921 if (ale_encap(sc, &m_head)) {
1924 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1925 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1931 * If there's a BPF listener, bounce a copy of this frame
1934 ETHER_BPF_MTAP(ifp, m_head);
1939 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1940 sc->ale_cdata.ale_tx_prod);
1941 /* Set a timeout in case the chip goes out to lunch. */
1942 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1947 ale_watchdog(struct ale_softc *sc)
1951 ALE_LOCK_ASSERT(sc);
1953 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1957 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1958 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1960 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1961 ale_init_locked(sc);
1964 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1966 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1967 ale_init_locked(sc);
1968 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1969 ale_start_locked(ifp);
1973 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1975 struct ale_softc *sc;
1977 struct mii_data *mii;
1981 ifr = (struct ifreq *)data;
1985 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1986 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1987 ifr->ifr_mtu > ETHERMTU))
1989 else if (ifp->if_mtu != ifr->ifr_mtu) {
1991 ifp->if_mtu = ifr->ifr_mtu;
1992 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1993 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1994 ale_init_locked(sc);
2001 if ((ifp->if_flags & IFF_UP) != 0) {
2002 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2003 if (((ifp->if_flags ^ sc->ale_if_flags)
2004 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2007 ale_init_locked(sc);
2010 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2013 sc->ale_if_flags = ifp->if_flags;
2019 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2025 mii = device_get_softc(sc->ale_miibus);
2026 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2030 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2031 if ((mask & IFCAP_TXCSUM) != 0 &&
2032 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2033 ifp->if_capenable ^= IFCAP_TXCSUM;
2034 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2035 ifp->if_hwassist |= ALE_CSUM_FEATURES;
2037 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
2039 if ((mask & IFCAP_RXCSUM) != 0 &&
2040 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
2041 ifp->if_capenable ^= IFCAP_RXCSUM;
2042 if ((mask & IFCAP_TSO4) != 0 &&
2043 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2044 ifp->if_capenable ^= IFCAP_TSO4;
2045 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2046 ifp->if_hwassist |= CSUM_TSO;
2048 ifp->if_hwassist &= ~CSUM_TSO;
2051 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2052 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2053 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2054 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2055 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2056 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2057 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2058 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2059 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2060 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2061 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2062 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2063 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2064 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2065 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2066 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2067 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2071 VLAN_CAPABILITIES(ifp);
2074 error = ether_ioctl(ifp, cmd, data);
2082 ale_mac_config(struct ale_softc *sc)
2084 struct mii_data *mii;
2087 ALE_LOCK_ASSERT(sc);
2089 mii = device_get_softc(sc->ale_miibus);
2090 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2091 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2092 MAC_CFG_SPEED_MASK);
2093 /* Reprogram MAC with resolved speed/duplex. */
2094 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2097 reg |= MAC_CFG_SPEED_10_100;
2100 reg |= MAC_CFG_SPEED_1000;
2103 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2104 reg |= MAC_CFG_FULL_DUPLEX;
2105 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2106 reg |= MAC_CFG_TX_FC;
2107 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2108 reg |= MAC_CFG_RX_FC;
2110 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2114 ale_stats_clear(struct ale_softc *sc)
2120 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2121 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2122 i += sizeof(uint32_t);
2124 /* Read Tx statistics. */
2125 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2126 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2127 i += sizeof(uint32_t);
2132 ale_stats_update(struct ale_softc *sc)
2134 struct ale_hw_stats *stat;
2135 struct smb sb, *smb;
2140 ALE_LOCK_ASSERT(sc);
2143 stat = &sc->ale_stats;
2146 /* Read Rx statistics. */
2147 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2148 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2149 i += sizeof(uint32_t);
2151 /* Read Tx statistics. */
2152 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2153 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2154 i += sizeof(uint32_t);
2158 stat->rx_frames += smb->rx_frames;
2159 stat->rx_bcast_frames += smb->rx_bcast_frames;
2160 stat->rx_mcast_frames += smb->rx_mcast_frames;
2161 stat->rx_pause_frames += smb->rx_pause_frames;
2162 stat->rx_control_frames += smb->rx_control_frames;
2163 stat->rx_crcerrs += smb->rx_crcerrs;
2164 stat->rx_lenerrs += smb->rx_lenerrs;
2165 stat->rx_bytes += smb->rx_bytes;
2166 stat->rx_runts += smb->rx_runts;
2167 stat->rx_fragments += smb->rx_fragments;
2168 stat->rx_pkts_64 += smb->rx_pkts_64;
2169 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2170 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2171 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2172 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2173 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2174 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2175 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2176 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2177 stat->rx_rrs_errs += smb->rx_rrs_errs;
2178 stat->rx_alignerrs += smb->rx_alignerrs;
2179 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2180 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2181 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2184 stat->tx_frames += smb->tx_frames;
2185 stat->tx_bcast_frames += smb->tx_bcast_frames;
2186 stat->tx_mcast_frames += smb->tx_mcast_frames;
2187 stat->tx_pause_frames += smb->tx_pause_frames;
2188 stat->tx_excess_defer += smb->tx_excess_defer;
2189 stat->tx_control_frames += smb->tx_control_frames;
2190 stat->tx_deferred += smb->tx_deferred;
2191 stat->tx_bytes += smb->tx_bytes;
2192 stat->tx_pkts_64 += smb->tx_pkts_64;
2193 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2194 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2195 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2196 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2197 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2198 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2199 stat->tx_single_colls += smb->tx_single_colls;
2200 stat->tx_multi_colls += smb->tx_multi_colls;
2201 stat->tx_late_colls += smb->tx_late_colls;
2202 stat->tx_excess_colls += smb->tx_excess_colls;
2203 stat->tx_abort += smb->tx_abort;
2204 stat->tx_underrun += smb->tx_underrun;
2205 stat->tx_desc_underrun += smb->tx_desc_underrun;
2206 stat->tx_lenerrs += smb->tx_lenerrs;
2207 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2208 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2209 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2211 /* Update counters in ifnet. */
2212 ifp->if_opackets += smb->tx_frames;
2214 ifp->if_collisions += smb->tx_single_colls +
2215 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2216 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2220 * tx_pkts_truncated counter looks suspicious. It constantly
2221 * increments with no sign of Tx errors. This may indicate
2222 * the counter name is not correct one so I've removed the
2223 * counter in output errors.
2225 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2228 ifp->if_ipackets += smb->rx_frames;
2230 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2231 smb->rx_runts + smb->rx_pkts_truncated +
2232 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2239 struct ale_softc *sc;
2242 sc = (struct ale_softc *)arg;
2244 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2245 if ((status & ALE_INTRS) == 0)
2246 return (FILTER_STRAY);
2247 /* Disable interrupts. */
2248 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2249 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2251 return (FILTER_HANDLED);
2255 ale_int_task(void *arg, int pending)
2257 struct ale_softc *sc;
2262 sc = (struct ale_softc *)arg;
2264 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2266 if (sc->ale_morework != 0)
2267 status |= INTR_RX_PKT;
2268 if ((status & ALE_INTRS) == 0)
2271 /* Acknowledge interrupts but still disable interrupts. */
2272 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2276 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2277 more = ale_rxeof(sc, sc->ale_process_limit);
2279 sc->ale_morework = 1;
2280 else if (more == EIO) {
2281 sc->ale_stats.reset_brk_seq++;
2282 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2283 ale_init_locked(sc);
2288 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2289 if ((status & INTR_DMA_RD_TO_RST) != 0)
2290 device_printf(sc->ale_dev,
2291 "DMA read error! -- resetting\n");
2292 if ((status & INTR_DMA_WR_TO_RST) != 0)
2293 device_printf(sc->ale_dev,
2294 "DMA write error! -- resetting\n");
2295 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2296 ale_init_locked(sc);
2300 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2301 ale_start_locked(ifp);
2304 if (more == EAGAIN ||
2305 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2307 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2314 /* Re-enable interrupts. */
2315 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2319 ale_txeof(struct ale_softc *sc)
2322 struct ale_txdesc *txd;
2323 uint32_t cons, prod;
2326 ALE_LOCK_ASSERT(sc);
2330 if (sc->ale_cdata.ale_tx_cnt == 0)
2333 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2334 sc->ale_cdata.ale_tx_ring_map,
2335 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2336 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2337 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2338 sc->ale_cdata.ale_tx_cmb_map,
2339 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2340 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2342 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2343 cons = sc->ale_cdata.ale_tx_cons;
2345 * Go through our Tx list and free mbufs for those
2346 * frames which have been transmitted.
2348 for (prog = 0; cons != prod; prog++,
2349 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2350 if (sc->ale_cdata.ale_tx_cnt <= 0)
2353 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2354 sc->ale_cdata.ale_tx_cnt--;
2355 txd = &sc->ale_cdata.ale_txdesc[cons];
2356 if (txd->tx_m != NULL) {
2357 /* Reclaim transmitted mbufs. */
2358 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2359 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2360 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2368 sc->ale_cdata.ale_tx_cons = cons;
2370 * Unarm watchdog timer only when there is no pending
2371 * Tx descriptors in queue.
2373 if (sc->ale_cdata.ale_tx_cnt == 0)
2374 sc->ale_watchdog_timer = 0;
2379 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2380 uint32_t length, uint32_t *prod)
2382 struct ale_rx_page *rx_page;
2385 /* Update consumer position. */
2386 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2388 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2390 * End of Rx page reached, let hardware reuse
2394 *rx_page->cmb_addr = 0;
2395 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2397 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2399 /* Switch to alternate Rx page. */
2400 sc->ale_cdata.ale_rx_curp ^= 1;
2402 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2403 /* Page flipped, sync CMB and Rx page. */
2404 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2405 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2406 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2407 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2408 /* Sync completed, cache updated producer index. */
2409 *prod = *rx_page->cmb_addr;
2415 * It seems that AR81xx controller can compute partial checksum.
2416 * The partial checksum value can be used to accelerate checksum
2417 * computation for fragmented TCP/UDP packets. Upper network stack
2418 * already takes advantage of the partial checksum value in IP
2419 * reassembly stage. But I'm not sure the correctness of the
2420 * partial hardware checksum assistance due to lack of data sheet.
2421 * In addition, the Rx feature of controller that requires copying
2422 * for every frames effectively nullifies one of most nice offload
2423 * capability of controller.
2426 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2433 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2434 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2435 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2437 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2438 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2439 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2440 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2441 m->m_pkthdr.csum_flags |=
2442 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2443 m->m_pkthdr.csum_data = 0xffff;
2446 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2447 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2448 p = mtod(m, char *);
2450 if ((status & ALE_RD_802_3) != 0)
2451 p += LLC_SNAPFRAMELEN;
2452 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2453 (status & ALE_RD_VLAN) != 0)
2454 p += ETHER_VLAN_ENCAP_LEN;
2455 ip = (struct ip *)p;
2456 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2458 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2460 m->m_pkthdr.csum_data = 0xffff;
2464 * Don't mark bad checksum for TCP/UDP frames
2465 * as fragmented frames may always have set
2466 * bad checksummed bit of frame status.
2470 /* Process received frames. */
2472 ale_rxeof(struct ale_softc *sc, int count)
2474 struct ale_rx_page *rx_page;
2478 uint32_t length, prod, seqno, status, vtags;
2482 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2483 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2484 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2485 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2488 * Don't directly access producer index as hardware may
2489 * update it while Rx handler is in progress. It would
2490 * be even better if there is a way to let hardware
2491 * know how far driver processed its received frames.
2492 * Alternatively, hardware could provide a way to disable
2493 * CMB updates until driver acknowledges the end of CMB
2496 prod = *rx_page->cmb_addr;
2497 for (prog = 0; prog < count; prog++) {
2498 if (rx_page->cons >= prod)
2500 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2501 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2502 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2504 * Normally I believe this should not happen unless
2505 * severe driver bug or corrupted memory. However
2506 * it seems to happen under certain conditions which
2507 * is triggered by abrupt Rx events such as initiation
2508 * of bulk transfer of remote host. It's not easy to
2509 * reproduce this and I doubt it could be related
2510 * with FIFO overflow of hardware or activity of Tx
2511 * CMB updates. I also remember similar behaviour
2512 * seen on RealTek 8139 which uses resembling Rx
2516 device_printf(sc->ale_dev,
2517 "garbled seq: %u, expected: %u -- "
2518 "resetting!\n", seqno,
2519 sc->ale_cdata.ale_rx_seqno);
2522 /* Frame received. */
2523 sc->ale_cdata.ale_rx_seqno++;
2524 length = ALE_RX_BYTES(le32toh(rs->length));
2525 status = le32toh(rs->flags);
2526 if ((status & ALE_RD_ERROR) != 0) {
2528 * We want to pass the following frames to upper
2529 * layer regardless of error status of Rx return
2532 * o IP/TCP/UDP checksum is bad.
2533 * o frame length and protocol specific length
2536 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2537 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2538 ALE_RD_TRUNC)) != 0) {
2539 ale_rx_update_page(sc, &rx_page, length, &prod);
2544 * m_devget(9) is major bottle-neck of ale(4)(It comes
2545 * from hardware limitation). For jumbo frames we could
2546 * get a slightly better performance if driver use
2547 * m_getjcl(9) with proper buffer size argument. However
2548 * that would make code more complicated and I don't
2549 * think users would expect good Rx performance numbers
2550 * on these low-end consumer ethernet controller.
2552 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2553 ETHER_ALIGN, ifp, NULL);
2556 ale_rx_update_page(sc, &rx_page, length, &prod);
2559 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2560 (status & ALE_RD_IPV4) != 0)
2561 ale_rxcsum(sc, m, status);
2562 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2563 (status & ALE_RD_VLAN) != 0) {
2564 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2565 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2566 m->m_flags |= M_VLANTAG;
2569 /* Pass it to upper layer. */
2571 (*ifp->if_input)(ifp, m);
2574 ale_rx_update_page(sc, &rx_page, length, &prod);
2577 return (count > 0 ? 0 : EAGAIN);
2583 struct ale_softc *sc;
2584 struct mii_data *mii;
2586 sc = (struct ale_softc *)arg;
2588 ALE_LOCK_ASSERT(sc);
2590 mii = device_get_softc(sc->ale_miibus);
2592 ale_stats_update(sc);
2594 * Reclaim Tx buffers that have been transferred. It's not
2595 * needed here but it would release allocated mbuf chains
2596 * faster and limit the maximum delay to a hz.
2600 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2604 ale_reset(struct ale_softc *sc)
2609 /* Initialize PCIe module. From Linux. */
2610 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2612 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2613 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2615 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2619 device_printf(sc->ale_dev, "master reset timeout!\n");
2621 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2622 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2628 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2634 struct ale_softc *sc;
2636 sc = (struct ale_softc *)xsc;
2638 ale_init_locked(sc);
2643 ale_init_locked(struct ale_softc *sc)
2646 struct mii_data *mii;
2647 uint8_t eaddr[ETHER_ADDR_LEN];
2649 uint32_t reg, rxf_hi, rxf_lo;
2651 ALE_LOCK_ASSERT(sc);
2654 mii = device_get_softc(sc->ale_miibus);
2656 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2659 * Cancel any pending I/O.
2663 * Reset the chip to a known state.
2666 /* Initialize Tx descriptors, DMA memory blocks. */
2667 ale_init_rx_pages(sc);
2668 ale_init_tx_ring(sc);
2670 /* Reprogram the station address. */
2671 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2672 CSR_WRITE_4(sc, ALE_PAR0,
2673 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2674 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2676 * Clear WOL status and disable all WOL feature as WOL
2677 * would interfere Rx operation under normal environments.
2679 CSR_READ_4(sc, ALE_WOL_CFG);
2680 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2682 * Set Tx descriptor/RXF0/CMB base addresses. They share
2683 * the same high address part of DMAable region.
2685 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2686 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2687 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2688 CSR_WRITE_4(sc, ALE_TPD_CNT,
2689 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2690 /* Set Rx page base address, note we use single queue. */
2691 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2692 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2693 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2694 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2695 /* Set Tx/Rx CMB addresses. */
2696 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2697 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2698 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2699 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2700 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2701 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2702 /* Mark RXF0 is valid. */
2703 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2704 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2706 * No need to initialize RFX1/RXF2/RXF3. We don't use
2710 /* Set Rx page size, excluding guard frame size. */
2711 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2712 /* Tell hardware that we're ready to load DMA blocks. */
2713 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2715 /* Set Rx/Tx interrupt trigger threshold. */
2716 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2717 (4 << INT_TRIG_TX_THRESH_SHIFT));
2720 * Set interrupt trigger timer, its purpose and relation
2721 * with interrupt moderation mechanism is not clear yet.
2723 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2724 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2725 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2727 /* Configure interrupt moderation timer. */
2728 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2729 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2730 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2731 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2732 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2733 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2734 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2735 reg |= MASTER_IM_RX_TIMER_ENB;
2736 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2737 reg |= MASTER_IM_TX_TIMER_ENB;
2738 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2739 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2741 /* Set Maximum frame size of controller. */
2742 if (ifp->if_mtu < ETHERMTU)
2743 sc->ale_max_frame_size = ETHERMTU;
2745 sc->ale_max_frame_size = ifp->if_mtu;
2746 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2748 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2749 /* Configure IPG/IFG parameters. */
2750 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2751 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2752 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2753 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2754 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2755 /* Set parameters for half-duplex media. */
2756 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2757 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2758 HDPX_CFG_LCOL_MASK) |
2759 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2760 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2761 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2762 HDPX_CFG_ABEBT_MASK) |
2763 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2764 HDPX_CFG_JAMIPG_MASK));
2766 /* Configure Tx jumbo frame parameters. */
2767 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2768 if (ifp->if_mtu < ETHERMTU)
2769 reg = sc->ale_max_frame_size;
2770 else if (ifp->if_mtu < 6 * 1024)
2771 reg = (sc->ale_max_frame_size * 2) / 3;
2773 reg = sc->ale_max_frame_size / 2;
2774 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2775 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2776 TX_JUMBO_THRESH_UNIT_SHIFT);
2778 /* Configure TxQ. */
2779 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2780 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2781 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2782 TXQ_CFG_TPD_BURST_MASK;
2783 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2785 /* Configure Rx jumbo frame & flow control parameters. */
2786 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2787 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2788 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2789 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2790 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2791 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2792 RX_JUMBO_LKAH_MASK));
2793 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2794 rxf_hi = (reg * 7) / 10;
2795 rxf_lo = (reg * 3)/ 10;
2796 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2797 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2798 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2799 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2800 RX_FIFO_PAUSE_THRESH_HI_MASK));
2804 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2805 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2807 /* Configure RxQ. */
2808 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2809 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2811 /* Configure DMA parameters. */
2813 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2814 reg |= DMA_CFG_TXCMB_ENB;
2815 CSR_WRITE_4(sc, ALE_DMA_CFG,
2816 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2817 sc->ale_dma_rd_burst | reg |
2818 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2819 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2820 DMA_CFG_RD_DELAY_CNT_MASK) |
2821 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2822 DMA_CFG_WR_DELAY_CNT_MASK));
2825 * Hardware can be configured to issue SMB interrupt based
2826 * on programmed interval. Since there is a callout that is
2827 * invoked for every hz in driver we use that instead of
2828 * relying on periodic SMB interrupt.
2830 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2831 /* Clear MAC statistics. */
2832 ale_stats_clear(sc);
2835 * Configure Tx/Rx MACs.
2836 * - Auto-padding for short frames.
2837 * - Enable CRC generation.
2838 * Actual reconfiguration of MAC for resolved speed/duplex
2839 * is followed after detection of link establishment.
2840 * AR81xx always does checksum computation regardless of
2841 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2842 * cause Rx handling issue for fragmented IP datagrams due
2845 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2846 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2847 MAC_CFG_PREAMBLE_MASK);
2848 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2849 reg |= MAC_CFG_SPEED_10_100;
2851 reg |= MAC_CFG_SPEED_1000;
2852 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2854 /* Set up the receive filter. */
2858 /* Acknowledge all pending interrupts and clear it. */
2859 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2860 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2861 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2863 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2864 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2866 sc->ale_flags &= ~ALE_FLAG_LINK;
2867 /* Switch to the current media. */
2870 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2874 ale_stop(struct ale_softc *sc)
2877 struct ale_txdesc *txd;
2881 ALE_LOCK_ASSERT(sc);
2883 * Mark the interface down and cancel the watchdog timer.
2886 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2887 sc->ale_flags &= ~ALE_FLAG_LINK;
2888 callout_stop(&sc->ale_tick_ch);
2889 sc->ale_watchdog_timer = 0;
2890 ale_stats_update(sc);
2891 /* Disable interrupts. */
2892 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2893 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2894 /* Disable queue processing and DMA. */
2895 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2896 reg &= ~TXQ_CFG_ENB;
2897 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2898 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2899 reg &= ~RXQ_CFG_ENB;
2900 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2901 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2902 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2903 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2905 /* Stop Rx/Tx MACs. */
2907 /* Disable interrupts which might be touched in taskq handler. */
2908 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2911 * Free TX mbufs still in the queues.
2913 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2914 txd = &sc->ale_cdata.ale_txdesc[i];
2915 if (txd->tx_m != NULL) {
2916 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2917 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2918 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2927 ale_stop_mac(struct ale_softc *sc)
2932 ALE_LOCK_ASSERT(sc);
2934 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2935 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2936 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2937 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2940 for (i = ALE_TIMEOUT; i > 0; i--) {
2941 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2947 device_printf(sc->ale_dev,
2948 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2952 ale_init_tx_ring(struct ale_softc *sc)
2954 struct ale_txdesc *txd;
2957 ALE_LOCK_ASSERT(sc);
2959 sc->ale_cdata.ale_tx_prod = 0;
2960 sc->ale_cdata.ale_tx_cons = 0;
2961 sc->ale_cdata.ale_tx_cnt = 0;
2963 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2964 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2965 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2966 txd = &sc->ale_cdata.ale_txdesc[i];
2969 *sc->ale_cdata.ale_tx_cmb = 0;
2970 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2971 sc->ale_cdata.ale_tx_cmb_map,
2972 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2973 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2974 sc->ale_cdata.ale_tx_ring_map,
2975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2979 ale_init_rx_pages(struct ale_softc *sc)
2981 struct ale_rx_page *rx_page;
2984 ALE_LOCK_ASSERT(sc);
2986 sc->ale_morework = 0;
2987 sc->ale_cdata.ale_rx_seqno = 0;
2988 sc->ale_cdata.ale_rx_curp = 0;
2990 for (i = 0; i < ALE_RX_PAGES; i++) {
2991 rx_page = &sc->ale_cdata.ale_rx_page[i];
2992 bzero(rx_page->page_addr, sc->ale_pagesize);
2993 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2995 *rx_page->cmb_addr = 0;
2996 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2998 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2999 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3004 ale_rxvlan(struct ale_softc *sc)
3009 ALE_LOCK_ASSERT(sc);
3012 reg = CSR_READ_4(sc, ALE_MAC_CFG);
3013 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3014 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3015 reg |= MAC_CFG_VLAN_TAG_STRIP;
3016 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3020 ale_rxfilter(struct ale_softc *sc)
3023 struct ifmultiaddr *ifma;
3028 ALE_LOCK_ASSERT(sc);
3032 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3033 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3034 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3035 rxcfg |= MAC_CFG_BCAST;
3036 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3037 if ((ifp->if_flags & IFF_PROMISC) != 0)
3038 rxcfg |= MAC_CFG_PROMISC;
3039 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3040 rxcfg |= MAC_CFG_ALLMULTI;
3041 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3042 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3043 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3047 /* Program new filter. */
3048 bzero(mchash, sizeof(mchash));
3050 if_maddr_rlock(ifp);
3051 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) {
3052 if (ifma->ifma_addr->sa_family != AF_LINK)
3054 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3055 ifma->ifma_addr), ETHER_ADDR_LEN);
3056 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3058 if_maddr_runlock(ifp);
3060 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3061 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3062 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3066 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3072 value = *(int *)arg1;
3073 error = sysctl_handle_int(oidp, &value, 0, req);
3074 if (error || req->newptr == NULL)
3076 if (value < low || value > high)
3078 *(int *)arg1 = value;
3084 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3086 return (sysctl_int_range(oidp, arg1, arg2, req,
3087 ALE_PROC_MIN, ALE_PROC_MAX));
3091 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3094 return (sysctl_int_range(oidp, arg1, arg2, req,
3095 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));