2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
36 #include <sys/socket.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/queue.h>
41 #include <sys/taskqueue.h>
43 #include <sys/sglist.h>
44 #include <sys/sysctl.h>
46 #include <sys/counter.h>
48 #include <net/ethernet.h>
50 #include <net/if_vlan_var.h>
51 #include <netinet/in.h>
52 #include <netinet/ip.h>
53 #include <netinet/ip6.h>
54 #include <netinet/tcp.h>
55 #include <machine/in_cksum.h>
56 #include <machine/md_var.h>
60 #include <machine/bus.h>
61 #include <sys/selinfo.h>
62 #include <net/if_var.h>
63 #include <net/netmap.h>
64 #include <dev/netmap/netmap_kern.h>
67 #include "common/common.h"
68 #include "common/t4_regs.h"
69 #include "common/t4_regs_values.h"
70 #include "common/t4_msg.h"
72 #include "t4_mp_ring.h"
74 #ifdef T4_PKT_TIMESTAMP
75 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
77 #define RX_COPY_THRESHOLD MINCLSIZE
81 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
82 * 0-7 are valid values.
84 static int fl_pktshift = 2;
85 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
88 * Pad ethernet payload up to this boundary.
89 * -1: driver should figure out a good value.
91 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
94 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
98 * -1: driver should figure out a good value.
99 * 64 or 128 are the only other valid values.
101 static int spg_len = -1;
102 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
106 * -1: no congestion feedback (not recommended).
107 * 0: backpressure the channel instead of dropping packets right away.
108 * 1: no backpressure, drop packets for the congested queue immediately.
110 static int cong_drop = 0;
111 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
114 * Deliver multiple frames in the same free list buffer if they fit.
115 * -1: let the driver decide whether to enable buffer packing or not.
116 * 0: disable buffer packing.
117 * 1: enable buffer packing.
119 static int buffer_packing = -1;
120 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
123 * Start next frame in a packed buffer at this boundary.
124 * -1: driver should figure out a good value.
125 * T4: driver will ignore this and use the same value as fl_pad above.
126 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
128 static int fl_pack = -1;
129 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
132 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
133 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
134 * 1: ok to create mbuf(s) within a cluster if there is room.
136 static int allow_mbufs_in_cluster = 1;
137 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
140 * Largest rx cluster size that the driver is allowed to allocate.
142 static int largest_rx_cluster = MJUM16BYTES;
143 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
146 * Size of cluster allocation that's most likely to succeed. The driver will
147 * fall back to this size if it fails to allocate clusters larger than this.
149 static int safest_rx_cluster = PAGE_SIZE;
150 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
153 * The interrupt holdoff timers are multiplied by this value on T6+.
154 * 1 and 3-17 (both inclusive) are legal values.
156 static int tscale = 1;
157 TUNABLE_INT("hw.cxgbe.tscale", &tscale);
160 u_int wr_type; /* type 0 or type 1 */
161 u_int npkt; /* # of packets in this work request */
162 u_int plen; /* total payload (sum of all packets) */
163 u_int len16; /* # of 16B pieces used by this work request */
166 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
169 struct sglist_seg seg[TX_SGL_SEGS];
172 static int service_iq(struct sge_iq *, int);
173 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
174 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
175 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
176 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
177 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
179 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
180 bus_addr_t *, void **);
181 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
183 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
185 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
186 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
187 struct sysctl_oid *, struct sge_fl *);
188 static int alloc_fwq(struct adapter *);
189 static int free_fwq(struct adapter *);
190 static int alloc_mgmtq(struct adapter *);
191 static int free_mgmtq(struct adapter *);
192 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
193 struct sysctl_oid *);
194 static int free_rxq(struct vi_info *, struct sge_rxq *);
196 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
197 struct sysctl_oid *);
198 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
201 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
202 struct sysctl_oid *);
203 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
204 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
205 struct sysctl_oid *);
206 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
208 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
209 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
211 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
213 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
214 static int free_eq(struct adapter *, struct sge_eq *);
215 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
216 struct sysctl_oid *);
217 static int free_wrq(struct adapter *, struct sge_wrq *);
218 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
219 struct sysctl_oid *);
220 static int free_txq(struct vi_info *, struct sge_txq *);
221 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
222 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
223 static int refill_fl(struct adapter *, struct sge_fl *, int);
224 static void refill_sfl(void *);
225 static int alloc_fl_sdesc(struct sge_fl *);
226 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
227 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
228 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
229 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
231 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
232 static inline u_int txpkt_len16(u_int, u_int);
233 static inline u_int txpkt_vm_len16(u_int, u_int);
234 static inline u_int txpkts0_len16(u_int);
235 static inline u_int txpkts1_len16(void);
236 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
237 struct mbuf *, u_int);
238 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
239 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
240 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
241 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
242 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
243 struct mbuf *, const struct txpkts *, u_int);
244 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
245 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
246 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
247 static inline uint16_t read_hw_cidx(struct sge_eq *);
248 static inline u_int reclaimable_tx_desc(struct sge_eq *);
249 static inline u_int total_available_tx_desc(struct sge_eq *);
250 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
251 static void tx_reclaim(void *, int);
252 static __be64 get_flit(struct sglist_seg *, int, int);
253 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
255 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
257 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
258 static void wrq_tx_drain(void *, int);
259 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
261 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
262 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
263 static int sysctl_tc(SYSCTL_HANDLER_ARGS);
265 static counter_u64_t extfree_refs;
266 static counter_u64_t extfree_rels;
268 an_handler_t t4_an_handler;
269 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
270 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
274 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
278 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
280 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
287 t4_register_an_handler(an_handler_t h)
291 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
292 loc = (uintptr_t *) &t4_an_handler;
293 atomic_store_rel_ptr(loc, new);
299 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
301 const struct cpl_fw6_msg *cpl =
302 __containerof(rpl, struct cpl_fw6_msg, data[0]);
305 panic("%s: fw_msg type %d", __func__, cpl->type);
307 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
313 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
317 if (type >= nitems(t4_fw_msg_handler))
321 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
322 * handler dispatch table. Reject any attempt to install a handler for
325 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
328 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
329 loc = (uintptr_t *) &t4_fw_msg_handler[type];
330 atomic_store_rel_ptr(loc, new);
336 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
340 panic("%s: opcode 0x%02x on iq %p with payload %p",
341 __func__, rss->opcode, iq, m);
343 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
344 __func__, rss->opcode, iq, m);
351 t4_register_cpl_handler(int opcode, cpl_handler_t h)
355 if (opcode >= nitems(t4_cpl_handler))
358 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
359 loc = (uintptr_t *) &t4_cpl_handler[opcode];
360 atomic_store_rel_ptr(loc, new);
366 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
373 if (fl_pktshift < 0 || fl_pktshift > 7) {
374 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
375 " using 2 instead.\n", fl_pktshift);
379 if (spg_len != 64 && spg_len != 128) {
382 #if defined(__i386__) || defined(__amd64__)
383 len = cpu_clflush_line_size > 64 ? 128 : 64;
388 printf("Invalid hw.cxgbe.spg_len value (%d),"
389 " using %d instead.\n", spg_len, len);
394 if (cong_drop < -1 || cong_drop > 1) {
395 printf("Invalid hw.cxgbe.cong_drop value (%d),"
396 " using 0 instead.\n", cong_drop);
400 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
401 printf("Invalid hw.cxgbe.tscale value (%d),"
402 " using 1 instead.\n", tscale);
406 extfree_refs = counter_u64_alloc(M_WAITOK);
407 extfree_rels = counter_u64_alloc(M_WAITOK);
408 counter_u64_zero(extfree_refs);
409 counter_u64_zero(extfree_rels);
411 t4_an_handler = an_not_handled;
412 for (i = 0; i < nitems(t4_fw_msg_handler); i++)
413 t4_fw_msg_handler[i] = fw_msg_not_handled;
414 for (i = 0; i < nitems(t4_cpl_handler); i++)
415 t4_cpl_handler[i] = cpl_not_handled;
417 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
418 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
419 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
420 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
421 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
422 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
426 t4_sge_modunload(void)
429 counter_u64_free(extfree_refs);
430 counter_u64_free(extfree_rels);
434 t4_sge_extfree_refs(void)
438 rels = counter_u64_fetch(extfree_rels);
439 refs = counter_u64_fetch(extfree_refs);
441 return (refs - rels);
445 setup_pad_and_pack_boundaries(struct adapter *sc)
448 int pad, pack, pad_shift;
450 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
451 X_INGPADBOUNDARY_SHIFT;
453 if (fl_pad < (1 << pad_shift) ||
454 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
457 * If there is any chance that we might use buffer packing and
458 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
459 * it to the minimum allowed in all other cases.
461 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
464 * For fl_pad = 0 we'll still write a reasonable value to the
465 * register but all the freelists will opt out of padding.
466 * We'll complain here only if the user tried to set it to a
467 * value greater than 0 that was invalid.
470 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
471 " (%d), using %d instead.\n", fl_pad, pad);
474 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
475 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
476 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
479 if (fl_pack != -1 && fl_pack != pad) {
480 /* Complain but carry on. */
481 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
482 " using %d instead.\n", fl_pack, pad);
488 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
489 !powerof2(fl_pack)) {
490 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
491 MPASS(powerof2(pack));
499 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
500 " (%d), using %d instead.\n", fl_pack, pack);
503 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
505 v = V_INGPACKBOUNDARY(0);
507 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
509 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
510 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
514 * adap->params.vpd.cclk must be set up before this is called.
517 t4_tweak_chip_settings(struct adapter *sc)
521 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
522 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
523 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
524 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
525 static int sge_flbuf_sizes[] = {
527 #if MJUMPAGESIZE != MCLBYTES
529 MJUMPAGESIZE - CL_METADATA_SIZE,
530 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
534 MCLBYTES - MSIZE - CL_METADATA_SIZE,
535 MJUM9BYTES - CL_METADATA_SIZE,
536 MJUM16BYTES - CL_METADATA_SIZE,
539 KASSERT(sc->flags & MASTER_PF,
540 ("%s: trying to change chip settings when not master.", __func__));
542 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
543 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
544 V_EGRSTATUSPAGESIZE(spg_len == 128);
545 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
547 setup_pad_and_pack_boundaries(sc);
549 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
550 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
551 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
552 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
553 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
554 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
555 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
556 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
557 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
559 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
560 ("%s: hw buffer size table too big", __func__));
561 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
562 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
566 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
567 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
568 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
570 KASSERT(intr_timer[0] <= timer_max,
571 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
573 for (i = 1; i < nitems(intr_timer); i++) {
574 KASSERT(intr_timer[i] >= intr_timer[i - 1],
575 ("%s: timers not listed in increasing order (%d)",
578 while (intr_timer[i] > timer_max) {
579 if (i == nitems(intr_timer) - 1) {
580 intr_timer[i] = timer_max;
583 intr_timer[i] += intr_timer[i - 1];
588 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
589 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
590 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
591 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
592 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
593 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
594 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
595 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
596 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
598 if (chip_id(sc) >= CHELSIO_T6) {
599 m = V_TSCALE(M_TSCALE);
603 v = V_TSCALE(tscale - 2);
604 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
607 /* 4K, 16K, 64K, 256K DDP "page sizes" */
608 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
609 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
611 m = v = F_TDDPTAGTCB;
612 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
614 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
616 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
617 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
621 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
622 * padding is in use, the buffer's start and end need to be aligned to the pad
623 * boundary as well. We'll just make sure that the size is a multiple of the
624 * boundary here, it is up to the buffer allocation code to make sure the start
625 * of the buffer is aligned as well.
628 hwsz_ok(struct adapter *sc, int hwsz)
630 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
632 return (hwsz >= 64 && (hwsz & mask) == 0);
636 * XXX: driver really should be able to deal with unexpected settings.
639 t4_read_chip_settings(struct adapter *sc)
641 struct sge *s = &sc->sge;
642 struct sge_params *sp = &sc->params.sge;
645 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
646 static int sw_buf_sizes[] = { /* Sorted by size */
648 #if MJUMPAGESIZE != MCLBYTES
654 struct sw_zone_info *swz, *safe_swz;
655 struct hw_buf_info *hwb;
659 r = sc->params.sge.sge_control;
661 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
666 * If this changes then every single use of PAGE_SHIFT in the driver
667 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
669 if (sp->page_shift != PAGE_SHIFT) {
670 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
674 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
675 hwb = &s->hw_buf_info[0];
676 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
677 r = sc->params.sge.sge_fl_buffer_size[i];
679 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
684 * Create a sorted list in decreasing order of hw buffer sizes (and so
685 * increasing order of spare area) for each software zone.
687 * If padding is enabled then the start and end of the buffer must align
688 * to the pad boundary; if packing is enabled then they must align with
689 * the pack boundary as well. Allocations from the cluster zones are
690 * aligned to min(size, 4K), so the buffer starts at that alignment and
691 * ends at hwb->size alignment. If mbuf inlining is allowed the
692 * starting alignment will be reduced to MSIZE and the driver will
693 * exercise appropriate caution when deciding on the best buffer layout
696 n = 0; /* no usable buffer size to begin with */
697 swz = &s->sw_zone_info[0];
699 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
700 int8_t head = -1, tail = -1;
702 swz->size = sw_buf_sizes[i];
703 swz->zone = m_getzone(swz->size);
704 swz->type = m_gettype(swz->size);
706 if (swz->size < PAGE_SIZE) {
707 MPASS(powerof2(swz->size));
708 if (fl_pad && (swz->size % sp->pad_boundary != 0))
712 if (swz->size == safest_rx_cluster)
715 hwb = &s->hw_buf_info[0];
716 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
717 if (hwb->zidx != -1 || hwb->size > swz->size)
721 MPASS(hwb->size % sp->pad_boundary == 0);
726 else if (hwb->size < s->hw_buf_info[tail].size) {
727 s->hw_buf_info[tail].next = j;
731 struct hw_buf_info *t;
733 for (cur = &head; *cur != -1; cur = &t->next) {
734 t = &s->hw_buf_info[*cur];
735 if (hwb->size == t->size) {
739 if (hwb->size > t->size) {
747 swz->head_hwidx = head;
748 swz->tail_hwidx = tail;
752 if (swz->size - s->hw_buf_info[tail].size >=
754 sc->flags |= BUF_PACKING_OK;
758 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
764 if (safe_swz != NULL) {
765 s->safe_hwidx1 = safe_swz->head_hwidx;
766 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
769 hwb = &s->hw_buf_info[i];
772 MPASS(hwb->size % sp->pad_boundary == 0);
774 spare = safe_swz->size - hwb->size;
775 if (spare >= CL_METADATA_SIZE) {
782 if (sc->flags & IS_VF)
785 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
786 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
788 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
792 m = v = F_TDDPTAGTCB;
793 r = t4_read_reg(sc, A_ULP_RX_CTL);
795 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
799 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
801 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
802 r = t4_read_reg(sc, A_TP_PARA_REG5);
804 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
808 t4_init_tp_params(sc, 1);
810 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
811 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
817 t4_create_dma_tag(struct adapter *sc)
821 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
822 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
823 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
826 device_printf(sc->dev,
827 "failed to create main DMA tag: %d\n", rc);
834 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
835 struct sysctl_oid_list *children)
837 struct sge_params *sp = &sc->params.sge;
839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
840 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
841 "freelist buffer sizes");
843 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
844 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
846 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
847 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
849 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
850 NULL, sp->spg_len, "status page size (bytes)");
852 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
853 NULL, cong_drop, "congestion drop setting");
855 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
856 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
860 t4_destroy_dma_tag(struct adapter *sc)
863 bus_dma_tag_destroy(sc->dmat);
869 * Allocate and initialize the firmware event queue and the management queue.
871 * Returns errno on failure. Resources allocated up to that point may still be
872 * allocated. Caller is responsible for cleanup in case this function fails.
875 t4_setup_adapter_queues(struct adapter *sc)
879 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
881 sysctl_ctx_init(&sc->ctx);
882 sc->flags |= ADAP_SYSCTL_CTX;
885 * Firmware event queue
892 * Management queue. This is just a control queue that uses the fwq as
895 if (!(sc->flags & IS_VF))
896 rc = alloc_mgmtq(sc);
905 t4_teardown_adapter_queues(struct adapter *sc)
908 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
910 /* Do this before freeing the queue */
911 if (sc->flags & ADAP_SYSCTL_CTX) {
912 sysctl_ctx_free(&sc->ctx);
913 sc->flags &= ~ADAP_SYSCTL_CTX;
923 first_vector(struct vi_info *vi)
925 struct adapter *sc = vi->pi->adapter;
927 if (sc->intr_count == 1)
930 return (vi->first_intr);
934 * Given an arbitrary "index," come up with an iq that can be used by other
935 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
936 * The iq returned is guaranteed to be something that takes direct interrupts.
938 static struct sge_iq *
939 vi_intr_iq(struct vi_info *vi, int idx)
941 struct adapter *sc = vi->pi->adapter;
942 struct sge *s = &sc->sge;
943 struct sge_iq *iq = NULL;
946 if (sc->intr_count == 1)
947 return (&sc->sge.fwq);
951 /* Do not consider any netmap-only interrupts */
952 if (vi->flags & INTR_RXQ && vi->nnmrxq > vi->nrxq)
953 nintr -= vi->nnmrxq - vi->nrxq;
956 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
957 __func__, vi, sc->intr_count));
960 if (vi->flags & INTR_RXQ) {
962 iq = &s->rxq[vi->first_rxq + i].iq;
968 if (vi->flags & INTR_OFLD_RXQ) {
969 if (i < vi->nofldrxq) {
970 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
976 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
977 vi, vi->flags & INTR_ALL, idx, nintr);
980 KASSERT(iq->flags & IQ_INTR,
981 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
982 vi->flags & INTR_ALL, idx));
986 /* Maximum payload that can be delivered with a single iq descriptor */
988 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
994 payload = sc->tt.rx_coalesce ?
995 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
998 /* large enough even when hw VLAN extraction is disabled */
999 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1000 ETHER_VLAN_ENCAP_LEN + mtu;
1009 t4_setup_vi_queues(struct vi_info *vi)
1011 int rc = 0, i, j, intr_idx, iqid;
1012 struct sge_rxq *rxq;
1013 struct sge_txq *txq;
1014 struct sge_wrq *ctrlq;
1016 struct sge_ofld_rxq *ofld_rxq;
1017 struct sge_wrq *ofld_txq;
1021 struct sge_nm_rxq *nm_rxq;
1022 struct sge_nm_txq *nm_txq;
1025 struct port_info *pi = vi->pi;
1026 struct adapter *sc = pi->adapter;
1027 struct ifnet *ifp = vi->ifp;
1028 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1029 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1030 int maxp, mtu = ifp->if_mtu;
1032 /* Interrupt vector to start from (when using multiple vectors) */
1033 intr_idx = first_vector(vi);
1036 saved_idx = intr_idx;
1037 if (ifp->if_capabilities & IFCAP_NETMAP) {
1039 /* netmap is supported with direct interrupts only. */
1040 MPASS(vi->flags & INTR_RXQ);
1043 * We don't have buffers to back the netmap rx queues
1044 * right now so we create the queues in a way that
1045 * doesn't set off any congestion signal in the chip.
1047 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1048 CTLFLAG_RD, NULL, "rx queues");
1049 for_each_nm_rxq(vi, i, nm_rxq) {
1050 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1056 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1057 CTLFLAG_RD, NULL, "tx queues");
1058 for_each_nm_txq(vi, i, nm_txq) {
1059 iqid = vi->first_nm_rxq + (i % vi->nnmrxq);
1060 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
1066 /* Normal rx queues and netmap rx queues share the same interrupts. */
1067 intr_idx = saved_idx;
1071 * First pass over all NIC and TOE rx queues:
1072 * a) initialize iq and fl
1073 * b) allocate queue iff it will take direct interrupts.
1075 maxp = mtu_to_max_payload(sc, mtu, 0);
1076 if (vi->flags & INTR_RXQ) {
1077 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1078 CTLFLAG_RD, NULL, "rx queues");
1080 for_each_rxq(vi, i, rxq) {
1082 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1084 snprintf(name, sizeof(name), "%s rxq%d-fl",
1085 device_get_nameunit(vi->dev), i);
1086 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1088 if (vi->flags & INTR_RXQ) {
1089 rxq->iq.flags |= IQ_INTR;
1090 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1097 if (ifp->if_capabilities & IFCAP_NETMAP)
1098 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1101 maxp = mtu_to_max_payload(sc, mtu, 1);
1102 if (vi->flags & INTR_OFLD_RXQ) {
1103 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1105 "rx queues for offloaded TCP connections");
1107 for_each_ofld_rxq(vi, i, ofld_rxq) {
1109 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx,
1112 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1113 device_get_nameunit(vi->dev), i);
1114 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1116 if (vi->flags & INTR_OFLD_RXQ) {
1117 ofld_rxq->iq.flags |= IQ_INTR;
1118 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1127 * Second pass over all NIC and TOE rx queues. The queues forwarding
1128 * their interrupts are allocated now.
1131 if (!(vi->flags & INTR_RXQ)) {
1132 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1133 CTLFLAG_RD, NULL, "rx queues");
1134 for_each_rxq(vi, i, rxq) {
1135 MPASS(!(rxq->iq.flags & IQ_INTR));
1137 intr_idx = vi_intr_iq(vi, j)->abs_id;
1139 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1146 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
1147 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1149 "rx queues for offloaded TCP connections");
1150 for_each_ofld_rxq(vi, i, ofld_rxq) {
1151 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1153 intr_idx = vi_intr_iq(vi, j)->abs_id;
1155 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1164 * Now the tx queues. Only one pass needed.
1166 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1169 for_each_txq(vi, i, txq) {
1170 iqid = vi_intr_iq(vi, j)->cntxt_id;
1171 snprintf(name, sizeof(name), "%s txq%d",
1172 device_get_nameunit(vi->dev), i);
1173 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1176 rc = alloc_txq(vi, txq, i, oid);
1182 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1183 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1184 for_each_ofld_txq(vi, i, ofld_txq) {
1185 struct sysctl_oid *oid2;
1187 iqid = vi_intr_iq(vi, j)->cntxt_id;
1188 snprintf(name, sizeof(name), "%s ofld_txq%d",
1189 device_get_nameunit(vi->dev), i);
1190 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1193 snprintf(name, sizeof(name), "%d", i);
1194 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1195 name, CTLFLAG_RD, NULL, "offload tx queue");
1197 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1205 * Finally, the control queue.
1207 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF)
1209 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1210 NULL, "ctrl queue");
1211 ctrlq = &sc->sge.ctrlq[pi->port_id];
1212 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1213 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1214 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1216 rc = alloc_wrq(sc, vi, ctrlq, oid);
1220 t4_teardown_vi_queues(vi);
1229 t4_teardown_vi_queues(struct vi_info *vi)
1232 struct port_info *pi = vi->pi;
1233 struct adapter *sc = pi->adapter;
1234 struct sge_rxq *rxq;
1235 struct sge_txq *txq;
1237 struct sge_ofld_rxq *ofld_rxq;
1238 struct sge_wrq *ofld_txq;
1241 struct sge_nm_rxq *nm_rxq;
1242 struct sge_nm_txq *nm_txq;
1245 /* Do this before freeing the queues */
1246 if (vi->flags & VI_SYSCTL_CTX) {
1247 sysctl_ctx_free(&vi->ctx);
1248 vi->flags &= ~VI_SYSCTL_CTX;
1252 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1253 for_each_nm_txq(vi, i, nm_txq) {
1254 free_nm_txq(vi, nm_txq);
1257 for_each_nm_rxq(vi, i, nm_rxq) {
1258 free_nm_rxq(vi, nm_rxq);
1264 * Take down all the tx queues first, as they reference the rx queues
1265 * (for egress updates, etc.).
1268 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
1269 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1271 for_each_txq(vi, i, txq) {
1275 for_each_ofld_txq(vi, i, ofld_txq) {
1276 free_wrq(sc, ofld_txq);
1281 * Then take down the rx queues that forward their interrupts, as they
1282 * reference other rx queues.
1285 for_each_rxq(vi, i, rxq) {
1286 if ((rxq->iq.flags & IQ_INTR) == 0)
1290 for_each_ofld_rxq(vi, i, ofld_rxq) {
1291 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1292 free_ofld_rxq(vi, ofld_rxq);
1297 * Then take down the rx queues that take direct interrupts.
1300 for_each_rxq(vi, i, rxq) {
1301 if (rxq->iq.flags & IQ_INTR)
1305 for_each_ofld_rxq(vi, i, ofld_rxq) {
1306 if (ofld_rxq->iq.flags & IQ_INTR)
1307 free_ofld_rxq(vi, ofld_rxq);
1315 * Deals with errors and the firmware event queue. All data rx queues forward
1316 * their interrupt to the firmware event queue.
1319 t4_intr_all(void *arg)
1321 struct adapter *sc = arg;
1322 struct sge_iq *fwq = &sc->sge.fwq;
1325 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1327 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1331 /* Deals with error interrupts */
1333 t4_intr_err(void *arg)
1335 struct adapter *sc = arg;
1337 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1338 t4_slow_intr_handler(sc);
1342 t4_intr_evt(void *arg)
1344 struct sge_iq *iq = arg;
1346 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1348 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1355 struct sge_iq *iq = arg;
1357 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1359 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1364 t4_vi_intr(void *arg)
1366 struct irq *irq = arg;
1369 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) {
1370 t4_nm_intr(irq->nm_rxq);
1371 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON);
1374 if (irq->rxq != NULL)
1379 * Deals with anything and everything on the given ingress queue.
1382 service_iq(struct sge_iq *iq, int budget)
1385 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1386 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1387 struct adapter *sc = iq->adapter;
1388 struct iq_desc *d = &iq->desc[iq->cidx];
1389 int ndescs = 0, limit;
1390 int rsp_type, refill;
1392 uint16_t fl_hw_cidx;
1394 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1395 #if defined(INET) || defined(INET6)
1396 const struct timeval lro_timeout = {0, sc->lro_timeout};
1399 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1401 limit = budget ? budget : iq->qsize / 16;
1403 if (iq->flags & IQ_HAS_FL) {
1405 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1408 fl_hw_cidx = 0; /* to silence gcc warning */
1412 * We always come back and check the descriptor ring for new indirect
1413 * interrupts and other responses after running a single handler.
1416 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1422 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1423 lq = be32toh(d->rsp.pldbuflen_qid);
1426 case X_RSPD_TYPE_FLBUF:
1428 KASSERT(iq->flags & IQ_HAS_FL,
1429 ("%s: data for an iq (%p) with no freelist",
1432 m0 = get_fl_payload(sc, fl, lq);
1433 if (__predict_false(m0 == NULL))
1435 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1436 #ifdef T4_PKT_TIMESTAMP
1438 * 60 bit timestamp for the payload is
1439 * *(uint64_t *)m0->m_pktdat. Note that it is
1440 * in the leading free-space in the mbuf. The
1441 * kernel can clobber it during a pullup,
1442 * m_copymdata, etc. You need to make sure that
1443 * the mbuf reaches you unmolested if you care
1444 * about the timestamp.
1446 *(uint64_t *)m0->m_pktdat =
1447 be64toh(ctrl->u.last_flit) &
1453 case X_RSPD_TYPE_CPL:
1454 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1455 ("%s: bad opcode %02x.", __func__,
1457 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1460 case X_RSPD_TYPE_INTR:
1463 * Interrupts should be forwarded only to queues
1464 * that are not forwarding their interrupts.
1465 * This means service_iq can recurse but only 1
1468 KASSERT(budget == 0,
1469 ("%s: budget %u, rsp_type %u", __func__,
1473 * There are 1K interrupt-capable queues (qids 0
1474 * through 1023). A response type indicating a
1475 * forwarded interrupt with a qid >= 1K is an
1476 * iWARP async notification.
1479 t4_an_handler(iq, &d->rsp);
1483 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1485 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1487 if (service_iq(q, q->qsize / 16) == 0) {
1488 atomic_cmpset_int(&q->state,
1489 IQS_BUSY, IQS_IDLE);
1491 STAILQ_INSERT_TAIL(&iql, q,
1499 ("%s: illegal response type %d on iq %p",
1500 __func__, rsp_type, iq));
1502 "%s: illegal response type %d on iq %p",
1503 device_get_nameunit(sc->dev), rsp_type, iq);
1508 if (__predict_false(++iq->cidx == iq->sidx)) {
1510 iq->gen ^= F_RSPD_GEN;
1513 if (__predict_false(++ndescs == limit)) {
1514 t4_write_reg(sc, sc->sge_gts_reg,
1516 V_INGRESSQID(iq->cntxt_id) |
1517 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1520 #if defined(INET) || defined(INET6)
1521 if (iq->flags & IQ_LRO_ENABLED &&
1522 sc->lro_timeout != 0) {
1523 tcp_lro_flush_inactive(&rxq->lro,
1529 if (iq->flags & IQ_HAS_FL) {
1531 refill_fl(sc, fl, 32);
1534 return (EINPROGRESS);
1539 refill_fl(sc, fl, 32);
1541 fl_hw_cidx = fl->hw_cidx;
1546 if (STAILQ_EMPTY(&iql))
1550 * Process the head only, and send it to the back of the list if
1551 * it's still not done.
1553 q = STAILQ_FIRST(&iql);
1554 STAILQ_REMOVE_HEAD(&iql, link);
1555 if (service_iq(q, q->qsize / 8) == 0)
1556 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1558 STAILQ_INSERT_TAIL(&iql, q, link);
1561 #if defined(INET) || defined(INET6)
1562 if (iq->flags & IQ_LRO_ENABLED) {
1563 struct lro_ctrl *lro = &rxq->lro;
1564 struct lro_entry *l;
1566 while (!SLIST_EMPTY(&lro->lro_active)) {
1567 l = SLIST_FIRST(&lro->lro_active);
1568 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1569 tcp_lro_flush(lro, l);
1574 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1575 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1577 if (iq->flags & IQ_HAS_FL) {
1581 starved = refill_fl(sc, fl, 64);
1583 if (__predict_false(starved != 0))
1584 add_fl_to_sfl(sc, fl);
1591 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1593 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1596 MPASS(cll->region3 >= CL_METADATA_SIZE);
1601 static inline struct cluster_metadata *
1602 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1606 if (cl_has_metadata(fl, cll)) {
1607 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1609 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1615 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1617 uma_zone_t zone = arg1;
1620 uma_zfree(zone, cl);
1621 counter_u64_add(extfree_rels, 1);
1623 return (EXT_FREE_OK);
1627 * The mbuf returned by this function could be allocated from zone_mbuf or
1628 * constructed in spare room in the cluster.
1630 * The mbuf carries the payload in one of these ways
1631 * a) frame inside the mbuf (mbuf from zone_mbuf)
1632 * b) m_cljset (for clusters without metadata) zone_mbuf
1633 * c) m_extaddref (cluster with metadata) inline mbuf
1634 * d) m_extaddref (cluster with metadata) zone_mbuf
1636 static struct mbuf *
1637 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1641 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1642 struct cluster_layout *cll = &sd->cll;
1643 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1644 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1645 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1649 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1650 len = min(remaining, blen);
1651 payload = sd->cl + cll->region1 + fl->rx_offset;
1652 if (fl->flags & FL_BUF_PACKING) {
1653 const u_int l = fr_offset + len;
1654 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1656 if (fl->rx_offset + len + pad < hwb->size)
1658 MPASS(fl->rx_offset + blen <= hwb->size);
1660 MPASS(fl->rx_offset == 0); /* not packing */
1664 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1667 * Copy payload into a freshly allocated mbuf.
1670 m = fr_offset == 0 ?
1671 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1674 fl->mbuf_allocated++;
1675 #ifdef T4_PKT_TIMESTAMP
1676 /* Leave room for a timestamp */
1679 /* copy data to mbuf */
1680 bcopy(payload, mtod(m, caddr_t), len);
1682 } else if (sd->nmbuf * MSIZE < cll->region1) {
1685 * There's spare room in the cluster for an mbuf. Create one
1686 * and associate it with the payload that's in the cluster.
1690 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1691 /* No bzero required */
1692 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA,
1693 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1696 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1698 if (sd->nmbuf++ == 0)
1699 counter_u64_add(extfree_refs, 1);
1704 * Grab an mbuf from zone_mbuf and associate it with the
1705 * payload in the cluster.
1708 m = fr_offset == 0 ?
1709 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1712 fl->mbuf_allocated++;
1714 m_extaddref(m, payload, blen, &clm->refcount,
1715 rxb_free, swz->zone, sd->cl);
1716 if (sd->nmbuf++ == 0)
1717 counter_u64_add(extfree_refs, 1);
1719 m_cljset(m, sd->cl, swz->type);
1720 sd->cl = NULL; /* consumed, not a recycle candidate */
1724 m->m_pkthdr.len = remaining;
1727 if (fl->flags & FL_BUF_PACKING) {
1728 fl->rx_offset += blen;
1729 MPASS(fl->rx_offset <= hwb->size);
1730 if (fl->rx_offset < hwb->size)
1731 return (m); /* without advancing the cidx */
1734 if (__predict_false(++fl->cidx % 8 == 0)) {
1735 uint16_t cidx = fl->cidx / 8;
1737 if (__predict_false(cidx == fl->sidx))
1738 fl->cidx = cidx = 0;
1746 static struct mbuf *
1747 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1749 struct mbuf *m0, *m, **pnext;
1751 const u_int total = G_RSPD_LEN(len_newbuf);
1753 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1754 M_ASSERTPKTHDR(fl->m0);
1755 MPASS(fl->m0->m_pkthdr.len == total);
1756 MPASS(fl->remaining < total);
1760 remaining = fl->remaining;
1761 fl->flags &= ~FL_BUF_RESUME;
1765 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1767 if (__predict_false(++fl->cidx % 8 == 0)) {
1768 uint16_t cidx = fl->cidx / 8;
1770 if (__predict_false(cidx == fl->sidx))
1771 fl->cidx = cidx = 0;
1777 * Payload starts at rx_offset in the current hw buffer. Its length is
1778 * 'len' and it may span multiple hw buffers.
1781 m0 = get_scatter_segment(sc, fl, 0, total);
1784 remaining = total - m0->m_len;
1785 pnext = &m0->m_next;
1786 while (remaining > 0) {
1788 MPASS(fl->rx_offset == 0);
1789 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1790 if (__predict_false(m == NULL)) {
1793 fl->remaining = remaining;
1794 fl->flags |= FL_BUF_RESUME;
1799 remaining -= m->m_len;
1808 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1810 struct sge_rxq *rxq = iq_to_rxq(iq);
1811 struct ifnet *ifp = rxq->ifp;
1812 struct adapter *sc = iq->adapter;
1813 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1814 #if defined(INET) || defined(INET6)
1815 struct lro_ctrl *lro = &rxq->lro;
1818 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1821 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1822 m0->m_len -= sc->params.sge.fl_pktshift;
1823 m0->m_data += sc->params.sge.fl_pktshift;
1825 m0->m_pkthdr.rcvif = ifp;
1826 M_HASHTYPE_SET(m0, M_HASHTYPE_OPAQUE);
1827 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1829 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
1830 if (ifp->if_capenable & IFCAP_RXCSUM &&
1831 cpl->l2info & htobe32(F_RXF_IP)) {
1832 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1833 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1835 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1836 cpl->l2info & htobe32(F_RXF_IP6)) {
1837 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1842 if (__predict_false(cpl->ip_frag))
1843 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1845 m0->m_pkthdr.csum_data = 0xffff;
1849 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1850 m0->m_flags |= M_VLANTAG;
1851 rxq->vlan_extraction++;
1854 #if defined(INET) || defined(INET6)
1855 if (iq->flags & IQ_LRO_ENABLED &&
1856 tcp_lro_rx(lro, m0, 0) == 0) {
1857 /* queued for LRO */
1860 ifp->if_input(ifp, m0);
1866 * Must drain the wrq or make sure that someone else will.
1869 wrq_tx_drain(void *arg, int n)
1871 struct sge_wrq *wrq = arg;
1872 struct sge_eq *eq = &wrq->eq;
1875 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1876 drain_wrq_wr_list(wrq->adapter, wrq);
1881 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1883 struct sge_eq *eq = &wrq->eq;
1884 u_int available, dbdiff; /* # of hardware descriptors */
1887 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1889 EQ_LOCK_ASSERT_OWNED(eq);
1890 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1891 wr = STAILQ_FIRST(&wrq->wr_list);
1892 MPASS(wr != NULL); /* Must be called with something useful to do */
1893 MPASS(eq->pidx == eq->dbidx);
1897 eq->cidx = read_hw_cidx(eq);
1898 if (eq->pidx == eq->cidx)
1899 available = eq->sidx - 1;
1901 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1903 MPASS(wr->wrq == wrq);
1904 n = howmany(wr->wr_len, EQ_ESIZE);
1908 dst = (void *)&eq->desc[eq->pidx];
1909 if (__predict_true(eq->sidx - eq->pidx > n)) {
1910 /* Won't wrap, won't end exactly at the status page. */
1911 bcopy(&wr->wr[0], dst, wr->wr_len);
1914 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1916 bcopy(&wr->wr[0], dst, first_portion);
1917 if (wr->wr_len > first_portion) {
1918 bcopy(&wr->wr[first_portion], &eq->desc[0],
1919 wr->wr_len - first_portion);
1921 eq->pidx = n - (eq->sidx - eq->pidx);
1923 wrq->tx_wrs_copied++;
1925 if (available < eq->sidx / 4 &&
1926 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1927 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1929 eq->equeqidx = eq->pidx;
1930 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1931 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1932 eq->equeqidx = eq->pidx;
1937 ring_eq_db(sc, eq, dbdiff);
1941 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1943 MPASS(wrq->nwr_pending > 0);
1945 MPASS(wrq->ndesc_needed >= n);
1946 wrq->ndesc_needed -= n;
1947 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1950 ring_eq_db(sc, eq, dbdiff);
1954 * Doesn't fail. Holds on to work requests it can't send right away.
1957 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1960 struct sge_eq *eq = &wrq->eq;
1963 EQ_LOCK_ASSERT_OWNED(eq);
1965 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1966 MPASS((wr->wr_len & 0x7) == 0);
1968 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1970 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1972 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1973 return; /* commit_wrq_wr will drain wr_list as well. */
1975 drain_wrq_wr_list(sc, wrq);
1977 /* Doorbell must have caught up to the pidx. */
1978 MPASS(eq->pidx == eq->dbidx);
1982 t4_update_fl_bufsize(struct ifnet *ifp)
1984 struct vi_info *vi = ifp->if_softc;
1985 struct adapter *sc = vi->pi->adapter;
1986 struct sge_rxq *rxq;
1988 struct sge_ofld_rxq *ofld_rxq;
1991 int i, maxp, mtu = ifp->if_mtu;
1993 maxp = mtu_to_max_payload(sc, mtu, 0);
1994 for_each_rxq(vi, i, rxq) {
1998 find_best_refill_source(sc, fl, maxp);
2002 maxp = mtu_to_max_payload(sc, mtu, 1);
2003 for_each_ofld_rxq(vi, i, ofld_rxq) {
2007 find_best_refill_source(sc, fl, maxp);
2014 mbuf_nsegs(struct mbuf *m)
2018 KASSERT(m->m_pkthdr.l5hlen > 0,
2019 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2021 return (m->m_pkthdr.l5hlen);
2025 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2029 m->m_pkthdr.l5hlen = nsegs;
2033 mbuf_len16(struct mbuf *m)
2038 n = m->m_pkthdr.PH_loc.eigth[0];
2039 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2045 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2049 m->m_pkthdr.PH_loc.eigth[0] = len16;
2053 needs_tso(struct mbuf *m)
2058 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
2059 KASSERT(m->m_pkthdr.tso_segsz > 0,
2060 ("%s: TSO requested in mbuf %p but MSS not provided",
2069 needs_l3_csum(struct mbuf *m)
2074 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2080 needs_l4_csum(struct mbuf *m)
2085 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2086 CSUM_TCP_IPV6 | CSUM_TSO))
2092 needs_vlan_insertion(struct mbuf *m)
2097 if (m->m_flags & M_VLANTAG) {
2098 KASSERT(m->m_pkthdr.ether_vtag != 0,
2099 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2107 m_advance(struct mbuf **pm, int *poffset, int len)
2109 struct mbuf *m = *pm;
2110 int offset = *poffset;
2116 if (offset + len < m->m_len) {
2118 p = mtod(m, uintptr_t) + offset;
2121 len -= m->m_len - offset;
2132 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2133 * must have at least one mbuf that's not empty.
2136 count_mbuf_nsegs(struct mbuf *m)
2138 vm_paddr_t lastb, next;
2146 for (; m; m = m->m_next) {
2149 if (__predict_false(len == 0))
2151 va = mtod(m, vm_offset_t);
2152 next = pmap_kextract(va);
2153 nsegs += sglist_count(m->m_data, len);
2154 if (lastb + 1 == next)
2156 lastb = pmap_kextract(va + len - 1);
2164 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2165 * a) caller can assume it's been freed if this function returns with an error.
2166 * b) it may get defragged up if the gather list is too long for the hardware.
2169 parse_pkt(struct adapter *sc, struct mbuf **mp)
2171 struct mbuf *m0 = *mp, *m;
2172 int rc, nsegs, defragged = 0, offset;
2173 struct ether_header *eh;
2175 #if defined(INET) || defined(INET6)
2181 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2190 * First count the number of gather list segments in the payload.
2191 * Defrag the mbuf if nsegs exceeds the hardware limit.
2194 MPASS(m0->m_pkthdr.len > 0);
2195 nsegs = count_mbuf_nsegs(m0);
2196 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2197 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2201 *mp = m0 = m; /* update caller's copy after defrag */
2205 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2206 m0 = m_pullup(m0, m0->m_pkthdr.len);
2208 /* Should have left well enough alone. */
2212 *mp = m0; /* update caller's copy after pullup */
2215 set_mbuf_nsegs(m0, nsegs);
2216 if (sc->flags & IS_VF)
2217 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2219 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2221 if (!needs_tso(m0) &&
2222 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2226 eh = mtod(m, struct ether_header *);
2227 eh_type = ntohs(eh->ether_type);
2228 if (eh_type == ETHERTYPE_VLAN) {
2229 struct ether_vlan_header *evh = (void *)eh;
2231 eh_type = ntohs(evh->evl_proto);
2232 m0->m_pkthdr.l2hlen = sizeof(*evh);
2234 m0->m_pkthdr.l2hlen = sizeof(*eh);
2237 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2241 case ETHERTYPE_IPV6:
2243 struct ip6_hdr *ip6 = l3hdr;
2245 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2247 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2254 struct ip *ip = l3hdr;
2256 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2261 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2262 " with the same INET/INET6 options as the kernel.",
2266 #if defined(INET) || defined(INET6)
2267 if (needs_tso(m0)) {
2268 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2269 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2277 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2279 struct sge_eq *eq = &wrq->eq;
2280 struct adapter *sc = wrq->adapter;
2281 int ndesc, available;
2286 ndesc = howmany(len16, EQ_ESIZE / 16);
2287 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2291 if (!STAILQ_EMPTY(&wrq->wr_list))
2292 drain_wrq_wr_list(sc, wrq);
2294 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2297 wr = alloc_wrqe(len16 * 16, wrq);
2298 if (__predict_false(wr == NULL))
2301 cookie->ndesc = ndesc;
2305 eq->cidx = read_hw_cidx(eq);
2306 if (eq->pidx == eq->cidx)
2307 available = eq->sidx - 1;
2309 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2310 if (available < ndesc)
2313 cookie->pidx = eq->pidx;
2314 cookie->ndesc = ndesc;
2315 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2317 w = &eq->desc[eq->pidx];
2318 IDXINCR(eq->pidx, ndesc, eq->sidx);
2319 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2321 wrq->ss_pidx = cookie->pidx;
2322 wrq->ss_len = len16 * 16;
2331 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2333 struct sge_eq *eq = &wrq->eq;
2334 struct adapter *sc = wrq->adapter;
2336 struct wrq_cookie *prev, *next;
2338 if (cookie->pidx == -1) {
2339 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2345 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2346 pidx = cookie->pidx;
2347 MPASS(pidx >= 0 && pidx < eq->sidx);
2348 if (__predict_false(w == &wrq->ss[0])) {
2349 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2351 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2352 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2353 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2356 wrq->tx_wrs_direct++;
2359 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2360 next = TAILQ_NEXT(cookie, link);
2362 MPASS(pidx == eq->dbidx);
2363 if (next == NULL || ndesc >= 16)
2364 ring_eq_db(wrq->adapter, eq, ndesc);
2366 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2368 next->ndesc += ndesc;
2371 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2372 prev->ndesc += ndesc;
2374 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2376 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2377 drain_wrq_wr_list(sc, wrq);
2380 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2381 /* Doorbell must have caught up to the pidx. */
2382 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2389 can_resume_eth_tx(struct mp_ring *r)
2391 struct sge_eq *eq = r->cookie;
2393 return (total_available_tx_desc(eq) > eq->sidx / 8);
2397 cannot_use_txpkts(struct mbuf *m)
2399 /* maybe put a GL limit too, to avoid silliness? */
2401 return (needs_tso(m));
2405 discard_tx(struct sge_eq *eq)
2408 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2412 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2413 * be consumed. Return the actual number consumed. 0 indicates a stall.
2416 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2418 struct sge_txq *txq = r->cookie;
2419 struct sge_eq *eq = &txq->eq;
2420 struct ifnet *ifp = txq->ifp;
2421 struct vi_info *vi = ifp->if_softc;
2422 struct port_info *pi = vi->pi;
2423 struct adapter *sc = pi->adapter;
2424 u_int total, remaining; /* # of packets */
2425 u_int available, dbdiff; /* # of hardware descriptors */
2427 struct mbuf *m0, *tail;
2429 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2431 remaining = IDXDIFF(pidx, cidx, r->size);
2432 MPASS(remaining > 0); /* Must not be called without work to do. */
2436 if (__predict_false(discard_tx(eq))) {
2437 while (cidx != pidx) {
2438 m0 = r->items[cidx];
2440 if (++cidx == r->size)
2443 reclaim_tx_descs(txq, 2048);
2448 /* How many hardware descriptors do we have readily available. */
2449 if (eq->pidx == eq->cidx)
2450 available = eq->sidx - 1;
2452 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2453 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2455 while (remaining > 0) {
2457 m0 = r->items[cidx];
2459 MPASS(m0->m_nextpkt == NULL);
2461 if (available < SGE_MAX_WR_NDESC) {
2462 available += reclaim_tx_descs(txq, 64);
2463 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2464 break; /* out of descriptors */
2467 next_cidx = cidx + 1;
2468 if (__predict_false(next_cidx == r->size))
2471 wr = (void *)&eq->desc[eq->pidx];
2472 if (sc->flags & IS_VF) {
2475 ETHER_BPF_MTAP(ifp, m0);
2476 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2478 } else if (remaining > 1 &&
2479 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2481 /* pkts at cidx, next_cidx should both be in txp. */
2482 MPASS(txp.npkt == 2);
2483 tail = r->items[next_cidx];
2484 MPASS(tail->m_nextpkt == NULL);
2485 ETHER_BPF_MTAP(ifp, m0);
2486 ETHER_BPF_MTAP(ifp, tail);
2487 m0->m_nextpkt = tail;
2489 if (__predict_false(++next_cidx == r->size))
2492 while (next_cidx != pidx) {
2493 if (add_to_txpkts(r->items[next_cidx], &txp,
2496 tail->m_nextpkt = r->items[next_cidx];
2497 tail = tail->m_nextpkt;
2498 ETHER_BPF_MTAP(ifp, tail);
2499 if (__predict_false(++next_cidx == r->size))
2503 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2505 remaining -= txp.npkt;
2509 ETHER_BPF_MTAP(ifp, m0);
2510 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2512 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2516 IDXINCR(eq->pidx, n, eq->sidx);
2518 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2519 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2520 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2522 eq->equeqidx = eq->pidx;
2523 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2524 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2525 eq->equeqidx = eq->pidx;
2528 if (dbdiff >= 16 && remaining >= 4) {
2529 ring_eq_db(sc, eq, dbdiff);
2530 available += reclaim_tx_descs(txq, 4 * dbdiff);
2537 ring_eq_db(sc, eq, dbdiff);
2538 reclaim_tx_descs(txq, 32);
2547 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2551 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2552 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2553 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2554 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2558 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2559 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2560 if (pktc_idx >= 0) {
2561 iq->intr_params |= F_QINTR_CNT_EN;
2562 iq->intr_pktc_idx = pktc_idx;
2564 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2565 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2569 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2573 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2574 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2575 if (sc->flags & BUF_PACKING_OK &&
2576 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2577 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2578 fl->flags |= FL_BUF_PACKING;
2579 find_best_refill_source(sc, fl, maxp);
2580 find_safe_refill_source(sc, fl);
2584 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2585 uint8_t tx_chan, uint16_t iqid, char *name)
2587 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2589 eq->flags = eqtype & EQ_TYPEMASK;
2590 eq->tx_chan = tx_chan;
2592 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2593 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2597 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2598 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2602 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2603 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2605 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2609 rc = bus_dmamem_alloc(*tag, va,
2610 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2612 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2616 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2618 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2623 free_ring(sc, *tag, *map, *pa, *va);
2629 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2630 bus_addr_t pa, void *va)
2633 bus_dmamap_unload(tag, map);
2635 bus_dmamem_free(tag, va, map);
2637 bus_dma_tag_destroy(tag);
2643 * Allocates the ring for an ingress queue and an optional freelist. If the
2644 * freelist is specified it will be allocated and then associated with the
2647 * Returns errno on failure. Resources allocated up to that point may still be
2648 * allocated. Caller is responsible for cleanup in case this function fails.
2650 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2651 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2652 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2655 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2656 int intr_idx, int cong)
2658 int rc, i, cntxt_id;
2661 struct port_info *pi = vi->pi;
2662 struct adapter *sc = iq->adapter;
2663 struct sge_params *sp = &sc->params.sge;
2666 len = iq->qsize * IQ_ESIZE;
2667 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2668 (void **)&iq->desc);
2672 bzero(&c, sizeof(c));
2673 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2674 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2675 V_FW_IQ_CMD_VFN(0));
2677 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2680 /* Special handling for firmware event queue */
2681 if (iq == &sc->sge.fwq)
2682 v |= F_FW_IQ_CMD_IQASYNCH;
2684 if (iq->flags & IQ_INTR) {
2685 KASSERT(intr_idx < sc->intr_count,
2686 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2688 v |= F_FW_IQ_CMD_IQANDST;
2689 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2691 c.type_to_iqandstindex = htobe32(v |
2692 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2693 V_FW_IQ_CMD_VIID(vi->viid) |
2694 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2695 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2696 F_FW_IQ_CMD_IQGTSMODE |
2697 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2698 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2699 c.iqsize = htobe16(iq->qsize);
2700 c.iqaddr = htobe64(iq->ba);
2702 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2705 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2707 len = fl->qsize * EQ_ESIZE;
2708 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2709 &fl->ba, (void **)&fl->desc);
2713 /* Allocate space for one software descriptor per buffer. */
2714 rc = alloc_fl_sdesc(fl);
2716 device_printf(sc->dev,
2717 "failed to setup fl software descriptors: %d\n",
2722 if (fl->flags & FL_BUF_PACKING) {
2723 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2724 fl->buf_boundary = sp->pack_boundary;
2726 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2727 fl->buf_boundary = 16;
2729 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2730 fl->buf_boundary = sp->pad_boundary;
2732 c.iqns_to_fl0congen |=
2733 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2734 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2735 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2736 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2739 c.iqns_to_fl0congen |=
2740 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2741 F_FW_IQ_CMD_FL0CONGCIF |
2742 F_FW_IQ_CMD_FL0CONGEN);
2744 c.fl0dcaen_to_fl0cidxfthresh =
2745 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
2746 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
2747 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
2748 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
2749 c.fl0size = htobe16(fl->qsize);
2750 c.fl0addr = htobe64(fl->ba);
2753 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2755 device_printf(sc->dev,
2756 "failed to create ingress queue: %d\n", rc);
2761 iq->gen = F_RSPD_GEN;
2762 iq->intr_next = iq->intr_params;
2763 iq->cntxt_id = be16toh(c.iqid);
2764 iq->abs_id = be16toh(c.physiqid);
2765 iq->flags |= IQ_ALLOCATED;
2767 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2768 if (cntxt_id >= sc->sge.niq) {
2769 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2770 cntxt_id, sc->sge.niq - 1);
2772 sc->sge.iqmap[cntxt_id] = iq;
2777 iq->flags |= IQ_HAS_FL;
2778 fl->cntxt_id = be16toh(c.fl0id);
2779 fl->pidx = fl->cidx = 0;
2781 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2782 if (cntxt_id >= sc->sge.neq) {
2783 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2784 __func__, cntxt_id, sc->sge.neq - 1);
2786 sc->sge.eqmap[cntxt_id] = (void *)fl;
2789 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2790 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2791 uint32_t mask = (1 << s_qpp) - 1;
2792 volatile uint8_t *udb;
2794 udb = sc->udbs_base + UDBS_DB_OFFSET;
2795 udb += (qid >> s_qpp) << PAGE_SHIFT;
2797 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2798 udb += qid << UDBS_SEG_SHIFT;
2801 fl->udb = (volatile void *)udb;
2803 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2806 /* Enough to make sure the SGE doesn't think it's starved */
2807 refill_fl(sc, fl, fl->lowat);
2811 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
2812 uint32_t param, val;
2814 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2815 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2816 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2821 for (i = 0; i < 4; i++) {
2822 if (cong & (1 << i))
2823 val |= 1 << (i << 2);
2827 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2829 /* report error but carry on */
2830 device_printf(sc->dev,
2831 "failed to set congestion manager context for "
2832 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2836 /* Enable IQ interrupts */
2837 atomic_store_rel_int(&iq->state, IQS_IDLE);
2838 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
2839 V_INGRESSQID(iq->cntxt_id));
2845 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2848 struct adapter *sc = iq->adapter;
2852 return (0); /* nothing to do */
2854 dev = vi ? vi->dev : sc->dev;
2856 if (iq->flags & IQ_ALLOCATED) {
2857 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2858 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2859 fl ? fl->cntxt_id : 0xffff, 0xffff);
2862 "failed to free queue %p: %d\n", iq, rc);
2865 iq->flags &= ~IQ_ALLOCATED;
2868 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2870 bzero(iq, sizeof(*iq));
2873 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2877 free_fl_sdesc(sc, fl);
2879 if (mtx_initialized(&fl->fl_lock))
2880 mtx_destroy(&fl->fl_lock);
2882 bzero(fl, sizeof(*fl));
2889 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
2890 struct sysctl_oid *oid, struct sge_fl *fl)
2892 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2894 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2896 children = SYSCTL_CHILDREN(oid);
2898 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2899 &fl->ba, "bus address of descriptor ring");
2900 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2901 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
2902 "desc ring size in bytes");
2903 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2904 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2905 "SGE context id of the freelist");
2906 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2907 fl_pad ? 1 : 0, "padding enabled");
2908 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2909 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2910 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2911 0, "consumer index");
2912 if (fl->flags & FL_BUF_PACKING) {
2913 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2914 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2916 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2917 0, "producer index");
2918 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2919 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2920 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2921 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2922 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2923 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2924 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2925 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2926 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2927 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2931 alloc_fwq(struct adapter *sc)
2934 struct sge_iq *fwq = &sc->sge.fwq;
2935 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2936 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2938 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2939 fwq->flags |= IQ_INTR; /* always */
2940 if (sc->flags & IS_VF)
2943 intr_idx = sc->intr_count > 1 ? 1 : 0;
2944 fwq->set_tcb_rpl = t4_filter_rpl;
2945 fwq->l2t_write_rpl = do_l2t_write_rpl;
2947 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2949 device_printf(sc->dev,
2950 "failed to create firmware event queue: %d\n", rc);
2954 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2955 NULL, "firmware event queue");
2956 children = SYSCTL_CHILDREN(oid);
2958 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2959 &fwq->ba, "bus address of descriptor ring");
2960 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2961 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
2962 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2963 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2964 "absolute id of the queue");
2965 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2966 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2967 "SGE context id of the queue");
2968 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2969 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2976 free_fwq(struct adapter *sc)
2978 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2982 alloc_mgmtq(struct adapter *sc)
2985 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2987 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2988 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2990 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2991 NULL, "management queue");
2993 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2994 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2995 sc->sge.fwq.cntxt_id, name);
2996 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2998 device_printf(sc->dev,
2999 "failed to create management queue: %d\n", rc);
3007 free_mgmtq(struct adapter *sc)
3010 return free_wrq(sc, &sc->sge.mgmtq);
3014 tnl_cong(struct port_info *pi, int drop)
3022 return (pi->rx_chan_map);
3026 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3027 struct sysctl_oid *oid)
3030 struct adapter *sc = vi->pi->adapter;
3031 struct sysctl_oid_list *children;
3034 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3035 tnl_cong(vi->pi, cong_drop));
3040 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3042 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3043 ("iq_base mismatch"));
3044 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3045 ("PF with non-zero iq_base"));
3048 * The freelist is just barely above the starvation threshold right now,
3049 * fill it up a bit more.
3052 refill_fl(sc, &rxq->fl, 128);
3053 FL_UNLOCK(&rxq->fl);
3055 #if defined(INET) || defined(INET6)
3056 rc = tcp_lro_init(&rxq->lro);
3059 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */
3061 if (vi->ifp->if_capenable & IFCAP_LRO)
3062 rxq->iq.flags |= IQ_LRO_ENABLED;
3066 children = SYSCTL_CHILDREN(oid);
3068 snprintf(name, sizeof(name), "%d", idx);
3069 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3071 children = SYSCTL_CHILDREN(oid);
3073 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3074 &rxq->iq.ba, "bus address of descriptor ring");
3075 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3076 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3077 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3078 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
3079 "absolute id of the queue");
3080 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3081 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
3082 "SGE context id of the queue");
3083 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3084 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
3086 #if defined(INET) || defined(INET6)
3087 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3088 &rxq->lro.lro_queued, 0, NULL);
3089 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3090 &rxq->lro.lro_flushed, 0, NULL);
3092 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3093 &rxq->rxcsum, "# of times hardware assisted with checksum");
3094 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3095 CTLFLAG_RD, &rxq->vlan_extraction,
3096 "# of times hardware extracted 802.1Q tag");
3098 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3104 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3108 #if defined(INET) || defined(INET6)
3110 tcp_lro_free(&rxq->lro);
3111 rxq->lro.ifp = NULL;
3115 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3117 bzero(rxq, sizeof(*rxq));
3124 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3125 int intr_idx, int idx, struct sysctl_oid *oid)
3127 struct port_info *pi = vi->pi;
3129 struct sysctl_oid_list *children;
3132 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
3137 children = SYSCTL_CHILDREN(oid);
3139 snprintf(name, sizeof(name), "%d", idx);
3140 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3142 children = SYSCTL_CHILDREN(oid);
3144 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3145 &ofld_rxq->iq.ba, "bus address of descriptor ring");
3146 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3147 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3148 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3149 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
3150 "I", "absolute id of the queue");
3151 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3152 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
3153 "I", "SGE context id of the queue");
3154 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3155 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
3158 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3164 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3168 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3170 bzero(ofld_rxq, sizeof(*ofld_rxq));
3178 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3179 int idx, struct sysctl_oid *oid)
3182 struct sysctl_oid_list *children;
3183 struct sysctl_ctx_list *ctx;
3186 struct adapter *sc = vi->pi->adapter;
3187 struct netmap_adapter *na = NA(vi->ifp);
3191 len = vi->qsize_rxq * IQ_ESIZE;
3192 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3193 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3197 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3198 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3199 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3205 nm_rxq->iq_cidx = 0;
3206 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3207 nm_rxq->iq_gen = F_RSPD_GEN;
3208 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3209 nm_rxq->fl_sidx = na->num_rx_desc;
3210 nm_rxq->intr_idx = intr_idx;
3213 children = SYSCTL_CHILDREN(oid);
3215 snprintf(name, sizeof(name), "%d", idx);
3216 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3218 children = SYSCTL_CHILDREN(oid);
3220 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3221 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3222 "I", "absolute id of the queue");
3223 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3224 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3225 "I", "SGE context id of the queue");
3226 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3227 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3230 children = SYSCTL_CHILDREN(oid);
3231 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3233 children = SYSCTL_CHILDREN(oid);
3235 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3236 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3237 "I", "SGE context id of the freelist");
3238 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3239 &nm_rxq->fl_cidx, 0, "consumer index");
3240 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3241 &nm_rxq->fl_pidx, 0, "producer index");
3248 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3250 struct adapter *sc = vi->pi->adapter;
3252 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3254 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3261 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3262 struct sysctl_oid *oid)
3266 struct port_info *pi = vi->pi;
3267 struct adapter *sc = pi->adapter;
3268 struct netmap_adapter *na = NA(vi->ifp);
3270 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3272 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3273 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3274 &nm_txq->ba, (void **)&nm_txq->desc);
3278 nm_txq->pidx = nm_txq->cidx = 0;
3279 nm_txq->sidx = na->num_tx_desc;
3281 nm_txq->iqidx = iqidx;
3282 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3283 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3284 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3285 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3287 snprintf(name, sizeof(name), "%d", idx);
3288 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3289 NULL, "netmap tx queue");
3290 children = SYSCTL_CHILDREN(oid);
3292 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3293 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3294 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3295 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3297 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3298 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3305 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3307 struct adapter *sc = vi->pi->adapter;
3309 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3317 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3320 struct fw_eq_ctrl_cmd c;
3321 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3323 bzero(&c, sizeof(c));
3325 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3326 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3327 V_FW_EQ_CTRL_CMD_VFN(0));
3328 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3329 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3330 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3331 c.physeqid_pkd = htobe32(0);
3332 c.fetchszm_to_iqid =
3333 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3334 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3335 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3337 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3338 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3339 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
3340 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3341 c.eqaddr = htobe64(eq->ba);
3343 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3345 device_printf(sc->dev,
3346 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3349 eq->flags |= EQ_ALLOCATED;
3351 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3352 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3353 if (cntxt_id >= sc->sge.neq)
3354 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3355 cntxt_id, sc->sge.neq - 1);
3356 sc->sge.eqmap[cntxt_id] = eq;
3362 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3365 struct fw_eq_eth_cmd c;
3366 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3368 bzero(&c, sizeof(c));
3370 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3371 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3372 V_FW_EQ_ETH_CMD_VFN(0));
3373 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3374 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3375 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3376 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3377 c.fetchszm_to_iqid =
3378 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3379 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3380 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3381 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3382 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3383 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3384 c.eqaddr = htobe64(eq->ba);
3386 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3388 device_printf(vi->dev,
3389 "failed to create Ethernet egress queue: %d\n", rc);
3392 eq->flags |= EQ_ALLOCATED;
3394 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3395 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3396 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3397 if (cntxt_id >= sc->sge.neq)
3398 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3399 cntxt_id, sc->sge.neq - 1);
3400 sc->sge.eqmap[cntxt_id] = eq;
3407 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3410 struct fw_eq_ofld_cmd c;
3411 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3413 bzero(&c, sizeof(c));
3415 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3416 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3417 V_FW_EQ_OFLD_CMD_VFN(0));
3418 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3419 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3420 c.fetchszm_to_iqid =
3421 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3422 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3423 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3425 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3426 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3427 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3428 c.eqaddr = htobe64(eq->ba);
3430 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3432 device_printf(vi->dev,
3433 "failed to create egress queue for TCP offload: %d\n", rc);
3436 eq->flags |= EQ_ALLOCATED;
3438 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3439 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3440 if (cntxt_id >= sc->sge.neq)
3441 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3442 cntxt_id, sc->sge.neq - 1);
3443 sc->sge.eqmap[cntxt_id] = eq;
3450 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3455 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3457 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3458 len = qsize * EQ_ESIZE;
3459 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3460 &eq->ba, (void **)&eq->desc);
3464 eq->pidx = eq->cidx = 0;
3465 eq->equeqidx = eq->dbidx = 0;
3466 eq->doorbells = sc->doorbells;
3468 switch (eq->flags & EQ_TYPEMASK) {
3470 rc = ctrl_eq_alloc(sc, eq);
3474 rc = eth_eq_alloc(sc, vi, eq);
3479 rc = ofld_eq_alloc(sc, vi, eq);
3484 panic("%s: invalid eq type %d.", __func__,
3485 eq->flags & EQ_TYPEMASK);
3488 device_printf(sc->dev,
3489 "failed to allocate egress queue(%d): %d\n",
3490 eq->flags & EQ_TYPEMASK, rc);
3493 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3494 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3495 isset(&eq->doorbells, DOORBELL_WCWR)) {
3496 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3497 uint32_t mask = (1 << s_qpp) - 1;
3498 volatile uint8_t *udb;
3500 udb = sc->udbs_base + UDBS_DB_OFFSET;
3501 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3502 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3503 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3504 clrbit(&eq->doorbells, DOORBELL_WCWR);
3506 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3509 eq->udb = (volatile void *)udb;
3516 free_eq(struct adapter *sc, struct sge_eq *eq)
3520 if (eq->flags & EQ_ALLOCATED) {
3521 switch (eq->flags & EQ_TYPEMASK) {
3523 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3528 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3534 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3540 panic("%s: invalid eq type %d.", __func__,
3541 eq->flags & EQ_TYPEMASK);
3544 device_printf(sc->dev,
3545 "failed to free egress queue (%d): %d\n",
3546 eq->flags & EQ_TYPEMASK, rc);
3549 eq->flags &= ~EQ_ALLOCATED;
3552 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3554 if (mtx_initialized(&eq->eq_lock))
3555 mtx_destroy(&eq->eq_lock);
3557 bzero(eq, sizeof(*eq));
3562 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3563 struct sysctl_oid *oid)
3566 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3567 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3569 rc = alloc_eq(sc, vi, &wrq->eq);
3574 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3575 TAILQ_INIT(&wrq->incomplete_wrs);
3576 STAILQ_INIT(&wrq->wr_list);
3577 wrq->nwr_pending = 0;
3578 wrq->ndesc_needed = 0;
3580 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3581 &wrq->eq.ba, "bus address of descriptor ring");
3582 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3583 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3584 "desc ring size in bytes");
3585 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3586 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3587 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3588 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3590 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3591 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3593 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3594 wrq->eq.sidx, "status page index");
3595 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3596 &wrq->tx_wrs_direct, "# of work requests (direct)");
3597 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3598 &wrq->tx_wrs_copied, "# of work requests (copied)");
3599 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3600 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3606 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3610 rc = free_eq(sc, &wrq->eq);
3614 bzero(wrq, sizeof(*wrq));
3619 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3620 struct sysctl_oid *oid)
3623 struct port_info *pi = vi->pi;
3624 struct adapter *sc = pi->adapter;
3625 struct sge_eq *eq = &txq->eq;
3627 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3629 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3632 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3636 rc = alloc_eq(sc, vi, eq);
3638 mp_ring_free(txq->r);
3643 /* Can't fail after this point. */
3646 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
3648 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
3649 ("eq_base mismatch"));
3650 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
3651 ("PF with non-zero eq_base"));
3653 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3655 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3656 if (sc->flags & IS_VF)
3657 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
3658 V_TXPKT_INTF(pi->tx_chan));
3660 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3661 V_TXPKT_INTF(pi->tx_chan) |
3662 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3663 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3664 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3666 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3669 snprintf(name, sizeof(name), "%d", idx);
3670 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3672 children = SYSCTL_CHILDREN(oid);
3674 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3675 &eq->ba, "bus address of descriptor ring");
3676 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3677 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3678 "desc ring size in bytes");
3679 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3680 &eq->abs_id, 0, "absolute id of the queue");
3681 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3682 &eq->cntxt_id, 0, "SGE context id of the queue");
3683 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3684 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3686 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3687 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3689 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3690 eq->sidx, "status page index");
3692 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3693 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3694 "traffic class (-1 means none)");
3696 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3697 &txq->txcsum, "# of times hardware assisted with checksum");
3698 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3699 CTLFLAG_RD, &txq->vlan_insertion,
3700 "# of times hardware inserted 802.1Q tag");
3701 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3702 &txq->tso_wrs, "# of TSO work requests");
3703 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3704 &txq->imm_wrs, "# of work requests with immediate data");
3705 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3706 &txq->sgl_wrs, "# of work requests with direct SGL");
3707 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3708 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3709 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3710 CTLFLAG_RD, &txq->txpkts0_wrs,
3711 "# of txpkts (type 0) work requests");
3712 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3713 CTLFLAG_RD, &txq->txpkts1_wrs,
3714 "# of txpkts (type 1) work requests");
3715 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3716 CTLFLAG_RD, &txq->txpkts0_pkts,
3717 "# of frames tx'd using type0 txpkts work requests");
3718 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3719 CTLFLAG_RD, &txq->txpkts1_pkts,
3720 "# of frames tx'd using type1 txpkts work requests");
3722 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3723 CTLFLAG_RD, &txq->r->enqueues,
3724 "# of enqueues to the mp_ring for this queue");
3725 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3726 CTLFLAG_RD, &txq->r->drops,
3727 "# of drops in the mp_ring for this queue");
3728 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3729 CTLFLAG_RD, &txq->r->starts,
3730 "# of normal consumer starts in the mp_ring for this queue");
3731 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3732 CTLFLAG_RD, &txq->r->stalls,
3733 "# of consumer stalls in the mp_ring for this queue");
3734 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3735 CTLFLAG_RD, &txq->r->restarts,
3736 "# of consumer restarts in the mp_ring for this queue");
3737 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3738 CTLFLAG_RD, &txq->r->abdications,
3739 "# of consumer abdications in the mp_ring for this queue");
3745 free_txq(struct vi_info *vi, struct sge_txq *txq)
3748 struct adapter *sc = vi->pi->adapter;
3749 struct sge_eq *eq = &txq->eq;
3751 rc = free_eq(sc, eq);
3755 sglist_free(txq->gl);
3756 free(txq->sdesc, M_CXGBE);
3757 mp_ring_free(txq->r);
3759 bzero(txq, sizeof(*txq));
3764 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3766 bus_addr_t *ba = arg;
3769 ("%s meant for single segment mappings only.", __func__));
3771 *ba = error ? 0 : segs->ds_addr;
3775 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3779 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3783 v = fl->dbval | V_PIDX(n);
3785 *fl->udb = htole32(v);
3787 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
3788 IDXINCR(fl->dbidx, n, fl->sidx);
3792 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3793 * recycled do not count towards this allocation budget.
3795 * Returns non-zero to indicate that this freelist should be added to the list
3796 * of starving freelists.
3799 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3802 struct fl_sdesc *sd;
3805 struct cluster_layout *cll;
3806 struct sw_zone_info *swz;
3807 struct cluster_metadata *clm;
3809 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3811 FL_LOCK_ASSERT_OWNED(fl);
3814 * We always stop at the begining of the hardware descriptor that's just
3815 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3816 * which would mean an empty freelist to the chip.
3818 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3819 if (fl->pidx == max_pidx * 8)
3822 d = &fl->desc[fl->pidx];
3823 sd = &fl->sdesc[fl->pidx];
3824 cll = &fl->cll_def; /* default layout */
3825 swz = &sc->sge.sw_zone_info[cll->zidx];
3829 if (sd->cl != NULL) {
3831 if (sd->nmbuf == 0) {
3833 * Fast recycle without involving any atomics on
3834 * the cluster's metadata (if the cluster has
3835 * metadata). This happens when all frames
3836 * received in the cluster were small enough to
3837 * fit within a single mbuf each.
3839 fl->cl_fast_recycled++;
3841 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3843 MPASS(clm->refcount == 1);
3849 * Cluster is guaranteed to have metadata. Clusters
3850 * without metadata always take the fast recycle path
3851 * when they're recycled.
3853 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3856 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3858 counter_u64_add(extfree_rels, 1);
3861 sd->cl = NULL; /* gave up my reference */
3863 MPASS(sd->cl == NULL);
3865 cl = uma_zalloc(swz->zone, M_NOWAIT);
3866 if (__predict_false(cl == NULL)) {
3867 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3868 fl->cll_def.zidx == fl->cll_alt.zidx)
3871 /* fall back to the safe zone */
3873 swz = &sc->sge.sw_zone_info[cll->zidx];
3879 pa = pmap_kextract((vm_offset_t)cl);
3883 *d = htobe64(pa | cll->hwidx);
3884 clm = cl_metadata(sc, fl, cll, cl);
3896 if (__predict_false(++fl->pidx % 8 == 0)) {
3897 uint16_t pidx = fl->pidx / 8;
3899 if (__predict_false(pidx == fl->sidx)) {
3905 if (pidx == max_pidx)
3908 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3913 if (fl->pidx / 8 != fl->dbidx)
3916 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3920 * Attempt to refill all starving freelists.
3923 refill_sfl(void *arg)
3925 struct adapter *sc = arg;
3926 struct sge_fl *fl, *fl_temp;
3928 mtx_assert(&sc->sfl_lock, MA_OWNED);
3929 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3931 refill_fl(sc, fl, 64);
3932 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3933 TAILQ_REMOVE(&sc->sfl, fl, link);
3934 fl->flags &= ~FL_STARVING;
3939 if (!TAILQ_EMPTY(&sc->sfl))
3940 callout_schedule(&sc->sfl_callout, hz / 5);
3944 alloc_fl_sdesc(struct sge_fl *fl)
3947 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3954 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3956 struct fl_sdesc *sd;
3957 struct cluster_metadata *clm;
3958 struct cluster_layout *cll;
3962 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3967 clm = cl_metadata(sc, fl, cll, sd->cl);
3969 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3970 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3971 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3972 counter_u64_add(extfree_rels, 1);
3977 free(fl->sdesc, M_CXGBE);
3982 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3989 rc = sglist_append_mbuf(gl, m);
3990 if (__predict_false(rc != 0)) {
3991 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3992 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3995 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3996 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3997 mbuf_nsegs(m), gl->sg_nseg));
3998 KASSERT(gl->sg_nseg > 0 &&
3999 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
4000 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4001 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4005 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4008 txpkt_len16(u_int nsegs, u_int tso)
4014 nsegs--; /* first segment is part of ulptx_sgl */
4015 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4016 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4018 n += sizeof(struct cpl_tx_pkt_lso_core);
4020 return (howmany(n, 16));
4024 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4028 txpkt_vm_len16(u_int nsegs, u_int tso)
4034 nsegs--; /* first segment is part of ulptx_sgl */
4035 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4036 sizeof(struct cpl_tx_pkt_core) +
4037 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4039 n += sizeof(struct cpl_tx_pkt_lso_core);
4041 return (howmany(n, 16));
4045 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4049 txpkts0_len16(u_int nsegs)
4055 nsegs--; /* first segment is part of ulptx_sgl */
4056 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4057 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4058 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4060 return (howmany(n, 16));
4064 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4072 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4074 return (howmany(n, 16));
4078 imm_payload(u_int ndesc)
4082 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4083 sizeof(struct cpl_tx_pkt_core);
4089 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4090 * software descriptor, and advance the pidx. It is guaranteed that enough
4091 * descriptors are available.
4093 * The return value is the # of hardware descriptors used.
4096 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4097 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4099 struct sge_eq *eq = &txq->eq;
4100 struct tx_sdesc *txsd;
4101 struct cpl_tx_pkt_core *cpl;
4102 uint32_t ctrl; /* used in many unrelated places */
4104 int csum_type, len16, ndesc, pktlen, nsegs;
4107 TXQ_LOCK_ASSERT_OWNED(txq);
4109 MPASS(available > 0 && available < eq->sidx);
4111 len16 = mbuf_len16(m0);
4112 nsegs = mbuf_nsegs(m0);
4113 pktlen = m0->m_pkthdr.len;
4114 ctrl = sizeof(struct cpl_tx_pkt_core);
4116 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4117 ndesc = howmany(len16, EQ_ESIZE / 16);
4118 MPASS(ndesc <= available);
4120 /* Firmware work request header */
4121 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4122 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4123 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4125 ctrl = V_FW_WR_LEN16(len16);
4126 wr->equiq_to_len16 = htobe32(ctrl);
4131 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4132 * vlantci is ignored unless the ethtype is 0x8100, so it's
4133 * simpler to always copy it rather than making it
4134 * conditional. Also, it seems that we do not have to set
4135 * vlantci or fake the ethtype when doing VLAN tag insertion.
4137 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4140 if (needs_tso(m0)) {
4141 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4143 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4144 m0->m_pkthdr.l4hlen > 0,
4145 ("%s: mbuf %p needs TSO but missing header lengths",
4148 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4149 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4150 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4151 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4152 ctrl |= V_LSO_ETHHDR_LEN(1);
4153 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4156 lso->lso_ctrl = htobe32(ctrl);
4157 lso->ipid_ofst = htobe16(0);
4158 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4159 lso->seqno_offset = htobe32(0);
4160 lso->len = htobe32(pktlen);
4162 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4163 csum_type = TX_CSUM_TCPIP6;
4165 csum_type = TX_CSUM_TCPIP;
4167 cpl = (void *)(lso + 1);
4171 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4172 csum_type = TX_CSUM_TCPIP;
4173 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4174 csum_type = TX_CSUM_UDPIP;
4175 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4176 csum_type = TX_CSUM_TCPIP6;
4177 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4178 csum_type = TX_CSUM_UDPIP6;
4180 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4182 * XXX: The firmware appears to stomp on the
4183 * fragment/flags field of the IP header when
4184 * using TX_CSUM_IP. Fall back to doing
4185 * software checksums.
4193 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4194 offsetof(struct ip, ip_sum));
4195 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4196 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4197 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4201 cpl = (void *)(wr + 1);
4204 /* Checksum offload */
4206 if (needs_l3_csum(m0) == 0)
4207 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4208 if (csum_type >= 0) {
4209 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4210 ("%s: mbuf %p needs checksum offload but missing header lengths",
4213 if (chip_id(sc) <= CHELSIO_T5) {
4214 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4217 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4220 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4221 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4223 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4224 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4225 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4226 txq->txcsum++; /* some hardware assistance provided */
4228 /* VLAN tag insertion */
4229 if (needs_vlan_insertion(m0)) {
4230 ctrl1 |= F_TXPKT_VLAN_VLD |
4231 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4232 txq->vlan_insertion++;
4236 cpl->ctrl0 = txq->cpl_ctrl0;
4238 cpl->len = htobe16(pktlen);
4239 cpl->ctrl1 = htobe64(ctrl1);
4242 dst = (void *)(cpl + 1);
4245 * A packet using TSO will use up an entire descriptor for the
4246 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4247 * If this descriptor is the last descriptor in the ring, wrap
4248 * around to the front of the ring explicitly for the start of
4251 if (dst == (void *)&eq->desc[eq->sidx]) {
4252 dst = (void *)&eq->desc[0];
4253 write_gl_to_txd(txq, m0, &dst, 0);
4255 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4260 txsd = &txq->sdesc[eq->pidx];
4262 txsd->desc_used = ndesc;
4268 * Write a txpkt WR for this packet to the hardware descriptors, update the
4269 * software descriptor, and advance the pidx. It is guaranteed that enough
4270 * descriptors are available.
4272 * The return value is the # of hardware descriptors used.
4275 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4276 struct mbuf *m0, u_int available)
4278 struct sge_eq *eq = &txq->eq;
4279 struct tx_sdesc *txsd;
4280 struct cpl_tx_pkt_core *cpl;
4281 uint32_t ctrl; /* used in many unrelated places */
4283 int len16, ndesc, pktlen, nsegs;
4286 TXQ_LOCK_ASSERT_OWNED(txq);
4288 MPASS(available > 0 && available < eq->sidx);
4290 len16 = mbuf_len16(m0);
4291 nsegs = mbuf_nsegs(m0);
4292 pktlen = m0->m_pkthdr.len;
4293 ctrl = sizeof(struct cpl_tx_pkt_core);
4295 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4296 else if (pktlen <= imm_payload(2) && available >= 2) {
4297 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4299 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4300 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4303 ndesc = howmany(len16, EQ_ESIZE / 16);
4304 MPASS(ndesc <= available);
4306 /* Firmware work request header */
4307 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4308 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4309 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4311 ctrl = V_FW_WR_LEN16(len16);
4312 wr->equiq_to_len16 = htobe32(ctrl);
4315 if (needs_tso(m0)) {
4316 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4318 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4319 m0->m_pkthdr.l4hlen > 0,
4320 ("%s: mbuf %p needs TSO but missing header lengths",
4323 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4324 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4325 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4326 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4327 ctrl |= V_LSO_ETHHDR_LEN(1);
4328 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4331 lso->lso_ctrl = htobe32(ctrl);
4332 lso->ipid_ofst = htobe16(0);
4333 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4334 lso->seqno_offset = htobe32(0);
4335 lso->len = htobe32(pktlen);
4337 cpl = (void *)(lso + 1);
4341 cpl = (void *)(wr + 1);
4343 /* Checksum offload */
4345 if (needs_l3_csum(m0) == 0)
4346 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4347 if (needs_l4_csum(m0) == 0)
4348 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4349 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4350 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4351 txq->txcsum++; /* some hardware assistance provided */
4353 /* VLAN tag insertion */
4354 if (needs_vlan_insertion(m0)) {
4355 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4356 txq->vlan_insertion++;
4360 cpl->ctrl0 = txq->cpl_ctrl0;
4362 cpl->len = htobe16(pktlen);
4363 cpl->ctrl1 = htobe64(ctrl1);
4366 dst = (void *)(cpl + 1);
4369 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4374 for (m = m0; m != NULL; m = m->m_next) {
4375 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4381 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4388 txsd = &txq->sdesc[eq->pidx];
4390 txsd->desc_used = ndesc;
4396 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4398 u_int needed, nsegs1, nsegs2, l1, l2;
4400 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4403 nsegs1 = mbuf_nsegs(m);
4404 nsegs2 = mbuf_nsegs(n);
4405 if (nsegs1 + nsegs2 == 2) {
4407 l1 = l2 = txpkts1_len16();
4410 l1 = txpkts0_len16(nsegs1);
4411 l2 = txpkts0_len16(nsegs2);
4413 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4414 needed = howmany(txp->len16, EQ_ESIZE / 16);
4415 if (needed > SGE_MAX_WR_NDESC || needed > available)
4418 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4419 if (txp->plen > 65535)
4423 set_mbuf_len16(m, l1);
4424 set_mbuf_len16(n, l2);
4430 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4432 u_int plen, len16, needed, nsegs;
4434 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4436 nsegs = mbuf_nsegs(m);
4437 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4440 plen = txp->plen + m->m_pkthdr.len;
4444 if (txp->wr_type == 0)
4445 len16 = txpkts0_len16(nsegs);
4447 len16 = txpkts1_len16();
4448 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4449 if (needed > SGE_MAX_WR_NDESC || needed > available)
4454 txp->len16 += len16;
4455 set_mbuf_len16(m, len16);
4461 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4462 * the software descriptor, and advance the pidx. It is guaranteed that enough
4463 * descriptors are available.
4465 * The return value is the # of hardware descriptors used.
4468 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4469 struct mbuf *m0, const struct txpkts *txp, u_int available)
4471 struct sge_eq *eq = &txq->eq;
4472 struct tx_sdesc *txsd;
4473 struct cpl_tx_pkt_core *cpl;
4476 int ndesc, checkwrap;
4480 TXQ_LOCK_ASSERT_OWNED(txq);
4481 MPASS(txp->npkt > 0);
4482 MPASS(txp->plen < 65536);
4484 MPASS(m0->m_nextpkt != NULL);
4485 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4486 MPASS(available > 0 && available < eq->sidx);
4488 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4489 MPASS(ndesc <= available);
4491 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4492 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4493 ctrl = V_FW_WR_LEN16(txp->len16);
4494 wr->equiq_to_len16 = htobe32(ctrl);
4495 wr->plen = htobe16(txp->plen);
4496 wr->npkt = txp->npkt;
4498 wr->type = txp->wr_type;
4502 * At this point we are 16B into a hardware descriptor. If checkwrap is
4503 * set then we know the WR is going to wrap around somewhere. We'll
4504 * check for that at appropriate points.
4506 checkwrap = eq->sidx - ndesc < eq->pidx;
4507 for (m = m0; m != NULL; m = m->m_nextpkt) {
4508 if (txp->wr_type == 0) {
4509 struct ulp_txpkt *ulpmc;
4510 struct ulptx_idata *ulpsc;
4512 /* ULP master command */
4514 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4515 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4516 ulpmc->len = htobe32(mbuf_len16(m));
4518 /* ULP subcommand */
4519 ulpsc = (void *)(ulpmc + 1);
4520 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4522 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4524 cpl = (void *)(ulpsc + 1);
4526 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4527 cpl = (void *)&eq->desc[0];
4528 txq->txpkts0_pkts += txp->npkt;
4532 txq->txpkts1_pkts += txp->npkt;
4536 /* Checksum offload */
4538 if (needs_l3_csum(m) == 0)
4539 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4540 if (needs_l4_csum(m) == 0)
4541 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4542 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4543 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4544 txq->txcsum++; /* some hardware assistance provided */
4546 /* VLAN tag insertion */
4547 if (needs_vlan_insertion(m)) {
4548 ctrl1 |= F_TXPKT_VLAN_VLD |
4549 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4550 txq->vlan_insertion++;
4554 cpl->ctrl0 = txq->cpl_ctrl0;
4556 cpl->len = htobe16(m->m_pkthdr.len);
4557 cpl->ctrl1 = htobe64(ctrl1);
4561 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4562 flitp = (void *)&eq->desc[0];
4564 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4568 txsd = &txq->sdesc[eq->pidx];
4570 txsd->desc_used = ndesc;
4576 * If the SGL ends on an address that is not 16 byte aligned, this function will
4577 * add a 0 filled flit at the end.
4580 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4582 struct sge_eq *eq = &txq->eq;
4583 struct sglist *gl = txq->gl;
4584 struct sglist_seg *seg;
4585 __be64 *flitp, *wrap;
4586 struct ulptx_sgl *usgl;
4587 int i, nflits, nsegs;
4589 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4590 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4591 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4592 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4595 nsegs = gl->sg_nseg;
4598 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4599 flitp = (__be64 *)(*to);
4600 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4601 seg = &gl->sg_segs[0];
4602 usgl = (void *)flitp;
4605 * We start at a 16 byte boundary somewhere inside the tx descriptor
4606 * ring, so we're at least 16 bytes away from the status page. There is
4607 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4610 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4611 V_ULPTX_NSGE(nsegs));
4612 usgl->len0 = htobe32(seg->ss_len);
4613 usgl->addr0 = htobe64(seg->ss_paddr);
4616 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4618 /* Won't wrap around at all */
4620 for (i = 0; i < nsegs - 1; i++, seg++) {
4621 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4622 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4625 usgl->sge[i / 2].len[1] = htobe32(0);
4629 /* Will wrap somewhere in the rest of the SGL */
4631 /* 2 flits already written, write the rest flit by flit */
4632 flitp = (void *)(usgl + 1);
4633 for (i = 0; i < nflits - 2; i++) {
4635 flitp = (void *)eq->desc;
4636 *flitp++ = get_flit(seg, nsegs - 1, i);
4641 MPASS(((uintptr_t)flitp) & 0xf);
4645 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4646 if (__predict_false(flitp == wrap))
4647 *to = (void *)eq->desc;
4649 *to = (void *)flitp;
4653 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4656 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4657 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4659 if (__predict_true((uintptr_t)(*to) + len <=
4660 (uintptr_t)&eq->desc[eq->sidx])) {
4661 bcopy(from, *to, len);
4664 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4666 bcopy(from, *to, portion);
4668 portion = len - portion; /* remaining */
4669 bcopy(from, (void *)eq->desc, portion);
4670 (*to) = (caddr_t)eq->desc + portion;
4675 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4683 clrbit(&db, DOORBELL_WCWR);
4686 switch (ffs(db) - 1) {
4688 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4691 case DOORBELL_WCWR: {
4692 volatile uint64_t *dst, *src;
4696 * Queues whose 128B doorbell segment fits in the page do not
4697 * use relative qid (udb_qid is always 0). Only queues with
4698 * doorbell segments can do WCWR.
4700 KASSERT(eq->udb_qid == 0 && n == 1,
4701 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4702 __func__, eq->doorbells, n, eq->dbidx, eq));
4704 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4707 src = (void *)&eq->desc[i];
4708 while (src != (void *)&eq->desc[i + 1])
4714 case DOORBELL_UDBWC:
4715 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4720 t4_write_reg(sc, sc->sge_kdoorbell_reg,
4721 V_QID(eq->cntxt_id) | V_PIDX(n));
4725 IDXINCR(eq->dbidx, n, eq->sidx);
4729 reclaimable_tx_desc(struct sge_eq *eq)
4733 hw_cidx = read_hw_cidx(eq);
4734 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4738 total_available_tx_desc(struct sge_eq *eq)
4740 uint16_t hw_cidx, pidx;
4742 hw_cidx = read_hw_cidx(eq);
4745 if (pidx == hw_cidx)
4746 return (eq->sidx - 1);
4748 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4751 static inline uint16_t
4752 read_hw_cidx(struct sge_eq *eq)
4754 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4755 uint16_t cidx = spg->cidx; /* stable snapshot */
4757 return (be16toh(cidx));
4761 * Reclaim 'n' descriptors approximately.
4764 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4766 struct tx_sdesc *txsd;
4767 struct sge_eq *eq = &txq->eq;
4768 u_int can_reclaim, reclaimed;
4770 TXQ_LOCK_ASSERT_OWNED(txq);
4774 can_reclaim = reclaimable_tx_desc(eq);
4775 while (can_reclaim && reclaimed < n) {
4777 struct mbuf *m, *nextpkt;
4779 txsd = &txq->sdesc[eq->cidx];
4780 ndesc = txsd->desc_used;
4782 /* Firmware doesn't return "partial" credits. */
4783 KASSERT(can_reclaim >= ndesc,
4784 ("%s: unexpected number of credits: %d, %d",
4785 __func__, can_reclaim, ndesc));
4787 for (m = txsd->m; m != NULL; m = nextpkt) {
4788 nextpkt = m->m_nextpkt;
4789 m->m_nextpkt = NULL;
4793 can_reclaim -= ndesc;
4794 IDXINCR(eq->cidx, ndesc, eq->sidx);
4801 tx_reclaim(void *arg, int n)
4803 struct sge_txq *txq = arg;
4804 struct sge_eq *eq = &txq->eq;
4807 if (TXQ_TRYLOCK(txq) == 0)
4809 n = reclaim_tx_descs(txq, 32);
4810 if (eq->cidx == eq->pidx)
4811 eq->equeqidx = eq->pidx;
4817 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4819 int i = (idx / 3) * 2;
4825 rc = htobe32(segs[i].ss_len);
4827 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4832 return (htobe64(segs[i].ss_paddr));
4834 return (htobe64(segs[i + 1].ss_paddr));
4841 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4843 int8_t zidx, hwidx, idx;
4844 uint16_t region1, region3;
4845 int spare, spare_needed, n;
4846 struct sw_zone_info *swz;
4847 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4850 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4851 * large enough for the max payload and cluster metadata. Otherwise
4852 * settle for the largest bufsize that leaves enough room in the cluster
4855 * Without buffer packing: Look for the smallest zone which has a
4856 * bufsize large enough for the max payload. Settle for the largest
4857 * bufsize available if there's nothing big enough for max payload.
4859 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4860 swz = &sc->sge.sw_zone_info[0];
4862 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4863 if (swz->size > largest_rx_cluster) {
4864 if (__predict_true(hwidx != -1))
4868 * This is a misconfiguration. largest_rx_cluster is
4869 * preventing us from finding a refill source. See
4870 * dev.t5nex.<n>.buffer_sizes to figure out why.
4872 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4873 " refill source for fl %p (dma %u). Ignored.\n",
4874 largest_rx_cluster, fl, maxp);
4876 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4877 hwb = &hwb_list[idx];
4878 spare = swz->size - hwb->size;
4879 if (spare < spare_needed)
4882 hwidx = idx; /* best option so far */
4883 if (hwb->size >= maxp) {
4885 if ((fl->flags & FL_BUF_PACKING) == 0)
4886 goto done; /* stop looking (not packing) */
4888 if (swz->size >= safest_rx_cluster)
4889 goto done; /* stop looking (packing) */
4891 break; /* keep looking, next zone */
4895 /* A usable hwidx has been located. */
4897 hwb = &hwb_list[hwidx];
4899 swz = &sc->sge.sw_zone_info[zidx];
4901 region3 = swz->size - hwb->size;
4904 * Stay within this zone and see if there is a better match when mbuf
4905 * inlining is allowed. Remember that the hwidx's are sorted in
4906 * decreasing order of size (so in increasing order of spare area).
4908 for (idx = hwidx; idx != -1; idx = hwb->next) {
4909 hwb = &hwb_list[idx];
4910 spare = swz->size - hwb->size;
4912 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4916 * Do not inline mbufs if doing so would violate the pad/pack
4917 * boundary alignment requirement.
4919 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4921 if (fl->flags & FL_BUF_PACKING &&
4922 (MSIZE % sc->params.sge.pack_boundary) != 0)
4925 if (spare < CL_METADATA_SIZE + MSIZE)
4927 n = (spare - CL_METADATA_SIZE) / MSIZE;
4928 if (n > howmany(hwb->size, maxp))
4932 if (fl->flags & FL_BUF_PACKING) {
4933 region1 = n * MSIZE;
4934 region3 = spare - region1;
4937 region3 = spare - region1;
4942 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4943 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4944 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4945 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4946 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4947 sc->sge.sw_zone_info[zidx].size,
4948 ("%s: bad buffer layout for fl %p, maxp %d. "
4949 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4950 sc->sge.sw_zone_info[zidx].size, region1,
4951 sc->sge.hw_buf_info[hwidx].size, region3));
4952 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4953 KASSERT(region3 >= CL_METADATA_SIZE,
4954 ("%s: no room for metadata. fl %p, maxp %d; "
4955 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4956 sc->sge.sw_zone_info[zidx].size, region1,
4957 sc->sge.hw_buf_info[hwidx].size, region3));
4958 KASSERT(region1 % MSIZE == 0,
4959 ("%s: bad mbuf region for fl %p, maxp %d. "
4960 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4961 sc->sge.sw_zone_info[zidx].size, region1,
4962 sc->sge.hw_buf_info[hwidx].size, region3));
4965 fl->cll_def.zidx = zidx;
4966 fl->cll_def.hwidx = hwidx;
4967 fl->cll_def.region1 = region1;
4968 fl->cll_def.region3 = region3;
4972 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4974 struct sge *s = &sc->sge;
4975 struct hw_buf_info *hwb;
4976 struct sw_zone_info *swz;
4980 if (fl->flags & FL_BUF_PACKING)
4981 hwidx = s->safe_hwidx2; /* with room for metadata */
4982 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4983 hwidx = s->safe_hwidx2;
4984 hwb = &s->hw_buf_info[hwidx];
4985 swz = &s->sw_zone_info[hwb->zidx];
4986 spare = swz->size - hwb->size;
4988 /* no good if there isn't room for an mbuf as well */
4989 if (spare < CL_METADATA_SIZE + MSIZE)
4990 hwidx = s->safe_hwidx1;
4992 hwidx = s->safe_hwidx1;
4995 /* No fallback source */
4996 fl->cll_alt.hwidx = -1;
4997 fl->cll_alt.zidx = -1;
5002 hwb = &s->hw_buf_info[hwidx];
5003 swz = &s->sw_zone_info[hwb->zidx];
5004 spare = swz->size - hwb->size;
5005 fl->cll_alt.hwidx = hwidx;
5006 fl->cll_alt.zidx = hwb->zidx;
5007 if (allow_mbufs_in_cluster &&
5008 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5009 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5011 fl->cll_alt.region1 = 0;
5012 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5016 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5018 mtx_lock(&sc->sfl_lock);
5020 if ((fl->flags & FL_DOOMED) == 0) {
5021 fl->flags |= FL_STARVING;
5022 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5023 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5026 mtx_unlock(&sc->sfl_lock);
5030 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5032 struct sge_wrq *wrq = (void *)eq;
5034 atomic_readandclear_int(&eq->equiq);
5035 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5039 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5041 struct sge_txq *txq = (void *)eq;
5043 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5045 atomic_readandclear_int(&eq->equiq);
5046 mp_ring_check_drainage(txq->r, 0);
5047 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5051 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5054 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5055 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5056 struct adapter *sc = iq->adapter;
5057 struct sge *s = &sc->sge;
5059 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5060 &handle_wrq_egr_update, &handle_eth_egr_update,
5061 &handle_wrq_egr_update};
5063 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5066 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5067 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5072 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5073 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5074 offsetof(struct cpl_fw6_msg, data));
5077 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5079 struct adapter *sc = iq->adapter;
5080 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5082 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5085 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5086 const struct rss_header *rss2;
5088 rss2 = (const struct rss_header *)&cpl->data[0];
5089 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5092 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5096 * t4_handle_wrerr_rpl - process a FW work request error message
5097 * @adap: the adapter
5098 * @rpl: start of the FW message
5101 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5103 u8 opcode = *(const u8 *)rpl;
5104 const struct fw_error_cmd *e = (const void *)rpl;
5107 if (opcode != FW_ERROR_CMD) {
5109 "%s: Received WRERR_RPL message with opcode %#x\n",
5110 device_get_nameunit(adap->dev), opcode);
5113 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5114 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5116 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5117 case FW_ERROR_TYPE_EXCEPTION:
5118 log(LOG_ERR, "exception info:\n");
5119 for (i = 0; i < nitems(e->u.exception.info); i++)
5120 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5121 be32toh(e->u.exception.info[i]));
5124 case FW_ERROR_TYPE_HWMODULE:
5125 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5126 be32toh(e->u.hwmodule.regaddr),
5127 be32toh(e->u.hwmodule.regval));
5129 case FW_ERROR_TYPE_WR:
5130 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5131 be16toh(e->u.wr.cidx),
5132 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5133 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5134 be32toh(e->u.wr.eqid));
5135 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5136 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5140 case FW_ERROR_TYPE_ACL:
5141 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5142 be16toh(e->u.acl.cidx),
5143 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5144 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5145 be32toh(e->u.acl.eqid),
5146 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5148 for (i = 0; i < nitems(e->u.acl.val); i++)
5149 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5153 log(LOG_ERR, "type %#x\n",
5154 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5161 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5163 uint16_t *id = arg1;
5166 return sysctl_handle_int(oidp, &i, 0, req);
5170 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5172 struct sge *s = arg1;
5173 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5174 struct sw_zone_info *swz = &s->sw_zone_info[0];
5179 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5180 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5181 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5186 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5190 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5196 sysctl_tc(SYSCTL_HANDLER_ARGS)
5198 struct vi_info *vi = arg1;
5199 struct port_info *pi;
5201 struct sge_txq *txq;
5202 struct tx_cl_rl_params *tc;
5203 int qidx = arg2, rc, tc_idx;
5204 uint32_t fw_queue, fw_class;
5206 MPASS(qidx >= 0 && qidx < vi->ntxq);
5209 txq = &sc->sge.txq[vi->first_txq + qidx];
5211 tc_idx = txq->tc_idx;
5212 rc = sysctl_handle_int(oidp, &tc_idx, 0, req);
5213 if (rc != 0 || req->newptr == NULL)
5216 if (sc->flags & IS_VF)
5219 /* Note that -1 is legitimate input (it means unbind). */
5220 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls)
5223 mtx_lock(&sc->tc_lock);
5224 if (tc_idx == txq->tc_idx) {
5225 rc = 0; /* No change, nothing to do. */
5229 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
5230 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
5231 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id);
5234 fw_class = 0xffffffff; /* Unbind. */
5237 * Bind to a different class.
5239 tc = &pi->sched_params->cl_rl[tc_idx];
5240 if (tc->flags & TX_CLRL_ERROR) {
5241 /* Previous attempt to set the cl-rl params failed. */
5246 * Ok to proceed. Place a reference on the new class
5247 * while still holding on to the reference on the
5248 * previous class, if any.
5254 mtx_unlock(&sc->tc_lock);
5256 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc");
5259 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class);
5260 end_synchronized_op(sc, 0);
5262 mtx_lock(&sc->tc_lock);
5264 if (txq->tc_idx != -1) {
5265 tc = &pi->sched_params->cl_rl[txq->tc_idx];
5266 MPASS(tc->refcount > 0);
5269 txq->tc_idx = tc_idx;
5270 } else if (tc_idx != -1) {
5271 tc = &pi->sched_params->cl_rl[tc_idx];
5272 MPASS(tc->refcount > 0);
5276 mtx_unlock(&sc->tc_lock);