contrib/llvm/utils/TableGen/TableGen.cpp

   1 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the main function for LLVM's TableGen.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AsmMatcherEmitter.h"
  15 #include "AsmWriterEmitter.h"
  16 #include "CallingConvEmitter.h"
  17 #include "CodeEmitterGen.h"
  18 #include "DAGISelEmitter.h"
  19 #include "DFAPacketizerEmitter.h"
  20 #include "DisassemblerEmitter.h"
  21 #include "EDEmitter.h"
  22 #include "FastISelEmitter.h"
  23 #include "InstrInfoEmitter.h"
  24 #include "IntrinsicEmitter.h"
  25 #include "PseudoLoweringEmitter.h"
  26 #include "RegisterInfoEmitter.h"
  27 #include "SubtargetEmitter.h"
  28 #include "SetTheory.h"
  29
  30 #include "llvm/Support/CommandLine.h"
  31 #include "llvm/Support/PrettyStackTrace.h"
  32 #include "llvm/Support/Signals.h"
  33 #include "llvm/TableGen/Error.h"
  34 #include "llvm/TableGen/Main.h"
  35 #include "llvm/TableGen/Record.h"
  36 #include "llvm/TableGen/TableGenAction.h"
  37
  38 using namespace llvm;
  39
  40 enum ActionType {
  41   PrintRecords,
  42   GenEmitter,
  43   GenRegisterInfo,
  44   GenInstrInfo,
  45   GenAsmWriter,
  46   GenAsmMatcher,
  47   GenDisassembler,
  48   GenPseudoLowering,
  49   GenCallingConv,
  50   GenDAGISel,
  51   GenDFAPacketizer,
  52   GenFastISel,
  53   GenSubtarget,
  54   GenIntrinsic,
  55   GenTgtIntrinsic,
  56   GenEDInfo,
  57   PrintEnums,
  58   PrintSets
  59 };
  60
  61 namespace {
  62   cl::opt<ActionType>
  63   Action(cl::desc("Action to perform:"),
  64          cl::values(clEnumValN(PrintRecords, "print-records",
  65                                "Print all records to stdout (default)"),
  66                     clEnumValN(GenEmitter, "gen-emitter",
  67                                "Generate machine code emitter"),
  68                     clEnumValN(GenRegisterInfo, "gen-register-info",
  69                                "Generate registers and register classes info"),
  70                     clEnumValN(GenInstrInfo, "gen-instr-info",
  71                                "Generate instruction descriptions"),
  72                     clEnumValN(GenCallingConv, "gen-callingconv",
  73                                "Generate calling convention descriptions"),
  74                     clEnumValN(GenAsmWriter, "gen-asm-writer",
  75                                "Generate assembly writer"),
  76                     clEnumValN(GenDisassembler, "gen-disassembler",
  77                                "Generate disassembler"),
  78                     clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
  79                                "Generate pseudo instruction lowering"),
  80                     clEnumValN(GenAsmMatcher, "gen-asm-matcher",
  81                                "Generate assembly instruction matcher"),
  82                     clEnumValN(GenDAGISel, "gen-dag-isel",
  83                                "Generate a DAG instruction selector"),
  84                     clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
  85                                "Generate DFA Packetizer for VLIW targets"),
  86                     clEnumValN(GenFastISel, "gen-fast-isel",
  87                                "Generate a \"fast\" instruction selector"),
  88                     clEnumValN(GenSubtarget, "gen-subtarget",
  89                                "Generate subtarget enumerations"),
  90                     clEnumValN(GenIntrinsic, "gen-intrinsic",
  91                                "Generate intrinsic information"),
  92                     clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic",
  93                                "Generate target intrinsic information"),
  94                     clEnumValN(GenEDInfo, "gen-enhanced-disassembly-info",
  95                                "Generate enhanced disassembly info"),
  96                     clEnumValN(PrintEnums, "print-enums",
  97                                "Print enum values for a class"),
  98                     clEnumValN(PrintSets, "print-sets",
  99                                "Print expanded sets for testing DAG exprs"),
 100                     clEnumValEnd));
 101
 102   cl::opt<std::string>
 103   Class("class", cl::desc("Print Enum list for this class"),
 104           cl::value_desc("class name"));
 105
 106   class LLVMTableGenAction : public TableGenAction {
 107   public:
 108     bool operator()(raw_ostream &OS, RecordKeeper &Records) {
 109       switch (Action) {
 110       case PrintRecords:
 111         OS << Records;           // No argument, dump all contents
 112         break;
 113       case GenEmitter:
 114         CodeEmitterGen(Records).run(OS);
 115         break;
 116       case GenRegisterInfo:
 117         RegisterInfoEmitter(Records).run(OS);
 118         break;
 119       case GenInstrInfo:
 120         InstrInfoEmitter(Records).run(OS);
 121         break;
 122       case GenCallingConv:
 123         CallingConvEmitter(Records).run(OS);
 124         break;
 125       case GenAsmWriter:
 126         AsmWriterEmitter(Records).run(OS);
 127         break;
 128       case GenAsmMatcher:
 129         AsmMatcherEmitter(Records).run(OS);
 130         break;
 131       case GenDisassembler:
 132         DisassemblerEmitter(Records).run(OS);
 133         break;
 134       case GenPseudoLowering:
 135         PseudoLoweringEmitter(Records).run(OS);
 136         break;
 137       case GenDAGISel:
 138         DAGISelEmitter(Records).run(OS);
 139         break;
 140       case GenDFAPacketizer:
 141         DFAGen(Records).run(OS);
 142         break;
 143       case GenFastISel:
 144         FastISelEmitter(Records).run(OS);
 145         break;
 146       case GenSubtarget:
 147         SubtargetEmitter(Records).run(OS);
 148         break;
 149       case GenIntrinsic:
 150         IntrinsicEmitter(Records).run(OS);
 151         break;
 152       case GenTgtIntrinsic:
 153         IntrinsicEmitter(Records, true).run(OS);
 154         break;
 155       case GenEDInfo:
 156         EDEmitter(Records).run(OS);
 157         break;
 158       case PrintEnums:
 159       {
 160         std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
 161         for (unsigned i = 0, e = Recs.size(); i != e; ++i)
 162           OS << Recs[i]->getName() << ", ";
 163         OS << "\n";
 164         break;
 165       }
 166       case PrintSets:
 167       {
 168         SetTheory Sets;
 169         Sets.addFieldExpander("Set", "Elements");
 170         std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
 171         for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
 172           OS << Recs[i]->getName() << " = [";
 173           const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
 174           assert(Elts && "Couldn't expand Set instance");
 175           for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
 176             OS << ' ' << (*Elts)[ei]->getName();
 177           OS << " ]\n";
 178         }
 179         break;
 180       }
 181       }
 182
 183       return false;
 184     }
 185   };
 186 }
 187
 188 int main(int argc, char **argv) {
 189   sys::PrintStackTraceOnErrorSignal();
 190   PrettyStackTraceProgram X(argc, argv);
 191   cl::ParseCommandLineOptions(argc, argv);
 192
 193   LLVMTableGenAction Action;
 194   return TableGenMain(argv[0], Action);
 195 }