1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure
43 * Setups up the function pointers to no-op functions
45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 struct e1000_nvm_info *nvm = &hw->nvm;
48 DEBUGFUNC("e1000_init_nvm_ops_generic");
50 /* Initialize function pointers */
51 nvm->ops.init_params = e1000_null_ops_generic;
52 nvm->ops.acquire = e1000_null_ops_generic;
53 nvm->ops.read = e1000_null_read_nvm;
54 nvm->ops.release = e1000_null_nvm_generic;
55 nvm->ops.reload = e1000_reload_nvm_generic;
56 nvm->ops.update = e1000_null_ops_generic;
57 nvm->ops.valid_led_default = e1000_null_led_default;
58 nvm->ops.validate = e1000_null_ops_generic;
59 nvm->ops.write = e1000_null_write_nvm;
63 * e1000_null_nvm_read - No-op function, return 0
64 * @hw: pointer to the HW structure
66 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
68 DEBUGFUNC("e1000_null_read_nvm");
73 * e1000_null_nvm_generic - No-op function, return void
74 * @hw: pointer to the HW structure
76 void e1000_null_nvm_generic(struct e1000_hw *hw)
78 DEBUGFUNC("e1000_null_nvm_generic");
83 * e1000_null_led_default - No-op function, return 0
84 * @hw: pointer to the HW structure
86 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
88 DEBUGFUNC("e1000_null_led_default");
93 * e1000_null_write_nvm - No-op function, return 0
94 * @hw: pointer to the HW structure
96 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
98 DEBUGFUNC("e1000_null_write_nvm");
103 * e1000_raise_eec_clk - Raise EEPROM clock
104 * @hw: pointer to the HW structure
105 * @eecd: pointer to the EEPROM
107 * Enable/Raise the EEPROM clock bit.
109 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
111 *eecd = *eecd | E1000_EECD_SK;
112 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
113 E1000_WRITE_FLUSH(hw);
114 usec_delay(hw->nvm.delay_usec);
118 * e1000_lower_eec_clk - Lower EEPROM clock
119 * @hw: pointer to the HW structure
120 * @eecd: pointer to the EEPROM
122 * Clear/Lower the EEPROM clock bit.
124 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
126 *eecd = *eecd & ~E1000_EECD_SK;
127 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
128 E1000_WRITE_FLUSH(hw);
129 usec_delay(hw->nvm.delay_usec);
133 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
134 * @hw: pointer to the HW structure
135 * @data: data to send to the EEPROM
136 * @count: number of bits to shift out
138 * We need to shift 'count' bits out to the EEPROM. So, the value in the
139 * "data" parameter will be shifted out to the EEPROM one bit at a time.
140 * In order to do this, "data" must be broken down into bits.
142 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
144 struct e1000_nvm_info *nvm = &hw->nvm;
145 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
148 DEBUGFUNC("e1000_shift_out_eec_bits");
150 mask = 0x01 << (count - 1);
151 if (nvm->type == e1000_nvm_eeprom_microwire)
152 eecd &= ~E1000_EECD_DO;
154 if (nvm->type == e1000_nvm_eeprom_spi)
155 eecd |= E1000_EECD_DO;
158 eecd &= ~E1000_EECD_DI;
161 eecd |= E1000_EECD_DI;
163 E1000_WRITE_REG(hw, E1000_EECD, eecd);
164 E1000_WRITE_FLUSH(hw);
166 usec_delay(nvm->delay_usec);
168 e1000_raise_eec_clk(hw, &eecd);
169 e1000_lower_eec_clk(hw, &eecd);
174 eecd &= ~E1000_EECD_DI;
175 E1000_WRITE_REG(hw, E1000_EECD, eecd);
179 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
180 * @hw: pointer to the HW structure
181 * @count: number of bits to shift in
183 * In order to read a register from the EEPROM, we need to shift 'count' bits
184 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
185 * the EEPROM (setting the SK bit), and then reading the value of the data out
186 * "DO" bit. During this "shifting in" process the data in "DI" bit should
189 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
195 DEBUGFUNC("e1000_shift_in_eec_bits");
197 eecd = E1000_READ_REG(hw, E1000_EECD);
199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
202 for (i = 0; i < count; i++) {
204 e1000_raise_eec_clk(hw, &eecd);
206 eecd = E1000_READ_REG(hw, E1000_EECD);
208 eecd &= ~E1000_EECD_DI;
209 if (eecd & E1000_EECD_DO)
212 e1000_lower_eec_clk(hw, &eecd);
219 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
220 * @hw: pointer to the HW structure
221 * @ee_reg: EEPROM flag for polling
223 * Polls the EEPROM status bit for either read or write completion based
224 * upon the value of 'ee_reg'.
226 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
228 u32 attempts = 100000;
230 s32 ret_val = -E1000_ERR_NVM;
232 DEBUGFUNC("e1000_poll_eerd_eewr_done");
234 for (i = 0; i < attempts; i++) {
235 if (ee_reg == E1000_NVM_POLL_READ)
236 reg = E1000_READ_REG(hw, E1000_EERD);
238 reg = E1000_READ_REG(hw, E1000_EEWR);
240 if (reg & E1000_NVM_RW_REG_DONE) {
241 ret_val = E1000_SUCCESS;
252 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
253 * @hw: pointer to the HW structure
255 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
256 * Return successful if access grant bit set, else clear the request for
257 * EEPROM access and return -E1000_ERR_NVM (-1).
259 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
261 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
262 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
263 s32 ret_val = E1000_SUCCESS;
265 DEBUGFUNC("e1000_acquire_nvm_generic");
267 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
268 eecd = E1000_READ_REG(hw, E1000_EECD);
271 if (eecd & E1000_EECD_GNT)
274 eecd = E1000_READ_REG(hw, E1000_EECD);
279 eecd &= ~E1000_EECD_REQ;
280 E1000_WRITE_REG(hw, E1000_EECD, eecd);
281 DEBUGOUT("Could not acquire NVM grant\n");
282 ret_val = -E1000_ERR_NVM;
289 * e1000_standby_nvm - Return EEPROM to standby state
290 * @hw: pointer to the HW structure
292 * Return the EEPROM to a standby state.
294 static void e1000_standby_nvm(struct e1000_hw *hw)
296 struct e1000_nvm_info *nvm = &hw->nvm;
297 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
299 DEBUGFUNC("e1000_standby_nvm");
301 if (nvm->type == e1000_nvm_eeprom_microwire) {
302 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
303 E1000_WRITE_REG(hw, E1000_EECD, eecd);
304 E1000_WRITE_FLUSH(hw);
305 usec_delay(nvm->delay_usec);
307 e1000_raise_eec_clk(hw, &eecd);
310 eecd |= E1000_EECD_CS;
311 E1000_WRITE_REG(hw, E1000_EECD, eecd);
312 E1000_WRITE_FLUSH(hw);
313 usec_delay(nvm->delay_usec);
315 e1000_lower_eec_clk(hw, &eecd);
316 } else if (nvm->type == e1000_nvm_eeprom_spi) {
317 /* Toggle CS to flush commands */
318 eecd |= E1000_EECD_CS;
319 E1000_WRITE_REG(hw, E1000_EECD, eecd);
320 E1000_WRITE_FLUSH(hw);
321 usec_delay(nvm->delay_usec);
322 eecd &= ~E1000_EECD_CS;
323 E1000_WRITE_REG(hw, E1000_EECD, eecd);
324 E1000_WRITE_FLUSH(hw);
325 usec_delay(nvm->delay_usec);
330 * e1000_stop_nvm - Terminate EEPROM command
331 * @hw: pointer to the HW structure
333 * Terminates the current command by inverting the EEPROM's chip select pin.
335 void e1000_stop_nvm(struct e1000_hw *hw)
339 DEBUGFUNC("e1000_stop_nvm");
341 eecd = E1000_READ_REG(hw, E1000_EECD);
342 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
344 eecd |= E1000_EECD_CS;
345 e1000_lower_eec_clk(hw, &eecd);
346 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
347 /* CS on Microwire is active-high */
348 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
349 E1000_WRITE_REG(hw, E1000_EECD, eecd);
350 e1000_raise_eec_clk(hw, &eecd);
351 e1000_lower_eec_clk(hw, &eecd);
356 * e1000_release_nvm_generic - Release exclusive access to EEPROM
357 * @hw: pointer to the HW structure
359 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
361 void e1000_release_nvm_generic(struct e1000_hw *hw)
365 DEBUGFUNC("e1000_release_nvm_generic");
369 eecd = E1000_READ_REG(hw, E1000_EECD);
370 eecd &= ~E1000_EECD_REQ;
371 E1000_WRITE_REG(hw, E1000_EECD, eecd);
375 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
376 * @hw: pointer to the HW structure
378 * Setups the EEPROM for reading and writing.
380 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
382 struct e1000_nvm_info *nvm = &hw->nvm;
383 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
384 s32 ret_val = E1000_SUCCESS;
387 DEBUGFUNC("e1000_ready_nvm_eeprom");
389 if (nvm->type == e1000_nvm_eeprom_microwire) {
390 /* Clear SK and DI */
391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
392 E1000_WRITE_REG(hw, E1000_EECD, eecd);
394 eecd |= E1000_EECD_CS;
395 E1000_WRITE_REG(hw, E1000_EECD, eecd);
396 } else if (nvm->type == e1000_nvm_eeprom_spi) {
397 u16 timeout = NVM_MAX_RETRY_SPI;
399 /* Clear SK and CS */
400 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
401 E1000_WRITE_REG(hw, E1000_EECD, eecd);
402 E1000_WRITE_FLUSH(hw);
406 * Read "Status Register" repeatedly until the LSB is cleared.
407 * The EEPROM will signal that the command has been completed
408 * by clearing bit 0 of the internal status register. If it's
409 * not cleared within 'timeout', then error out.
412 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
413 hw->nvm.opcode_bits);
414 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
415 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
419 e1000_standby_nvm(hw);
424 DEBUGOUT("SPI NVM Status error\n");
425 ret_val = -E1000_ERR_NVM;
435 * e1000_read_nvm_spi - Read EEPROM's using SPI
436 * @hw: pointer to the HW structure
437 * @offset: offset of word in the EEPROM to read
438 * @words: number of words to read
439 * @data: word read from the EEPROM
441 * Reads a 16 bit word from the EEPROM.
443 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
445 struct e1000_nvm_info *nvm = &hw->nvm;
449 u8 read_opcode = NVM_READ_OPCODE_SPI;
451 DEBUGFUNC("e1000_read_nvm_spi");
454 * A check for invalid values: offset too large, too many words,
455 * and not enough words.
457 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
459 DEBUGOUT("nvm parameter(s) out of bounds\n");
460 ret_val = -E1000_ERR_NVM;
464 ret_val = nvm->ops.acquire(hw);
468 ret_val = e1000_ready_nvm_eeprom(hw);
472 e1000_standby_nvm(hw);
474 if ((nvm->address_bits == 8) && (offset >= 128))
475 read_opcode |= NVM_A8_OPCODE_SPI;
477 /* Send the READ command (opcode + addr) */
478 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
479 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
482 * Read the data. SPI NVMs increment the address with each byte
483 * read and will roll over if reading beyond the end. This allows
484 * us to read the whole NVM from any offset
486 for (i = 0; i < words; i++) {
487 word_in = e1000_shift_in_eec_bits(hw, 16);
488 data[i] = (word_in >> 8) | (word_in << 8);
492 nvm->ops.release(hw);
499 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
500 * @hw: pointer to the HW structure
501 * @offset: offset of word in the EEPROM to read
502 * @words: number of words to read
503 * @data: word read from the EEPROM
505 * Reads a 16 bit word from the EEPROM.
507 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
510 struct e1000_nvm_info *nvm = &hw->nvm;
513 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
515 DEBUGFUNC("e1000_read_nvm_microwire");
518 * A check for invalid values: offset too large, too many words,
519 * and not enough words.
521 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
523 DEBUGOUT("nvm parameter(s) out of bounds\n");
524 ret_val = -E1000_ERR_NVM;
528 ret_val = nvm->ops.acquire(hw);
532 ret_val = e1000_ready_nvm_eeprom(hw);
536 for (i = 0; i < words; i++) {
537 /* Send the READ command (opcode + addr) */
538 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
539 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
543 * Read the data. For microwire, each word requires the
544 * overhead of setup and tear-down.
546 data[i] = e1000_shift_in_eec_bits(hw, 16);
547 e1000_standby_nvm(hw);
551 nvm->ops.release(hw);
558 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
559 * @hw: pointer to the HW structure
560 * @offset: offset of word in the EEPROM to read
561 * @words: number of words to read
562 * @data: word read from the EEPROM
564 * Reads a 16 bit word from the EEPROM using the EERD register.
566 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
568 struct e1000_nvm_info *nvm = &hw->nvm;
570 s32 ret_val = E1000_SUCCESS;
572 DEBUGFUNC("e1000_read_nvm_eerd");
575 * A check for invalid values: offset too large, too many words,
576 * too many words for the offset, and not enough words.
578 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
580 DEBUGOUT("nvm parameter(s) out of bounds\n");
581 ret_val = -E1000_ERR_NVM;
585 for (i = 0; i < words; i++) {
586 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
587 E1000_NVM_RW_REG_START;
589 E1000_WRITE_REG(hw, E1000_EERD, eerd);
590 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
594 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
595 E1000_NVM_RW_REG_DATA);
603 * e1000_write_nvm_spi - Write to EEPROM using SPI
604 * @hw: pointer to the HW structure
605 * @offset: offset within the EEPROM to be written to
606 * @words: number of words to write
607 * @data: 16 bit word(s) to be written to the EEPROM
609 * Writes data to EEPROM at offset using SPI interface.
611 * If e1000_update_nvm_checksum is not called after this function , the
612 * EEPROM will most likely contain an invalid checksum.
614 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
616 struct e1000_nvm_info *nvm = &hw->nvm;
620 DEBUGFUNC("e1000_write_nvm_spi");
623 * A check for invalid values: offset too large, too many words,
624 * and not enough words.
626 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
628 DEBUGOUT("nvm parameter(s) out of bounds\n");
629 ret_val = -E1000_ERR_NVM;
633 ret_val = nvm->ops.acquire(hw);
637 while (widx < words) {
638 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
640 ret_val = e1000_ready_nvm_eeprom(hw);
644 e1000_standby_nvm(hw);
646 /* Send the WRITE ENABLE command (8 bit opcode) */
647 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
650 e1000_standby_nvm(hw);
653 * Some SPI eeproms use the 8th address bit embedded in the
656 if ((nvm->address_bits == 8) && (offset >= 128))
657 write_opcode |= NVM_A8_OPCODE_SPI;
659 /* Send the Write command (8-bit opcode + addr) */
660 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
661 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
664 /* Loop to allow for up to whole page write of eeprom */
665 while (widx < words) {
666 u16 word_out = data[widx];
667 word_out = (word_out >> 8) | (word_out << 8);
668 e1000_shift_out_eec_bits(hw, word_out, 16);
671 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
672 e1000_standby_nvm(hw);
680 nvm->ops.release(hw);
687 * e1000_write_nvm_microwire - Writes EEPROM using microwire
688 * @hw: pointer to the HW structure
689 * @offset: offset within the EEPROM to be written to
690 * @words: number of words to write
691 * @data: 16 bit word(s) to be written to the EEPROM
693 * Writes data to EEPROM at offset using microwire interface.
695 * If e1000_update_nvm_checksum is not called after this function , the
696 * EEPROM will most likely contain an invalid checksum.
698 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
701 struct e1000_nvm_info *nvm = &hw->nvm;
704 u16 words_written = 0;
707 DEBUGFUNC("e1000_write_nvm_microwire");
710 * A check for invalid values: offset too large, too many words,
711 * and not enough words.
713 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
715 DEBUGOUT("nvm parameter(s) out of bounds\n");
716 ret_val = -E1000_ERR_NVM;
720 ret_val = nvm->ops.acquire(hw);
724 ret_val = e1000_ready_nvm_eeprom(hw);
728 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
729 (u16)(nvm->opcode_bits + 2));
731 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
733 e1000_standby_nvm(hw);
735 while (words_written < words) {
736 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
739 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
742 e1000_shift_out_eec_bits(hw, data[words_written], 16);
744 e1000_standby_nvm(hw);
746 for (widx = 0; widx < 200; widx++) {
747 eecd = E1000_READ_REG(hw, E1000_EECD);
748 if (eecd & E1000_EECD_DO)
754 DEBUGOUT("NVM Write did not complete\n");
755 ret_val = -E1000_ERR_NVM;
759 e1000_standby_nvm(hw);
764 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
765 (u16)(nvm->opcode_bits + 2));
767 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
770 nvm->ops.release(hw);
777 * e1000_read_pba_string_generic - Read device part number
778 * @hw: pointer to the HW structure
779 * @pba_num: pointer to device part number
780 * @pba_num_size: size of part number buffer
782 * Reads the product board assembly (PBA) number from the EEPROM and stores
783 * the value in pba_num.
785 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
794 DEBUGFUNC("e1000_read_pba_string_generic");
796 if (pba_num == NULL) {
797 DEBUGOUT("PBA string buffer was null\n");
798 ret_val = E1000_ERR_INVALID_ARGUMENT;
802 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
804 DEBUGOUT("NVM Read Error\n");
808 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
810 DEBUGOUT("NVM Read Error\n");
815 * if nvm_data is not ptr guard the PBA must be in legacy format which
816 * means pba_ptr is actually our second data word for the PBA number
817 * and we can decode it into an ascii string
819 if (nvm_data != NVM_PBA_PTR_GUARD) {
820 DEBUGOUT("NVM PBA number is not stored as string\n");
822 /* we will need 11 characters to store the PBA */
823 if (pba_num_size < 11) {
824 DEBUGOUT("PBA string buffer too small\n");
825 return E1000_ERR_NO_SPACE;
828 /* extract hex string from data and pba_ptr */
829 pba_num[0] = (nvm_data >> 12) & 0xF;
830 pba_num[1] = (nvm_data >> 8) & 0xF;
831 pba_num[2] = (nvm_data >> 4) & 0xF;
832 pba_num[3] = nvm_data & 0xF;
833 pba_num[4] = (pba_ptr >> 12) & 0xF;
834 pba_num[5] = (pba_ptr >> 8) & 0xF;
837 pba_num[8] = (pba_ptr >> 4) & 0xF;
838 pba_num[9] = pba_ptr & 0xF;
840 /* put a null character on the end of our string */
843 /* switch all the data but the '-' to hex char */
844 for (offset = 0; offset < 10; offset++) {
845 if (pba_num[offset] < 0xA)
846 pba_num[offset] += '0';
847 else if (pba_num[offset] < 0x10)
848 pba_num[offset] += 'A' - 0xA;
854 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
856 DEBUGOUT("NVM Read Error\n");
860 if (length == 0xFFFF || length == 0) {
861 DEBUGOUT("NVM PBA number section invalid length\n");
862 ret_val = E1000_ERR_NVM_PBA_SECTION;
865 /* check if pba_num buffer is big enough */
866 if (pba_num_size < (((u32)length * 2) - 1)) {
867 DEBUGOUT("PBA string buffer too small\n");
868 ret_val = E1000_ERR_NO_SPACE;
872 /* trim pba length from start of string */
876 for (offset = 0; offset < length; offset++) {
877 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
879 DEBUGOUT("NVM Read Error\n");
882 pba_num[offset * 2] = (u8)(nvm_data >> 8);
883 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
885 pba_num[offset * 2] = '\0';
892 * e1000_read_pba_length_generic - Read device part number length
893 * @hw: pointer to the HW structure
894 * @pba_num_size: size of part number buffer
896 * Reads the product board assembly (PBA) number length from the EEPROM and
897 * stores the value in pba_num_size.
899 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
906 DEBUGFUNC("e1000_read_pba_length_generic");
908 if (pba_num_size == NULL) {
909 DEBUGOUT("PBA buffer size was null\n");
910 ret_val = E1000_ERR_INVALID_ARGUMENT;
914 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
916 DEBUGOUT("NVM Read Error\n");
920 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
922 DEBUGOUT("NVM Read Error\n");
926 /* if data is not ptr guard the PBA must be in legacy format */
927 if (nvm_data != NVM_PBA_PTR_GUARD) {
932 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
934 DEBUGOUT("NVM Read Error\n");
938 if (length == 0xFFFF || length == 0) {
939 DEBUGOUT("NVM PBA number section invalid length\n");
940 ret_val = E1000_ERR_NVM_PBA_SECTION;
945 * Convert from length in u16 values to u8 chars, add 1 for NULL,
946 * and subtract 2 because length field is included in length.
948 *pba_num_size = ((u32)length * 2) - 1;
955 * e1000_read_mac_addr_generic - Read device MAC address
956 * @hw: pointer to the HW structure
958 * Reads the device MAC address from the EEPROM and stores the value.
959 * Since devices with two ports use the same EEPROM, we increment the
960 * last bit in the MAC address for the second port.
962 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
968 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
969 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
971 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
972 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
974 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
975 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
977 for (i = 0; i < ETH_ADDR_LEN; i++)
978 hw->mac.addr[i] = hw->mac.perm_addr[i];
980 return E1000_SUCCESS;
984 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
985 * @hw: pointer to the HW structure
987 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
988 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
990 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
992 s32 ret_val = E1000_SUCCESS;
996 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
998 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
999 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1001 DEBUGOUT("NVM Read Error\n");
1004 checksum += nvm_data;
1007 if (checksum != (u16) NVM_SUM) {
1008 DEBUGOUT("NVM Checksum Invalid\n");
1009 ret_val = -E1000_ERR_NVM;
1018 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1019 * @hw: pointer to the HW structure
1021 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1022 * up to the checksum. Then calculates the EEPROM checksum and writes the
1023 * value to the EEPROM.
1025 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1031 DEBUGFUNC("e1000_update_nvm_checksum");
1033 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1034 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1036 DEBUGOUT("NVM Read Error while updating checksum.\n");
1039 checksum += nvm_data;
1041 checksum = (u16) NVM_SUM - checksum;
1042 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1044 DEBUGOUT("NVM Write Error while updating checksum.\n");
1051 * e1000_reload_nvm_generic - Reloads EEPROM
1052 * @hw: pointer to the HW structure
1054 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1055 * extended control register.
1057 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1061 DEBUGFUNC("e1000_reload_nvm_generic");
1064 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1065 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1066 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1067 E1000_WRITE_FLUSH(hw);