1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() || MF.hasMSInlineAsm() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned IsLP64) {
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
119 case X86::EH_RETURN64: {
120 SmallSet<uint16_t, 8> Uses;
121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MBBI->getOperand(i);
123 if (!MO.isReg() || MO.isDef())
125 unsigned Reg = MO.getReg();
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
134 if (!Uses.count(*CS))
143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
144 /// stack pointer by a constant value.
146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
147 unsigned StackPtr, int64_t NumBytes,
148 bool Is64Bit, bool IsLP64, bool UseLEA,
149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
154 Opc = getLEArOpcode(IsLP64);
157 ? getSUBriOpcode(IsLP64, Offset)
158 : getADDriOpcode(IsLP64, Offset);
160 uint64_t Chunk = (1LL << 31) - 1;
161 DebugLoc DL = MBB.findDebugLoc(MBBI);
164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
166 // Use push / pop instead.
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
205 unsigned StackPtr, uint64_t *NumBytes = NULL) {
206 if (MBBI == MBB.begin()) return;
208 MachineBasicBlock::iterator PI = prior(MBBI);
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
213 PI->getOperand(0).getReg() == StackPtr) {
215 *NumBytes += PI->getOperand(2).getImm();
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
219 PI->getOperand(0).getReg() == StackPtr) {
221 *NumBytes -= PI->getOperand(2).getImm();
226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
228 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = NULL) {
231 // FIXME: THIS ISN'T RUN!!!
234 if (MBBI == MBB.end()) return;
236 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 if (NI == MBB.end()) return;
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
242 NI->getOperand(0).getReg() == StackPtr) {
244 *NumBytes -= NI->getOperand(2).getImm();
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
249 NI->getOperand(0).getReg() == StackPtr) {
251 *NumBytes += NI->getOperand(2).getImm();
257 /// mergeSPUpdates - Checks the instruction before/after the passed
258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
261 static int mergeSPUpdates(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &MBBI,
264 bool doMergeWithPrevious) {
265 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
266 (!doMergeWithPrevious && MBBI == MBB.end()))
269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
277 PI->getOperand(0).getReg() == StackPtr){
278 Offset += PI->getOperand(2).getImm();
280 if (!doMergeWithPrevious) MBBI = NI;
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
283 PI->getOperand(0).getReg() == StackPtr) {
284 Offset -= PI->getOperand(2).getImm();
286 if (!doMergeWithPrevious) MBBI = NI;
292 static bool isEAXLiveIn(MachineFunction &MF) {
293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 unsigned FramePtr) const {
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineModuleInfo &MMI = MF.getMMI();
311 // Add callee saved registers to move list.
312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
313 if (CSI.empty()) return;
315 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
317 bool HasFP = hasFP(MF);
319 // Calculate amount of bytes used for return address storing.
320 int stackGrowth = -RegInfo->getSlotSize();
322 // FIXME: This is dirty hack. The code itself is pretty mess right now.
323 // It should be rewritten from scratch and generalized sometimes.
325 // Determine maximum offset (minimum due to stack growth).
326 int64_t MaxOffset = 0;
327 for (std::vector<CalleeSavedInfo>::const_iterator
328 I = CSI.begin(), E = CSI.end(); I != E; ++I)
329 MaxOffset = std::min(MaxOffset,
330 MFI->getObjectOffset(I->getFrameIdx()));
332 // Calculate offsets.
333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
334 for (std::vector<CalleeSavedInfo>::const_iterator
335 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
337 unsigned Reg = I->getReg();
338 Offset = MaxOffset - Offset + saveAreaOffset;
340 // Don't output a new machine move if we're re-saving the frame
341 // pointer. This happens when the PrologEpilogInserter has inserted an extra
342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
343 // generates one when frame pointers are used. If we generate a "machine
344 // move" for this extra "PUSH", the linker will lose track of the fact that
345 // the frame pointer should have the value of the first "PUSH" when it's
348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
349 // another bug. I.e., one where we generate a prolog like this:
357 // The immediate re-push of EBP is unnecessary. At the least, it's an
358 // optimization bug. EBP can be used as a scratch register in certain
359 // cases, but probably not when we have a frame pointer.
360 if (HasFP && FramePtr == Reg)
363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
364 MachineLocation CSSrc(Reg);
365 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
369 /// getCompactUnwindRegNum - Get the compact unwind number for a given
370 /// register. The number corresponds to the enum lists in
371 /// compact_unwind_encoding.h.
372 static int getCompactUnwindRegNum(unsigned Reg, bool is64Bit) {
373 static const uint16_t CU32BitRegs[] = {
374 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
376 static const uint16_t CU64BitRegs[] = {
377 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
379 const uint16_t *CURegs = is64Bit ? CU64BitRegs : CU32BitRegs;
380 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
387 // Number of registers that can be saved in a compact unwind encoding.
388 #define CU_NUM_SAVED_REGS 6
390 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
391 /// used with frameless stacks. It is passed the number of registers to be saved
392 /// and an array of the registers saved.
394 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
395 unsigned RegCount, bool Is64Bit) {
396 // The saved registers are numbered from 1 to 6. In order to encode the order
397 // in which they were saved, we re-number them according to their place in the
398 // register order. The re-numbering is relative to the last re-numbered
399 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
408 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
409 int CUReg = getCompactUnwindRegNum(SavedRegs[i], Is64Bit);
410 if (CUReg == -1) return ~0U;
411 SavedRegs[i] = CUReg;
415 std::swap(SavedRegs[0], SavedRegs[5]);
416 std::swap(SavedRegs[1], SavedRegs[4]);
417 std::swap(SavedRegs[2], SavedRegs[3]);
419 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
420 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
421 unsigned Countless = 0;
422 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
423 if (SavedRegs[j] < SavedRegs[i])
426 RenumRegs[i] = SavedRegs[i] - Countless - 1;
429 // Take the renumbered values and encode them into a 10-bit number.
430 uint32_t permutationEncoding = 0;
433 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
434 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
438 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
439 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
443 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
444 + 3 * RenumRegs[4] + RenumRegs[5];
447 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
451 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
454 permutationEncoding |= RenumRegs[5];
458 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
459 "Invalid compact register encoding!");
460 return permutationEncoding;
463 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
464 /// compact encoding with a frame pointer.
466 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
468 // Encode the registers in the order they were saved, 3-bits per register. The
469 // registers are numbered from 1 to CU_NUM_SAVED_REGS.
471 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) {
472 unsigned Reg = SavedRegs[I];
473 if (Reg == 0) continue;
475 int CURegNum = getCompactUnwindRegNum(Reg, Is64Bit);
476 if (CURegNum == -1) return ~0U;
478 // Encode the 3-bit register number in order, skipping over 3-bits for each
480 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
483 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
487 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
488 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
489 unsigned FramePtr = RegInfo->getFrameRegister(MF);
490 unsigned StackPtr = RegInfo->getStackRegister();
492 bool Is64Bit = STI.is64Bit();
493 bool HasFP = hasFP(MF);
495 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
496 unsigned SavedRegIdx = 0;
498 unsigned OffsetSize = (Is64Bit ? 8 : 4);
500 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
501 unsigned PushInstrSize = 1;
502 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
503 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
504 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
506 unsigned StackDivide = (Is64Bit ? 8 : 4);
508 unsigned InstrOffset = 0;
509 unsigned StackAdjust = 0;
510 unsigned StackSize = 0;
512 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
513 bool ExpectEnd = false;
514 for (MachineBasicBlock::iterator
515 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
516 MachineInstr &MI = *MBBI;
517 unsigned Opc = MI.getOpcode();
518 if (Opc == X86::PROLOG_LABEL) continue;
519 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
521 // We don't exect any more prolog instructions.
522 if (ExpectEnd) return CU::UNWIND_MODE_DWARF;
524 if (Opc == PushInstr) {
525 // If there are too many saved registers, we cannot use compact encoding.
526 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return CU::UNWIND_MODE_DWARF;
528 unsigned Reg = MI.getOperand(0).getReg();
529 if (Reg == (Is64Bit ? X86::RAX : X86::EAX)) {
534 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
535 StackAdjust += OffsetSize;
536 InstrOffset += PushInstrSize;
537 } else if (Opc == MoveInstr) {
538 unsigned SrcReg = MI.getOperand(1).getReg();
539 unsigned DstReg = MI.getOperand(0).getReg();
541 if (DstReg != FramePtr || SrcReg != StackPtr)
542 return CU::UNWIND_MODE_DWARF;
545 memset(SavedRegs, 0, sizeof(SavedRegs));
547 InstrOffset += MoveInstrSize;
548 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
549 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
551 // We already have a stack size.
552 return CU::UNWIND_MODE_DWARF;
554 if (!MI.getOperand(0).isReg() ||
555 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
556 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
557 // We need this to be a stack adjustment pointer. Something like:
559 // %RSP<def> = SUB64ri8 %RSP, 48
560 return CU::UNWIND_MODE_DWARF;
562 StackSize = MI.getOperand(2).getImm() / StackDivide;
563 SubtractInstrIdx += InstrOffset;
568 // Encode that we are using EBP/RBP as the frame pointer.
569 uint32_t CompactUnwindEncoding = 0;
570 StackAdjust /= StackDivide;
572 if ((StackAdjust & 0xFF) != StackAdjust)
573 // Offset was too big for compact encoding.
574 return CU::UNWIND_MODE_DWARF;
576 // Get the encoding of the saved registers when we have a frame pointer.
577 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
578 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
580 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
581 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
582 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
585 uint32_t TotalStackSize = StackAdjust + StackSize;
586 if ((TotalStackSize & 0xFF) == TotalStackSize) {
587 // Frameless stack with a small stack size.
588 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
590 // Encode the stack size.
591 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
593 if ((StackAdjust & 0x7) != StackAdjust)
594 // The extra stack adjustments are too big for us to handle.
595 return CU::UNWIND_MODE_DWARF;
597 // Frameless stack with an offset too large for us to encode compactly.
598 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
600 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
602 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
604 // Encode any extra stack stack adjustments (done via push instructions).
605 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
608 // Encode the number of registers saved.
609 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
611 // Get the encoding of the saved registers when we don't have a frame
614 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
616 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
618 // Encode the register encoding.
619 CompactUnwindEncoding |=
620 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
623 return CompactUnwindEncoding;
626 /// usesTheStack - This function checks if any of the users of EFLAGS
627 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
628 /// to use the stack, and if we don't adjust the stack we clobber the first
630 /// See X86InstrInfo::copyPhysReg.
631 static bool usesTheStack(MachineFunction &MF) {
632 MachineRegisterInfo &MRI = MF.getRegInfo();
634 for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS),
635 re = MRI.reg_end(); ri != re; ++ri)
642 /// emitPrologue - Push callee-saved registers onto the stack, which
643 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
644 /// space for local variables. Also emit labels used by the exception handler to
645 /// generate the exception handling frames.
646 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
647 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
648 MachineBasicBlock::iterator MBBI = MBB.begin();
649 MachineFrameInfo *MFI = MF.getFrameInfo();
650 const Function *Fn = MF.getFunction();
651 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
652 const X86InstrInfo &TII = *TM.getInstrInfo();
653 MachineModuleInfo &MMI = MF.getMMI();
654 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
655 bool needsFrameMoves = MMI.hasDebugInfo() ||
656 Fn->needsUnwindTableEntry();
657 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
658 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
659 bool HasFP = hasFP(MF);
660 bool Is64Bit = STI.is64Bit();
661 bool IsLP64 = STI.isTarget64BitLP64();
662 bool IsWin64 = STI.isTargetWin64();
663 bool UseLEA = STI.useLeaForSP();
664 unsigned StackAlign = getStackAlignment();
665 unsigned SlotSize = RegInfo->getSlotSize();
666 unsigned FramePtr = RegInfo->getFrameRegister(MF);
667 unsigned StackPtr = RegInfo->getStackRegister();
668 unsigned BasePtr = RegInfo->getBaseRegister();
671 // If we're forcing a stack realignment we can't rely on just the frame
672 // info, we need to know the ABI stack alignment as well in case we
673 // have a call out. Otherwise just make sure we have some alignment - we'll
674 // go with the minimum SlotSize.
675 if (ForceStackAlign) {
677 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
678 else if (MaxAlign < SlotSize)
682 // Add RETADDR move area to callee saved frame size.
683 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
684 if (TailCallReturnAddrDelta < 0)
685 X86FI->setCalleeSavedFrameSize(
686 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
688 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
689 // function, and use up to 128 bytes of stack space, don't have a frame
690 // pointer, calls, or dynamic alloca then we do not need to adjust the
691 // stack pointer (we fit in the Red Zone). We also check that we don't
692 // push and pop from the stack.
693 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
694 Attribute::NoRedZone) &&
695 !RegInfo->needsStackRealignment(MF) &&
696 !MFI->hasVarSizedObjects() && // No dynamic alloca.
697 !MFI->adjustsStack() && // No calls.
698 !IsWin64 && // Win64 has no Red Zone
699 !usesTheStack(MF) && // Don't push and pop.
700 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
701 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
702 if (HasFP) MinSize += SlotSize;
703 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
704 MFI->setStackSize(StackSize);
707 // Insert stack pointer adjustment for later moving of return addr. Only
708 // applies to tail call optimized functions where the callee argument stack
709 // size is bigger than the callers.
710 if (TailCallReturnAddrDelta < 0) {
712 BuildMI(MBB, MBBI, DL,
713 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
716 .addImm(-TailCallReturnAddrDelta)
717 .setMIFlag(MachineInstr::FrameSetup);
718 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
721 // Mapping for machine moves:
723 // DST: VirtualFP AND
724 // SRC: VirtualFP => DW_CFA_def_cfa_offset
725 // ELSE => DW_CFA_def_cfa
727 // SRC: VirtualFP AND
728 // DST: Register => DW_CFA_def_cfa_register
731 // OFFSET < 0 => DW_CFA_offset_extended_sf
732 // REG < 64 => DW_CFA_offset + Reg
733 // ELSE => DW_CFA_offset_extended
735 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
736 uint64_t NumBytes = 0;
737 int stackGrowth = -SlotSize;
740 // Calculate required stack adjustment.
741 uint64_t FrameSize = StackSize - SlotSize;
742 if (RegInfo->needsStackRealignment(MF)) {
743 // Callee-saved registers are pushed on stack before the stack
745 FrameSize -= X86FI->getCalleeSavedFrameSize();
746 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
748 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
751 // Get the offset of the stack slot for the EBP register, which is
752 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
753 // Update the frame offset adjustment.
754 MFI->setOffsetAdjustment(-NumBytes);
756 // Save EBP/RBP into the appropriate stack slot.
757 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
758 .addReg(FramePtr, RegState::Kill)
759 .setMIFlag(MachineInstr::FrameSetup);
761 if (needsFrameMoves) {
762 // Mark the place where EBP/RBP was saved.
763 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
764 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
767 // Define the current CFA rule to use the provided offset.
769 MachineLocation SPDst(MachineLocation::VirtualFP);
770 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
771 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
773 MachineLocation SPDst(StackPtr);
774 MachineLocation SPSrc(StackPtr, stackGrowth);
775 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
778 // Change the rule for the FramePtr to be an "offset" rule.
779 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
780 MachineLocation FPSrc(FramePtr);
781 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
784 // Update EBP with the new base value.
785 BuildMI(MBB, MBBI, DL,
786 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
788 .setMIFlag(MachineInstr::FrameSetup);
790 if (needsFrameMoves) {
791 // Mark effective beginning of when frame pointer becomes valid.
792 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
793 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
796 // Define the current CFA to use the EBP/RBP register.
797 MachineLocation FPDst(FramePtr);
798 MachineLocation FPSrc(MachineLocation::VirtualFP);
799 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
802 // Mark the FramePtr as live-in in every block except the entry.
803 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
805 I->addLiveIn(FramePtr);
807 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
810 // Skip the callee-saved push instructions.
811 bool PushedRegs = false;
812 int StackOffset = 2 * stackGrowth;
814 while (MBBI != MBB.end() &&
815 (MBBI->getOpcode() == X86::PUSH32r ||
816 MBBI->getOpcode() == X86::PUSH64r)) {
818 MBBI->setFlag(MachineInstr::FrameSetup);
821 if (!HasFP && needsFrameMoves) {
822 // Mark callee-saved push instruction.
823 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
824 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
826 // Define the current CFA rule to use the provided offset.
827 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
828 MachineLocation SPDst(Ptr);
829 MachineLocation SPSrc(Ptr, StackOffset);
830 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
831 StackOffset += stackGrowth;
835 // Realign stack after we pushed callee-saved registers (so that we'll be
836 // able to calculate their offsets from the frame pointer).
838 // NOTE: We push the registers before realigning the stack, so
839 // vector callee-saved (xmm) registers may be saved w/o proper
840 // alignment in this way. However, currently these regs are saved in
841 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
842 // this shouldn't be a problem.
843 if (RegInfo->needsStackRealignment(MF)) {
844 assert(HasFP && "There should be a frame pointer if stack is realigned.");
846 BuildMI(MBB, MBBI, DL,
847 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
850 .setMIFlag(MachineInstr::FrameSetup);
852 // The EFLAGS implicit def is dead.
853 MI->getOperand(3).setIsDead();
856 // If there is an SUB32ri of ESP immediately before this instruction, merge
857 // the two. This can be the case when tail call elimination is enabled and
858 // the callee has more arguments then the caller.
859 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
861 // If there is an ADD32ri or SUB32ri of ESP immediately after this
862 // instruction, merge the two instructions.
863 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
865 // Adjust stack pointer: ESP -= numbytes.
867 // Windows and cygwin/mingw require a prologue helper routine when allocating
868 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
869 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
870 // stack and adjust the stack pointer in one go. The 64-bit version of
871 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
872 // responsible for adjusting the stack pointer. Touching the stack at 4K
873 // increments is necessary to ensure that the guard pages used by the OS
874 // virtual memory manager are allocated in correct sequence.
875 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
876 const char *StackProbeSymbol;
877 bool isSPUpdateNeeded = false;
880 if (STI.isTargetCygMing())
881 StackProbeSymbol = "___chkstk";
883 StackProbeSymbol = "__chkstk";
884 isSPUpdateNeeded = true;
886 } else if (STI.isTargetCygMing())
887 StackProbeSymbol = "_alloca";
889 StackProbeSymbol = "_chkstk";
891 // Check whether EAX is livein for this function.
892 bool isEAXAlive = isEAXLiveIn(MF);
895 // Sanity check that EAX is not livein for this function.
896 // It should not be, so throw an assert.
897 assert(!Is64Bit && "EAX is livein in x64 case!");
900 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
901 .addReg(X86::EAX, RegState::Kill)
902 .setMIFlag(MachineInstr::FrameSetup);
906 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
907 // Function prologue is responsible for adjusting the stack pointer.
908 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
910 .setMIFlag(MachineInstr::FrameSetup);
912 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
913 // We'll also use 4 already allocated bytes for EAX.
914 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
915 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
916 .setMIFlag(MachineInstr::FrameSetup);
919 BuildMI(MBB, MBBI, DL,
920 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
921 .addExternalSymbol(StackProbeSymbol)
922 .addReg(StackPtr, RegState::Define | RegState::Implicit)
923 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
924 .setMIFlag(MachineInstr::FrameSetup);
926 // MSVC x64's __chkstk needs to adjust %rsp.
927 // FIXME: %rax preserves the offset and should be available.
928 if (isSPUpdateNeeded)
929 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
930 UseLEA, TII, *RegInfo);
934 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
936 StackPtr, false, NumBytes - 4);
937 MI->setFlag(MachineInstr::FrameSetup);
938 MBB.insert(MBBI, MI);
941 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
942 UseLEA, TII, *RegInfo);
944 // If we need a base pointer, set it up here. It's whatever the value
945 // of the stack pointer is at this point. Any variable size objects
946 // will be allocated after this, so we can still use the base pointer
947 // to reference locals.
948 if (RegInfo->hasBasePointer(MF)) {
949 // Update the frame pointer with the current stack pointer.
950 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
951 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
953 .setMIFlag(MachineInstr::FrameSetup);
956 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
957 // Mark end of stack pointer adjustment.
958 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
959 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
962 if (!HasFP && NumBytes) {
963 // Define the current CFA rule to use the provided offset.
965 MachineLocation SPDst(MachineLocation::VirtualFP);
966 MachineLocation SPSrc(MachineLocation::VirtualFP,
967 -StackSize + stackGrowth);
968 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
970 MachineLocation SPDst(StackPtr);
971 MachineLocation SPSrc(StackPtr, stackGrowth);
972 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
976 // Emit DWARF info specifying the offsets of the callee-saved registers.
978 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
981 // Darwin 10.7 and greater has support for compact unwind encoding.
982 if (STI.getTargetTriple().isMacOSX() &&
983 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
984 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
987 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
988 MachineBasicBlock &MBB) const {
989 const MachineFrameInfo *MFI = MF.getFrameInfo();
990 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
991 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
992 const X86InstrInfo &TII = *TM.getInstrInfo();
993 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
994 assert(MBBI != MBB.end() && "Returning block has no instructions");
995 unsigned RetOpcode = MBBI->getOpcode();
996 DebugLoc DL = MBBI->getDebugLoc();
997 bool Is64Bit = STI.is64Bit();
998 bool IsLP64 = STI.isTarget64BitLP64();
999 bool UseLEA = STI.useLeaForSP();
1000 unsigned StackAlign = getStackAlignment();
1001 unsigned SlotSize = RegInfo->getSlotSize();
1002 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1003 unsigned StackPtr = RegInfo->getStackRegister();
1005 switch (RetOpcode) {
1007 llvm_unreachable("Can only insert epilog into returning blocks");
1010 case X86::TCRETURNdi:
1011 case X86::TCRETURNri:
1012 case X86::TCRETURNmi:
1013 case X86::TCRETURNdi64:
1014 case X86::TCRETURNri64:
1015 case X86::TCRETURNmi64:
1016 case X86::EH_RETURN:
1017 case X86::EH_RETURN64:
1018 break; // These are ok
1021 // Get the number of bytes to allocate from the FrameInfo.
1022 uint64_t StackSize = MFI->getStackSize();
1023 uint64_t MaxAlign = MFI->getMaxAlignment();
1024 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1025 uint64_t NumBytes = 0;
1027 // If we're forcing a stack realignment we can't rely on just the frame
1028 // info, we need to know the ABI stack alignment as well in case we
1029 // have a call out. Otherwise just make sure we have some alignment - we'll
1030 // go with the minimum.
1031 if (ForceStackAlign) {
1032 if (MFI->hasCalls())
1033 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1035 MaxAlign = MaxAlign ? MaxAlign : 4;
1039 // Calculate required stack adjustment.
1040 uint64_t FrameSize = StackSize - SlotSize;
1041 if (RegInfo->needsStackRealignment(MF)) {
1042 // Callee-saved registers were pushed on stack before the stack
1044 FrameSize -= CSSize;
1045 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1047 NumBytes = FrameSize - CSSize;
1051 BuildMI(MBB, MBBI, DL,
1052 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1054 NumBytes = StackSize - CSSize;
1057 // Skip the callee-saved pop instructions.
1058 while (MBBI != MBB.begin()) {
1059 MachineBasicBlock::iterator PI = prior(MBBI);
1060 unsigned Opc = PI->getOpcode();
1062 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1063 !PI->isTerminator())
1068 MachineBasicBlock::iterator FirstCSPop = MBBI;
1070 DL = MBBI->getDebugLoc();
1072 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1073 // instruction, merge the two instructions.
1074 if (NumBytes || MFI->hasVarSizedObjects())
1075 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1077 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1078 // slot before popping them off! Same applies for the case, when stack was
1080 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1081 if (RegInfo->needsStackRealignment(MF))
1084 unsigned Opc = getLEArOpcode(IsLP64);
1085 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1086 FramePtr, false, -CSSize);
1088 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1089 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1092 } else if (NumBytes) {
1093 // Adjust stack pointer back: ESP += numbytes.
1094 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
1098 // We're returning from function via eh_return.
1099 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1100 MBBI = MBB.getLastNonDebugInstr();
1101 MachineOperand &DestAddr = MBBI->getOperand(0);
1102 assert(DestAddr.isReg() && "Offset should be in register!");
1103 BuildMI(MBB, MBBI, DL,
1104 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1105 StackPtr).addReg(DestAddr.getReg());
1106 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1107 RetOpcode == X86::TCRETURNmi ||
1108 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1109 RetOpcode == X86::TCRETURNmi64) {
1110 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1111 // Tail call return: adjust the stack pointer and jump to callee.
1112 MBBI = MBB.getLastNonDebugInstr();
1113 MachineOperand &JumpTarget = MBBI->getOperand(0);
1114 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1115 assert(StackAdjust.isImm() && "Expecting immediate value.");
1117 // Adjust stack pointer.
1118 int StackAdj = StackAdjust.getImm();
1119 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1121 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1123 // Incoporate the retaddr area.
1124 Offset = StackAdj-MaxTCDelta;
1125 assert(Offset >= 0 && "Offset should never be negative");
1128 // Check for possible merge with preceding ADD instruction.
1129 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1130 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
1131 UseLEA, TII, *RegInfo);
1134 // Jump to label or value in register.
1135 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1136 MachineInstrBuilder MIB =
1137 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1138 ? X86::TAILJMPd : X86::TAILJMPd64));
1139 if (JumpTarget.isGlobal())
1140 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1141 JumpTarget.getTargetFlags());
1143 assert(JumpTarget.isSymbol());
1144 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1145 JumpTarget.getTargetFlags());
1147 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1148 MachineInstrBuilder MIB =
1149 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1150 ? X86::TAILJMPm : X86::TAILJMPm64));
1151 for (unsigned i = 0; i != 5; ++i)
1152 MIB.addOperand(MBBI->getOperand(i));
1153 } else if (RetOpcode == X86::TCRETURNri64) {
1154 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1155 addReg(JumpTarget.getReg(), RegState::Kill);
1157 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1158 addReg(JumpTarget.getReg(), RegState::Kill);
1161 MachineInstr *NewMI = prior(MBBI);
1162 NewMI->copyImplicitOps(MF, MBBI);
1164 // Delete the pseudo instruction TCRETURN.
1166 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1167 (X86FI->getTCReturnAddrDelta() < 0)) {
1168 // Add the return addr area delta back since we are not tail calling.
1169 int delta = -1*X86FI->getTCReturnAddrDelta();
1170 MBBI = MBB.getLastNonDebugInstr();
1172 // Check for possible merge with preceding ADD instruction.
1173 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1174 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1179 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1180 const X86RegisterInfo *RegInfo =
1181 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1182 const MachineFrameInfo *MFI = MF.getFrameInfo();
1183 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1184 uint64_t StackSize = MFI->getStackSize();
1186 if (RegInfo->hasBasePointer(MF)) {
1187 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1189 // Skip the saved EBP.
1190 return Offset + RegInfo->getSlotSize();
1192 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1193 return Offset + StackSize;
1195 } else if (RegInfo->needsStackRealignment(MF)) {
1197 // Skip the saved EBP.
1198 return Offset + RegInfo->getSlotSize();
1200 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1201 return Offset + StackSize;
1203 // FIXME: Support tail calls
1206 return Offset + StackSize;
1208 // Skip the saved EBP.
1209 Offset += RegInfo->getSlotSize();
1211 // Skip the RETADDR move area
1212 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1213 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1214 if (TailCallReturnAddrDelta < 0)
1215 Offset -= TailCallReturnAddrDelta;
1221 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1222 unsigned &FrameReg) const {
1223 const X86RegisterInfo *RegInfo =
1224 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1225 // We can't calculate offset from frame pointer if the stack is realigned,
1226 // so enforce usage of stack/base pointer. The base pointer is used when we
1227 // have dynamic allocas in addition to dynamic realignment.
1228 if (RegInfo->hasBasePointer(MF))
1229 FrameReg = RegInfo->getBaseRegister();
1230 else if (RegInfo->needsStackRealignment(MF))
1231 FrameReg = RegInfo->getStackRegister();
1233 FrameReg = RegInfo->getFrameRegister(MF);
1234 return getFrameIndexOffset(MF, FI);
1237 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1238 MachineBasicBlock::iterator MI,
1239 const std::vector<CalleeSavedInfo> &CSI,
1240 const TargetRegisterInfo *TRI) const {
1244 DebugLoc DL = MBB.findDebugLoc(MI);
1246 MachineFunction &MF = *MBB.getParent();
1248 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1249 unsigned FPReg = TRI->getFrameRegister(MF);
1250 unsigned CalleeFrameSize = 0;
1252 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1253 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1255 // Push GPRs. It increases frame size.
1256 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1257 for (unsigned i = CSI.size(); i != 0; --i) {
1258 unsigned Reg = CSI[i-1].getReg();
1259 if (!X86::GR64RegClass.contains(Reg) &&
1260 !X86::GR32RegClass.contains(Reg))
1262 // Add the callee-saved register as live-in. It's killed at the spill.
1265 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1267 CalleeFrameSize += SlotSize;
1268 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1269 .setMIFlag(MachineInstr::FrameSetup);
1272 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1274 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1275 // It can be done by spilling XMMs to stack frame.
1276 // Note that only Win64 ABI might spill XMMs.
1277 for (unsigned i = CSI.size(); i != 0; --i) {
1278 unsigned Reg = CSI[i-1].getReg();
1279 if (X86::GR64RegClass.contains(Reg) ||
1280 X86::GR32RegClass.contains(Reg))
1282 // Add the callee-saved register as live-in. It's killed at the spill.
1284 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1285 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1292 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1293 MachineBasicBlock::iterator MI,
1294 const std::vector<CalleeSavedInfo> &CSI,
1295 const TargetRegisterInfo *TRI) const {
1299 DebugLoc DL = MBB.findDebugLoc(MI);
1301 MachineFunction &MF = *MBB.getParent();
1302 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1304 // Reload XMMs from stack frame.
1305 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1306 unsigned Reg = CSI[i].getReg();
1307 if (X86::GR64RegClass.contains(Reg) ||
1308 X86::GR32RegClass.contains(Reg))
1310 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1311 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1316 unsigned FPReg = TRI->getFrameRegister(MF);
1317 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1318 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1319 unsigned Reg = CSI[i].getReg();
1320 if (!X86::GR64RegClass.contains(Reg) &&
1321 !X86::GR32RegClass.contains(Reg))
1324 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1326 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1332 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1333 RegScavenger *RS) const {
1334 MachineFrameInfo *MFI = MF.getFrameInfo();
1335 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1336 unsigned SlotSize = RegInfo->getSlotSize();
1338 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1339 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1341 if (TailCallReturnAddrDelta < 0) {
1342 // create RETURNADDR area
1351 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1352 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1356 assert((TailCallReturnAddrDelta <= 0) &&
1357 "The Delta should always be zero or negative");
1358 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1360 // Create a frame entry for the EBP register that must be saved.
1361 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1363 TFI.getOffsetOfLocalArea() +
1364 TailCallReturnAddrDelta,
1366 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1367 "Slot for EBP register must be last in order to be found!");
1371 // Spill the BasePtr if it's used.
1372 if (RegInfo->hasBasePointer(MF))
1373 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1377 HasNestArgument(const MachineFunction *MF) {
1378 const Function *F = MF->getFunction();
1379 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1381 if (I->hasNestAttr())
1387 /// GetScratchRegister - Get a temp register for performing work in the
1388 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1389 /// and the properties of the function either one or two registers will be
1390 /// needed. Set primary to true for the first register, false for the second.
1392 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1393 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1396 if (CallingConvention == CallingConv::HiPE) {
1398 return Primary ? X86::R14 : X86::R13;
1400 return Primary ? X86::EBX : X86::EDI;
1404 return Primary ? X86::R11 : X86::R12;
1406 bool IsNested = HasNestArgument(&MF);
1408 if (CallingConvention == CallingConv::X86_FastCall ||
1409 CallingConvention == CallingConv::Fast) {
1411 report_fatal_error("Segmented stacks does not support fastcall with "
1412 "nested function.");
1413 return Primary ? X86::EAX : X86::ECX;
1416 return Primary ? X86::EDX : X86::EAX;
1417 return Primary ? X86::ECX : X86::EAX;
1420 // The stack limit in the TCB is set to this many bytes above the actual stack
1422 static const uint64_t kSplitStackAvailable = 256;
1425 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1426 MachineBasicBlock &prologueMBB = MF.front();
1427 MachineFrameInfo *MFI = MF.getFrameInfo();
1428 const X86InstrInfo &TII = *TM.getInstrInfo();
1430 bool Is64Bit = STI.is64Bit();
1431 unsigned TlsReg, TlsOffset;
1434 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1435 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1436 "Scratch register is live-in");
1438 if (MF.getFunction()->isVarArg())
1439 report_fatal_error("Segmented stacks do not support vararg functions.");
1440 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1441 !STI.isTargetWin32() && !STI.isTargetFreeBSD())
1442 report_fatal_error("Segmented stacks not supported on this platform.");
1444 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1445 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1446 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1447 bool IsNested = false;
1449 // We need to know if the function has a nest argument only in 64 bit mode.
1451 IsNested = HasNestArgument(&MF);
1453 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1454 // allocMBB needs to be last (terminating) instruction.
1456 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1457 e = prologueMBB.livein_end(); i != e; i++) {
1458 allocMBB->addLiveIn(*i);
1459 checkMBB->addLiveIn(*i);
1463 allocMBB->addLiveIn(X86::R10);
1465 MF.push_front(allocMBB);
1466 MF.push_front(checkMBB);
1468 // Eventually StackSize will be calculated by a link-time pass; which will
1469 // also decide whether checking code needs to be injected into this particular
1471 StackSize = MFI->getStackSize();
1473 // When the frame size is less than 256 we just compare the stack
1474 // boundary directly to the value of the stack pointer, per gcc.
1475 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1477 // Read the limit off the current stacklet off the stack_guard location.
1479 if (STI.isTargetLinux()) {
1482 } else if (STI.isTargetDarwin()) {
1484 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1485 } else if (STI.isTargetFreeBSD()) {
1489 report_fatal_error("Segmented stacks not supported on this platform.");
1492 if (CompareStackPointer)
1493 ScratchReg = X86::RSP;
1495 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1496 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1498 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1499 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1501 if (STI.isTargetLinux()) {
1504 } else if (STI.isTargetDarwin()) {
1506 TlsOffset = 0x48 + 90*4;
1507 } else if (STI.isTargetWin32()) {
1509 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1510 } else if (STI.isTargetFreeBSD()) {
1511 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1513 report_fatal_error("Segmented stacks not supported on this platform.");
1516 if (CompareStackPointer)
1517 ScratchReg = X86::ESP;
1519 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1520 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1522 if (STI.isTargetLinux() || STI.isTargetWin32()) {
1523 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1524 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1525 } else if (STI.isTargetDarwin()) {
1527 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1528 unsigned ScratchReg2;
1530 if (CompareStackPointer) {
1531 // The primary scratch register is available for holding the TLS offset
1532 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1533 SaveScratch2 = false;
1535 // Need to use a second register to hold the TLS offset
1536 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1538 // Unfortunately, with fastcc the second scratch register may hold an arg
1539 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1542 // If Scratch2 is live-in then it needs to be saved
1543 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1544 "Scratch register is live-in and not saved");
1547 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1548 .addReg(ScratchReg2, RegState::Kill);
1550 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1552 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1554 .addReg(ScratchReg2).addImm(1).addReg(0)
1559 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1563 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1564 // It jumps to normal execution of the function body.
1565 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1567 // On 32 bit we first push the arguments size and then the frame size. On 64
1568 // bit, we pass the stack frame size in r10 and the argument size in r11.
1570 // Functions with nested arguments use R10, so it needs to be saved across
1571 // the call to _morestack
1574 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1576 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1578 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1579 .addImm(X86FI->getArgumentStackSize());
1580 MF.getRegInfo().setPhysRegUsed(X86::R10);
1581 MF.getRegInfo().setPhysRegUsed(X86::R11);
1583 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1584 .addImm(X86FI->getArgumentStackSize());
1585 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1589 // __morestack is in libgcc
1591 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1592 .addExternalSymbol("__morestack");
1594 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1595 .addExternalSymbol("__morestack");
1598 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1600 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1602 allocMBB->addSuccessor(&prologueMBB);
1604 checkMBB->addSuccessor(allocMBB);
1605 checkMBB->addSuccessor(&prologueMBB);
1612 /// Erlang programs may need a special prologue to handle the stack size they
1613 /// might need at runtime. That is because Erlang/OTP does not implement a C
1614 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1615 /// (for more information see Eric Stenman's Ph.D. thesis:
1616 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1619 /// temp0 = sp - MaxStack
1620 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1624 /// call inc_stack # doubles the stack space
1625 /// temp0 = sp - MaxStack
1626 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1627 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1628 const X86InstrInfo &TII = *TM.getInstrInfo();
1629 MachineFrameInfo *MFI = MF.getFrameInfo();
1630 const unsigned SlotSize = TM.getRegisterInfo()->getSlotSize();
1631 const bool Is64Bit = STI.is64Bit();
1633 // HiPE-specific values
1634 const unsigned HipeLeafWords = 24;
1635 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1636 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1637 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1638 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1639 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1641 assert(STI.isTargetLinux() &&
1642 "HiPE prologue is only supported on Linux operating systems.");
1644 // Compute the largest caller's frame that is needed to fit the callees'
1645 // frames. This 'MaxStack' is computed from:
1647 // a) the fixed frame size, which is the space needed for all spilled temps,
1648 // b) outgoing on-stack parameter areas, and
1649 // c) the minimum stack space this function needs to make available for the
1650 // functions it calls (a tunable ABI property).
1651 if (MFI->hasCalls()) {
1652 unsigned MoreStackForCalls = 0;
1654 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1655 MBBI != MBBE; ++MBBI)
1656 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1661 // Get callee operand.
1662 const MachineOperand &MO = MI->getOperand(0);
1664 // Only take account of global function calls (no closures etc.).
1668 const Function *F = dyn_cast<Function>(MO.getGlobal());
1672 // Do not update 'MaxStack' for primitive and built-in functions
1673 // (encoded with names either starting with "erlang."/"bif_" or not
1674 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1675 // "_", such as the BIF "suspend_0") as they are executed on another
1677 if (F->getName().find("erlang.") != StringRef::npos ||
1678 F->getName().find("bif_") != StringRef::npos ||
1679 F->getName().find_first_of("._") == StringRef::npos)
1682 unsigned CalleeStkArity =
1683 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1684 if (HipeLeafWords - 1 > CalleeStkArity)
1685 MoreStackForCalls = std::max(MoreStackForCalls,
1686 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1688 MaxStack += MoreStackForCalls;
1691 // If the stack frame needed is larger than the guaranteed then runtime checks
1692 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1693 if (MaxStack > Guaranteed) {
1694 MachineBasicBlock &prologueMBB = MF.front();
1695 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1696 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1698 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1699 E = prologueMBB.livein_end(); I != E; I++) {
1700 stackCheckMBB->addLiveIn(*I);
1701 incStackMBB->addLiveIn(*I);
1704 MF.push_front(incStackMBB);
1705 MF.push_front(stackCheckMBB);
1707 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1708 unsigned LEAop, CMPop, CALLop;
1712 LEAop = X86::LEA64r;
1713 CMPop = X86::CMP64rm;
1714 CALLop = X86::CALL64pcrel32;
1715 SPLimitOffset = 0x90;
1719 LEAop = X86::LEA32r;
1720 CMPop = X86::CMP32rm;
1721 CALLop = X86::CALLpcrel32;
1722 SPLimitOffset = 0x4c;
1725 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1726 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1727 "HiPE prologue scratch register is live-in");
1729 // Create new MBB for StackCheck:
1730 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1731 SPReg, false, -MaxStack);
1732 // SPLimitOffset is in a fixed heap location (pointed by BP).
1733 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1734 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1735 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1737 // Create new MBB for IncStack:
1738 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1739 addExternalSymbol("inc_stack_0");
1740 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1741 SPReg, false, -MaxStack);
1742 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1743 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1744 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1746 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1747 stackCheckMBB->addSuccessor(incStackMBB, 1);
1748 incStackMBB->addSuccessor(&prologueMBB, 99);
1749 incStackMBB->addSuccessor(incStackMBB, 1);
1756 void X86FrameLowering::
1757 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1758 MachineBasicBlock::iterator I) const {
1759 const X86InstrInfo &TII = *TM.getInstrInfo();
1760 const X86RegisterInfo &RegInfo = *TM.getRegisterInfo();
1761 unsigned StackPtr = RegInfo.getStackRegister();
1762 bool reseveCallFrame = hasReservedCallFrame(MF);
1763 int Opcode = I->getOpcode();
1764 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1765 bool IsLP64 = STI.isTarget64BitLP64();
1766 DebugLoc DL = I->getDebugLoc();
1767 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1768 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1771 if (!reseveCallFrame) {
1772 // If the stack pointer can be changed after prologue, turn the
1773 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1774 // adjcallstackdown instruction into 'add ESP, <amt>'
1775 // TODO: consider using push / pop instead of sub + store / add
1779 // We need to keep the stack aligned properly. To do this, we round the
1780 // amount of space needed for the outgoing arguments up to the next
1781 // alignment boundary.
1782 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1783 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1785 MachineInstr *New = 0;
1786 if (Opcode == TII.getCallFrameSetupOpcode()) {
1787 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1792 assert(Opcode == TII.getCallFrameDestroyOpcode());
1794 // Factor out the amount the callee already popped.
1795 Amount -= CalleeAmt;
1798 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1799 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1800 .addReg(StackPtr).addImm(Amount);
1805 // The EFLAGS implicit def is dead.
1806 New->getOperand(3).setIsDead();
1808 // Replace the pseudo instruction with a new instruction.
1815 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1816 // If we are performing frame pointer elimination and if the callee pops
1817 // something off the stack pointer, add it back. We do this until we have
1818 // more advanced stack pointer tracking ability.
1819 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1820 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1821 .addReg(StackPtr).addImm(CalleeAmt);
1823 // The EFLAGS implicit def is dead.
1824 New->getOperand(3).setIsDead();
1826 // We are not tracking the stack pointer adjustment by the callee, so make
1827 // sure we restore the stack pointer immediately after the call, there may
1828 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1829 MachineBasicBlock::iterator B = MBB.begin();
1830 while (I != B && !llvm::prior(I)->isCall())