2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * Copyright (c) 2012 Ian Lepore
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
39 #include <machine/bus.h>
41 #include <dev/uart/uart.h>
42 #include <dev/uart/uart_cpu.h>
43 #include <dev/uart/uart_bus.h>
44 #include <arm/at91/at91_usartreg.h>
45 #include <arm/at91/at91_pdcreg.h>
46 #include <arm/at91/at91_piovar.h>
47 #include <arm/at91/at91_pioreg.h>
48 #include <arm/at91/at91rm92reg.h>
49 #include <arm/at91/at91var.h>
53 #define DEFAULT_RCLK at91_master_clock
54 #define USART_DEFAULT_FIFO_BYTES 128
56 #define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \
57 USART_CSR_DSRIC | USART_CSR_RIIC)
60 * High-level UART interface.
62 struct at91_usart_rx {
68 struct at91_usart_softc {
69 struct uart_softc base;
73 #define HAS_TIMEOUT 0x1
74 #define USE_RTS0_WORKAROUND 0x2
76 struct at91_usart_rx ping_pong[2];
77 struct at91_usart_rx *ping;
78 struct at91_usart_rx *pong;
81 #define RD4(bas, reg) \
82 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
83 #define WR4(bas, reg, value) \
84 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
86 #define SIGCHG(c, i, s, d) \
89 i |= (i & s) ? s : s | d; \
91 i = (i & s) ? (i & ~s) | d : i; \
95 #define BAUD2DIVISOR(b) \
96 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
99 * Low-level UART interface.
101 static int at91_usart_probe(struct uart_bas *bas);
102 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
103 static void at91_usart_term(struct uart_bas *bas);
104 static void at91_usart_putc(struct uart_bas *bas, int);
105 static int at91_usart_rxready(struct uart_bas *bas);
106 static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx);
108 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
111 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
112 int stopbits, int parity)
117 * Assume 3-wire RS-232 configuration.
118 * XXX Not sure how uart will present the other modes to us, so
119 * XXX they are unimplemented. maybe ioctl?
121 mr = USART_MR_MODE_NORMAL;
122 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
125 * Or in the databits requested
128 mr &= ~USART_MR_MODE9;
131 mr |= USART_MR_CHRL_5BITS;
134 mr |= USART_MR_CHRL_6BITS;
137 mr |= USART_MR_CHRL_7BITS;
140 mr |= USART_MR_CHRL_8BITS;
143 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
153 case UART_PARITY_NONE:
154 mr |= USART_MR_PAR_NONE;
156 case UART_PARITY_ODD:
157 mr |= USART_MR_PAR_ODD;
159 case UART_PARITY_EVEN:
160 mr |= USART_MR_PAR_EVEN;
162 case UART_PARITY_MARK:
163 mr |= USART_MR_PAR_MARK;
165 case UART_PARITY_SPACE:
166 mr |= USART_MR_PAR_SPACE;
173 * Or in the stop bits. Note: The hardware supports 1.5 stop
174 * bits in async mode, but there's no way to specify that
175 * AFAICT. Instead, rely on the convention documented at
176 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
177 * states that 1.5 stop bits are used for 5 bit bytes and
178 * 2 stop bits only for longer bytes.
181 mr |= USART_MR_NBSTOP_1;
182 else if (databits > 5)
183 mr |= USART_MR_NBSTOP_2;
185 mr |= USART_MR_NBSTOP_1_5;
188 * We want normal plumbing mode too, none of this fancy
189 * loopback or echo mode.
191 mr |= USART_MR_CHMODE_NORMAL;
193 mr &= ~USART_MR_MSBF; /* lsb first */
194 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
196 WR4(bas, USART_MR, mr);
199 * Set the baud rate (only if we know our master clock rate)
201 if (DEFAULT_RCLK != 0)
202 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
205 * Set the receive timeout based on the baud rate. The idea is to
206 * compromise between being responsive on an interactive connection and
207 * giving a bulk data sender a bit of time to queue up a new buffer
208 * without mistaking it for a stopping point in the transmission. For
209 * 19.2kbps and below, use 20 * bit time (2 characters). For faster
210 * connections use 500 microseconds worth of bits.
212 if (baudrate <= 19200)
213 WR4(bas, USART_RTOR, 20);
215 WR4(bas, USART_RTOR, baudrate / 2000);
216 WR4(bas, USART_CR, USART_CR_STTTO);
218 /* XXX Need to take possible synchronous mode into account */
222 static struct uart_ops at91_usart_ops = {
223 .probe = at91_usart_probe,
224 .init = at91_usart_init,
225 .term = at91_usart_term,
226 .putc = at91_usart_putc,
227 .rxready = at91_usart_rxready,
228 .getc = at91_usart_getc,
232 at91_usart_probe(struct uart_bas *bas)
235 /* We know that this is always here */
240 * Initialize this device for use as a console.
243 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
247 at91_usart_param(bas, baudrate, databits, stopbits, parity);
249 /* Reset the rx and tx buffers and turn on rx and tx */
250 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
251 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
252 WR4(bas, USART_IDR, 0xffffffff);
256 * Free resources now that we're no longer the console. This appears to
257 * be never called, and I'm unsure quite what to do if I am called.
260 at91_usart_term(struct uart_bas *bas)
267 * Put a character of console output (so we do it here polling rather than
271 at91_usart_putc(struct uart_bas *bas, int c)
274 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
276 WR4(bas, USART_THR, c);
280 * Check for a character available.
283 at91_usart_rxready(struct uart_bas *bas)
286 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
290 * Block waiting for a character.
293 at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx)
298 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
303 c = RD4(bas, USART_RHR) & 0xff;
308 static int at91_usart_bus_probe(struct uart_softc *sc);
309 static int at91_usart_bus_attach(struct uart_softc *sc);
310 static int at91_usart_bus_flush(struct uart_softc *, int);
311 static int at91_usart_bus_getsig(struct uart_softc *);
312 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
313 static int at91_usart_bus_ipend(struct uart_softc *);
314 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
315 static int at91_usart_bus_receive(struct uart_softc *);
316 static int at91_usart_bus_setsig(struct uart_softc *, int);
317 static int at91_usart_bus_transmit(struct uart_softc *);
319 static kobj_method_t at91_usart_methods[] = {
320 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
321 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
322 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
323 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
324 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
325 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
326 KOBJMETHOD(uart_param, at91_usart_bus_param),
327 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
328 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
329 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
335 at91_usart_bus_probe(struct uart_softc *sc)
339 value = USART_DEFAULT_FIFO_BYTES;
340 resource_int_value(device_get_name(sc->sc_dev),
341 device_get_unit(sc->sc_dev), "fifo_bytes", &value);
342 value = roundup2(value, arm_dcache_align);
343 sc->sc_txfifosz = value;
344 sc->sc_rxfifosz = value;
350 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
355 *(bus_addr_t *)arg = segs[0].ds_addr;
359 at91_usart_requires_rts0_workaround(struct uart_softc *sc)
364 unit = device_get_unit(sc->sc_dev);
367 * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the
368 * usart device interally (so-called 'erratum 39', but it's 41.14 in rev
369 * I of the manual). This prevents use of the hardware flow control
370 * feature in the usart itself. It also means that if we are to
371 * implement RTS/CTS flow via the tty layer logic, we must use pin PA21
372 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We
373 * can only safely do so if we've been given permission via a hint,
374 * otherwise we might manipulate a pin that's attached to who-knows-what
375 * and Bad Things could happen.
377 if (at91_is_rm92() && unit == 1) {
379 resource_int_value(device_get_name(sc->sc_dev), unit,
380 "use_rts0_workaround", &value);
382 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
383 at91_pio_gpio_output(AT91RM92_PIOA_BASE,
385 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
394 at91_usart_bus_attach(struct uart_softc *sc)
399 struct at91_usart_softc *atsc;
401 atsc = (struct at91_usart_softc *)sc;
403 if (at91_usart_requires_rts0_workaround(sc))
404 atsc->flags |= USE_RTS0_WORKAROUND;
407 * See if we have a TIMEOUT bit. We disable all interrupts as
408 * a side effect. Boot loaders may have enabled them. Since
409 * a TIMEOUT interrupt can't happen without other setup, the
410 * apparent race here can't actually happen.
412 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
413 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
414 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
415 atsc->flags |= HAS_TIMEOUT;
416 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
419 * Allocate transmit DMA tag and map. We allow a transmit buffer
420 * to be any size, but it must map to a single contiguous physical
423 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
424 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
425 BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
426 NULL, &atsc->tx_tag);
429 err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
433 if (atsc->flags & HAS_TIMEOUT) {
435 * Allocate receive DMA tags, maps, and buffers.
436 * The receive buffers should be aligned to arm_dcache_align,
437 * otherwise partial cache line flushes on every receive
438 * interrupt are pretty much guaranteed.
440 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),
441 arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT,
442 BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1,
443 sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL,
447 for (i = 0; i < 2; i++) {
448 err = bus_dmamem_alloc(atsc->rx_tag,
449 (void **)&atsc->ping_pong[i].buffer,
450 BUS_DMA_NOWAIT, &atsc->ping_pong[i].map);
453 err = bus_dmamap_load(atsc->rx_tag,
454 atsc->ping_pong[i].map,
455 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
456 at91_getaddr, &atsc->ping_pong[i].pa, 0);
459 bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map,
460 BUS_DMASYNC_PREREAD);
462 atsc->ping = &atsc->ping_pong[0];
463 atsc->pong = &atsc->ping_pong[1];
466 /* Turn on rx and tx */
467 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
468 WR4(&sc->sc_bas, USART_CR, cr);
469 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
472 * Setup the PDC to receive data. We use the ping-pong buffers
473 * so that we can more easily bounce between the two and so that
474 * we get an interrupt 1/2 way through the software 'fifo' we have
477 if (atsc->flags & HAS_TIMEOUT) {
478 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
479 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
480 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
481 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
482 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
485 * Set the receive timeout to be 1.5 character times
488 WR4(&sc->sc_bas, USART_RTOR, 15);
489 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
490 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
491 USART_CSR_RXBUFF | USART_CSR_ENDRX);
493 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
495 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS);
497 /* Prime sc->hwsig with the initial hw line states. */
498 at91_usart_bus_getsig(sc);
505 at91_usart_bus_transmit(struct uart_softc *sc)
508 struct at91_usart_softc *atsc;
512 atsc = (struct at91_usart_softc *)sc;
513 uart_lock(sc->sc_hwmtx);
514 if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
515 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) {
519 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
522 * Setup the PDC to transfer the data and interrupt us when it
523 * is done. We've already requested the interrupt.
525 WR4(&sc->sc_bas, PDC_TPR, addr);
526 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
527 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
528 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
530 uart_unlock(sc->sc_hwmtx);
535 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
537 uint32_t new, old, cr;
538 struct at91_usart_softc *atsc;
540 atsc = (struct at91_usart_softc *)sc;
546 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
548 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
549 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
553 cr |= USART_CR_DTREN;
555 cr |= USART_CR_DTRDIS;
557 cr |= USART_CR_RTSEN;
559 cr |= USART_CR_RTSDIS;
561 uart_lock(sc->sc_hwmtx);
562 WR4(&sc->sc_bas, USART_CR, cr);
563 if (atsc->flags & USE_RTS0_WORKAROUND) {
564 /* Signal is active-low. */
566 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
568 at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21);
570 uart_unlock(sc->sc_hwmtx);
576 at91_usart_bus_receive(struct uart_softc *sc)
583 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
584 int stopbits, int parity)
587 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
592 at91_rx_put(struct uart_softc *sc, int key)
596 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
597 kdb_alt_break(key, &sc->sc_altbrk);
599 uart_rx_put(sc, key);
603 at91_usart_bus_ipend(struct uart_softc *sc)
605 struct at91_usart_softc *atsc;
606 struct at91_usart_rx *p;
611 atsc = (struct at91_usart_softc *)sc;
612 uart_lock(sc->sc_hwmtx);
613 csr = RD4(&sc->sc_bas, USART_CSR);
615 if (csr & USART_CSR_OVRE) {
616 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
617 ipend |= SER_INT_OVERRUN;
620 if (csr & USART_DCE_CHANGE_BITS)
621 ipend |= SER_INT_SIGCHG;
623 if (csr & USART_CSR_ENDTX) {
624 bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
625 BUS_DMASYNC_POSTWRITE);
626 bus_dmamap_unload(atsc->tx_tag, atsc->tx_map);
628 if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
630 ipend |= SER_INT_TXIDLE;
631 WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
636 * Due to the contraints of the DMA engine present in the
637 * atmel chip, I can't just say I have a rx interrupt pending
638 * and do all the work elsewhere. I need to look at the CSR
639 * bits right now and do things based on them to avoid races.
641 if (atsc->flags & HAS_TIMEOUT) {
642 if (csr & USART_CSR_RXBUFF) {
644 * We have a buffer overflow. Consume data from ping
645 * and give it back to the hardware before worrying
646 * about pong, to minimze data loss. Insert an overrun
647 * marker after the contents of the pong buffer.
649 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
650 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
651 BUS_DMASYNC_POSTREAD);
652 for (i = 0; i < sc->sc_rxfifosz; i++)
653 at91_rx_put(sc, atsc->ping->buffer[i]);
654 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
655 BUS_DMASYNC_PREREAD);
656 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
657 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
658 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
659 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
660 BUS_DMASYNC_POSTREAD);
661 for (i = 0; i < sc->sc_rxfifosz; i++)
662 at91_rx_put(sc, atsc->pong->buffer[i]);
663 uart_rx_put(sc, UART_STAT_OVERRUN);
664 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
665 BUS_DMASYNC_PREREAD);
666 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
667 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
668 ipend |= SER_INT_RXREADY;
669 } else if (csr & USART_CSR_ENDRX) {
671 * Consume data from ping of ping pong buffer, but leave
672 * current pong in place, as it has become the new ping.
673 * We need to copy data and setup the old ping as the
674 * new pong when we're done.
676 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
677 BUS_DMASYNC_POSTREAD);
678 for (i = 0; i < sc->sc_rxfifosz; i++)
679 at91_rx_put(sc, atsc->ping->buffer[i]);
681 atsc->ping = atsc->pong;
683 bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
684 BUS_DMASYNC_PREREAD);
685 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
686 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
687 ipend |= SER_INT_RXREADY;
688 } else if (csr & USART_CSR_TIMEOUT) {
690 * On a timeout, one of the following applies:
691 * 1. Two empty buffers. The last received byte exactly
692 * filled a buffer, causing an ENDTX that got
693 * processed earlier; no new bytes have arrived.
694 * 2. Ping buffer contains some data and pong is empty.
695 * This should be the most common timeout condition.
696 * 3. Ping buffer is full and pong is now being filled.
697 * This is exceedingly rare; it can happen only if
698 * the ping buffer is almost full when a timeout is
699 * signaled, and then dataflow resumes and the ping
700 * buffer filled up between the time we read the
701 * status register above and the point where the
702 * RXTDIS takes effect here. Yes, it can happen.
703 * Because dataflow can resume at any time following a
704 * timeout (it may have already resumed before we get
705 * here), it's important to minimize the time the PDC is
706 * disabled -- just long enough to take the ping buffer
707 * out of service (so we can consume it) and install the
708 * pong buffer as the active one. Note that in case 3
709 * the hardware has already done the ping-pong swap.
711 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
712 if (RD4(&sc->sc_bas, PDC_RNCR) == 0) {
713 len = sc->sc_rxfifosz;
715 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
716 WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa);
717 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
718 WR4(&sc->sc_bas, PDC_RNCR, 0);
720 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
721 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
722 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
723 BUS_DMASYNC_POSTREAD);
724 for (i = 0; i < len; i++)
725 at91_rx_put(sc, atsc->ping->buffer[i]);
726 bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
727 BUS_DMASYNC_PREREAD);
729 atsc->ping = atsc->pong;
731 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
732 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
733 ipend |= SER_INT_RXREADY;
735 } else if (csr & USART_CSR_RXRDY) {
737 * We have another charater in a device that doesn't support
738 * timeouts, so we do it one character at a time.
740 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
741 ipend |= SER_INT_RXREADY;
744 if (csr & USART_CSR_RXBRK) {
745 ipend |= SER_INT_BREAK;
746 WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
748 uart_unlock(sc->sc_hwmtx);
753 at91_usart_bus_flush(struct uart_softc *sc, int what)
760 at91_usart_bus_getsig(struct uart_softc *sc)
762 uint32_t csr, new, old, sig;
765 * Note that the atmel channel status register DCE status bits reflect
766 * the electrical state of the lines, not the logical state. Since they
767 * are logically active-low signals, we invert the tests here.
772 csr = RD4(&sc->sc_bas, USART_CSR);
773 SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR);
774 SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS);
775 SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD);
776 SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI);
777 new = sig & ~SER_MASK_DELTA;
778 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
784 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
788 case UART_IOCTL_BREAK:
789 case UART_IOCTL_IFLOW:
790 case UART_IOCTL_OFLOW:
792 case UART_IOCTL_BAUD:
793 /* only if we know our master clock rate */
794 if (DEFAULT_RCLK != 0)
795 WR4(&sc->sc_bas, USART_BRGR,
796 BAUD2DIVISOR(*(int *)data));
802 struct uart_class at91_usart_class = {
805 sizeof(struct at91_usart_softc),
806 .uc_ops = &at91_usart_ops,