1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS * table_entry;
57 symbolS * personality_routine;
58 int personality_index;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency = 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result;
101 ARM_FLOAT_ABI_SOFTFP,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant;
137 static arm_feature_set arm_arch_used;
138 static arm_feature_set thumb_arch_used;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26 = FALSE;
142 static int atpcs = FALSE;
143 static int support_interwork = FALSE;
144 static int uses_apcs_float = FALSE;
145 static int pic_code = FALSE;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set *legacy_cpu = NULL;
151 static const arm_feature_set *legacy_fpu = NULL;
153 static const arm_feature_set *mcpu_cpu_opt = NULL;
154 static const arm_feature_set *mcpu_fpu_opt = NULL;
155 static const arm_feature_set *march_cpu_opt = NULL;
156 static const arm_feature_set *march_fpu_opt = NULL;
157 static const arm_feature_set *mfpu_opt = NULL;
158 static const arm_feature_set *object_arch = NULL;
160 /* Constants for known architecture features. */
161 static const arm_feature_set fpu_default = FPU_DEFAULT;
162 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
163 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
164 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
165 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
166 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
167 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
168 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
169 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
172 static const arm_feature_set cpu_default = CPU_DEFAULT;
175 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
176 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
177 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
178 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
179 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
180 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
181 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
182 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
183 static const arm_feature_set arm_ext_v4t_5 =
184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
185 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
186 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
187 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
188 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
189 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
190 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
191 static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
192 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
193 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
194 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
195 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
196 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
197 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
198 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_arch_any = ARM_ANY;
201 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
203 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
205 static const arm_feature_set arm_cext_iwmmxt2 =
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
207 static const arm_feature_set arm_cext_iwmmxt =
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
209 static const arm_feature_set arm_cext_xscale =
210 ARM_FEATURE (0, ARM_CEXT_XSCALE);
211 static const arm_feature_set arm_cext_maverick =
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
213 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
214 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
215 static const arm_feature_set fpu_vfp_ext_v1xd =
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
217 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
218 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
219 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
220 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
221 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
224 static int mfloat_abi_opt = -1;
225 /* Record user cpu selection for object attributes. */
226 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
227 /* Must be long enough to hold any of the names in arm_cpus. */
228 static char selected_cpu_name[16];
231 static int meabi_flags = EABI_DEFAULT;
233 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245 symbolS * GOT_symbol;
248 /* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
252 static int thumb_mode = 0;
254 /* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
266 Important differences from the old Thumb mode:
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
277 static bfd_boolean unified_syntax = FALSE;
292 enum neon_el_type type;
296 #define NEON_MAX_TYPE_ELS 4
300 struct neon_type_el el[NEON_MAX_TYPE_ELS];
307 unsigned long instruction;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
315 struct neon_type vectype;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
321 bfd_reloc_code_real_type type;
330 struct neon_type_el vectype;
331 unsigned present : 1; /* Operand present. */
332 unsigned isreg : 1; /* Operand was a register. */
333 unsigned immisreg : 1; /* .imm field is a second register. */
334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle : 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc : 1; /* Operand has relocation suffix. */
344 unsigned writeback : 1; /* Operand has trailing ! */
345 unsigned preind : 1; /* Preindexed address. */
346 unsigned postind : 1; /* Postindexed address. */
347 unsigned negative : 1; /* Index register was negated. */
348 unsigned shifted : 1; /* Shift applied to operation. */
349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
353 static struct arm_it inst;
355 #define NUM_FLOAT_VALS 8
357 const char * fp_const[] =
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
362 /* Number of littlenums required to hold an extended precision number. */
363 #define MAX_LITTLENUMS 6
365 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
375 #define CP_T_X 0x00008000
376 #define CP_T_Y 0x00400000
378 #define CONDS_BIT 0x00100000
379 #define LOAD_BIT 0x00100000
381 #define DOUBLE_LOAD_FLAG 0x00000001
385 const char * template;
389 #define COND_ALWAYS 0xE
393 const char *template;
397 struct asm_barrier_opt
399 const char *template;
403 /* The bit that distinguishes CPSR and SPSR. */
404 #define SPSR_BIT (1 << 22)
406 /* The individual PSR flag bits. */
407 #define PSR_c (1 << 16)
408 #define PSR_x (1 << 17)
409 #define PSR_s (1 << 18)
410 #define PSR_f (1 << 19)
415 bfd_reloc_code_real_type reloc;
420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
429 /* Bits for DEFINED field in neon_typed_alias. */
430 #define NTA_HASTYPE 1
431 #define NTA_HASINDEX 2
433 struct neon_typed_alias
435 unsigned char defined;
437 struct neon_type_el eltype;
440 /* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
467 /* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
474 unsigned char number;
476 unsigned char builtin;
477 struct neon_typed_alias *neon;
480 /* Diagnostics used when we don't get a register of the expected type. */
481 const char *const reg_expected_msgs[] =
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
506 /* Some well known registers that we refer to directly elsewhere. */
511 /* ARM instructions take 4bytes in the object file, Thumb instructions
517 /* Basic string to match. */
518 const char *template;
520 /* Parameters to instruction. */
521 unsigned char operands[8];
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag : 4;
526 /* Basic instruction code. */
527 unsigned int avalue : 28;
529 /* Thumb-format instruction code. */
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set *avariant;
534 const arm_feature_set *tvariant;
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode) (void);
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode) (void);
543 /* Defines for various bits that we will want to toggle. */
544 #define INST_IMMEDIATE 0x02000000
545 #define OFFSET_REG 0x02000000
546 #define HWOFFSET_IMM 0x00400000
547 #define SHIFT_BY_REG 0x00000010
548 #define PRE_INDEX 0x01000000
549 #define INDEX_UP 0x00800000
550 #define WRITE_BACK 0x00200000
551 #define LDM_TYPE_2_OR_3 0x00400000
552 #define CPSI_MMOD 0x00020000
554 #define LITERAL_MASK 0xf000f000
555 #define OPCODE_MASK 0xfe1fffff
556 #define V4_STR_BIT 0x00000020
558 #define T2_SUBS_PC_LR 0xf3de8f00
560 #define DATA_OP_SHIFT 21
562 #define T2_OPCODE_MASK 0xfe1fffff
563 #define T2_DATA_OP_SHIFT 21
565 /* Codes to distinguish the arithmetic instructions. */
576 #define OPCODE_CMP 10
577 #define OPCODE_CMN 11
578 #define OPCODE_ORR 12
579 #define OPCODE_MOV 13
580 #define OPCODE_BIC 14
581 #define OPCODE_MVN 15
583 #define T2_OPCODE_AND 0
584 #define T2_OPCODE_BIC 1
585 #define T2_OPCODE_ORR 2
586 #define T2_OPCODE_ORN 3
587 #define T2_OPCODE_EOR 4
588 #define T2_OPCODE_ADD 8
589 #define T2_OPCODE_ADC 10
590 #define T2_OPCODE_SBC 11
591 #define T2_OPCODE_SUB 13
592 #define T2_OPCODE_RSB 14
594 #define T_OPCODE_MUL 0x4340
595 #define T_OPCODE_TST 0x4200
596 #define T_OPCODE_CMN 0x42c0
597 #define T_OPCODE_NEG 0x4240
598 #define T_OPCODE_MVN 0x43c0
600 #define T_OPCODE_ADD_R3 0x1800
601 #define T_OPCODE_SUB_R3 0x1a00
602 #define T_OPCODE_ADD_HI 0x4400
603 #define T_OPCODE_ADD_ST 0xb000
604 #define T_OPCODE_SUB_ST 0xb080
605 #define T_OPCODE_ADD_SP 0xa800
606 #define T_OPCODE_ADD_PC 0xa000
607 #define T_OPCODE_ADD_I8 0x3000
608 #define T_OPCODE_SUB_I8 0x3800
609 #define T_OPCODE_ADD_I3 0x1c00
610 #define T_OPCODE_SUB_I3 0x1e00
612 #define T_OPCODE_ASR_R 0x4100
613 #define T_OPCODE_LSL_R 0x4080
614 #define T_OPCODE_LSR_R 0x40c0
615 #define T_OPCODE_ROR_R 0x41c0
616 #define T_OPCODE_ASR_I 0x1000
617 #define T_OPCODE_LSL_I 0x0000
618 #define T_OPCODE_LSR_I 0x0800
620 #define T_OPCODE_MOV_I8 0x2000
621 #define T_OPCODE_CMP_I8 0x2800
622 #define T_OPCODE_CMP_LR 0x4280
623 #define T_OPCODE_MOV_HR 0x4600
624 #define T_OPCODE_CMP_HR 0x4500
626 #define T_OPCODE_LDR_PC 0x4800
627 #define T_OPCODE_LDR_SP 0x9800
628 #define T_OPCODE_STR_SP 0x9000
629 #define T_OPCODE_LDR_IW 0x6800
630 #define T_OPCODE_STR_IW 0x6000
631 #define T_OPCODE_LDR_IH 0x8800
632 #define T_OPCODE_STR_IH 0x8000
633 #define T_OPCODE_LDR_IB 0x7800
634 #define T_OPCODE_STR_IB 0x7000
635 #define T_OPCODE_LDR_RW 0x5800
636 #define T_OPCODE_STR_RW 0x5000
637 #define T_OPCODE_LDR_RH 0x5a00
638 #define T_OPCODE_STR_RH 0x5200
639 #define T_OPCODE_LDR_RB 0x5c00
640 #define T_OPCODE_STR_RB 0x5400
642 #define T_OPCODE_PUSH 0xb400
643 #define T_OPCODE_POP 0xbc00
645 #define T_OPCODE_BRANCH 0xe000
647 #define THUMB_SIZE 2 /* Size of thumb instruction. */
648 #define THUMB_PP_PC_LR 0x0100
649 #define THUMB_LOAD_BIT 0x0800
650 #define THUMB2_LOAD_BIT 0x00100000
652 #define BAD_ARGS _("bad arguments to instruction")
653 #define BAD_PC _("r15 not allowed here")
654 #define BAD_SP _("r13 not allowed here")
655 #define BAD_COND _("instruction cannot be conditional")
656 #define BAD_OVERLAP _("registers may not be the same")
657 #define BAD_HIREG _("lo register required")
658 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
659 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
660 #define BAD_BRANCH _("branch must be last instruction in IT block")
661 #define BAD_NOT_IT _("instruction not allowed in IT block")
662 #define BAD_FPU _("selected FPU does not support instruction")
663 #define BAD_VMRS _("APSR_nzcv may only be used with fpscr")
665 static struct hash_control *arm_ops_hsh;
666 static struct hash_control *arm_cond_hsh;
667 static struct hash_control *arm_shift_hsh;
668 static struct hash_control *arm_psr_hsh;
669 static struct hash_control *arm_v7m_psr_hsh;
670 static struct hash_control *arm_reg_hsh;
671 static struct hash_control *arm_reloc_hsh;
672 static struct hash_control *arm_barrier_opt_hsh;
674 /* Stuff needed to resolve the label ambiguity
684 symbolS * last_label_seen;
685 static int label_is_thumb_function_name = FALSE;
687 /* Literal pool structure. Held on a per-section
688 and per-sub-section basis. */
690 #define MAX_LITERAL_POOL_SIZE 1024
691 typedef struct literal_pool
693 expressionS literals [MAX_LITERAL_POOL_SIZE];
694 unsigned int next_free_entry;
699 struct literal_pool * next;
702 /* Pointer to a linked list of literal pools. */
703 literal_pool * list_of_pools = NULL;
705 /* State variables for IT block handling. */
706 static bfd_boolean current_it_mask = 0;
707 static int current_cc;
712 /* This array holds the chars that always start a comment. If the
713 pre-processor is disabled, these aren't very useful. */
714 const char comment_chars[] = "@";
716 /* This array holds the chars that only start a comment at the beginning of
717 a line. If the line seems to have the form '# 123 filename'
718 .line and .file directives will appear in the pre-processed output. */
719 /* Note that input_file.c hand checks for '#' at the beginning of the
720 first line of the input file. This is because the compiler outputs
721 #NO_APP at the beginning of its output. */
722 /* Also note that comments like this one will always work. */
723 const char line_comment_chars[] = "#";
725 const char line_separator_chars[] = ";";
727 /* Chars that can be used to separate mant
728 from exp in floating point numbers. */
729 const char EXP_CHARS[] = "eE";
731 /* Chars that mean this number is a floating point constant. */
735 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
737 /* Prefix characters that indicate the start of an immediate
739 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
741 /* Separator character handling. */
743 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
746 skip_past_char (char ** str, char c)
756 #define skip_past_comma(str) skip_past_char (str, ',')
758 /* Arithmetic expressions (possibly involving symbols). */
760 /* Return TRUE if anything in the expression is a bignum. */
763 walk_no_bignums (symbolS * sp)
765 if (symbol_get_value_expression (sp)->X_op == O_big)
768 if (symbol_get_value_expression (sp)->X_add_symbol)
770 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
771 || (symbol_get_value_expression (sp)->X_op_symbol
772 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
778 static int in_my_get_expression = 0;
780 /* Third argument to my_get_expression. */
781 #define GE_NO_PREFIX 0
782 #define GE_IMM_PREFIX 1
783 #define GE_OPT_PREFIX 2
784 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
786 #define GE_OPT_PREFIX_BIG 3
789 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
794 /* In unified syntax, all prefixes are optional. */
796 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
801 case GE_NO_PREFIX: break;
803 if (!is_immediate_prefix (**str))
805 inst.error = _("immediate expression requires a # prefix");
811 case GE_OPT_PREFIX_BIG:
812 if (is_immediate_prefix (**str))
818 memset (ep, 0, sizeof (expressionS));
820 save_in = input_line_pointer;
821 input_line_pointer = *str;
822 in_my_get_expression = 1;
823 seg = expression (ep);
824 in_my_get_expression = 0;
826 if (ep->X_op == O_illegal)
828 /* We found a bad expression in md_operand(). */
829 *str = input_line_pointer;
830 input_line_pointer = save_in;
831 if (inst.error == NULL)
832 inst.error = _("bad expression");
837 if (seg != absolute_section
838 && seg != text_section
839 && seg != data_section
840 && seg != bss_section
841 && seg != undefined_section)
843 inst.error = _("bad segment");
844 *str = input_line_pointer;
845 input_line_pointer = save_in;
850 /* Get rid of any bignums now, so that we don't generate an error for which
851 we can't establish a line number later on. Big numbers are never valid
852 in instructions, which is where this routine is always called. */
853 if (prefix_mode != GE_OPT_PREFIX_BIG
854 && (ep->X_op == O_big
856 && (walk_no_bignums (ep->X_add_symbol)
858 && walk_no_bignums (ep->X_op_symbol))))))
860 inst.error = _("invalid constant");
861 *str = input_line_pointer;
862 input_line_pointer = save_in;
866 *str = input_line_pointer;
867 input_line_pointer = save_in;
871 /* Turn a string in input_line_pointer into a floating point constant
872 of type TYPE, and store the appropriate bytes in *LITP. The number
873 of LITTLENUMS emitted is stored in *SIZEP. An error message is
874 returned, or NULL on OK.
876 Note that fp constants aren't represent in the normal way on the ARM.
877 In big endian mode, things are as expected. However, in little endian
878 mode fp constants are big-endian word-wise, and little-endian byte-wise
879 within the words. For example, (double) 1.1 in big endian mode is
880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
881 the byte sequence 99 99 f1 3f 9a 99 99 99.
883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
886 md_atof (int type, char * litP, int * sizeP)
889 LITTLENUM_TYPE words[MAX_LITTLENUMS];
921 return _("bad call to MD_ATOF()");
924 t = atof_ieee (input_line_pointer, type, words);
926 input_line_pointer = t;
929 if (target_big_endian)
931 for (i = 0; i < prec; i++)
933 md_number_to_chars (litP, (valueT) words[i], 2);
939 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
940 for (i = prec - 1; i >= 0; i--)
942 md_number_to_chars (litP, (valueT) words[i], 2);
946 /* For a 4 byte float the order of elements in `words' is 1 0.
947 For an 8 byte float the order is 1 0 3 2. */
948 for (i = 0; i < prec; i += 2)
950 md_number_to_chars (litP, (valueT) words[i + 1], 2);
951 md_number_to_chars (litP + 2, (valueT) words[i], 2);
959 /* We handle all bad expressions here, so that we can report the faulty
960 instruction in the error message. */
962 md_operand (expressionS * expr)
964 if (in_my_get_expression)
965 expr->X_op = O_illegal;
968 /* Immediate values. */
970 /* Generic immediate-value read function for use in directives.
971 Accepts anything that 'expression' can fold to a constant.
972 *val receives the number. */
975 immediate_for_directive (int *val)
978 exp.X_op = O_illegal;
980 if (is_immediate_prefix (*input_line_pointer))
982 input_line_pointer++;
986 if (exp.X_op != O_constant)
988 as_bad (_("expected #constant"));
989 ignore_rest_of_line ();
992 *val = exp.X_add_number;
997 /* Register parsing. */
999 /* Generic register parser. CCP points to what should be the
1000 beginning of a register name. If it is indeed a valid register
1001 name, advance CCP over it and return the reg_entry structure;
1002 otherwise return NULL. Does not issue diagnostics. */
1004 static struct reg_entry *
1005 arm_reg_parse_multi (char **ccp)
1009 struct reg_entry *reg;
1011 #ifdef REGISTER_PREFIX
1012 if (*start != REGISTER_PREFIX)
1016 #ifdef OPTIONAL_REGISTER_PREFIX
1017 if (*start == OPTIONAL_REGISTER_PREFIX)
1022 if (!ISALPHA (*p) || !is_name_beginner (*p))
1027 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1029 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1039 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1040 enum arm_reg_type type)
1042 /* Alternative syntaxes are accepted for a few register classes. */
1049 /* Generic coprocessor register names are allowed for these. */
1050 if (reg && reg->type == REG_TYPE_CN)
1055 /* For backward compatibility, a bare number is valid here. */
1057 unsigned long processor = strtoul (start, ccp, 10);
1058 if (*ccp != start && processor <= 15)
1062 case REG_TYPE_MMXWC:
1063 /* WC includes WCG. ??? I'm not sure this is true for all
1064 instructions that take WC registers. */
1065 if (reg && reg->type == REG_TYPE_MMXWCG)
1076 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1077 return value is the register number or FAIL. */
1080 arm_reg_parse (char **ccp, enum arm_reg_type type)
1083 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1086 /* Do not allow a scalar (reg+index) to parse as a register. */
1087 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1090 if (reg && reg->type == type)
1093 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1100 /* Parse a Neon type specifier. *STR should point at the leading '.'
1101 character. Does no verification at this stage that the type fits the opcode
1108 Can all be legally parsed by this function.
1110 Fills in neon_type struct pointer with parsed information, and updates STR
1111 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1112 type, FAIL if not. */
1115 parse_neon_type (struct neon_type *type, char **str)
1122 while (type->elems < NEON_MAX_TYPE_ELS)
1124 enum neon_el_type thistype = NT_untyped;
1125 unsigned thissize = -1u;
1132 /* Just a size without an explicit type. */
1136 switch (TOLOWER (*ptr))
1138 case 'i': thistype = NT_integer; break;
1139 case 'f': thistype = NT_float; break;
1140 case 'p': thistype = NT_poly; break;
1141 case 's': thistype = NT_signed; break;
1142 case 'u': thistype = NT_unsigned; break;
1144 thistype = NT_float;
1149 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1155 /* .f is an abbreviation for .f32. */
1156 if (thistype == NT_float && !ISDIGIT (*ptr))
1161 thissize = strtoul (ptr, &ptr, 10);
1163 if (thissize != 8 && thissize != 16 && thissize != 32
1166 as_bad (_("bad size %d in type specifier"), thissize);
1174 type->el[type->elems].type = thistype;
1175 type->el[type->elems].size = thissize;
1180 /* Empty/missing type is not a successful parse. */
1181 if (type->elems == 0)
1189 /* Errors may be set multiple times during parsing or bit encoding
1190 (particularly in the Neon bits), but usually the earliest error which is set
1191 will be the most meaningful. Avoid overwriting it with later (cascading)
1192 errors by calling this function. */
1195 first_error (const char *err)
1201 /* Parse a single type, e.g. ".s32", leading period included. */
1203 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1206 struct neon_type optype;
1210 if (parse_neon_type (&optype, &str) == SUCCESS)
1212 if (optype.elems == 1)
1213 *vectype = optype.el[0];
1216 first_error (_("only one type should be specified for operand"));
1222 first_error (_("vector type expected"));
1234 /* Special meanings for indices (which have a range of 0-7), which will fit into
1237 #define NEON_ALL_LANES 15
1238 #define NEON_INTERLEAVE_LANES 14
1240 /* Parse either a register or a scalar, with an optional type. Return the
1241 register number, and optionally fill in the actual type of the register
1242 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1243 type/index information in *TYPEINFO. */
1246 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1247 enum arm_reg_type *rtype,
1248 struct neon_typed_alias *typeinfo)
1251 struct reg_entry *reg = arm_reg_parse_multi (&str);
1252 struct neon_typed_alias atype;
1253 struct neon_type_el parsetype;
1257 atype.eltype.type = NT_invtype;
1258 atype.eltype.size = -1;
1260 /* Try alternate syntax for some types of register. Note these are mutually
1261 exclusive with the Neon syntax extensions. */
1264 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1272 /* Undo polymorphism when a set of register types may be accepted. */
1273 if ((type == REG_TYPE_NDQ
1274 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1275 || (type == REG_TYPE_VFSD
1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1277 || (type == REG_TYPE_NSDQ
1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1279 || reg->type == REG_TYPE_NQ))
1280 || (type == REG_TYPE_MMXWC
1281 && (reg->type == REG_TYPE_MMXWCG)))
1284 if (type != reg->type)
1290 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1292 if ((atype.defined & NTA_HASTYPE) != 0)
1294 first_error (_("can't redefine type for operand"));
1297 atype.defined |= NTA_HASTYPE;
1298 atype.eltype = parsetype;
1301 if (skip_past_char (&str, '[') == SUCCESS)
1303 if (type != REG_TYPE_VFD)
1305 first_error (_("only D registers may be indexed"));
1309 if ((atype.defined & NTA_HASINDEX) != 0)
1311 first_error (_("can't change index for operand"));
1315 atype.defined |= NTA_HASINDEX;
1317 if (skip_past_char (&str, ']') == SUCCESS)
1318 atype.index = NEON_ALL_LANES;
1323 my_get_expression (&exp, &str, GE_NO_PREFIX);
1325 if (exp.X_op != O_constant)
1327 first_error (_("constant expression required"));
1331 if (skip_past_char (&str, ']') == FAIL)
1334 atype.index = exp.X_add_number;
1349 /* Like arm_reg_parse, but allow allow the following extra features:
1350 - If RTYPE is non-zero, return the (possibly restricted) type of the
1351 register (e.g. Neon double or quad reg when either has been requested).
1352 - If this is a Neon vector type with additional type information, fill
1353 in the struct pointed to by VECTYPE (if non-NULL).
1354 This function will fault on encountering a scalar.
1358 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1359 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1361 struct neon_typed_alias atype;
1363 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1368 /* Do not allow a scalar (reg+index) to parse as a register. */
1369 if ((atype.defined & NTA_HASINDEX) != 0)
1371 first_error (_("register operand expected, but got scalar"));
1376 *vectype = atype.eltype;
1383 #define NEON_SCALAR_REG(X) ((X) >> 4)
1384 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1386 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1387 have enough information to be able to do a good job bounds-checking. So, we
1388 just do easy checks here, and do further checks later. */
1391 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1395 struct neon_typed_alias atype;
1397 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1399 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1402 if (atype.index == NEON_ALL_LANES)
1404 first_error (_("scalar must have an index"));
1407 else if (atype.index >= 64 / elsize)
1409 first_error (_("scalar index out of range"));
1414 *type = atype.eltype;
1418 return reg * 16 + atype.index;
1421 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1423 parse_reg_list (char ** strp)
1425 char * str = * strp;
1429 /* We come back here if we get ranges concatenated by '+' or '|'. */
1444 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1446 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1456 first_error (_("bad range in register list"));
1460 for (i = cur_reg + 1; i < reg; i++)
1462 if (range & (1 << i))
1464 (_("Warning: duplicated register (r%d) in register list"),
1472 if (range & (1 << reg))
1473 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1475 else if (reg <= cur_reg)
1476 as_tsktsk (_("Warning: register range not in ascending order"));
1481 while (skip_past_comma (&str) != FAIL
1482 || (in_range = 1, *str++ == '-'));
1487 first_error (_("missing `}'"));
1495 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1498 if (expr.X_op == O_constant)
1500 if (expr.X_add_number
1501 != (expr.X_add_number & 0x0000ffff))
1503 inst.error = _("invalid register mask");
1507 if ((range & expr.X_add_number) != 0)
1509 int regno = range & expr.X_add_number;
1512 regno = (1 << regno) - 1;
1514 (_("Warning: duplicated register (r%d) in register list"),
1518 range |= expr.X_add_number;
1522 if (inst.reloc.type != 0)
1524 inst.error = _("expression too complex");
1528 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1529 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1530 inst.reloc.pc_rel = 0;
1534 if (*str == '|' || *str == '+')
1540 while (another_range);
1546 /* Types of registers in a list. */
1555 /* Parse a VFP register list. If the string is invalid return FAIL.
1556 Otherwise return the number of registers, and set PBASE to the first
1557 register. Parses registers of type ETYPE.
1558 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1559 - Q registers can be used to specify pairs of D registers
1560 - { } can be omitted from around a singleton register list
1561 FIXME: This is not implemented, as it would require backtracking in
1564 This could be done (the meaning isn't really ambiguous), but doesn't
1565 fit in well with the current parsing framework.
1566 - 32 D registers may be used (also true for VFPv3).
1567 FIXME: Types are ignored in these register lists, which is probably a
1571 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1576 enum arm_reg_type regtype = 0;
1580 unsigned long mask = 0;
1585 inst.error = _("expecting {");
1594 regtype = REG_TYPE_VFS;
1599 regtype = REG_TYPE_VFD;
1602 case REGLIST_NEON_D:
1603 regtype = REG_TYPE_NDQ;
1607 if (etype != REGLIST_VFP_S)
1609 /* VFPv3 allows 32 D registers. */
1610 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
1614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1617 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1624 base_reg = max_regs;
1628 int setmask = 1, addregs = 1;
1630 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1632 if (new_base == FAIL)
1634 first_error (_(reg_expected_msgs[regtype]));
1638 if (new_base >= max_regs)
1640 first_error (_("register out of range in list"));
1644 /* Note: a value of 2 * n is returned for the register Q<n>. */
1645 if (regtype == REG_TYPE_NQ)
1651 if (new_base < base_reg)
1652 base_reg = new_base;
1654 if (mask & (setmask << new_base))
1656 first_error (_("invalid register list"));
1660 if ((mask >> new_base) != 0 && ! warned)
1662 as_tsktsk (_("register list not in ascending order"));
1666 mask |= setmask << new_base;
1669 if (*str == '-') /* We have the start of a range expression */
1675 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1678 inst.error = gettext (reg_expected_msgs[regtype]);
1682 if (high_range >= max_regs)
1684 first_error (_("register out of range in list"));
1688 if (regtype == REG_TYPE_NQ)
1689 high_range = high_range + 1;
1691 if (high_range <= new_base)
1693 inst.error = _("register range not in ascending order");
1697 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1699 if (mask & (setmask << new_base))
1701 inst.error = _("invalid register list");
1705 mask |= setmask << new_base;
1710 while (skip_past_comma (&str) != FAIL);
1714 /* Sanity check -- should have raised a parse error above. */
1715 if (count == 0 || count > max_regs)
1720 /* Final test -- the registers must be consecutive. */
1722 for (i = 0; i < count; i++)
1724 if ((mask & (1u << i)) == 0)
1726 inst.error = _("non-contiguous register range");
1736 /* True if two alias types are the same. */
1739 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1747 if (a->defined != b->defined)
1750 if ((a->defined & NTA_HASTYPE) != 0
1751 && (a->eltype.type != b->eltype.type
1752 || a->eltype.size != b->eltype.size))
1755 if ((a->defined & NTA_HASINDEX) != 0
1756 && (a->index != b->index))
1762 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1763 The base register is put in *PBASE.
1764 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1766 The register stride (minus one) is put in bit 4 of the return value.
1767 Bits [6:5] encode the list length (minus one).
1768 The type of the list elements is put in *ELTYPE, if non-NULL. */
1770 #define NEON_LANE(X) ((X) & 0xf)
1771 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1772 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1775 parse_neon_el_struct_list (char **str, unsigned *pbase,
1776 struct neon_type_el *eltype)
1783 int leading_brace = 0;
1784 enum arm_reg_type rtype = REG_TYPE_NDQ;
1786 const char *const incr_error = "register stride must be 1 or 2";
1787 const char *const type_error = "mismatched element/structure types in list";
1788 struct neon_typed_alias firsttype;
1790 if (skip_past_char (&ptr, '{') == SUCCESS)
1795 struct neon_typed_alias atype;
1796 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1800 first_error (_(reg_expected_msgs[rtype]));
1807 if (rtype == REG_TYPE_NQ)
1814 else if (reg_incr == -1)
1816 reg_incr = getreg - base_reg;
1817 if (reg_incr < 1 || reg_incr > 2)
1819 first_error (_(incr_error));
1823 else if (getreg != base_reg + reg_incr * count)
1825 first_error (_(incr_error));
1829 if (!neon_alias_types_same (&atype, &firsttype))
1831 first_error (_(type_error));
1835 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1839 struct neon_typed_alias htype;
1840 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1842 lane = NEON_INTERLEAVE_LANES;
1843 else if (lane != NEON_INTERLEAVE_LANES)
1845 first_error (_(type_error));
1850 else if (reg_incr != 1)
1852 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1856 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1859 first_error (_(reg_expected_msgs[rtype]));
1862 if (!neon_alias_types_same (&htype, &firsttype))
1864 first_error (_(type_error));
1867 count += hireg + dregs - getreg;
1871 /* If we're using Q registers, we can't use [] or [n] syntax. */
1872 if (rtype == REG_TYPE_NQ)
1878 if ((atype.defined & NTA_HASINDEX) != 0)
1882 else if (lane != atype.index)
1884 first_error (_(type_error));
1888 else if (lane == -1)
1889 lane = NEON_INTERLEAVE_LANES;
1890 else if (lane != NEON_INTERLEAVE_LANES)
1892 first_error (_(type_error));
1897 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
1899 /* No lane set by [x]. We must be interleaving structures. */
1901 lane = NEON_INTERLEAVE_LANES;
1904 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
1905 || (count > 1 && reg_incr == -1))
1907 first_error (_("error parsing element/structure list"));
1911 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
1913 first_error (_("expected }"));
1921 *eltype = firsttype.eltype;
1926 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
1929 /* Parse an explicit relocation suffix on an expression. This is
1930 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1931 arm_reloc_hsh contains no entries, so this function can only
1932 succeed if there is no () after the word. Returns -1 on error,
1933 BFD_RELOC_UNUSED if there wasn't any suffix. */
1935 parse_reloc (char **str)
1937 struct reloc_entry *r;
1941 return BFD_RELOC_UNUSED;
1946 while (*q && *q != ')' && *q != ',')
1951 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1958 /* Directives: register aliases. */
1960 static struct reg_entry *
1961 insert_reg_alias (char *str, int number, int type)
1963 struct reg_entry *new;
1966 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1969 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1971 /* Only warn about a redefinition if it's not defined as the
1973 else if (new->number != number || new->type != type)
1974 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1979 name = xstrdup (str);
1980 new = xmalloc (sizeof (struct reg_entry));
1983 new->number = number;
1985 new->builtin = FALSE;
1988 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1995 insert_neon_reg_alias (char *str, int number, int type,
1996 struct neon_typed_alias *atype)
1998 struct reg_entry *reg = insert_reg_alias (str, number, type);
2002 first_error (_("attempt to redefine typed alias"));
2008 reg->neon = xmalloc (sizeof (struct neon_typed_alias));
2009 *reg->neon = *atype;
2013 /* Look for the .req directive. This is of the form:
2015 new_register_name .req existing_register_name
2017 If we find one, or if it looks sufficiently like one that we want to
2018 handle any error here, return non-zero. Otherwise return zero. */
2021 create_register_alias (char * newname, char *p)
2023 struct reg_entry *old;
2024 char *oldname, *nbuf;
2027 /* The input scrubber ensures that whitespace after the mnemonic is
2028 collapsed to single spaces. */
2030 if (strncmp (oldname, " .req ", 6) != 0)
2034 if (*oldname == '\0')
2037 old = hash_find (arm_reg_hsh, oldname);
2040 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2044 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2045 the desired alias name, and p points to its end. If not, then
2046 the desired alias name is in the global original_case_string. */
2047 #ifdef TC_CASE_SENSITIVE
2050 newname = original_case_string;
2051 nlen = strlen (newname);
2054 nbuf = alloca (nlen + 1);
2055 memcpy (nbuf, newname, nlen);
2058 /* Create aliases under the new name as stated; an all-lowercase
2059 version of the new name; and an all-uppercase version of the new
2061 insert_reg_alias (nbuf, old->number, old->type);
2063 for (p = nbuf; *p; p++)
2066 if (strncmp (nbuf, newname, nlen))
2067 insert_reg_alias (nbuf, old->number, old->type);
2069 for (p = nbuf; *p; p++)
2072 if (strncmp (nbuf, newname, nlen))
2073 insert_reg_alias (nbuf, old->number, old->type);
2078 /* Create a Neon typed/indexed register alias using directives, e.g.:
2083 These typed registers can be used instead of the types specified after the
2084 Neon mnemonic, so long as all operands given have types. Types can also be
2085 specified directly, e.g.:
2086 vadd d0.s32, d1.s32, d2.s32
2090 create_neon_reg_alias (char *newname, char *p)
2092 enum arm_reg_type basetype;
2093 struct reg_entry *basereg;
2094 struct reg_entry mybasereg;
2095 struct neon_type ntype;
2096 struct neon_typed_alias typeinfo;
2097 char *namebuf, *nameend;
2100 typeinfo.defined = 0;
2101 typeinfo.eltype.type = NT_invtype;
2102 typeinfo.eltype.size = -1;
2103 typeinfo.index = -1;
2107 if (strncmp (p, " .dn ", 5) == 0)
2108 basetype = REG_TYPE_VFD;
2109 else if (strncmp (p, " .qn ", 5) == 0)
2110 basetype = REG_TYPE_NQ;
2119 basereg = arm_reg_parse_multi (&p);
2121 if (basereg && basereg->type != basetype)
2123 as_bad (_("bad type for register"));
2127 if (basereg == NULL)
2130 /* Try parsing as an integer. */
2131 my_get_expression (&exp, &p, GE_NO_PREFIX);
2132 if (exp.X_op != O_constant)
2134 as_bad (_("expression must be constant"));
2137 basereg = &mybasereg;
2138 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2144 typeinfo = *basereg->neon;
2146 if (parse_neon_type (&ntype, &p) == SUCCESS)
2148 /* We got a type. */
2149 if (typeinfo.defined & NTA_HASTYPE)
2151 as_bad (_("can't redefine the type of a register alias"));
2155 typeinfo.defined |= NTA_HASTYPE;
2156 if (ntype.elems != 1)
2158 as_bad (_("you must specify a single type only"));
2161 typeinfo.eltype = ntype.el[0];
2164 if (skip_past_char (&p, '[') == SUCCESS)
2167 /* We got a scalar index. */
2169 if (typeinfo.defined & NTA_HASINDEX)
2171 as_bad (_("can't redefine the index of a scalar alias"));
2175 my_get_expression (&exp, &p, GE_NO_PREFIX);
2177 if (exp.X_op != O_constant)
2179 as_bad (_("scalar index must be constant"));
2183 typeinfo.defined |= NTA_HASINDEX;
2184 typeinfo.index = exp.X_add_number;
2186 if (skip_past_char (&p, ']') == FAIL)
2188 as_bad (_("expecting ]"));
2193 namelen = nameend - newname;
2194 namebuf = alloca (namelen + 1);
2195 strncpy (namebuf, newname, namelen);
2196 namebuf[namelen] = '\0';
2198 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2199 typeinfo.defined != 0 ? &typeinfo : NULL);
2201 /* Insert name in all uppercase. */
2202 for (p = namebuf; *p; p++)
2205 if (strncmp (namebuf, newname, namelen))
2206 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2207 typeinfo.defined != 0 ? &typeinfo : NULL);
2209 /* Insert name in all lowercase. */
2210 for (p = namebuf; *p; p++)
2213 if (strncmp (namebuf, newname, namelen))
2214 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2215 typeinfo.defined != 0 ? &typeinfo : NULL);
2220 /* Should never be called, as .req goes between the alias and the
2221 register name, not at the beginning of the line. */
2223 s_req (int a ATTRIBUTE_UNUSED)
2225 as_bad (_("invalid syntax for .req directive"));
2229 s_dn (int a ATTRIBUTE_UNUSED)
2231 as_bad (_("invalid syntax for .dn directive"));
2235 s_qn (int a ATTRIBUTE_UNUSED)
2237 as_bad (_("invalid syntax for .qn directive"));
2240 /* The .unreq directive deletes an alias which was previously defined
2241 by .req. For example:
2247 s_unreq (int a ATTRIBUTE_UNUSED)
2252 name = input_line_pointer;
2254 while (*input_line_pointer != 0
2255 && *input_line_pointer != ' '
2256 && *input_line_pointer != '\n')
2257 ++input_line_pointer;
2259 saved_char = *input_line_pointer;
2260 *input_line_pointer = 0;
2263 as_bad (_("invalid syntax for .unreq directive"));
2266 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
2269 as_bad (_("unknown register alias '%s'"), name);
2270 else if (reg->builtin)
2271 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2275 hash_delete (arm_reg_hsh, name);
2276 free ((char *) reg->name);
2283 *input_line_pointer = saved_char;
2284 demand_empty_rest_of_line ();
2287 /* Directives: Instruction set selection. */
2290 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2291 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2292 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2293 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2295 static enum mstate mapstate = MAP_UNDEFINED;
2298 mapping_state (enum mstate state)
2301 const char * symname;
2304 if (mapstate == state)
2305 /* The mapping symbol has already been emitted.
2306 There is nothing else to do. */
2315 type = BSF_NO_FLAGS;
2319 type = BSF_NO_FLAGS;
2323 type = BSF_NO_FLAGS;
2331 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2333 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
2334 symbol_table_insert (symbolP);
2335 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2340 THUMB_SET_FUNC (symbolP, 0);
2341 ARM_SET_THUMB (symbolP, 0);
2342 ARM_SET_INTERWORK (symbolP, support_interwork);
2346 THUMB_SET_FUNC (symbolP, 1);
2347 ARM_SET_THUMB (symbolP, 1);
2348 ARM_SET_INTERWORK (symbolP, support_interwork);
2357 #define mapping_state(x) /* nothing */
2360 /* Find the real, Thumb encoded start of a Thumb function. */
2363 find_real_start (symbolS * symbolP)
2366 const char * name = S_GET_NAME (symbolP);
2367 symbolS * new_target;
2369 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2370 #define STUB_NAME ".real_start_of"
2375 /* The compiler may generate BL instructions to local labels because
2376 it needs to perform a branch to a far away location. These labels
2377 do not have a corresponding ".real_start_of" label. We check
2378 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2379 the ".real_start_of" convention for nonlocal branches. */
2380 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2383 real_start = ACONCAT ((STUB_NAME, name, NULL));
2384 new_target = symbol_find (real_start);
2386 if (new_target == NULL)
2388 as_warn ("Failed to find real start of function: %s\n", name);
2389 new_target = symbolP;
2396 opcode_select (int width)
2403 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2404 as_bad (_("selected processor does not support THUMB opcodes"));
2407 /* No need to force the alignment, since we will have been
2408 coming from ARM mode, which is word-aligned. */
2409 record_alignment (now_seg, 1);
2411 mapping_state (MAP_THUMB);
2417 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2418 as_bad (_("selected processor does not support ARM opcodes"));
2423 frag_align (2, 0, 0);
2425 record_alignment (now_seg, 1);
2427 mapping_state (MAP_ARM);
2431 as_bad (_("invalid instruction size selected (%d)"), width);
2436 s_arm (int ignore ATTRIBUTE_UNUSED)
2439 demand_empty_rest_of_line ();
2443 s_thumb (int ignore ATTRIBUTE_UNUSED)
2446 demand_empty_rest_of_line ();
2450 s_code (int unused ATTRIBUTE_UNUSED)
2454 temp = get_absolute_expression ();
2459 opcode_select (temp);
2463 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2468 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2470 /* If we are not already in thumb mode go into it, EVEN if
2471 the target processor does not support thumb instructions.
2472 This is used by gcc/config/arm/lib1funcs.asm for example
2473 to compile interworking support functions even if the
2474 target processor should not support interworking. */
2478 record_alignment (now_seg, 1);
2481 demand_empty_rest_of_line ();
2485 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2489 /* The following label is the name/address of the start of a Thumb function.
2490 We need to know this for the interworking support. */
2491 label_is_thumb_function_name = TRUE;
2494 /* Perform a .set directive, but also mark the alias as
2495 being a thumb function. */
2498 s_thumb_set (int equiv)
2500 /* XXX the following is a duplicate of the code for s_set() in read.c
2501 We cannot just call that code as we need to get at the symbol that
2508 /* Especial apologies for the random logic:
2509 This just grew, and could be parsed much more simply!
2511 name = input_line_pointer;
2512 delim = get_symbol_end ();
2513 end_name = input_line_pointer;
2516 if (*input_line_pointer != ',')
2519 as_bad (_("expected comma after name \"%s\""), name);
2521 ignore_rest_of_line ();
2525 input_line_pointer++;
2528 if (name[0] == '.' && name[1] == '\0')
2530 /* XXX - this should not happen to .thumb_set. */
2534 if ((symbolP = symbol_find (name)) == NULL
2535 && (symbolP = md_undefined_symbol (name)) == NULL)
2538 /* When doing symbol listings, play games with dummy fragments living
2539 outside the normal fragment chain to record the file and line info
2541 if (listing & LISTING_SYMBOLS)
2543 extern struct list_info_struct * listing_tail;
2544 fragS * dummy_frag = xmalloc (sizeof (fragS));
2546 memset (dummy_frag, 0, sizeof (fragS));
2547 dummy_frag->fr_type = rs_fill;
2548 dummy_frag->line = listing_tail;
2549 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2550 dummy_frag->fr_symbol = symbolP;
2554 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2557 /* "set" symbols are local unless otherwise specified. */
2558 SF_SET_LOCAL (symbolP);
2559 #endif /* OBJ_COFF */
2560 } /* Make a new symbol. */
2562 symbol_table_insert (symbolP);
2567 && S_IS_DEFINED (symbolP)
2568 && S_GET_SEGMENT (symbolP) != reg_section)
2569 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2571 pseudo_set (symbolP);
2573 demand_empty_rest_of_line ();
2575 /* XXX Now we come to the Thumb specific bit of code. */
2577 THUMB_SET_FUNC (symbolP, 1);
2578 ARM_SET_THUMB (symbolP, 1);
2579 #if defined OBJ_ELF || defined OBJ_COFF
2580 ARM_SET_INTERWORK (symbolP, support_interwork);
2584 /* Directives: Mode selection. */
2586 /* .syntax [unified|divided] - choose the new unified syntax
2587 (same for Arm and Thumb encoding, modulo slight differences in what
2588 can be represented) or the old divergent syntax for each mode. */
2590 s_syntax (int unused ATTRIBUTE_UNUSED)
2594 name = input_line_pointer;
2595 delim = get_symbol_end ();
2597 if (!strcasecmp (name, "unified"))
2598 unified_syntax = TRUE;
2599 else if (!strcasecmp (name, "divided"))
2600 unified_syntax = FALSE;
2603 as_bad (_("unrecognized syntax mode \"%s\""), name);
2606 *input_line_pointer = delim;
2607 demand_empty_rest_of_line ();
2610 /* Directives: sectioning and alignment. */
2612 /* Same as s_align_ptwo but align 0 => align 2. */
2615 s_align (int unused ATTRIBUTE_UNUSED)
2620 long max_alignment = 15;
2622 temp = get_absolute_expression ();
2623 if (temp > max_alignment)
2624 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2627 as_bad (_("alignment negative. 0 assumed."));
2631 if (*input_line_pointer == ',')
2633 input_line_pointer++;
2634 temp_fill = get_absolute_expression ();
2646 /* Only make a frag if we HAVE to. */
2647 if (temp && !need_pass_2)
2649 if (!fill_p && subseg_text_p (now_seg))
2650 frag_align_code (temp, 0);
2652 frag_align (temp, (int) temp_fill, 0);
2654 demand_empty_rest_of_line ();
2656 record_alignment (now_seg, temp);
2660 s_bss (int ignore ATTRIBUTE_UNUSED)
2662 /* We don't support putting frags in the BSS segment, we fake it by
2663 marking in_bss, then looking at s_skip for clues. */
2664 subseg_set (bss_section, 0);
2665 demand_empty_rest_of_line ();
2666 mapping_state (MAP_DATA);
2670 s_even (int ignore ATTRIBUTE_UNUSED)
2672 /* Never make frag if expect extra pass. */
2674 frag_align (1, 0, 0);
2676 record_alignment (now_seg, 1);
2678 demand_empty_rest_of_line ();
2681 /* Directives: Literal pools. */
2683 static literal_pool *
2684 find_literal_pool (void)
2686 literal_pool * pool;
2688 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2690 if (pool->section == now_seg
2691 && pool->sub_section == now_subseg)
2698 static literal_pool *
2699 find_or_make_literal_pool (void)
2701 /* Next literal pool ID number. */
2702 static unsigned int latest_pool_num = 1;
2703 literal_pool * pool;
2705 pool = find_literal_pool ();
2709 /* Create a new pool. */
2710 pool = xmalloc (sizeof (* pool));
2714 pool->next_free_entry = 0;
2715 pool->section = now_seg;
2716 pool->sub_section = now_subseg;
2717 pool->next = list_of_pools;
2718 pool->symbol = NULL;
2720 /* Add it to the list. */
2721 list_of_pools = pool;
2724 /* New pools, and emptied pools, will have a NULL symbol. */
2725 if (pool->symbol == NULL)
2727 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
2728 (valueT) 0, &zero_address_frag);
2729 pool->id = latest_pool_num ++;
2736 /* Add the literal in the global 'inst'
2737 structure to the relevent literal pool. */
2740 add_to_lit_pool (void)
2742 literal_pool * pool;
2745 pool = find_or_make_literal_pool ();
2747 /* Check if this literal value is already in the pool. */
2748 for (entry = 0; entry < pool->next_free_entry; entry ++)
2750 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2751 && (inst.reloc.exp.X_op == O_constant)
2752 && (pool->literals[entry].X_add_number
2753 == inst.reloc.exp.X_add_number)
2754 && (pool->literals[entry].X_unsigned
2755 == inst.reloc.exp.X_unsigned))
2758 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2759 && (inst.reloc.exp.X_op == O_symbol)
2760 && (pool->literals[entry].X_add_number
2761 == inst.reloc.exp.X_add_number)
2762 && (pool->literals[entry].X_add_symbol
2763 == inst.reloc.exp.X_add_symbol)
2764 && (pool->literals[entry].X_op_symbol
2765 == inst.reloc.exp.X_op_symbol))
2769 /* Do we need to create a new entry? */
2770 if (entry == pool->next_free_entry)
2772 if (entry >= MAX_LITERAL_POOL_SIZE)
2774 inst.error = _("literal pool overflow");
2778 pool->literals[entry] = inst.reloc.exp;
2779 pool->next_free_entry += 1;
2782 inst.reloc.exp.X_op = O_symbol;
2783 inst.reloc.exp.X_add_number = ((int) entry) * 4;
2784 inst.reloc.exp.X_add_symbol = pool->symbol;
2789 /* Can't use symbol_new here, so have to create a symbol and then at
2790 a later date assign it a value. Thats what these functions do. */
2793 symbol_locate (symbolS * symbolP,
2794 const char * name, /* It is copied, the caller can modify. */
2795 segT segment, /* Segment identifier (SEG_<something>). */
2796 valueT valu, /* Symbol value. */
2797 fragS * frag) /* Associated fragment. */
2799 unsigned int name_length;
2800 char * preserved_copy_of_name;
2802 name_length = strlen (name) + 1; /* +1 for \0. */
2803 obstack_grow (¬es, name, name_length);
2804 preserved_copy_of_name = obstack_finish (¬es);
2806 #ifdef tc_canonicalize_symbol_name
2807 preserved_copy_of_name =
2808 tc_canonicalize_symbol_name (preserved_copy_of_name);
2811 S_SET_NAME (symbolP, preserved_copy_of_name);
2813 S_SET_SEGMENT (symbolP, segment);
2814 S_SET_VALUE (symbolP, valu);
2815 symbol_clear_list_pointers (symbolP);
2817 symbol_set_frag (symbolP, frag);
2819 /* Link to end of symbol chain. */
2821 extern int symbol_table_frozen;
2823 if (symbol_table_frozen)
2827 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
2829 obj_symbol_new_hook (symbolP);
2831 #ifdef tc_symbol_new_hook
2832 tc_symbol_new_hook (symbolP);
2836 verify_symbol_chain (symbol_rootP, symbol_lastP);
2837 #endif /* DEBUG_SYMS */
2842 s_ltorg (int ignored ATTRIBUTE_UNUSED)
2845 literal_pool * pool;
2848 pool = find_literal_pool ();
2850 || pool->symbol == NULL
2851 || pool->next_free_entry == 0)
2854 mapping_state (MAP_DATA);
2856 /* Align pool as you have word accesses.
2857 Only make a frag if we have to. */
2859 frag_align (2, 0, 0);
2861 record_alignment (now_seg, 2);
2863 sprintf (sym_name, "$$lit_\002%x", pool->id);
2865 symbol_locate (pool->symbol, sym_name, now_seg,
2866 (valueT) frag_now_fix (), frag_now);
2867 symbol_table_insert (pool->symbol);
2869 ARM_SET_THUMB (pool->symbol, thumb_mode);
2871 #if defined OBJ_COFF || defined OBJ_ELF
2872 ARM_SET_INTERWORK (pool->symbol, support_interwork);
2875 for (entry = 0; entry < pool->next_free_entry; entry ++)
2876 /* First output the expression in the instruction to the pool. */
2877 emit_expr (&(pool->literals[entry]), 4); /* .word */
2879 /* Mark the pool as empty. */
2880 pool->next_free_entry = 0;
2881 pool->symbol = NULL;
2885 /* Forward declarations for functions below, in the MD interface
2887 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
2888 static valueT create_unwind_entry (int);
2889 static void start_unwind_section (const segT, int);
2890 static void add_unwind_opcode (valueT, int);
2891 static void flush_pending_unwind (void);
2893 /* Directives: Data. */
2896 s_arm_elf_cons (int nbytes)
2900 #ifdef md_flush_pending_output
2901 md_flush_pending_output ();
2904 if (is_it_end_of_statement ())
2906 demand_empty_rest_of_line ();
2910 #ifdef md_cons_align
2911 md_cons_align (nbytes);
2914 mapping_state (MAP_DATA);
2918 char *base = input_line_pointer;
2922 if (exp.X_op != O_symbol)
2923 emit_expr (&exp, (unsigned int) nbytes);
2926 char *before_reloc = input_line_pointer;
2927 reloc = parse_reloc (&input_line_pointer);
2930 as_bad (_("unrecognized relocation suffix"));
2931 ignore_rest_of_line ();
2934 else if (reloc == BFD_RELOC_UNUSED)
2935 emit_expr (&exp, (unsigned int) nbytes);
2938 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2939 int size = bfd_get_reloc_size (howto);
2941 if (reloc == BFD_RELOC_ARM_PLT32)
2943 as_bad (_("(plt) is only valid on branch targets"));
2944 reloc = BFD_RELOC_UNUSED;
2949 as_bad (_("%s relocations do not fit in %d bytes"),
2950 howto->name, nbytes);
2953 /* We've parsed an expression stopping at O_symbol.
2954 But there may be more expression left now that we
2955 have parsed the relocation marker. Parse it again.
2956 XXX Surely there is a cleaner way to do this. */
2957 char *p = input_line_pointer;
2959 char *save_buf = alloca (input_line_pointer - base);
2960 memcpy (save_buf, base, input_line_pointer - base);
2961 memmove (base + (input_line_pointer - before_reloc),
2962 base, before_reloc - base);
2964 input_line_pointer = base + (input_line_pointer-before_reloc);
2966 memcpy (base, save_buf, p - base);
2968 offset = nbytes - size;
2969 p = frag_more ((int) nbytes);
2970 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2971 size, &exp, 0, reloc);
2976 while (*input_line_pointer++ == ',');
2978 /* Put terminator back into stream. */
2979 input_line_pointer --;
2980 demand_empty_rest_of_line ();
2984 /* Parse a .rel31 directive. */
2987 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2994 if (*input_line_pointer == '1')
2995 highbit = 0x80000000;
2996 else if (*input_line_pointer != '0')
2997 as_bad (_("expected 0 or 1"));
2999 input_line_pointer++;
3000 if (*input_line_pointer != ',')
3001 as_bad (_("missing comma"));
3002 input_line_pointer++;
3004 #ifdef md_flush_pending_output
3005 md_flush_pending_output ();
3008 #ifdef md_cons_align
3012 mapping_state (MAP_DATA);
3017 md_number_to_chars (p, highbit, 4);
3018 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3019 BFD_RELOC_ARM_PREL31);
3021 demand_empty_rest_of_line ();
3024 /* Directives: AEABI stack-unwind tables. */
3026 /* Parse an unwind_fnstart directive. Simply records the current location. */
3029 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3031 demand_empty_rest_of_line ();
3032 /* Mark the start of the function. */
3033 unwind.proc_start = expr_build_dot ();
3035 /* Reset the rest of the unwind info. */
3036 unwind.opcode_count = 0;
3037 unwind.table_entry = NULL;
3038 unwind.personality_routine = NULL;
3039 unwind.personality_index = -1;
3040 unwind.frame_size = 0;
3041 unwind.fp_offset = 0;
3044 unwind.sp_restored = 0;
3048 /* Parse a handlerdata directive. Creates the exception handling table entry
3049 for the function. */
3052 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3054 demand_empty_rest_of_line ();
3055 if (unwind.table_entry)
3056 as_bad (_("dupicate .handlerdata directive"));
3058 create_unwind_entry (1);
3061 /* Parse an unwind_fnend directive. Generates the index table entry. */
3064 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3070 demand_empty_rest_of_line ();
3072 /* Add eh table entry. */
3073 if (unwind.table_entry == NULL)
3074 val = create_unwind_entry (0);
3078 /* Add index table entry. This is two words. */
3079 start_unwind_section (unwind.saved_seg, 1);
3080 frag_align (2, 0, 0);
3081 record_alignment (now_seg, 2);
3083 ptr = frag_more (8);
3085 where = frag_now_fix () - 8;
3087 /* Self relative offset of the function start. */
3088 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3089 BFD_RELOC_ARM_PREL31);
3091 /* Indicate dependency on EHABI-defined personality routines to the
3092 linker, if it hasn't been done already. */
3093 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3094 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3096 static const char *const name[] = {
3097 "__aeabi_unwind_cpp_pr0",
3098 "__aeabi_unwind_cpp_pr1",
3099 "__aeabi_unwind_cpp_pr2"
3101 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3102 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3103 marked_pr_dependency |= 1 << unwind.personality_index;
3104 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3105 = marked_pr_dependency;
3109 /* Inline exception table entry. */
3110 md_number_to_chars (ptr + 4, val, 4);
3112 /* Self relative offset of the table entry. */
3113 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3114 BFD_RELOC_ARM_PREL31);
3116 /* Restore the original section. */
3117 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3121 /* Parse an unwind_cantunwind directive. */
3124 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3126 demand_empty_rest_of_line ();
3127 if (unwind.personality_routine || unwind.personality_index != -1)
3128 as_bad (_("personality routine specified for cantunwind frame"));
3130 unwind.personality_index = -2;
3134 /* Parse a personalityindex directive. */
3137 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3141 if (unwind.personality_routine || unwind.personality_index != -1)
3142 as_bad (_("duplicate .personalityindex directive"));
3146 if (exp.X_op != O_constant
3147 || exp.X_add_number < 0 || exp.X_add_number > 15)
3149 as_bad (_("bad personality routine number"));
3150 ignore_rest_of_line ();
3154 unwind.personality_index = exp.X_add_number;
3156 demand_empty_rest_of_line ();
3160 /* Parse a personality directive. */
3163 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3167 if (unwind.personality_routine || unwind.personality_index != -1)
3168 as_bad (_("duplicate .personality directive"));
3170 name = input_line_pointer;
3171 c = get_symbol_end ();
3172 p = input_line_pointer;
3173 unwind.personality_routine = symbol_find_or_make (name);
3175 demand_empty_rest_of_line ();
3179 /* Parse a directive saving core registers. */
3182 s_arm_unwind_save_core (void)
3188 range = parse_reg_list (&input_line_pointer);
3191 as_bad (_("expected register list"));
3192 ignore_rest_of_line ();
3196 demand_empty_rest_of_line ();
3198 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3199 into .unwind_save {..., sp...}. We aren't bothered about the value of
3200 ip because it is clobbered by calls. */
3201 if (unwind.sp_restored && unwind.fp_reg == 12
3202 && (range & 0x3000) == 0x1000)
3204 unwind.opcode_count--;
3205 unwind.sp_restored = 0;
3206 range = (range | 0x2000) & ~0x1000;
3207 unwind.pending_offset = 0;
3213 /* See if we can use the short opcodes. These pop a block of up to 8
3214 registers starting with r4, plus maybe r14. */
3215 for (n = 0; n < 8; n++)
3217 /* Break at the first non-saved register. */
3218 if ((range & (1 << (n + 4))) == 0)
3221 /* See if there are any other bits set. */
3222 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3224 /* Use the long form. */
3225 op = 0x8000 | ((range >> 4) & 0xfff);
3226 add_unwind_opcode (op, 2);
3230 /* Use the short form. */
3232 op = 0xa8; /* Pop r14. */
3234 op = 0xa0; /* Do not pop r14. */
3236 add_unwind_opcode (op, 1);
3243 op = 0xb100 | (range & 0xf);
3244 add_unwind_opcode (op, 2);
3247 /* Record the number of bytes pushed. */
3248 for (n = 0; n < 16; n++)
3250 if (range & (1 << n))
3251 unwind.frame_size += 4;
3256 /* Parse a directive saving FPA registers. */
3259 s_arm_unwind_save_fpa (int reg)
3265 /* Get Number of registers to transfer. */
3266 if (skip_past_comma (&input_line_pointer) != FAIL)
3269 exp.X_op = O_illegal;
3271 if (exp.X_op != O_constant)
3273 as_bad (_("expected , <constant>"));
3274 ignore_rest_of_line ();
3278 num_regs = exp.X_add_number;
3280 if (num_regs < 1 || num_regs > 4)
3282 as_bad (_("number of registers must be in the range [1:4]"));
3283 ignore_rest_of_line ();
3287 demand_empty_rest_of_line ();
3292 op = 0xb4 | (num_regs - 1);
3293 add_unwind_opcode (op, 1);
3298 op = 0xc800 | (reg << 4) | (num_regs - 1);
3299 add_unwind_opcode (op, 2);
3301 unwind.frame_size += num_regs * 12;
3305 /* Parse a directive saving VFP registers for ARMv6 and above. */
3308 s_arm_unwind_save_vfp_armv6 (void)
3313 int num_vfpv3_regs = 0;
3314 int num_regs_below_16;
3316 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3319 as_bad (_("expected register list"));
3320 ignore_rest_of_line ();
3324 demand_empty_rest_of_line ();
3326 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3327 than FSTMX/FLDMX-style ones). */
3329 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3331 num_vfpv3_regs = count;
3332 else if (start + count > 16)
3333 num_vfpv3_regs = start + count - 16;
3335 if (num_vfpv3_regs > 0)
3337 int start_offset = start > 16 ? start - 16 : 0;
3338 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3339 add_unwind_opcode (op, 2);
3342 /* Generate opcode for registers numbered in the range 0 .. 15. */
3343 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3344 assert (num_regs_below_16 + num_vfpv3_regs == count);
3345 if (num_regs_below_16 > 0)
3347 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3348 add_unwind_opcode (op, 2);
3351 unwind.frame_size += count * 8;
3355 /* Parse a directive saving VFP registers for pre-ARMv6. */
3358 s_arm_unwind_save_vfp (void)
3364 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3367 as_bad (_("expected register list"));
3368 ignore_rest_of_line ();
3372 demand_empty_rest_of_line ();
3377 op = 0xb8 | (count - 1);
3378 add_unwind_opcode (op, 1);
3383 op = 0xb300 | (reg << 4) | (count - 1);
3384 add_unwind_opcode (op, 2);
3386 unwind.frame_size += count * 8 + 4;
3390 /* Parse a directive saving iWMMXt data registers. */
3393 s_arm_unwind_save_mmxwr (void)
3401 if (*input_line_pointer == '{')
3402 input_line_pointer++;
3406 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3410 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3415 as_tsktsk (_("register list not in ascending order"));
3418 if (*input_line_pointer == '-')
3420 input_line_pointer++;
3421 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3424 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3427 else if (reg >= hi_reg)
3429 as_bad (_("bad register range"));
3432 for (; reg < hi_reg; reg++)
3436 while (skip_past_comma (&input_line_pointer) != FAIL);
3438 if (*input_line_pointer == '}')
3439 input_line_pointer++;
3441 demand_empty_rest_of_line ();
3443 /* Generate any deferred opcodes because we're going to be looking at
3445 flush_pending_unwind ();
3447 for (i = 0; i < 16; i++)
3449 if (mask & (1 << i))
3450 unwind.frame_size += 8;
3453 /* Attempt to combine with a previous opcode. We do this because gcc
3454 likes to output separate unwind directives for a single block of
3456 if (unwind.opcode_count > 0)
3458 i = unwind.opcodes[unwind.opcode_count - 1];
3459 if ((i & 0xf8) == 0xc0)
3462 /* Only merge if the blocks are contiguous. */
3465 if ((mask & 0xfe00) == (1 << 9))
3467 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3468 unwind.opcode_count--;
3471 else if (i == 6 && unwind.opcode_count >= 2)
3473 i = unwind.opcodes[unwind.opcode_count - 2];
3477 op = 0xffff << (reg - 1);
3479 && ((mask & op) == (1u << (reg - 1))))
3481 op = (1 << (reg + i + 1)) - 1;
3482 op &= ~((1 << reg) - 1);
3484 unwind.opcode_count -= 2;
3491 /* We want to generate opcodes in the order the registers have been
3492 saved, ie. descending order. */
3493 for (reg = 15; reg >= -1; reg--)
3495 /* Save registers in blocks. */
3497 || !(mask & (1 << reg)))
3499 /* We found an unsaved reg. Generate opcodes to save the
3500 preceeding block. */
3506 op = 0xc0 | (hi_reg - 10);
3507 add_unwind_opcode (op, 1);
3512 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3513 add_unwind_opcode (op, 2);
3522 ignore_rest_of_line ();
3526 s_arm_unwind_save_mmxwcg (void)
3533 if (*input_line_pointer == '{')
3534 input_line_pointer++;
3538 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3542 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3548 as_tsktsk (_("register list not in ascending order"));
3551 if (*input_line_pointer == '-')
3553 input_line_pointer++;
3554 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3557 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3560 else if (reg >= hi_reg)
3562 as_bad (_("bad register range"));
3565 for (; reg < hi_reg; reg++)
3569 while (skip_past_comma (&input_line_pointer) != FAIL);
3571 if (*input_line_pointer == '}')
3572 input_line_pointer++;
3574 demand_empty_rest_of_line ();
3576 /* Generate any deferred opcodes because we're going to be looking at
3578 flush_pending_unwind ();
3580 for (reg = 0; reg < 16; reg++)
3582 if (mask & (1 << reg))
3583 unwind.frame_size += 4;
3586 add_unwind_opcode (op, 2);
3589 ignore_rest_of_line ();
3593 /* Parse an unwind_save directive.
3594 If the argument is non-zero, this is a .vsave directive. */
3597 s_arm_unwind_save (int arch_v6)
3600 struct reg_entry *reg;
3601 bfd_boolean had_brace = FALSE;
3603 /* Figure out what sort of save we have. */
3604 peek = input_line_pointer;
3612 reg = arm_reg_parse_multi (&peek);
3616 as_bad (_("register expected"));
3617 ignore_rest_of_line ();
3626 as_bad (_("FPA .unwind_save does not take a register list"));
3627 ignore_rest_of_line ();
3630 s_arm_unwind_save_fpa (reg->number);
3633 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
3636 s_arm_unwind_save_vfp_armv6 ();
3638 s_arm_unwind_save_vfp ();
3640 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
3641 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
3644 as_bad (_(".unwind_save does not support this kind of register"));
3645 ignore_rest_of_line ();
3650 /* Parse an unwind_movsp directive. */
3653 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
3659 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3662 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
3663 ignore_rest_of_line ();
3667 /* Optional constant. */
3668 if (skip_past_comma (&input_line_pointer) != FAIL)
3670 if (immediate_for_directive (&offset) == FAIL)
3676 demand_empty_rest_of_line ();
3678 if (reg == REG_SP || reg == REG_PC)
3680 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3684 if (unwind.fp_reg != REG_SP)
3685 as_bad (_("unexpected .unwind_movsp directive"));
3687 /* Generate opcode to restore the value. */
3689 add_unwind_opcode (op, 1);
3691 /* Record the information for later. */
3692 unwind.fp_reg = reg;
3693 unwind.fp_offset = unwind.frame_size - offset;
3694 unwind.sp_restored = 1;
3697 /* Parse an unwind_pad directive. */
3700 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
3704 if (immediate_for_directive (&offset) == FAIL)
3709 as_bad (_("stack increment must be multiple of 4"));
3710 ignore_rest_of_line ();
3714 /* Don't generate any opcodes, just record the details for later. */
3715 unwind.frame_size += offset;
3716 unwind.pending_offset += offset;
3718 demand_empty_rest_of_line ();
3721 /* Parse an unwind_setfp directive. */
3724 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
3730 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3731 if (skip_past_comma (&input_line_pointer) == FAIL)
3734 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3736 if (fp_reg == FAIL || sp_reg == FAIL)
3738 as_bad (_("expected <reg>, <reg>"));
3739 ignore_rest_of_line ();
3743 /* Optional constant. */
3744 if (skip_past_comma (&input_line_pointer) != FAIL)
3746 if (immediate_for_directive (&offset) == FAIL)
3752 demand_empty_rest_of_line ();
3754 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
3756 as_bad (_("register must be either sp or set by a previous"
3757 "unwind_movsp directive"));
3761 /* Don't generate any opcodes, just record the information for later. */
3762 unwind.fp_reg = fp_reg;
3765 unwind.fp_offset = unwind.frame_size - offset;
3767 unwind.fp_offset -= offset;
3770 /* Parse an unwind_raw directive. */
3773 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
3776 /* This is an arbitrary limit. */
3777 unsigned char op[16];
3781 if (exp.X_op == O_constant
3782 && skip_past_comma (&input_line_pointer) != FAIL)
3784 unwind.frame_size += exp.X_add_number;
3788 exp.X_op = O_illegal;
3790 if (exp.X_op != O_constant)
3792 as_bad (_("expected <offset>, <opcode>"));
3793 ignore_rest_of_line ();
3799 /* Parse the opcode. */
3804 as_bad (_("unwind opcode too long"));
3805 ignore_rest_of_line ();
3807 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
3809 as_bad (_("invalid unwind opcode"));
3810 ignore_rest_of_line ();
3813 op[count++] = exp.X_add_number;
3815 /* Parse the next byte. */
3816 if (skip_past_comma (&input_line_pointer) == FAIL)
3822 /* Add the opcode bytes in reverse order. */
3824 add_unwind_opcode (op[count], 1);
3826 demand_empty_rest_of_line ();
3830 /* Parse a .eabi_attribute directive. */
3833 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
3835 s_vendor_attribute (OBJ_ATTR_PROC);
3837 #endif /* OBJ_ELF */
3839 static void s_arm_arch (int);
3840 static void s_arm_arch_extension (int);
3841 static void s_arm_object_arch (int);
3842 static void s_arm_cpu (int);
3843 static void s_arm_fpu (int);
3848 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
3855 if (exp.X_op == O_symbol)
3856 exp.X_op = O_secrel;
3858 emit_expr (&exp, 4);
3860 while (*input_line_pointer++ == ',');
3862 input_line_pointer--;
3863 demand_empty_rest_of_line ();
3867 /* This table describes all the machine specific pseudo-ops the assembler
3868 has to support. The fields are:
3869 pseudo-op name without dot
3870 function to call to execute this pseudo-op
3871 Integer arg to pass to the function. */
3873 const pseudo_typeS md_pseudo_table[] =
3875 /* Never called because '.req' does not start a line. */
3876 { "req", s_req, 0 },
3877 /* Following two are likewise never called. */
3880 { "unreq", s_unreq, 0 },
3881 { "bss", s_bss, 0 },
3882 { "align", s_align, 0 },
3883 { "arm", s_arm, 0 },
3884 { "thumb", s_thumb, 0 },
3885 { "code", s_code, 0 },
3886 { "force_thumb", s_force_thumb, 0 },
3887 { "thumb_func", s_thumb_func, 0 },
3888 { "thumb_set", s_thumb_set, 0 },
3889 { "even", s_even, 0 },
3890 { "ltorg", s_ltorg, 0 },
3891 { "pool", s_ltorg, 0 },
3892 { "syntax", s_syntax, 0 },
3893 { "cpu", s_arm_cpu, 0 },
3894 { "arch", s_arm_arch, 0 },
3895 { "arch_extension", s_arm_arch_extension, 0 },
3896 { "object_arch", s_arm_object_arch, 0 },
3897 { "fpu", s_arm_fpu, 0 },
3899 { "word", s_arm_elf_cons, 4 },
3900 { "long", s_arm_elf_cons, 4 },
3901 { "rel31", s_arm_rel31, 0 },
3902 { "fnstart", s_arm_unwind_fnstart, 0 },
3903 { "fnend", s_arm_unwind_fnend, 0 },
3904 { "cantunwind", s_arm_unwind_cantunwind, 0 },
3905 { "personality", s_arm_unwind_personality, 0 },
3906 { "personalityindex", s_arm_unwind_personalityindex, 0 },
3907 { "handlerdata", s_arm_unwind_handlerdata, 0 },
3908 { "save", s_arm_unwind_save, 0 },
3909 { "vsave", s_arm_unwind_save, 1 },
3910 { "movsp", s_arm_unwind_movsp, 0 },
3911 { "pad", s_arm_unwind_pad, 0 },
3912 { "setfp", s_arm_unwind_setfp, 0 },
3913 { "unwind_raw", s_arm_unwind_raw, 0 },
3914 { "eabi_attribute", s_arm_eabi_attribute, 0 },
3918 /* These are used for dwarf. */
3922 /* These are used for dwarf2. */
3923 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
3924 { "loc", dwarf2_directive_loc, 0 },
3925 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
3927 { "extend", float_cons, 'x' },
3928 { "ldouble", float_cons, 'x' },
3929 { "packed", float_cons, 'p' },
3931 {"secrel32", pe_directive_secrel, 0},
3936 /* Parser functions used exclusively in instruction operands. */
3938 /* Generic immediate-value read function for use in insn parsing.
3939 STR points to the beginning of the immediate (the leading #);
3940 VAL receives the value; if the value is outside [MIN, MAX]
3941 issue an error. PREFIX_OPT is true if the immediate prefix is
3945 parse_immediate (char **str, int *val, int min, int max,
3946 bfd_boolean prefix_opt)
3949 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3950 if (exp.X_op != O_constant)
3952 inst.error = _("constant expression required");
3956 if (exp.X_add_number < min || exp.X_add_number > max)
3958 inst.error = _("immediate value out of range");
3962 *val = exp.X_add_number;
3966 /* Less-generic immediate-value read function with the possibility of loading a
3967 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
3968 instructions. Puts the result directly in inst.operands[i]. */
3971 parse_big_immediate (char **str, int i)
3976 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
3978 if (exp.X_op == O_constant)
3980 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
3981 /* If we're on a 64-bit host, then a 64-bit number can be returned using
3982 O_constant. We have to be careful not to break compilation for
3983 32-bit X_add_number, though. */
3984 if ((exp.X_add_number & ~0xffffffffl) != 0)
3986 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
3987 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
3988 inst.operands[i].regisimm = 1;
3991 else if (exp.X_op == O_big
3992 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
3993 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
3995 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
3996 /* Bignums have their least significant bits in
3997 generic_bignum[0]. Make sure we put 32 bits in imm and
3998 32 bits in reg, in a (hopefully) portable way. */
3999 assert (parts != 0);
4000 inst.operands[i].imm = 0;
4001 for (j = 0; j < parts; j++, idx++)
4002 inst.operands[i].imm |= generic_bignum[idx]
4003 << (LITTLENUM_NUMBER_OF_BITS * j);
4004 inst.operands[i].reg = 0;
4005 for (j = 0; j < parts; j++, idx++)
4006 inst.operands[i].reg |= generic_bignum[idx]
4007 << (LITTLENUM_NUMBER_OF_BITS * j);
4008 inst.operands[i].regisimm = 1;
4018 /* Returns the pseudo-register number of an FPA immediate constant,
4019 or FAIL if there isn't a valid constant here. */
4022 parse_fpa_immediate (char ** str)
4024 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4030 /* First try and match exact strings, this is to guarantee
4031 that some formats will work even for cross assembly. */
4033 for (i = 0; fp_const[i]; i++)
4035 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4039 *str += strlen (fp_const[i]);
4040 if (is_end_of_line[(unsigned char) **str])
4046 /* Just because we didn't get a match doesn't mean that the constant
4047 isn't valid, just that it is in a format that we don't
4048 automatically recognize. Try parsing it with the standard
4049 expression routines. */
4051 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4053 /* Look for a raw floating point number. */
4054 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4055 && is_end_of_line[(unsigned char) *save_in])
4057 for (i = 0; i < NUM_FLOAT_VALS; i++)
4059 for (j = 0; j < MAX_LITTLENUMS; j++)
4061 if (words[j] != fp_values[i][j])
4065 if (j == MAX_LITTLENUMS)
4073 /* Try and parse a more complex expression, this will probably fail
4074 unless the code uses a floating point prefix (eg "0f"). */
4075 save_in = input_line_pointer;
4076 input_line_pointer = *str;
4077 if (expression (&exp) == absolute_section
4078 && exp.X_op == O_big
4079 && exp.X_add_number < 0)
4081 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4083 if (gen_to_words (words, 5, (long) 15) == 0)
4085 for (i = 0; i < NUM_FLOAT_VALS; i++)
4087 for (j = 0; j < MAX_LITTLENUMS; j++)
4089 if (words[j] != fp_values[i][j])
4093 if (j == MAX_LITTLENUMS)
4095 *str = input_line_pointer;
4096 input_line_pointer = save_in;
4103 *str = input_line_pointer;
4104 input_line_pointer = save_in;
4105 inst.error = _("invalid FPA immediate expression");
4109 /* Returns 1 if a number has "quarter-precision" float format
4110 0baBbbbbbc defgh000 00000000 00000000. */
4113 is_quarter_float (unsigned imm)
4115 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4116 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4119 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4120 0baBbbbbbc defgh000 00000000 00000000.
4121 The zero and minus-zero cases need special handling, since they can't be
4122 encoded in the "quarter-precision" float format, but can nonetheless be
4123 loaded as integer constants. */
4126 parse_qfloat_immediate (char **ccp, int *immed)
4130 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4131 int found_fpchar = 0;
4133 skip_past_char (&str, '#');
4135 /* We must not accidentally parse an integer as a floating-point number. Make
4136 sure that the value we parse is not an integer by checking for special
4137 characters '.' or 'e'.
4138 FIXME: This is a horrible hack, but doing better is tricky because type
4139 information isn't in a very usable state at parse time. */
4141 skip_whitespace (fpnum);
4143 if (strncmp (fpnum, "0x", 2) == 0)
4147 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4148 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4158 if ((str = atof_ieee (str, 's', words)) != NULL)
4160 unsigned fpword = 0;
4163 /* Our FP word must be 32 bits (single-precision FP). */
4164 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4166 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4170 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4183 /* Shift operands. */
4186 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4189 struct asm_shift_name
4192 enum shift_kind kind;
4195 /* Third argument to parse_shift. */
4196 enum parse_shift_mode
4198 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4199 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4200 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4201 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4202 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4205 /* Parse a <shift> specifier on an ARM data processing instruction.
4206 This has three forms:
4208 (LSL|LSR|ASL|ASR|ROR) Rs
4209 (LSL|LSR|ASL|ASR|ROR) #imm
4212 Note that ASL is assimilated to LSL in the instruction encoding, and
4213 RRX to ROR #0 (which cannot be written as such). */
4216 parse_shift (char **str, int i, enum parse_shift_mode mode)
4218 const struct asm_shift_name *shift_name;
4219 enum shift_kind shift;
4224 for (p = *str; ISALPHA (*p); p++)
4229 inst.error = _("shift expression expected");
4233 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
4235 if (shift_name == NULL)
4237 inst.error = _("shift expression expected");
4241 shift = shift_name->kind;
4245 case NO_SHIFT_RESTRICT:
4246 case SHIFT_IMMEDIATE: break;
4248 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4249 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4251 inst.error = _("'LSL' or 'ASR' required");
4256 case SHIFT_LSL_IMMEDIATE:
4257 if (shift != SHIFT_LSL)
4259 inst.error = _("'LSL' required");
4264 case SHIFT_ASR_IMMEDIATE:
4265 if (shift != SHIFT_ASR)
4267 inst.error = _("'ASR' required");
4275 if (shift != SHIFT_RRX)
4277 /* Whitespace can appear here if the next thing is a bare digit. */
4278 skip_whitespace (p);
4280 if (mode == NO_SHIFT_RESTRICT
4281 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4283 inst.operands[i].imm = reg;
4284 inst.operands[i].immisreg = 1;
4286 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4289 inst.operands[i].shift_kind = shift;
4290 inst.operands[i].shifted = 1;
4295 /* Parse a <shifter_operand> for an ARM data processing instruction:
4298 #<immediate>, <rotate>
4302 where <shift> is defined by parse_shift above, and <rotate> is a
4303 multiple of 2 between 0 and 30. Validation of immediate operands
4304 is deferred to md_apply_fix. */
4307 parse_shifter_operand (char **str, int i)
4312 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4314 inst.operands[i].reg = value;
4315 inst.operands[i].isreg = 1;
4317 /* parse_shift will override this if appropriate */
4318 inst.reloc.exp.X_op = O_constant;
4319 inst.reloc.exp.X_add_number = 0;
4321 if (skip_past_comma (str) == FAIL)
4324 /* Shift operation on register. */
4325 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4328 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4331 if (skip_past_comma (str) == SUCCESS)
4333 /* #x, y -- ie explicit rotation by Y. */
4334 if (my_get_expression (&expr, str, GE_NO_PREFIX))
4337 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4339 inst.error = _("constant expression expected");
4343 value = expr.X_add_number;
4344 if (value < 0 || value > 30 || value % 2 != 0)
4346 inst.error = _("invalid rotation");
4349 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4351 inst.error = _("invalid constant");
4355 /* Convert to decoded value. md_apply_fix will put it back. */
4356 inst.reloc.exp.X_add_number
4357 = (((inst.reloc.exp.X_add_number << (32 - value))
4358 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4361 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4362 inst.reloc.pc_rel = 0;
4366 /* Group relocation information. Each entry in the table contains the
4367 textual name of the relocation as may appear in assembler source
4368 and must end with a colon.
4369 Along with this textual name are the relocation codes to be used if
4370 the corresponding instruction is an ALU instruction (ADD or SUB only),
4371 an LDR, an LDRS, or an LDC. */
4373 struct group_reloc_table_entry
4384 /* Varieties of non-ALU group relocation. */
4391 static struct group_reloc_table_entry group_reloc_table[] =
4392 { /* Program counter relative: */
4394 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4399 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4400 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4401 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4402 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4404 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4409 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4410 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4411 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4412 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4414 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4415 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4416 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4417 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4418 /* Section base relative */
4420 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4425 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4426 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4427 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4428 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4430 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4435 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4436 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4437 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4438 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4440 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4441 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4442 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4443 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4445 /* Given the address of a pointer pointing to the textual name of a group
4446 relocation as may appear in assembler source, attempt to find its details
4447 in group_reloc_table. The pointer will be updated to the character after
4448 the trailing colon. On failure, FAIL will be returned; SUCCESS
4449 otherwise. On success, *entry will be updated to point at the relevant
4450 group_reloc_table entry. */
4453 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4456 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4458 int length = strlen (group_reloc_table[i].name);
4460 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
4461 (*str)[length] == ':')
4463 *out = &group_reloc_table[i];
4464 *str += (length + 1);
4472 /* Parse a <shifter_operand> for an ARM data processing instruction
4473 (as for parse_shifter_operand) where group relocations are allowed:
4476 #<immediate>, <rotate>
4477 #:<group_reloc>:<expression>
4481 where <group_reloc> is one of the strings defined in group_reloc_table.
4482 The hashes are optional.
4484 Everything else is as for parse_shifter_operand. */
4486 static parse_operand_result
4487 parse_shifter_operand_group_reloc (char **str, int i)
4489 /* Determine if we have the sequence of characters #: or just :
4490 coming next. If we do, then we check for a group relocation.
4491 If we don't, punt the whole lot to parse_shifter_operand. */
4493 if (((*str)[0] == '#' && (*str)[1] == ':')
4494 || (*str)[0] == ':')
4496 struct group_reloc_table_entry *entry;
4498 if ((*str)[0] == '#')
4503 /* Try to parse a group relocation. Anything else is an error. */
4504 if (find_group_reloc_table_entry (str, &entry) == FAIL)
4506 inst.error = _("unknown group relocation");
4507 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4510 /* We now have the group relocation table entry corresponding to
4511 the name in the assembler source. Next, we parse the expression. */
4512 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
4513 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4515 /* Record the relocation type (always the ALU variant here). */
4516 inst.reloc.type = entry->alu_code;
4517 assert (inst.reloc.type != 0);
4519 return PARSE_OPERAND_SUCCESS;
4522 return parse_shifter_operand (str, i) == SUCCESS
4523 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4525 /* Never reached. */
4528 /* Parse all forms of an ARM address expression. Information is written
4529 to inst.operands[i] and/or inst.reloc.
4531 Preindexed addressing (.preind=1):
4533 [Rn, #offset] .reg=Rn .reloc.exp=offset
4534 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4535 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4536 .shift_kind=shift .reloc.exp=shift_imm
4538 These three may have a trailing ! which causes .writeback to be set also.
4540 Postindexed addressing (.postind=1, .writeback=1):
4542 [Rn], #offset .reg=Rn .reloc.exp=offset
4543 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4544 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4545 .shift_kind=shift .reloc.exp=shift_imm
4547 Unindexed addressing (.preind=0, .postind=0):
4549 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4553 [Rn]{!} shorthand for [Rn,#0]{!}
4554 =immediate .isreg=0 .reloc.exp=immediate
4555 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4557 It is the caller's responsibility to check for addressing modes not
4558 supported by the instruction, and to set inst.reloc.type. */
4560 static parse_operand_result
4561 parse_address_main (char **str, int i, int group_relocations,
4562 group_reloc_type group_type)
4567 if (skip_past_char (&p, '[') == FAIL)
4569 if (skip_past_char (&p, '=') == FAIL)
4571 /* bare address - translate to PC-relative offset */
4572 inst.reloc.pc_rel = 1;
4573 inst.operands[i].reg = REG_PC;
4574 inst.operands[i].isreg = 1;
4575 inst.operands[i].preind = 1;
4577 /* else a load-constant pseudo op, no special treatment needed here */
4579 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4580 return PARSE_OPERAND_FAIL;
4583 return PARSE_OPERAND_SUCCESS;
4586 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
4588 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4589 return PARSE_OPERAND_FAIL;
4591 inst.operands[i].reg = reg;
4592 inst.operands[i].isreg = 1;
4594 if (skip_past_comma (&p) == SUCCESS)
4596 inst.operands[i].preind = 1;
4599 else if (*p == '-') p++, inst.operands[i].negative = 1;
4601 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4603 inst.operands[i].imm = reg;
4604 inst.operands[i].immisreg = 1;
4606 if (skip_past_comma (&p) == SUCCESS)
4607 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4608 return PARSE_OPERAND_FAIL;
4610 else if (skip_past_char (&p, ':') == SUCCESS)
4612 /* FIXME: '@' should be used here, but it's filtered out by generic
4613 code before we get to see it here. This may be subject to
4616 my_get_expression (&exp, &p, GE_NO_PREFIX);
4617 if (exp.X_op != O_constant)
4619 inst.error = _("alignment must be constant");
4620 return PARSE_OPERAND_FAIL;
4622 inst.operands[i].imm = exp.X_add_number << 8;
4623 inst.operands[i].immisalign = 1;
4624 /* Alignments are not pre-indexes. */
4625 inst.operands[i].preind = 0;
4629 if (inst.operands[i].negative)
4631 inst.operands[i].negative = 0;
4635 if (group_relocations &&
4636 ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4639 struct group_reloc_table_entry *entry;
4641 /* Skip over the #: or : sequence. */
4647 /* Try to parse a group relocation. Anything else is an
4649 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
4651 inst.error = _("unknown group relocation");
4652 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4655 /* We now have the group relocation table entry corresponding to
4656 the name in the assembler source. Next, we parse the
4658 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4659 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4661 /* Record the relocation type. */
4665 inst.reloc.type = entry->ldr_code;
4669 inst.reloc.type = entry->ldrs_code;
4673 inst.reloc.type = entry->ldc_code;
4680 if (inst.reloc.type == 0)
4682 inst.error = _("this group relocation is not allowed on this instruction");
4683 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4687 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4688 return PARSE_OPERAND_FAIL;
4692 if (skip_past_char (&p, ']') == FAIL)
4694 inst.error = _("']' expected");
4695 return PARSE_OPERAND_FAIL;
4698 if (skip_past_char (&p, '!') == SUCCESS)
4699 inst.operands[i].writeback = 1;
4701 else if (skip_past_comma (&p) == SUCCESS)
4703 if (skip_past_char (&p, '{') == SUCCESS)
4705 /* [Rn], {expr} - unindexed, with option */
4706 if (parse_immediate (&p, &inst.operands[i].imm,
4707 0, 255, TRUE) == FAIL)
4708 return PARSE_OPERAND_FAIL;
4710 if (skip_past_char (&p, '}') == FAIL)
4712 inst.error = _("'}' expected at end of 'option' field");
4713 return PARSE_OPERAND_FAIL;
4715 if (inst.operands[i].preind)
4717 inst.error = _("cannot combine index with option");
4718 return PARSE_OPERAND_FAIL;
4721 return PARSE_OPERAND_SUCCESS;
4725 inst.operands[i].postind = 1;
4726 inst.operands[i].writeback = 1;
4728 if (inst.operands[i].preind)
4730 inst.error = _("cannot combine pre- and post-indexing");
4731 return PARSE_OPERAND_FAIL;
4735 else if (*p == '-') p++, inst.operands[i].negative = 1;
4737 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4739 /* We might be using the immediate for alignment already. If we
4740 are, OR the register number into the low-order bits. */
4741 if (inst.operands[i].immisalign)
4742 inst.operands[i].imm |= reg;
4744 inst.operands[i].imm = reg;
4745 inst.operands[i].immisreg = 1;
4747 if (skip_past_comma (&p) == SUCCESS)
4748 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4749 return PARSE_OPERAND_FAIL;
4753 if (inst.operands[i].negative)
4755 inst.operands[i].negative = 0;
4758 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4759 return PARSE_OPERAND_FAIL;
4764 /* If at this point neither .preind nor .postind is set, we have a
4765 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4766 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
4768 inst.operands[i].preind = 1;
4769 inst.reloc.exp.X_op = O_constant;
4770 inst.reloc.exp.X_add_number = 0;
4773 return PARSE_OPERAND_SUCCESS;
4777 parse_address (char **str, int i)
4779 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
4783 static parse_operand_result
4784 parse_address_group_reloc (char **str, int i, group_reloc_type type)
4786 return parse_address_main (str, i, 1, type);
4789 /* Parse an operand for a MOVW or MOVT instruction. */
4791 parse_half (char **str)
4796 skip_past_char (&p, '#');
4797 if (strncasecmp (p, ":lower16:", 9) == 0)
4798 inst.reloc.type = BFD_RELOC_ARM_MOVW;
4799 else if (strncasecmp (p, ":upper16:", 9) == 0)
4800 inst.reloc.type = BFD_RELOC_ARM_MOVT;
4802 if (inst.reloc.type != BFD_RELOC_UNUSED)
4808 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4811 if (inst.reloc.type == BFD_RELOC_UNUSED)
4813 if (inst.reloc.exp.X_op != O_constant)
4815 inst.error = _("constant expression expected");
4818 if (inst.reloc.exp.X_add_number < 0
4819 || inst.reloc.exp.X_add_number > 0xffff)
4821 inst.error = _("immediate value out of range");
4829 /* Miscellaneous. */
4831 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4832 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4834 parse_psr (char **str)
4837 unsigned long psr_field;
4838 const struct asm_psr *psr;
4841 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4842 feature for ease of use and backwards compatibility. */
4844 if (strncasecmp (p, "SPSR", 4) == 0)
4845 psr_field = SPSR_BIT;
4846 else if (strncasecmp (p, "CPSR", 4) == 0)
4853 while (ISALNUM (*p) || *p == '_');
4855 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
4866 /* A suffix follows. */
4872 while (ISALNUM (*p) || *p == '_');
4874 psr = hash_find_n (arm_psr_hsh, start, p - start);
4878 psr_field |= psr->field;
4883 goto error; /* Garbage after "[CS]PSR". */
4885 psr_field |= (PSR_c | PSR_f);
4891 inst.error = _("flag for {c}psr instruction expected");
4895 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4896 value suitable for splatting into the AIF field of the instruction. */
4899 parse_cps_flags (char **str)
4908 case '\0': case ',':
4911 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
4912 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
4913 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
4916 inst.error = _("unrecognized CPS flag");
4921 if (saw_a_flag == 0)
4923 inst.error = _("missing CPS flags");
4931 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4932 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4935 parse_endian_specifier (char **str)
4940 if (strncasecmp (s, "BE", 2))
4942 else if (strncasecmp (s, "LE", 2))
4946 inst.error = _("valid endian specifiers are be or le");
4950 if (ISALNUM (s[2]) || s[2] == '_')
4952 inst.error = _("valid endian specifiers are be or le");
4957 return little_endian;
4960 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4961 value suitable for poking into the rotate field of an sxt or sxta
4962 instruction, or FAIL on error. */
4965 parse_ror (char **str)
4970 if (strncasecmp (s, "ROR", 3) == 0)
4974 inst.error = _("missing rotation field after comma");
4978 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
4983 case 0: *str = s; return 0x0;
4984 case 8: *str = s; return 0x1;
4985 case 16: *str = s; return 0x2;
4986 case 24: *str = s; return 0x3;
4989 inst.error = _("rotation can only be 0, 8, 16, or 24");
4994 /* Parse a conditional code (from conds[] below). The value returned is in the
4995 range 0 .. 14, or FAIL. */
4997 parse_cond (char **str)
5000 const struct asm_cond *c;
5003 while (ISALPHA (*q))
5006 c = hash_find_n (arm_cond_hsh, p, q - p);
5009 inst.error = _("condition required");
5017 /* Parse an option for a barrier instruction. Returns the encoding for the
5020 parse_barrier (char **str)
5023 const struct asm_barrier_opt *o;
5026 while (ISALPHA (*q))
5029 o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
5037 /* Parse the operands of a table branch instruction. Similar to a memory
5040 parse_tb (char **str)
5045 if (skip_past_char (&p, '[') == FAIL)
5047 inst.error = _("'[' expected");
5051 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5053 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5056 inst.operands[0].reg = reg;
5058 if (skip_past_comma (&p) == FAIL)
5060 inst.error = _("',' expected");
5064 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5066 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5069 inst.operands[0].imm = reg;
5071 if (skip_past_comma (&p) == SUCCESS)
5073 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5075 if (inst.reloc.exp.X_add_number != 1)
5077 inst.error = _("invalid shift");
5080 inst.operands[0].shifted = 1;
5083 if (skip_past_char (&p, ']') == FAIL)
5085 inst.error = _("']' expected");
5092 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5093 information on the types the operands can take and how they are encoded.
5094 Up to four operands may be read; this function handles setting the
5095 ".present" field for each read operand itself.
5096 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5097 else returns FAIL. */
5100 parse_neon_mov (char **str, int *which_operand)
5102 int i = *which_operand, val;
5103 enum arm_reg_type rtype;
5105 struct neon_type_el optype;
5107 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5109 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5110 inst.operands[i].reg = val;
5111 inst.operands[i].isscalar = 1;
5112 inst.operands[i].vectype = optype;
5113 inst.operands[i++].present = 1;
5115 if (skip_past_comma (&ptr) == FAIL)
5118 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5121 inst.operands[i].reg = val;
5122 inst.operands[i].isreg = 1;
5123 inst.operands[i].present = 1;
5125 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5128 /* Cases 0, 1, 2, 3, 5 (D only). */
5129 if (skip_past_comma (&ptr) == FAIL)
5132 inst.operands[i].reg = val;
5133 inst.operands[i].isreg = 1;
5134 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5135 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5136 inst.operands[i].isvec = 1;
5137 inst.operands[i].vectype = optype;
5138 inst.operands[i++].present = 1;
5140 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5142 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5143 Case 13: VMOV <Sd>, <Rm> */
5144 inst.operands[i].reg = val;
5145 inst.operands[i].isreg = 1;
5146 inst.operands[i].present = 1;
5148 if (rtype == REG_TYPE_NQ)
5150 first_error (_("can't use Neon quad register here"));
5153 else if (rtype != REG_TYPE_VFS)
5156 if (skip_past_comma (&ptr) == FAIL)
5158 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5160 inst.operands[i].reg = val;
5161 inst.operands[i].isreg = 1;
5162 inst.operands[i].present = 1;
5165 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5166 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5167 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5168 Case 10: VMOV.F32 <Sd>, #<imm>
5169 Case 11: VMOV.F64 <Dd>, #<imm> */
5170 inst.operands[i].immisfloat = 1;
5171 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5174 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5175 Case 1: VMOV<c><q> <Dd>, <Dm>
5176 Case 8: VMOV.F32 <Sd>, <Sm>
5177 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5179 inst.operands[i].reg = val;
5180 inst.operands[i].isreg = 1;
5181 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5182 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5183 inst.operands[i].isvec = 1;
5184 inst.operands[i].vectype = optype;
5185 inst.operands[i].present = 1;
5187 if (skip_past_comma (&ptr) == SUCCESS)
5192 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5195 inst.operands[i].reg = val;
5196 inst.operands[i].isreg = 1;
5197 inst.operands[i++].present = 1;
5199 if (skip_past_comma (&ptr) == FAIL)
5202 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5205 inst.operands[i].reg = val;
5206 inst.operands[i].isreg = 1;
5207 inst.operands[i++].present = 1;
5210 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5211 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5212 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5216 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5220 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5223 inst.operands[i].reg = val;
5224 inst.operands[i].isreg = 1;
5225 inst.operands[i++].present = 1;
5227 if (skip_past_comma (&ptr) == FAIL)
5230 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5232 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5233 inst.operands[i].reg = val;
5234 inst.operands[i].isscalar = 1;
5235 inst.operands[i].present = 1;
5236 inst.operands[i].vectype = optype;
5238 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5240 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5241 inst.operands[i].reg = val;
5242 inst.operands[i].isreg = 1;
5243 inst.operands[i++].present = 1;
5245 if (skip_past_comma (&ptr) == FAIL)
5248 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5251 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5255 inst.operands[i].reg = val;
5256 inst.operands[i].isreg = 1;
5257 inst.operands[i].isvec = 1;
5258 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5259 inst.operands[i].vectype = optype;
5260 inst.operands[i].present = 1;
5262 if (rtype == REG_TYPE_VFS)
5266 if (skip_past_comma (&ptr) == FAIL)
5268 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5271 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5274 inst.operands[i].reg = val;
5275 inst.operands[i].isreg = 1;
5276 inst.operands[i].isvec = 1;
5277 inst.operands[i].issingle = 1;
5278 inst.operands[i].vectype = optype;
5279 inst.operands[i].present = 1;
5282 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5286 inst.operands[i].reg = val;
5287 inst.operands[i].isreg = 1;
5288 inst.operands[i].isvec = 1;
5289 inst.operands[i].issingle = 1;
5290 inst.operands[i].vectype = optype;
5291 inst.operands[i++].present = 1;
5296 first_error (_("parse error"));
5300 /* Successfully parsed the operands. Update args. */
5306 first_error (_("expected comma"));
5310 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5314 /* Matcher codes for parse_operands. */
5315 enum operand_parse_code
5317 OP_stop, /* end of line */
5319 OP_RR, /* ARM register */
5320 OP_RRnpc, /* ARM register, not r15 */
5321 OP_RRnpcb, /* ARM register, not r15, in square brackets */
5322 OP_RRw, /* ARM register, not r15, optional trailing ! */
5323 OP_RCP, /* Coprocessor number */
5324 OP_RCN, /* Coprocessor register */
5325 OP_RF, /* FPA register */
5326 OP_RVS, /* VFP single precision register */
5327 OP_RVD, /* VFP double precision register (0..15) */
5328 OP_RND, /* Neon double precision register (0..31) */
5329 OP_RNQ, /* Neon quad precision register */
5330 OP_RVSD, /* VFP single or double precision register */
5331 OP_RNDQ, /* Neon double or quad precision register */
5332 OP_RNSDQ, /* Neon single, double or quad precision register */
5333 OP_RNSC, /* Neon scalar D[X] */
5334 OP_RVC, /* VFP control register */
5335 OP_RMF, /* Maverick F register */
5336 OP_RMD, /* Maverick D register */
5337 OP_RMFX, /* Maverick FX register */
5338 OP_RMDX, /* Maverick DX register */
5339 OP_RMAX, /* Maverick AX register */
5340 OP_RMDS, /* Maverick DSPSC register */
5341 OP_RIWR, /* iWMMXt wR register */
5342 OP_RIWC, /* iWMMXt wC register */
5343 OP_RIWG, /* iWMMXt wCG register */
5344 OP_RXA, /* XScale accumulator register */
5346 OP_REGLST, /* ARM register list */
5347 OP_VRSLST, /* VFP single-precision register list */
5348 OP_VRDLST, /* VFP double-precision register list */
5349 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5350 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
5351 OP_NSTRLST, /* Neon element/structure list */
5353 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5354 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
5355 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5356 OP_RR_RNSC, /* ARM reg or Neon scalar. */
5357 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5358 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
5359 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
5360 OP_VMOV, /* Neon VMOV operands. */
5361 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */
5362 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5363 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5365 OP_I0, /* immediate zero */
5366 OP_I7, /* immediate value 0 .. 7 */
5367 OP_I15, /* 0 .. 15 */
5368 OP_I16, /* 1 .. 16 */
5369 OP_I16z, /* 0 .. 16 */
5370 OP_I31, /* 0 .. 31 */
5371 OP_I31w, /* 0 .. 31, optional trailing ! */
5372 OP_I32, /* 1 .. 32 */
5373 OP_I32z, /* 0 .. 32 */
5374 OP_I63, /* 0 .. 63 */
5375 OP_I63s, /* -64 .. 63 */
5376 OP_I64, /* 1 .. 64 */
5377 OP_I64z, /* 0 .. 64 */
5378 OP_I255, /* 0 .. 255 */
5380 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
5381 OP_I7b, /* 0 .. 7 */
5382 OP_I15b, /* 0 .. 15 */
5383 OP_I31b, /* 0 .. 31 */
5385 OP_SH, /* shifter operand */
5386 OP_SHG, /* shifter operand with possible group relocation */
5387 OP_ADDR, /* Memory address expression (any mode) */
5388 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
5389 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
5390 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
5391 OP_EXP, /* arbitrary expression */
5392 OP_EXPi, /* same, with optional immediate prefix */
5393 OP_EXPr, /* same, with optional relocation suffix */
5394 OP_HALF, /* 0 .. 65535 or low/high reloc. */
5396 OP_CPSF, /* CPS flags */
5397 OP_ENDI, /* Endianness specifier */
5398 OP_PSR, /* CPSR/SPSR mask for msr */
5399 OP_COND, /* conditional code */
5400 OP_TB, /* Table branch. */
5402 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
5403 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
5405 OP_RRnpc_I0, /* ARM register or literal 0 */
5406 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
5407 OP_RR_EXi, /* ARM register or expression with imm prefix */
5408 OP_RF_IF, /* FPA register or immediate */
5409 OP_RIWR_RIWC, /* iWMMXt R or C reg */
5410 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
5412 /* Optional operands. */
5413 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
5414 OP_oI31b, /* 0 .. 31 */
5415 OP_oI32b, /* 1 .. 32 */
5416 OP_oIffffb, /* 0 .. 65535 */
5417 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
5419 OP_oRR, /* ARM register */
5420 OP_oRRnpc, /* ARM register, not the PC */
5421 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5422 OP_oRND, /* Optional Neon double precision register */
5423 OP_oRNQ, /* Optional Neon quad precision register */
5424 OP_oRNDQ, /* Optional Neon double or quad precision register */
5425 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5426 OP_oSHll, /* LSL immediate */
5427 OP_oSHar, /* ASR immediate */
5428 OP_oSHllar, /* LSL or ASR immediate */
5429 OP_oROR, /* ROR 0/8/16/24 */
5430 OP_oBARRIER, /* Option argument for a barrier instruction. */
5432 OP_FIRST_OPTIONAL = OP_oI7b
5435 /* Generic instruction operand parser. This does no encoding and no
5436 semantic validation; it merely squirrels values away in the inst
5437 structure. Returns SUCCESS or FAIL depending on whether the
5438 specified grammar matched. */
5440 parse_operands (char *str, const unsigned char *pattern)
5442 unsigned const char *upat = pattern;
5443 char *backtrack_pos = 0;
5444 const char *backtrack_error = 0;
5445 int i, val, backtrack_index = 0;
5446 enum arm_reg_type rtype;
5447 parse_operand_result result;
5449 #define po_char_or_fail(chr) do { \
5450 if (skip_past_char (&str, chr) == FAIL) \
5454 #define po_reg_or_fail(regtype) do { \
5455 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5456 &inst.operands[i].vectype); \
5459 first_error (_(reg_expected_msgs[regtype])); \
5462 inst.operands[i].reg = val; \
5463 inst.operands[i].isreg = 1; \
5464 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5465 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5466 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5467 || rtype == REG_TYPE_VFD \
5468 || rtype == REG_TYPE_NQ); \
5471 #define po_reg_or_goto(regtype, label) do { \
5472 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5473 &inst.operands[i].vectype); \
5477 inst.operands[i].reg = val; \
5478 inst.operands[i].isreg = 1; \
5479 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5480 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5481 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5482 || rtype == REG_TYPE_VFD \
5483 || rtype == REG_TYPE_NQ); \
5486 #define po_imm_or_fail(min, max, popt) do { \
5487 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5489 inst.operands[i].imm = val; \
5492 #define po_scalar_or_goto(elsz, label) do { \
5493 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5496 inst.operands[i].reg = val; \
5497 inst.operands[i].isscalar = 1; \
5500 #define po_misc_or_fail(expr) do { \
5505 #define po_misc_or_fail_no_backtrack(expr) do { \
5507 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5508 backtrack_pos = 0; \
5509 if (result != PARSE_OPERAND_SUCCESS) \
5513 skip_whitespace (str);
5515 for (i = 0; upat[i] != OP_stop; i++)
5517 if (upat[i] >= OP_FIRST_OPTIONAL)
5519 /* Remember where we are in case we need to backtrack. */
5520 assert (!backtrack_pos);
5521 backtrack_pos = str;
5522 backtrack_error = inst.error;
5523 backtrack_index = i;
5526 if (i > 0 && (i > 1 || inst.operands[0].present))
5527 po_char_or_fail (',');
5535 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
5536 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
5537 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
5538 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
5539 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
5540 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
5542 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
5544 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
5546 /* Also accept generic coprocessor regs for unknown registers. */
5548 po_reg_or_fail (REG_TYPE_CN);
5550 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
5551 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
5552 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
5553 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
5554 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
5555 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
5556 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
5557 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
5558 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
5559 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
5561 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
5563 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
5564 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
5566 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5568 /* Neon scalar. Using an element size of 8 means that some invalid
5569 scalars are accepted here, so deal with those in later code. */
5570 case OP_RNSC: po_scalar_or_goto (8, failure); break;
5572 /* WARNING: We can expand to two operands here. This has the potential
5573 to totally confuse the backtracking mechanism! It will be OK at
5574 least as long as we don't try to use optional args as well,
5578 po_reg_or_goto (REG_TYPE_NDQ, try_imm);
5579 inst.operands[i].present = 1;
5581 skip_past_comma (&str);
5582 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
5585 /* Optional register operand was omitted. Unfortunately, it's in
5586 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5587 here (this is a bit grotty). */
5588 inst.operands[i] = inst.operands[i-1];
5589 inst.operands[i-1].present = 0;
5592 /* There's a possibility of getting a 64-bit immediate here, so
5593 we need special handling. */
5594 if (parse_big_immediate (&str, i) == FAIL)
5596 inst.error = _("immediate value is out of range");
5604 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
5607 po_imm_or_fail (0, 0, TRUE);
5612 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
5617 po_scalar_or_goto (8, try_rr);
5620 po_reg_or_fail (REG_TYPE_RN);
5626 po_scalar_or_goto (8, try_nsdq);
5629 po_reg_or_fail (REG_TYPE_NSDQ);
5635 po_scalar_or_goto (8, try_ndq);
5638 po_reg_or_fail (REG_TYPE_NDQ);
5644 po_scalar_or_goto (8, try_vfd);
5647 po_reg_or_fail (REG_TYPE_VFD);
5652 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5653 not careful then bad things might happen. */
5654 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
5659 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
5662 /* There's a possibility of getting a 64-bit immediate here, so
5663 we need special handling. */
5664 if (parse_big_immediate (&str, i) == FAIL)
5666 inst.error = _("immediate value is out of range");
5674 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
5677 po_imm_or_fail (0, 63, TRUE);
5682 po_char_or_fail ('[');
5683 po_reg_or_fail (REG_TYPE_RN);
5684 po_char_or_fail (']');
5689 po_reg_or_fail (REG_TYPE_RN);
5690 if (skip_past_char (&str, '!') == SUCCESS)
5691 inst.operands[i].writeback = 1;
5695 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
5696 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
5697 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
5698 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
5699 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
5700 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
5701 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
5702 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
5703 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
5704 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
5705 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
5706 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
5708 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
5710 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
5711 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
5713 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
5714 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
5715 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
5717 /* Immediate variants */
5719 po_char_or_fail ('{');
5720 po_imm_or_fail (0, 255, TRUE);
5721 po_char_or_fail ('}');
5725 /* The expression parser chokes on a trailing !, so we have
5726 to find it first and zap it. */
5729 while (*s && *s != ',')
5734 inst.operands[i].writeback = 1;
5736 po_imm_or_fail (0, 31, TRUE);
5744 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5749 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5754 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5756 if (inst.reloc.exp.X_op == O_symbol)
5758 val = parse_reloc (&str);
5761 inst.error = _("unrecognized relocation suffix");
5764 else if (val != BFD_RELOC_UNUSED)
5766 inst.operands[i].imm = val;
5767 inst.operands[i].hasreloc = 1;
5772 /* Operand for MOVW or MOVT. */
5774 po_misc_or_fail (parse_half (&str));
5777 /* Register or expression */
5778 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
5779 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
5781 /* Register or immediate */
5782 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
5783 I0: po_imm_or_fail (0, 0, FALSE); break;
5785 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
5787 if (!is_immediate_prefix (*str))
5790 val = parse_fpa_immediate (&str);
5793 /* FPA immediates are encoded as registers 8-15.
5794 parse_fpa_immediate has already applied the offset. */
5795 inst.operands[i].reg = val;
5796 inst.operands[i].isreg = 1;
5799 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
5800 I32z: po_imm_or_fail (0, 32, FALSE); break;
5802 /* Two kinds of register */
5805 struct reg_entry *rege = arm_reg_parse_multi (&str);
5807 || (rege->type != REG_TYPE_MMXWR
5808 && rege->type != REG_TYPE_MMXWC
5809 && rege->type != REG_TYPE_MMXWCG))
5811 inst.error = _("iWMMXt data or control register expected");
5814 inst.operands[i].reg = rege->number;
5815 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
5821 struct reg_entry *rege = arm_reg_parse_multi (&str);
5823 || (rege->type != REG_TYPE_MMXWC
5824 && rege->type != REG_TYPE_MMXWCG))
5826 inst.error = _("iWMMXt control register expected");
5829 inst.operands[i].reg = rege->number;
5830 inst.operands[i].isreg = 1;
5835 case OP_CPSF: val = parse_cps_flags (&str); break;
5836 case OP_ENDI: val = parse_endian_specifier (&str); break;
5837 case OP_oROR: val = parse_ror (&str); break;
5838 case OP_PSR: val = parse_psr (&str); break;
5839 case OP_COND: val = parse_cond (&str); break;
5840 case OP_oBARRIER:val = parse_barrier (&str); break;
5843 po_reg_or_goto (REG_TYPE_VFC, try_psr);
5844 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
5847 val = parse_psr (&str);
5851 po_reg_or_goto (REG_TYPE_RN, try_apsr);
5854 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5856 if (strncasecmp (str, "APSR_", 5) == 0)
5863 case 'c': found = (found & 1) ? 16 : found | 1; break;
5864 case 'n': found = (found & 2) ? 16 : found | 2; break;
5865 case 'z': found = (found & 4) ? 16 : found | 4; break;
5866 case 'v': found = (found & 8) ? 16 : found | 8; break;
5867 default: found = 16;
5871 inst.operands[i].isvec = 1;
5878 po_misc_or_fail (parse_tb (&str));
5881 /* Register lists */
5883 val = parse_reg_list (&str);
5886 inst.operands[1].writeback = 1;
5892 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
5896 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
5900 /* Allow Q registers too. */
5901 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5906 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5908 inst.operands[i].issingle = 1;
5913 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5918 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
5919 &inst.operands[i].vectype);
5922 /* Addressing modes */
5924 po_misc_or_fail (parse_address (&str, i));
5928 po_misc_or_fail_no_backtrack (
5929 parse_address_group_reloc (&str, i, GROUP_LDR));
5933 po_misc_or_fail_no_backtrack (
5934 parse_address_group_reloc (&str, i, GROUP_LDRS));
5938 po_misc_or_fail_no_backtrack (
5939 parse_address_group_reloc (&str, i, GROUP_LDC));
5943 po_misc_or_fail (parse_shifter_operand (&str, i));
5947 po_misc_or_fail_no_backtrack (
5948 parse_shifter_operand_group_reloc (&str, i));
5952 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
5956 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
5960 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
5964 as_fatal ("unhandled operand code %d", upat[i]);
5967 /* Various value-based sanity checks and shared operations. We
5968 do not signal immediate failures for the register constraints;
5969 this allows a syntax error to take precedence. */
5978 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
5979 inst.error = BAD_PC;
5997 inst.operands[i].imm = val;
6004 /* If we get here, this operand was successfully parsed. */
6005 inst.operands[i].present = 1;
6009 inst.error = BAD_ARGS;
6014 /* The parse routine should already have set inst.error, but set a
6015 defaut here just in case. */
6017 inst.error = _("syntax error");
6021 /* Do not backtrack over a trailing optional argument that
6022 absorbed some text. We will only fail again, with the
6023 'garbage following instruction' error message, which is
6024 probably less helpful than the current one. */
6025 if (backtrack_index == i && backtrack_pos != str
6026 && upat[i+1] == OP_stop)
6029 inst.error = _("syntax error");
6033 /* Try again, skipping the optional argument at backtrack_pos. */
6034 str = backtrack_pos;
6035 inst.error = backtrack_error;
6036 inst.operands[backtrack_index].present = 0;
6037 i = backtrack_index;
6041 /* Check that we have parsed all the arguments. */
6042 if (*str != '\0' && !inst.error)
6043 inst.error = _("garbage following instruction");
6045 return inst.error ? FAIL : SUCCESS;
6048 #undef po_char_or_fail
6049 #undef po_reg_or_fail
6050 #undef po_reg_or_goto
6051 #undef po_imm_or_fail
6052 #undef po_scalar_or_fail
6054 /* Shorthand macro for instruction encoding functions issuing errors. */
6055 #define constraint(expr, err) do { \
6063 /* Functions for operand encoding. ARM, then Thumb. */
6065 #define rotate_left(v, n) (v << (n % 32) | v >> ((32 - n) % 32))
6067 /* If VAL can be encoded in the immediate field of an ARM instruction,
6068 return the encoded form. Otherwise, return FAIL. */
6071 encode_arm_immediate (unsigned int val)
6075 for (i = 0; i < 32; i += 2)
6076 if ((a = rotate_left (val, i)) <= 0xff)
6077 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6082 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6083 return the encoded form. Otherwise, return FAIL. */
6085 encode_thumb32_immediate (unsigned int val)
6092 for (i = 1; i <= 24; i++)
6095 if ((val & ~(0xff << i)) == 0)
6096 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6100 if (val == ((a << 16) | a))
6102 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6106 if (val == ((a << 16) | a))
6107 return 0x200 | (a >> 8);
6111 /* Encode a VFP SP or DP register number into inst.instruction. */
6114 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6116 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6119 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
6122 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6125 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6130 first_error (_("D register out of range for selected VFP version"));
6138 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6142 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6146 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6150 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6154 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6158 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6166 /* Encode a <shift> in an ARM-format instruction. The immediate,
6167 if any, is handled by md_apply_fix. */
6169 encode_arm_shift (int i)
6171 if (inst.operands[i].shift_kind == SHIFT_RRX)
6172 inst.instruction |= SHIFT_ROR << 5;
6175 inst.instruction |= inst.operands[i].shift_kind << 5;
6176 if (inst.operands[i].immisreg)
6178 inst.instruction |= SHIFT_BY_REG;
6179 inst.instruction |= inst.operands[i].imm << 8;
6182 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6187 encode_arm_shifter_operand (int i)
6189 if (inst.operands[i].isreg)
6191 inst.instruction |= inst.operands[i].reg;
6192 encode_arm_shift (i);
6195 inst.instruction |= INST_IMMEDIATE;
6198 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6200 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
6202 assert (inst.operands[i].isreg);
6203 inst.instruction |= inst.operands[i].reg << 16;
6205 if (inst.operands[i].preind)
6209 inst.error = _("instruction does not accept preindexed addressing");
6212 inst.instruction |= PRE_INDEX;
6213 if (inst.operands[i].writeback)
6214 inst.instruction |= WRITE_BACK;
6217 else if (inst.operands[i].postind)
6219 assert (inst.operands[i].writeback);
6221 inst.instruction |= WRITE_BACK;
6223 else /* unindexed - only for coprocessor */
6225 inst.error = _("instruction does not accept unindexed addressing");
6229 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
6230 && (((inst.instruction & 0x000f0000) >> 16)
6231 == ((inst.instruction & 0x0000f000) >> 12)))
6232 as_warn ((inst.instruction & LOAD_BIT)
6233 ? _("destination register same as write-back base")
6234 : _("source register same as write-back base"));
6237 /* inst.operands[i] was set up by parse_address. Encode it into an
6238 ARM-format mode 2 load or store instruction. If is_t is true,
6239 reject forms that cannot be used with a T instruction (i.e. not
6242 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
6244 encode_arm_addr_mode_common (i, is_t);
6246 if (inst.operands[i].immisreg)
6248 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
6249 inst.instruction |= inst.operands[i].imm;
6250 if (!inst.operands[i].negative)
6251 inst.instruction |= INDEX_UP;
6252 if (inst.operands[i].shifted)
6254 if (inst.operands[i].shift_kind == SHIFT_RRX)
6255 inst.instruction |= SHIFT_ROR << 5;
6258 inst.instruction |= inst.operands[i].shift_kind << 5;
6259 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6263 else /* immediate offset in inst.reloc */
6265 if (inst.reloc.type == BFD_RELOC_UNUSED)
6266 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
6270 /* inst.operands[i] was set up by parse_address. Encode it into an
6271 ARM-format mode 3 load or store instruction. Reject forms that
6272 cannot be used with such instructions. If is_t is true, reject
6273 forms that cannot be used with a T instruction (i.e. not
6276 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
6278 if (inst.operands[i].immisreg && inst.operands[i].shifted)
6280 inst.error = _("instruction does not accept scaled register index");
6284 encode_arm_addr_mode_common (i, is_t);
6286 if (inst.operands[i].immisreg)
6288 inst.instruction |= inst.operands[i].imm;
6289 if (!inst.operands[i].negative)
6290 inst.instruction |= INDEX_UP;
6292 else /* immediate offset in inst.reloc */
6294 inst.instruction |= HWOFFSET_IMM;
6295 if (inst.reloc.type == BFD_RELOC_UNUSED)
6296 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
6300 /* inst.operands[i] was set up by parse_address. Encode it into an
6301 ARM-format instruction. Reject all forms which cannot be encoded
6302 into a coprocessor load/store instruction. If wb_ok is false,
6303 reject use of writeback; if unind_ok is false, reject use of
6304 unindexed addressing. If reloc_override is not 0, use it instead
6305 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6306 (in which case it is preserved). */
6309 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
6311 inst.instruction |= inst.operands[i].reg << 16;
6313 assert (!(inst.operands[i].preind && inst.operands[i].postind));
6315 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
6317 assert (!inst.operands[i].writeback);
6320 inst.error = _("instruction does not support unindexed addressing");
6323 inst.instruction |= inst.operands[i].imm;
6324 inst.instruction |= INDEX_UP;
6328 if (inst.operands[i].preind)
6329 inst.instruction |= PRE_INDEX;
6331 if (inst.operands[i].writeback)
6333 if (inst.operands[i].reg == REG_PC)
6335 inst.error = _("pc may not be used with write-back");
6340 inst.error = _("instruction does not support writeback");
6343 inst.instruction |= WRITE_BACK;
6347 inst.reloc.type = reloc_override;
6348 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
6349 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
6350 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
6353 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
6355 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
6361 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6362 Determine whether it can be performed with a move instruction; if
6363 it can, convert inst.instruction to that move instruction and
6364 return 1; if it can't, convert inst.instruction to a literal-pool
6365 load and return 0. If this is not a valid thing to do in the
6366 current context, set inst.error and return 1.
6368 inst.operands[i] describes the destination register. */
6371 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
6376 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
6380 if ((inst.instruction & tbit) == 0)
6382 inst.error = _("invalid pseudo operation");
6385 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
6387 inst.error = _("constant expression expected");
6390 if (inst.reloc.exp.X_op == O_constant)
6394 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
6396 /* This can be done with a mov(1) instruction. */
6397 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6398 inst.instruction |= inst.reloc.exp.X_add_number;
6404 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
6407 /* This can be done with a mov instruction. */
6408 inst.instruction &= LITERAL_MASK;
6409 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
6410 inst.instruction |= value & 0xfff;
6414 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
6417 /* This can be done with a mvn instruction. */
6418 inst.instruction &= LITERAL_MASK;
6419 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
6420 inst.instruction |= value & 0xfff;
6426 if (add_to_lit_pool () == FAIL)
6428 inst.error = _("literal pool insertion failed");
6431 inst.operands[1].reg = REG_PC;
6432 inst.operands[1].isreg = 1;
6433 inst.operands[1].preind = 1;
6434 inst.reloc.pc_rel = 1;
6435 inst.reloc.type = (thumb_p
6436 ? BFD_RELOC_ARM_THUMB_OFFSET
6438 ? BFD_RELOC_ARM_HWLITERAL
6439 : BFD_RELOC_ARM_LITERAL));
6443 /* Functions for instruction encoding, sorted by subarchitecture.
6444 First some generics; their names are taken from the conventional
6445 bit positions for register arguments in ARM format instructions. */
6455 inst.instruction |= inst.operands[0].reg << 12;
6461 inst.instruction |= inst.operands[0].reg << 12;
6462 inst.instruction |= inst.operands[1].reg;
6468 inst.instruction |= inst.operands[0].reg << 12;
6469 inst.instruction |= inst.operands[1].reg << 16;
6475 inst.instruction |= inst.operands[0].reg << 16;
6476 inst.instruction |= inst.operands[1].reg << 12;
6482 unsigned Rn = inst.operands[2].reg;
6483 /* Enforce restrictions on SWP instruction. */
6484 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
6485 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6486 _("Rn must not overlap other operands"));
6487 inst.instruction |= inst.operands[0].reg << 12;
6488 inst.instruction |= inst.operands[1].reg;
6489 inst.instruction |= Rn << 16;
6495 inst.instruction |= inst.operands[0].reg << 12;
6496 inst.instruction |= inst.operands[1].reg << 16;
6497 inst.instruction |= inst.operands[2].reg;
6503 inst.instruction |= inst.operands[0].reg;
6504 inst.instruction |= inst.operands[1].reg << 12;
6505 inst.instruction |= inst.operands[2].reg << 16;
6511 inst.instruction |= inst.operands[0].imm;
6517 inst.instruction |= inst.operands[0].reg << 12;
6518 encode_arm_cp_address (1, TRUE, TRUE, 0);
6521 /* ARM instructions, in alphabetical order by function name (except
6522 that wrapper functions appear immediately after the function they
6525 /* This is a pseudo-op of the form "adr rd, label" to be converted
6526 into a relative address of the form "add rd, pc, #label-.-8". */
6531 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6533 /* Frag hacking will turn this into a sub instruction if the offset turns
6534 out to be negative. */
6535 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
6536 inst.reloc.pc_rel = 1;
6537 inst.reloc.exp.X_add_number -= 8;
6540 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6541 into a relative address of the form:
6542 add rd, pc, #low(label-.-8)"
6543 add rd, rd, #high(label-.-8)" */
6548 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6550 /* Frag hacking will turn this into a sub instruction if the offset turns
6551 out to be negative. */
6552 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
6553 inst.reloc.pc_rel = 1;
6554 inst.size = INSN_SIZE * 2;
6555 inst.reloc.exp.X_add_number -= 8;
6561 if (!inst.operands[1].present)
6562 inst.operands[1].reg = inst.operands[0].reg;
6563 inst.instruction |= inst.operands[0].reg << 12;
6564 inst.instruction |= inst.operands[1].reg << 16;
6565 encode_arm_shifter_operand (2);
6571 if (inst.operands[0].present)
6573 constraint ((inst.instruction & 0xf0) != 0x40
6574 && inst.operands[0].imm != 0xf,
6575 "bad barrier type");
6576 inst.instruction |= inst.operands[0].imm;
6579 inst.instruction |= 0xf;
6585 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6586 constraint (msb > 32, _("bit-field extends past end of register"));
6587 /* The instruction encoding stores the LSB and MSB,
6588 not the LSB and width. */
6589 inst.instruction |= inst.operands[0].reg << 12;
6590 inst.instruction |= inst.operands[1].imm << 7;
6591 inst.instruction |= (msb - 1) << 16;
6599 /* #0 in second position is alternative syntax for bfc, which is
6600 the same instruction but with REG_PC in the Rm field. */
6601 if (!inst.operands[1].isreg)
6602 inst.operands[1].reg = REG_PC;
6604 msb = inst.operands[2].imm + inst.operands[3].imm;
6605 constraint (msb > 32, _("bit-field extends past end of register"));
6606 /* The instruction encoding stores the LSB and MSB,
6607 not the LSB and width. */
6608 inst.instruction |= inst.operands[0].reg << 12;
6609 inst.instruction |= inst.operands[1].reg;
6610 inst.instruction |= inst.operands[2].imm << 7;
6611 inst.instruction |= (msb - 1) << 16;
6617 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6618 _("bit-field extends past end of register"));
6619 inst.instruction |= inst.operands[0].reg << 12;
6620 inst.instruction |= inst.operands[1].reg;
6621 inst.instruction |= inst.operands[2].imm << 7;
6622 inst.instruction |= (inst.operands[3].imm - 1) << 16;
6625 /* ARM V5 breakpoint instruction (argument parse)
6626 BKPT <16 bit unsigned immediate>
6627 Instruction is not conditional.
6628 The bit pattern given in insns[] has the COND_ALWAYS condition,
6629 and it is an error if the caller tried to override that. */
6634 /* Top 12 of 16 bits to bits 19:8. */
6635 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
6637 /* Bottom 4 of 16 bits to bits 3:0. */
6638 inst.instruction |= inst.operands[0].imm & 0xf;
6642 encode_branch (int default_reloc)
6644 if (inst.operands[0].hasreloc)
6646 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
6647 _("the only suffix valid here is '(plt)'"));
6648 inst.reloc.type = BFD_RELOC_ARM_PLT32;
6652 inst.reloc.type = default_reloc;
6654 inst.reloc.pc_rel = 1;
6661 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6662 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6665 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6672 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6674 if (inst.cond == COND_ALWAYS)
6675 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6677 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6681 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6684 /* ARM V5 branch-link-exchange instruction (argument parse)
6685 BLX <target_addr> ie BLX(1)
6686 BLX{<condition>} <Rm> ie BLX(2)
6687 Unfortunately, there are two different opcodes for this mnemonic.
6688 So, the insns[].value is not used, and the code here zaps values
6689 into inst.instruction.
6690 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6695 if (inst.operands[0].isreg)
6697 /* Arg is a register; the opcode provided by insns[] is correct.
6698 It is not illegal to do "blx pc", just useless. */
6699 if (inst.operands[0].reg == REG_PC)
6700 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6702 inst.instruction |= inst.operands[0].reg;
6706 /* Arg is an address; this instruction cannot be executed
6707 conditionally, and the opcode must be adjusted. */
6708 constraint (inst.cond != COND_ALWAYS, BAD_COND);
6709 inst.instruction = 0xfa000000;
6711 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6712 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6715 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
6722 if (inst.operands[0].reg == REG_PC)
6723 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6725 inst.instruction |= inst.operands[0].reg;
6729 /* ARM v5TEJ. Jump to Jazelle code. */
6734 if (inst.operands[0].reg == REG_PC)
6735 as_tsktsk (_("use of r15 in bxj is not really useful"));
6737 inst.instruction |= inst.operands[0].reg;
6740 /* Co-processor data operation:
6741 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6742 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6746 inst.instruction |= inst.operands[0].reg << 8;
6747 inst.instruction |= inst.operands[1].imm << 20;
6748 inst.instruction |= inst.operands[2].reg << 12;
6749 inst.instruction |= inst.operands[3].reg << 16;
6750 inst.instruction |= inst.operands[4].reg;
6751 inst.instruction |= inst.operands[5].imm << 5;
6757 inst.instruction |= inst.operands[0].reg << 16;
6758 encode_arm_shifter_operand (1);
6761 /* Transfer between coprocessor and ARM registers.
6762 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6767 No special properties. */
6772 inst.instruction |= inst.operands[0].reg << 8;
6773 inst.instruction |= inst.operands[1].imm << 21;
6774 /* If this is a vector we are using the APSR_nzcv syntax, encode as r15 */
6775 if (inst.operands[2].isvec != 0)
6776 inst.instruction |= 15 << 12;
6778 inst.instruction |= inst.operands[2].reg << 12;
6779 inst.instruction |= inst.operands[3].reg << 16;
6780 inst.instruction |= inst.operands[4].reg;
6781 inst.instruction |= inst.operands[5].imm << 5;
6784 /* Transfer between coprocessor register and pair of ARM registers.
6785 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6790 Two XScale instructions are special cases of these:
6792 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6793 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6795 Result unpredicatable if Rd or Rn is R15. */
6800 inst.instruction |= inst.operands[0].reg << 8;
6801 inst.instruction |= inst.operands[1].imm << 4;
6802 inst.instruction |= inst.operands[2].reg << 12;
6803 inst.instruction |= inst.operands[3].reg << 16;
6804 inst.instruction |= inst.operands[4].reg;
6810 inst.instruction |= inst.operands[0].imm << 6;
6811 if (inst.operands[1].present)
6813 inst.instruction |= CPSI_MMOD;
6814 inst.instruction |= inst.operands[1].imm;
6821 inst.instruction |= inst.operands[0].imm;
6827 /* There is no IT instruction in ARM mode. We
6828 process it but do not generate code for it. */
6835 int base_reg = inst.operands[0].reg;
6836 int range = inst.operands[1].imm;
6838 inst.instruction |= base_reg << 16;
6839 inst.instruction |= range;
6841 if (inst.operands[1].writeback)
6842 inst.instruction |= LDM_TYPE_2_OR_3;
6844 if (inst.operands[0].writeback)
6846 inst.instruction |= WRITE_BACK;
6847 /* Check for unpredictable uses of writeback. */
6848 if (inst.instruction & LOAD_BIT)
6850 /* Not allowed in LDM type 2. */
6851 if ((inst.instruction & LDM_TYPE_2_OR_3)
6852 && ((range & (1 << REG_PC)) == 0))
6853 as_warn (_("writeback of base register is UNPREDICTABLE"));
6854 /* Only allowed if base reg not in list for other types. */
6855 else if (range & (1 << base_reg))
6856 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6860 /* Not allowed for type 2. */
6861 if (inst.instruction & LDM_TYPE_2_OR_3)
6862 as_warn (_("writeback of base register is UNPREDICTABLE"));
6863 /* Only allowed if base reg not in list, or first in list. */
6864 else if ((range & (1 << base_reg))
6865 && (range & ((1 << base_reg) - 1)))
6866 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6871 /* ARMv5TE load-consecutive (argument parse)
6880 constraint (inst.operands[0].reg % 2 != 0,
6881 _("first destination register must be even"));
6882 constraint (inst.operands[1].present
6883 && inst.operands[1].reg != inst.operands[0].reg + 1,
6884 _("can only load two consecutive registers"));
6885 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6886 constraint (!inst.operands[2].isreg, _("'[' expected"));
6888 if (!inst.operands[1].present)
6889 inst.operands[1].reg = inst.operands[0].reg + 1;
6891 if (inst.instruction & LOAD_BIT)
6893 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6894 register and the first register written; we have to diagnose
6895 overlap between the base and the second register written here. */
6897 if (inst.operands[2].reg == inst.operands[1].reg
6898 && (inst.operands[2].writeback || inst.operands[2].postind))
6899 as_warn (_("base register written back, and overlaps "
6900 "second destination register"));
6902 /* For an index-register load, the index register must not overlap the
6903 destination (even if not write-back). */
6904 else if (inst.operands[2].immisreg
6905 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6906 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
6907 as_warn (_("index register overlaps destination register"));
6910 inst.instruction |= inst.operands[0].reg << 12;
6911 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
6917 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6918 || inst.operands[1].postind || inst.operands[1].writeback
6919 || inst.operands[1].immisreg || inst.operands[1].shifted
6920 || inst.operands[1].negative
6921 /* This can arise if the programmer has written
6923 or if they have mistakenly used a register name as the last
6926 It is very difficult to distinguish between these two cases
6927 because "rX" might actually be a label. ie the register
6928 name has been occluded by a symbol of the same name. So we
6929 just generate a general 'bad addressing mode' type error
6930 message and leave it up to the programmer to discover the
6931 true cause and fix their mistake. */
6932 || (inst.operands[1].reg == REG_PC),
6935 constraint (inst.reloc.exp.X_op != O_constant
6936 || inst.reloc.exp.X_add_number != 0,
6937 _("offset must be zero in ARM encoding"));
6939 inst.instruction |= inst.operands[0].reg << 12;
6940 inst.instruction |= inst.operands[1].reg << 16;
6941 inst.reloc.type = BFD_RELOC_UNUSED;
6947 constraint (inst.operands[0].reg % 2 != 0,
6948 _("even register required"));
6949 constraint (inst.operands[1].present
6950 && inst.operands[1].reg != inst.operands[0].reg + 1,
6951 _("can only load two consecutive registers"));
6952 /* If op 1 were present and equal to PC, this function wouldn't
6953 have been called in the first place. */
6954 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6956 inst.instruction |= inst.operands[0].reg << 12;
6957 inst.instruction |= inst.operands[2].reg << 16;
6963 inst.instruction |= inst.operands[0].reg << 12;
6964 if (!inst.operands[1].isreg)
6965 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
6967 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
6973 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6975 if (inst.operands[1].preind)
6977 constraint (inst.reloc.exp.X_op != O_constant ||
6978 inst.reloc.exp.X_add_number != 0,
6979 _("this instruction requires a post-indexed address"));
6981 inst.operands[1].preind = 0;
6982 inst.operands[1].postind = 1;
6983 inst.operands[1].writeback = 1;
6985 inst.instruction |= inst.operands[0].reg << 12;
6986 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
6989 /* Halfword and signed-byte load/store operations. */
6994 inst.instruction |= inst.operands[0].reg << 12;
6995 if (!inst.operands[1].isreg)
6996 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
6998 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7004 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7006 if (inst.operands[1].preind)
7008 constraint (inst.reloc.exp.X_op != O_constant ||
7009 inst.reloc.exp.X_add_number != 0,
7010 _("this instruction requires a post-indexed address"));
7012 inst.operands[1].preind = 0;
7013 inst.operands[1].postind = 1;
7014 inst.operands[1].writeback = 1;
7016 inst.instruction |= inst.operands[0].reg << 12;
7017 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7020 /* Co-processor register load/store.
7021 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7025 inst.instruction |= inst.operands[0].reg << 8;
7026 inst.instruction |= inst.operands[1].reg << 12;
7027 encode_arm_cp_address (2, TRUE, TRUE, 0);
7033 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7034 if (inst.operands[0].reg == inst.operands[1].reg
7035 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7036 && !(inst.instruction & 0x00400000))
7037 as_tsktsk (_("Rd and Rm should be different in mla"));
7039 inst.instruction |= inst.operands[0].reg << 16;
7040 inst.instruction |= inst.operands[1].reg;
7041 inst.instruction |= inst.operands[2].reg << 8;
7042 inst.instruction |= inst.operands[3].reg << 12;
7048 inst.instruction |= inst.operands[0].reg << 12;
7049 encode_arm_shifter_operand (1);
7052 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7059 top = (inst.instruction & 0x00400000) != 0;
7060 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7061 _(":lower16: not allowed this instruction"));
7062 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7063 _(":upper16: not allowed instruction"));
7064 inst.instruction |= inst.operands[0].reg << 12;
7065 if (inst.reloc.type == BFD_RELOC_UNUSED)
7067 imm = inst.reloc.exp.X_add_number;
7068 /* The value is in two pieces: 0:11, 16:19. */
7069 inst.instruction |= (imm & 0x00000fff);
7070 inst.instruction |= (imm & 0x0000f000) << 4;
7074 static void do_vfp_nsyn_opcode (const char *);
7077 do_vfp_nsyn_mrs (void)
7079 if (inst.operands[0].isvec)
7081 if (inst.operands[1].reg != 1)
7082 first_error (_("operand 1 must be FPSCR"));
7083 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
7084 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
7085 do_vfp_nsyn_opcode ("fmstat");
7087 else if (inst.operands[1].isvec)
7088 do_vfp_nsyn_opcode ("fmrx");
7096 do_vfp_nsyn_msr (void)
7098 if (inst.operands[0].isvec)
7099 do_vfp_nsyn_opcode ("fmxr");
7111 /* The destination register can be r0-r14 or APSR_nzcv */
7112 if (inst.operands[0].reg > 14)
7114 inst.error = BAD_PC;
7118 /* If the destination is r13 and not in ARM mode then unprefictable */
7119 if (thumb_mode && inst.operands[0].reg == REG_SP)
7121 inst.error = BAD_SP;
7125 /* If the destination is APSR_nzcv */
7126 if (inst.operands[0].isvec && inst.operands[1].reg != 1)
7128 inst.error = BAD_VMRS;
7132 if (inst.operands[0].isvec)
7135 rt = inst.operands[0].reg;
7137 /* Or in the registers to use */
7138 inst.instruction |= rt << 12;
7139 inst.instruction |= inst.operands[1].reg << 16;
7145 /* The destination register can be r0-r14 or APSR_nzcv */
7146 if (inst.operands[1].reg > 14)
7148 inst.error = BAD_PC;
7152 /* If the destination is r13 and not in ARM mode then unprefictable */
7153 if (thumb_mode && inst.operands[0].reg == REG_SP)
7155 inst.error = BAD_SP;
7159 /* Or in the registers to use */
7160 inst.instruction |= inst.operands[1].reg << 12;
7161 inst.instruction |= inst.operands[0].reg << 16;
7167 if (do_vfp_nsyn_mrs () == SUCCESS)
7170 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7171 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7173 _("'CPSR' or 'SPSR' expected"));
7174 inst.instruction |= inst.operands[0].reg << 12;
7175 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7178 /* Two possible forms:
7179 "{C|S}PSR_<field>, Rm",
7180 "{C|S}PSR_f, #expression". */
7185 if (do_vfp_nsyn_msr () == SUCCESS)
7188 inst.instruction |= inst.operands[0].imm;
7189 if (inst.operands[1].isreg)
7190 inst.instruction |= inst.operands[1].reg;
7193 inst.instruction |= INST_IMMEDIATE;
7194 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7195 inst.reloc.pc_rel = 0;
7202 if (!inst.operands[2].present)
7203 inst.operands[2].reg = inst.operands[0].reg;
7204 inst.instruction |= inst.operands[0].reg << 16;
7205 inst.instruction |= inst.operands[1].reg;
7206 inst.instruction |= inst.operands[2].reg << 8;
7208 if (inst.operands[0].reg == inst.operands[1].reg
7209 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7210 as_tsktsk (_("Rd and Rm should be different in mul"));
7213 /* Long Multiply Parser
7214 UMULL RdLo, RdHi, Rm, Rs
7215 SMULL RdLo, RdHi, Rm, Rs
7216 UMLAL RdLo, RdHi, Rm, Rs
7217 SMLAL RdLo, RdHi, Rm, Rs. */
7222 inst.instruction |= inst.operands[0].reg << 12;
7223 inst.instruction |= inst.operands[1].reg << 16;
7224 inst.instruction |= inst.operands[2].reg;
7225 inst.instruction |= inst.operands[3].reg << 8;
7227 /* rdhi, rdlo and rm must all be different prior to ARMv6. */
7228 if (inst.operands[0].reg == inst.operands[1].reg
7229 || ((inst.operands[0].reg == inst.operands[2].reg
7230 || inst.operands[1].reg == inst.operands[2].reg)
7231 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)))
7232 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7238 if (inst.operands[0].present)
7240 /* Architectural NOP hints are CPSR sets with no bits selected. */
7241 inst.instruction &= 0xf0000000;
7242 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
7246 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7247 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7248 Condition defaults to COND_ALWAYS.
7249 Error if Rd, Rn or Rm are R15. */
7254 inst.instruction |= inst.operands[0].reg << 12;
7255 inst.instruction |= inst.operands[1].reg << 16;
7256 inst.instruction |= inst.operands[2].reg;
7257 if (inst.operands[3].present)
7258 encode_arm_shift (3);
7261 /* ARM V6 PKHTB (Argument Parse). */
7266 if (!inst.operands[3].present)
7268 /* If the shift specifier is omitted, turn the instruction
7269 into pkhbt rd, rm, rn. */
7270 inst.instruction &= 0xfff00010;
7271 inst.instruction |= inst.operands[0].reg << 12;
7272 inst.instruction |= inst.operands[1].reg;
7273 inst.instruction |= inst.operands[2].reg << 16;
7277 inst.instruction |= inst.operands[0].reg << 12;
7278 inst.instruction |= inst.operands[1].reg << 16;
7279 inst.instruction |= inst.operands[2].reg;
7280 encode_arm_shift (3);
7284 /* ARMv5TE: Preload-Cache
7288 Syntactically, like LDR with B=1, W=0, L=1. */
7293 constraint (!inst.operands[0].isreg,
7294 _("'[' expected after PLD mnemonic"));
7295 constraint (inst.operands[0].postind,
7296 _("post-indexed expression used in preload instruction"));
7297 constraint (inst.operands[0].writeback,
7298 _("writeback used in preload instruction"));
7299 constraint (!inst.operands[0].preind,
7300 _("unindexed addressing used in preload instruction"));
7301 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7304 /* ARMv7: PLI <addr_mode> */
7308 constraint (!inst.operands[0].isreg,
7309 _("'[' expected after PLI mnemonic"));
7310 constraint (inst.operands[0].postind,
7311 _("post-indexed expression used in preload instruction"));
7312 constraint (inst.operands[0].writeback,
7313 _("writeback used in preload instruction"));
7314 constraint (!inst.operands[0].preind,
7315 _("unindexed addressing used in preload instruction"));
7316 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7317 inst.instruction &= ~PRE_INDEX;
7323 inst.operands[1] = inst.operands[0];
7324 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
7325 inst.operands[0].isreg = 1;
7326 inst.operands[0].writeback = 1;
7327 inst.operands[0].reg = REG_SP;
7331 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7332 word at the specified address and the following word
7334 Unconditionally executed.
7335 Error if Rn is R15. */
7340 inst.instruction |= inst.operands[0].reg << 16;
7341 if (inst.operands[0].writeback)
7342 inst.instruction |= WRITE_BACK;
7345 /* ARM V6 ssat (argument parse). */
7350 inst.instruction |= inst.operands[0].reg << 12;
7351 inst.instruction |= (inst.operands[1].imm - 1) << 16;
7352 inst.instruction |= inst.operands[2].reg;
7354 if (inst.operands[3].present)
7355 encode_arm_shift (3);
7358 /* ARM V6 usat (argument parse). */
7363 inst.instruction |= inst.operands[0].reg << 12;
7364 inst.instruction |= inst.operands[1].imm << 16;
7365 inst.instruction |= inst.operands[2].reg;
7367 if (inst.operands[3].present)
7368 encode_arm_shift (3);
7371 /* ARM V6 ssat16 (argument parse). */
7376 inst.instruction |= inst.operands[0].reg << 12;
7377 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7378 inst.instruction |= inst.operands[2].reg;
7384 inst.instruction |= inst.operands[0].reg << 12;
7385 inst.instruction |= inst.operands[1].imm << 16;
7386 inst.instruction |= inst.operands[2].reg;
7389 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7390 preserving the other bits.
7392 setend <endian_specifier>, where <endian_specifier> is either
7398 if (inst.operands[0].imm)
7399 inst.instruction |= 0x200;
7405 unsigned int Rm = (inst.operands[1].present
7406 ? inst.operands[1].reg
7407 : inst.operands[0].reg);
7409 inst.instruction |= inst.operands[0].reg << 12;
7410 inst.instruction |= Rm;
7411 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
7413 inst.instruction |= inst.operands[2].reg << 8;
7414 inst.instruction |= SHIFT_BY_REG;
7417 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7423 inst.reloc.type = BFD_RELOC_ARM_SMC;
7424 inst.reloc.pc_rel = 0;
7430 inst.reloc.type = BFD_RELOC_ARM_SWI;
7431 inst.reloc.pc_rel = 0;
7434 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7435 SMLAxy{cond} Rd,Rm,Rs,Rn
7436 SMLAWy{cond} Rd,Rm,Rs,Rn
7437 Error if any register is R15. */
7442 inst.instruction |= inst.operands[0].reg << 16;
7443 inst.instruction |= inst.operands[1].reg;
7444 inst.instruction |= inst.operands[2].reg << 8;
7445 inst.instruction |= inst.operands[3].reg << 12;
7448 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7449 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7450 Error if any register is R15.
7451 Warning if Rdlo == Rdhi. */
7456 inst.instruction |= inst.operands[0].reg << 12;
7457 inst.instruction |= inst.operands[1].reg << 16;
7458 inst.instruction |= inst.operands[2].reg;
7459 inst.instruction |= inst.operands[3].reg << 8;
7461 if (inst.operands[0].reg == inst.operands[1].reg)
7462 as_tsktsk (_("rdhi and rdlo must be different"));
7465 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7466 SMULxy{cond} Rd,Rm,Rs
7467 Error if any register is R15. */
7472 inst.instruction |= inst.operands[0].reg << 16;
7473 inst.instruction |= inst.operands[1].reg;
7474 inst.instruction |= inst.operands[2].reg << 8;
7477 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7478 the same for both ARM and Thumb-2. */
7485 if (inst.operands[0].present)
7487 reg = inst.operands[0].reg;
7488 constraint (reg != 13, _("SRS base register must be r13"));
7493 inst.instruction |= reg << 16;
7494 inst.instruction |= inst.operands[1].imm;
7495 if (inst.operands[0].writeback || inst.operands[1].writeback)
7496 inst.instruction |= WRITE_BACK;
7499 /* ARM V6 strex (argument parse). */
7504 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7505 || inst.operands[2].postind || inst.operands[2].writeback
7506 || inst.operands[2].immisreg || inst.operands[2].shifted
7507 || inst.operands[2].negative
7508 /* See comment in do_ldrex(). */
7509 || (inst.operands[2].reg == REG_PC),
7512 constraint (inst.operands[0].reg == inst.operands[1].reg
7513 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
7515 constraint (inst.reloc.exp.X_op != O_constant
7516 || inst.reloc.exp.X_add_number != 0,
7517 _("offset must be zero in ARM encoding"));
7519 inst.instruction |= inst.operands[0].reg << 12;
7520 inst.instruction |= inst.operands[1].reg;
7521 inst.instruction |= inst.operands[2].reg << 16;
7522 inst.reloc.type = BFD_RELOC_UNUSED;
7528 constraint (inst.operands[1].reg % 2 != 0,
7529 _("even register required"));
7530 constraint (inst.operands[2].present
7531 && inst.operands[2].reg != inst.operands[1].reg + 1,
7532 _("can only store two consecutive registers"));
7533 /* If op 2 were present and equal to PC, this function wouldn't
7534 have been called in the first place. */
7535 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
7537 constraint (inst.operands[0].reg == inst.operands[1].reg
7538 || inst.operands[0].reg == inst.operands[1].reg + 1
7539 || inst.operands[0].reg == inst.operands[3].reg,
7542 inst.instruction |= inst.operands[0].reg << 12;
7543 inst.instruction |= inst.operands[1].reg;
7544 inst.instruction |= inst.operands[3].reg << 16;
7547 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7548 extends it to 32-bits, and adds the result to a value in another
7549 register. You can specify a rotation by 0, 8, 16, or 24 bits
7550 before extracting the 16-bit value.
7551 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7552 Condition defaults to COND_ALWAYS.
7553 Error if any register uses R15. */
7558 inst.instruction |= inst.operands[0].reg << 12;
7559 inst.instruction |= inst.operands[1].reg << 16;
7560 inst.instruction |= inst.operands[2].reg;
7561 inst.instruction |= inst.operands[3].imm << 10;
7566 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7567 Condition defaults to COND_ALWAYS.
7568 Error if any register uses R15. */
7573 inst.instruction |= inst.operands[0].reg << 12;
7574 inst.instruction |= inst.operands[1].reg;
7575 inst.instruction |= inst.operands[2].imm << 10;
7578 /* VFP instructions. In a logical order: SP variant first, monad
7579 before dyad, arithmetic then move then load/store. */
7582 do_vfp_sp_monadic (void)
7584 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7585 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7589 do_vfp_sp_dyadic (void)
7591 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7592 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7593 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7597 do_vfp_sp_compare_z (void)
7599 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7603 do_vfp_dp_sp_cvt (void)
7605 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7606 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7610 do_vfp_sp_dp_cvt (void)
7612 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7613 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7617 do_vfp_reg_from_sp (void)
7619 inst.instruction |= inst.operands[0].reg << 12;
7620 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7624 do_vfp_reg2_from_sp2 (void)
7626 constraint (inst.operands[2].imm != 2,
7627 _("only two consecutive VFP SP registers allowed here"));
7628 inst.instruction |= inst.operands[0].reg << 12;
7629 inst.instruction |= inst.operands[1].reg << 16;
7630 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7634 do_vfp_sp_from_reg (void)
7636 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
7637 inst.instruction |= inst.operands[1].reg << 12;
7641 do_vfp_sp2_from_reg2 (void)
7643 constraint (inst.operands[0].imm != 2,
7644 _("only two consecutive VFP SP registers allowed here"));
7645 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
7646 inst.instruction |= inst.operands[1].reg << 12;
7647 inst.instruction |= inst.operands[2].reg << 16;
7651 do_vfp_sp_ldst (void)
7653 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7654 encode_arm_cp_address (1, FALSE, TRUE, 0);
7658 do_vfp_dp_ldst (void)
7660 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7661 encode_arm_cp_address (1, FALSE, TRUE, 0);
7666 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
7668 if (inst.operands[0].writeback)
7669 inst.instruction |= WRITE_BACK;
7671 constraint (ldstm_type != VFP_LDSTMIA,
7672 _("this addressing mode requires base-register writeback"));
7673 inst.instruction |= inst.operands[0].reg << 16;
7674 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
7675 inst.instruction |= inst.operands[1].imm;
7679 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
7683 if (inst.operands[0].writeback)
7684 inst.instruction |= WRITE_BACK;
7686 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
7687 _("this addressing mode requires base-register writeback"));
7689 inst.instruction |= inst.operands[0].reg << 16;
7690 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7692 count = inst.operands[1].imm << 1;
7693 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
7696 inst.instruction |= count;
7700 do_vfp_sp_ldstmia (void)
7702 vfp_sp_ldstm (VFP_LDSTMIA);
7706 do_vfp_sp_ldstmdb (void)
7708 vfp_sp_ldstm (VFP_LDSTMDB);
7712 do_vfp_dp_ldstmia (void)
7714 vfp_dp_ldstm (VFP_LDSTMIA);
7718 do_vfp_dp_ldstmdb (void)
7720 vfp_dp_ldstm (VFP_LDSTMDB);
7724 do_vfp_xp_ldstmia (void)
7726 vfp_dp_ldstm (VFP_LDSTMIAX);
7730 do_vfp_xp_ldstmdb (void)
7732 vfp_dp_ldstm (VFP_LDSTMDBX);
7736 do_vfp_dp_rd_rm (void)
7738 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7739 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7743 do_vfp_dp_rn_rd (void)
7745 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
7746 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7750 do_vfp_dp_rd_rn (void)
7752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7753 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7757 do_vfp_dp_rd_rn_rm (void)
7759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7760 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7761 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
7767 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7771 do_vfp_dp_rm_rd_rn (void)
7773 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
7774 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7775 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
7778 /* VFPv3 instructions. */
7780 do_vfp_sp_const (void)
7782 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7783 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7784 inst.instruction |= (inst.operands[1].imm & 0x0f);
7788 do_vfp_dp_const (void)
7790 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7791 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7792 inst.instruction |= (inst.operands[1].imm & 0x0f);
7796 vfp_conv (int srcsize)
7798 unsigned immbits = srcsize - inst.operands[1].imm;
7799 inst.instruction |= (immbits & 1) << 5;
7800 inst.instruction |= (immbits >> 1);
7804 do_vfp_sp_conv_16 (void)
7806 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7811 do_vfp_dp_conv_16 (void)
7813 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7818 do_vfp_sp_conv_32 (void)
7820 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7825 do_vfp_dp_conv_32 (void)
7827 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7832 /* FPA instructions. Also in a logical order. */
7837 inst.instruction |= inst.operands[0].reg << 16;
7838 inst.instruction |= inst.operands[1].reg;
7842 do_fpa_ldmstm (void)
7844 inst.instruction |= inst.operands[0].reg << 12;
7845 switch (inst.operands[1].imm)
7847 case 1: inst.instruction |= CP_T_X; break;
7848 case 2: inst.instruction |= CP_T_Y; break;
7849 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
7854 if (inst.instruction & (PRE_INDEX | INDEX_UP))
7856 /* The instruction specified "ea" or "fd", so we can only accept
7857 [Rn]{!}. The instruction does not really support stacking or
7858 unstacking, so we have to emulate these by setting appropriate
7859 bits and offsets. */
7860 constraint (inst.reloc.exp.X_op != O_constant
7861 || inst.reloc.exp.X_add_number != 0,
7862 _("this instruction does not support indexing"));
7864 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
7865 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
7867 if (!(inst.instruction & INDEX_UP))
7868 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
7870 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
7872 inst.operands[2].preind = 0;
7873 inst.operands[2].postind = 1;
7877 encode_arm_cp_address (2, TRUE, TRUE, 0);
7881 /* iWMMXt instructions: strictly in alphabetical order. */
7884 do_iwmmxt_tandorc (void)
7886 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
7890 do_iwmmxt_textrc (void)
7892 inst.instruction |= inst.operands[0].reg << 12;
7893 inst.instruction |= inst.operands[1].imm;
7897 do_iwmmxt_textrm (void)
7899 inst.instruction |= inst.operands[0].reg << 12;
7900 inst.instruction |= inst.operands[1].reg << 16;
7901 inst.instruction |= inst.operands[2].imm;
7905 do_iwmmxt_tinsr (void)
7907 inst.instruction |= inst.operands[0].reg << 16;
7908 inst.instruction |= inst.operands[1].reg << 12;
7909 inst.instruction |= inst.operands[2].imm;
7913 do_iwmmxt_tmia (void)
7915 inst.instruction |= inst.operands[0].reg << 5;
7916 inst.instruction |= inst.operands[1].reg;
7917 inst.instruction |= inst.operands[2].reg << 12;
7921 do_iwmmxt_waligni (void)
7923 inst.instruction |= inst.operands[0].reg << 12;
7924 inst.instruction |= inst.operands[1].reg << 16;
7925 inst.instruction |= inst.operands[2].reg;
7926 inst.instruction |= inst.operands[3].imm << 20;
7930 do_iwmmxt_wmerge (void)
7932 inst.instruction |= inst.operands[0].reg << 12;
7933 inst.instruction |= inst.operands[1].reg << 16;
7934 inst.instruction |= inst.operands[2].reg;
7935 inst.instruction |= inst.operands[3].imm << 21;
7939 do_iwmmxt_wmov (void)
7941 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7942 inst.instruction |= inst.operands[0].reg << 12;
7943 inst.instruction |= inst.operands[1].reg << 16;
7944 inst.instruction |= inst.operands[1].reg;
7948 do_iwmmxt_wldstbh (void)
7951 inst.instruction |= inst.operands[0].reg << 12;
7953 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
7955 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
7956 encode_arm_cp_address (1, TRUE, FALSE, reloc);
7960 do_iwmmxt_wldstw (void)
7962 /* RIWR_RIWC clears .isreg for a control register. */
7963 if (!inst.operands[0].isreg)
7965 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7966 inst.instruction |= 0xf0000000;
7969 inst.instruction |= inst.operands[0].reg << 12;
7970 encode_arm_cp_address (1, TRUE, TRUE, 0);
7974 do_iwmmxt_wldstd (void)
7976 inst.instruction |= inst.operands[0].reg << 12;
7977 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
7978 && inst.operands[1].immisreg)
7980 inst.instruction &= ~0x1a000ff;
7981 inst.instruction |= (0xf << 28);
7982 if (inst.operands[1].preind)
7983 inst.instruction |= PRE_INDEX;
7984 if (!inst.operands[1].negative)
7985 inst.instruction |= INDEX_UP;
7986 if (inst.operands[1].writeback)
7987 inst.instruction |= WRITE_BACK;
7988 inst.instruction |= inst.operands[1].reg << 16;
7989 inst.instruction |= inst.reloc.exp.X_add_number << 4;
7990 inst.instruction |= inst.operands[1].imm;
7993 encode_arm_cp_address (1, TRUE, FALSE, 0);
7997 do_iwmmxt_wshufh (void)
7999 inst.instruction |= inst.operands[0].reg << 12;
8000 inst.instruction |= inst.operands[1].reg << 16;
8001 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
8002 inst.instruction |= (inst.operands[2].imm & 0x0f);
8006 do_iwmmxt_wzero (void)
8008 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8009 inst.instruction |= inst.operands[0].reg;
8010 inst.instruction |= inst.operands[0].reg << 12;
8011 inst.instruction |= inst.operands[0].reg << 16;
8015 do_iwmmxt_wrwrwr_or_imm5 (void)
8017 if (inst.operands[2].isreg)
8020 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
8021 _("immediate operand requires iWMMXt2"));
8023 if (inst.operands[2].imm == 0)
8025 switch ((inst.instruction >> 20) & 0xf)
8031 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8032 inst.operands[2].imm = 16;
8033 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
8039 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8040 inst.operands[2].imm = 32;
8041 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
8048 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8050 wrn = (inst.instruction >> 16) & 0xf;
8051 inst.instruction &= 0xff0fff0f;
8052 inst.instruction |= wrn;
8053 /* Bail out here; the instruction is now assembled. */
8058 /* Map 32 -> 0, etc. */
8059 inst.operands[2].imm &= 0x1f;
8060 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
8064 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8065 operations first, then control, shift, and load/store. */
8067 /* Insns like "foo X,Y,Z". */
8070 do_mav_triple (void)
8072 inst.instruction |= inst.operands[0].reg << 16;
8073 inst.instruction |= inst.operands[1].reg;
8074 inst.instruction |= inst.operands[2].reg << 12;
8077 /* Insns like "foo W,X,Y,Z".
8078 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8083 inst.instruction |= inst.operands[0].reg << 5;
8084 inst.instruction |= inst.operands[1].reg << 12;
8085 inst.instruction |= inst.operands[2].reg << 16;
8086 inst.instruction |= inst.operands[3].reg;
8089 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8093 inst.instruction |= inst.operands[1].reg << 12;
8096 /* Maverick shift immediate instructions.
8097 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8098 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8103 int imm = inst.operands[2].imm;
8105 inst.instruction |= inst.operands[0].reg << 12;
8106 inst.instruction |= inst.operands[1].reg << 16;
8108 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8109 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8110 Bit 4 should be 0. */
8111 imm = (imm & 0xf) | ((imm & 0x70) << 1);
8113 inst.instruction |= imm;
8116 /* XScale instructions. Also sorted arithmetic before move. */
8118 /* Xscale multiply-accumulate (argument parse)
8121 MIAxycc acc0,Rm,Rs. */
8126 inst.instruction |= inst.operands[1].reg;
8127 inst.instruction |= inst.operands[2].reg << 12;
8130 /* Xscale move-accumulator-register (argument parse)
8132 MARcc acc0,RdLo,RdHi. */
8137 inst.instruction |= inst.operands[1].reg << 12;
8138 inst.instruction |= inst.operands[2].reg << 16;
8141 /* Xscale move-register-accumulator (argument parse)
8143 MRAcc RdLo,RdHi,acc0. */
8148 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8149 inst.instruction |= inst.operands[0].reg << 12;
8150 inst.instruction |= inst.operands[1].reg << 16;
8153 /* Encoding functions relevant only to Thumb. */
8155 /* inst.operands[i] is a shifted-register operand; encode
8156 it into inst.instruction in the format used by Thumb32. */
8159 encode_thumb32_shifted_operand (int i)
8161 unsigned int value = inst.reloc.exp.X_add_number;
8162 unsigned int shift = inst.operands[i].shift_kind;
8164 constraint (inst.operands[i].immisreg,
8165 _("shift by register not allowed in thumb mode"));
8166 inst.instruction |= inst.operands[i].reg;
8167 if (shift == SHIFT_RRX)
8168 inst.instruction |= SHIFT_ROR << 4;
8171 constraint (inst.reloc.exp.X_op != O_constant,
8172 _("expression too complex"));
8174 constraint (value > 32
8175 || (value == 32 && (shift == SHIFT_LSL
8176 || shift == SHIFT_ROR)),
8177 _("shift expression is too large"));
8181 else if (value == 32)
8184 inst.instruction |= shift << 4;
8185 inst.instruction |= (value & 0x1c) << 10;
8186 inst.instruction |= (value & 0x03) << 6;
8191 /* inst.operands[i] was set up by parse_address. Encode it into a
8192 Thumb32 format load or store instruction. Reject forms that cannot
8193 be used with such instructions. If is_t is true, reject forms that
8194 cannot be used with a T instruction; if is_d is true, reject forms
8195 that cannot be used with a D instruction. */
8198 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
8200 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8202 constraint (!inst.operands[i].isreg,
8203 _("Instruction does not support =N addresses"));
8205 inst.instruction |= inst.operands[i].reg << 16;
8206 if (inst.operands[i].immisreg)
8208 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
8209 constraint (is_t || is_d, _("cannot use register index with this instruction"));
8210 constraint (inst.operands[i].negative,
8211 _("Thumb does not support negative register indexing"));
8212 constraint (inst.operands[i].postind,
8213 _("Thumb does not support register post-indexing"));
8214 constraint (inst.operands[i].writeback,
8215 _("Thumb does not support register indexing with writeback"));
8216 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
8217 _("Thumb supports only LSL in shifted register indexing"));
8219 inst.instruction |= inst.operands[i].imm;
8220 if (inst.operands[i].shifted)
8222 constraint (inst.reloc.exp.X_op != O_constant,
8223 _("expression too complex"));
8224 constraint (inst.reloc.exp.X_add_number < 0
8225 || inst.reloc.exp.X_add_number > 3,
8226 _("shift out of range"));
8227 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8229 inst.reloc.type = BFD_RELOC_UNUSED;
8231 else if (inst.operands[i].preind)
8233 constraint (is_pc && inst.operands[i].writeback,
8234 _("cannot use writeback with PC-relative addressing"));
8235 constraint (is_t && inst.operands[i].writeback,
8236 _("cannot use writeback with this instruction"));
8240 inst.instruction |= 0x01000000;
8241 if (inst.operands[i].writeback)
8242 inst.instruction |= 0x00200000;
8246 inst.instruction |= 0x00000c00;
8247 if (inst.operands[i].writeback)
8248 inst.instruction |= 0x00000100;
8250 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8252 else if (inst.operands[i].postind)
8254 assert (inst.operands[i].writeback);
8255 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
8256 constraint (is_t, _("cannot use post-indexing with this instruction"));
8259 inst.instruction |= 0x00200000;
8261 inst.instruction |= 0x00000900;
8262 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8264 else /* unindexed - only for coprocessor */
8265 inst.error = _("instruction does not accept unindexed addressing");
8268 /* Table of Thumb instructions which exist in both 16- and 32-bit
8269 encodings (the latter only in post-V6T2 cores). The index is the
8270 value used in the insns table below. When there is more than one
8271 possible 16-bit encoding for the instruction, this table always
8273 Also contains several pseudo-instructions used during relaxation. */
8274 #define T16_32_TAB \
8275 X(adc, 4140, eb400000), \
8276 X(adcs, 4140, eb500000), \
8277 X(add, 1c00, eb000000), \
8278 X(adds, 1c00, eb100000), \
8279 X(addi, 0000, f1000000), \
8280 X(addis, 0000, f1100000), \
8281 X(add_pc,000f, f20f0000), \
8282 X(add_sp,000d, f10d0000), \
8283 X(adr, 000f, f20f0000), \
8284 X(and, 4000, ea000000), \
8285 X(ands, 4000, ea100000), \
8286 X(asr, 1000, fa40f000), \
8287 X(asrs, 1000, fa50f000), \
8288 X(b, e000, f000b000), \
8289 X(bcond, d000, f0008000), \
8290 X(bic, 4380, ea200000), \
8291 X(bics, 4380, ea300000), \
8292 X(cmn, 42c0, eb100f00), \
8293 X(cmp, 2800, ebb00f00), \
8294 X(cpsie, b660, f3af8400), \
8295 X(cpsid, b670, f3af8600), \
8296 X(cpy, 4600, ea4f0000), \
8297 X(dec_sp,80dd, f1ad0d00), \
8298 X(eor, 4040, ea800000), \
8299 X(eors, 4040, ea900000), \
8300 X(inc_sp,00dd, f10d0d00), \
8301 X(ldmia, c800, e8900000), \
8302 X(ldr, 6800, f8500000), \
8303 X(ldrb, 7800, f8100000), \
8304 X(ldrh, 8800, f8300000), \
8305 X(ldrsb, 5600, f9100000), \
8306 X(ldrsh, 5e00, f9300000), \
8307 X(ldr_pc,4800, f85f0000), \
8308 X(ldr_pc2,4800, f85f0000), \
8309 X(ldr_sp,9800, f85d0000), \
8310 X(lsl, 0000, fa00f000), \
8311 X(lsls, 0000, fa10f000), \
8312 X(lsr, 0800, fa20f000), \
8313 X(lsrs, 0800, fa30f000), \
8314 X(mov, 2000, ea4f0000), \
8315 X(movs, 2000, ea5f0000), \
8316 X(mul, 4340, fb00f000), \
8317 X(muls, 4340, ffffffff), /* no 32b muls */ \
8318 X(mvn, 43c0, ea6f0000), \
8319 X(mvns, 43c0, ea7f0000), \
8320 X(neg, 4240, f1c00000), /* rsb #0 */ \
8321 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8322 X(orr, 4300, ea400000), \
8323 X(orrs, 4300, ea500000), \
8324 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8325 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8326 X(rev, ba00, fa90f080), \
8327 X(rev16, ba40, fa90f090), \
8328 X(revsh, bac0, fa90f0b0), \
8329 X(ror, 41c0, fa60f000), \
8330 X(rors, 41c0, fa70f000), \
8331 X(sbc, 4180, eb600000), \
8332 X(sbcs, 4180, eb700000), \
8333 X(stmia, c000, e8800000), \
8334 X(str, 6000, f8400000), \
8335 X(strb, 7000, f8000000), \
8336 X(strh, 8000, f8200000), \
8337 X(str_sp,9000, f84d0000), \
8338 X(sub, 1e00, eba00000), \
8339 X(subs, 1e00, ebb00000), \
8340 X(subi, 8000, f1a00000), \
8341 X(subis, 8000, f1b00000), \
8342 X(sxtb, b240, fa4ff080), \
8343 X(sxth, b200, fa0ff080), \
8344 X(tst, 4200, ea100f00), \
8345 X(uxtb, b2c0, fa5ff080), \
8346 X(uxth, b280, fa1ff080), \
8347 X(nop, bf00, f3af8000), \
8348 X(yield, bf10, f3af8001), \
8349 X(wfe, bf20, f3af8002), \
8350 X(wfi, bf30, f3af8003), \
8351 X(sev, bf40, f3af9004), /* typo, 8004? */
8353 /* To catch errors in encoding functions, the codes are all offset by
8354 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8355 as 16-bit instructions. */
8356 #define X(a,b,c) T_MNEM_##a
8357 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
8360 #define X(a,b,c) 0x##b
8361 static const unsigned short thumb_op16[] = { T16_32_TAB };
8362 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8365 #define X(a,b,c) 0x##c
8366 static const unsigned int thumb_op32[] = { T16_32_TAB };
8367 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8368 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8372 /* Thumb instruction encoders, in alphabetical order. */
8376 do_t_add_sub_w (void)
8380 Rd = inst.operands[0].reg;
8381 Rn = inst.operands[1].reg;
8383 constraint (Rd == 15, _("PC not allowed as destination"));
8384 inst.instruction |= (Rn << 16) | (Rd << 8);
8385 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8388 /* Parse an add or subtract instruction. We get here with inst.instruction
8389 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8396 Rd = inst.operands[0].reg;
8397 Rs = (inst.operands[1].present
8398 ? inst.operands[1].reg /* Rd, Rs, foo */
8399 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8407 flags = (inst.instruction == T_MNEM_adds
8408 || inst.instruction == T_MNEM_subs);
8410 narrow = (current_it_mask == 0);
8412 narrow = (current_it_mask != 0);
8413 if (!inst.operands[2].isreg)
8417 add = (inst.instruction == T_MNEM_add
8418 || inst.instruction == T_MNEM_adds);
8420 if (inst.size_req != 4)
8422 /* Attempt to use a narrow opcode, with relaxation if
8424 if (Rd == REG_SP && Rs == REG_SP && !flags)
8425 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
8426 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
8427 opcode = T_MNEM_add_sp;
8428 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
8429 opcode = T_MNEM_add_pc;
8430 else if (Rd <= 7 && Rs <= 7 && narrow)
8433 opcode = add ? T_MNEM_addis : T_MNEM_subis;
8435 opcode = add ? T_MNEM_addi : T_MNEM_subi;
8439 inst.instruction = THUMB_OP16(opcode);
8440 inst.instruction |= (Rd << 4) | Rs;
8441 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8442 if (inst.size_req != 2)
8443 inst.relax = opcode;
8446 constraint (inst.size_req == 2, BAD_HIREG);
8448 if (inst.size_req == 4
8449 || (inst.size_req != 2 && !opcode))
8453 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
8454 _("only SUBS PC, LR, #const allowed"));
8455 constraint (inst.reloc.exp.X_op != O_constant,
8456 _("expression too complex"));
8457 constraint (inst.reloc.exp.X_add_number < 0
8458 || inst.reloc.exp.X_add_number > 0xff,
8459 _("immediate value out of range"));
8460 inst.instruction = T2_SUBS_PC_LR
8461 | inst.reloc.exp.X_add_number;
8462 inst.reloc.type = BFD_RELOC_UNUSED;
8465 else if (Rs == REG_PC)
8467 /* Always use addw/subw. */
8468 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
8469 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8473 inst.instruction = THUMB_OP32 (inst.instruction);
8474 inst.instruction = (inst.instruction & 0xe1ffffff)
8477 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8479 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
8481 inst.instruction |= Rd << 8;
8482 inst.instruction |= Rs << 16;
8487 Rn = inst.operands[2].reg;
8488 /* See if we can do this with a 16-bit instruction. */
8489 if (!inst.operands[2].shifted && inst.size_req != 4)
8491 if (Rd > 7 || Rs > 7 || Rn > 7)
8496 inst.instruction = ((inst.instruction == T_MNEM_adds
8497 || inst.instruction == T_MNEM_add)
8500 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8504 if (inst.instruction == T_MNEM_add)
8508 inst.instruction = T_OPCODE_ADD_HI;
8509 inst.instruction |= (Rd & 8) << 4;
8510 inst.instruction |= (Rd & 7);
8511 inst.instruction |= Rn << 3;
8514 /* ... because addition is commutative! */
8517 inst.instruction = T_OPCODE_ADD_HI;
8518 inst.instruction |= (Rd & 8) << 4;
8519 inst.instruction |= (Rd & 7);
8520 inst.instruction |= Rs << 3;
8525 /* If we get here, it can't be done in 16 bits. */
8526 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
8527 _("shift must be constant"));
8528 inst.instruction = THUMB_OP32 (inst.instruction);
8529 inst.instruction |= Rd << 8;
8530 inst.instruction |= Rs << 16;
8531 encode_thumb32_shifted_operand (2);
8536 constraint (inst.instruction == T_MNEM_adds
8537 || inst.instruction == T_MNEM_subs,
8540 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
8542 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
8543 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
8546 inst.instruction = (inst.instruction == T_MNEM_add
8548 inst.instruction |= (Rd << 4) | Rs;
8549 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8553 Rn = inst.operands[2].reg;
8554 constraint (inst.operands[2].shifted, _("unshifted register required"));
8556 /* We now have Rd, Rs, and Rn set to registers. */
8557 if (Rd > 7 || Rs > 7 || Rn > 7)
8559 /* Can't do this for SUB. */
8560 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
8561 inst.instruction = T_OPCODE_ADD_HI;
8562 inst.instruction |= (Rd & 8) << 4;
8563 inst.instruction |= (Rd & 7);
8565 inst.instruction |= Rn << 3;
8567 inst.instruction |= Rs << 3;
8569 constraint (1, _("dest must overlap one source register"));
8573 inst.instruction = (inst.instruction == T_MNEM_add
8574 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
8575 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8583 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
8585 /* Defer to section relaxation. */
8586 inst.relax = inst.instruction;
8587 inst.instruction = THUMB_OP16 (inst.instruction);
8588 inst.instruction |= inst.operands[0].reg << 4;
8590 else if (unified_syntax && inst.size_req != 2)
8592 /* Generate a 32-bit opcode. */
8593 inst.instruction = THUMB_OP32 (inst.instruction);
8594 inst.instruction |= inst.operands[0].reg << 8;
8595 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
8596 inst.reloc.pc_rel = 1;
8600 /* Generate a 16-bit opcode. */
8601 inst.instruction = THUMB_OP16 (inst.instruction);
8602 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8603 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
8604 inst.reloc.pc_rel = 1;
8606 inst.instruction |= inst.operands[0].reg << 4;
8610 /* Arithmetic instructions for which there is just one 16-bit
8611 instruction encoding, and it allows only two low registers.
8612 For maximal compatibility with ARM syntax, we allow three register
8613 operands even when Thumb-32 instructions are not available, as long
8614 as the first two are identical. For instance, both "sbc r0,r1" and
8615 "sbc r0,r0,r1" are allowed. */
8621 Rd = inst.operands[0].reg;
8622 Rs = (inst.operands[1].present
8623 ? inst.operands[1].reg /* Rd, Rs, foo */
8624 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8625 Rn = inst.operands[2].reg;
8629 if (!inst.operands[2].isreg)
8631 /* For an immediate, we always generate a 32-bit opcode;
8632 section relaxation will shrink it later if possible. */
8633 inst.instruction = THUMB_OP32 (inst.instruction);
8634 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8635 inst.instruction |= Rd << 8;
8636 inst.instruction |= Rs << 16;
8637 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8643 /* See if we can do this with a 16-bit instruction. */
8644 if (THUMB_SETS_FLAGS (inst.instruction))
8645 narrow = current_it_mask == 0;
8647 narrow = current_it_mask != 0;
8649 if (Rd > 7 || Rn > 7 || Rs > 7)
8651 if (inst.operands[2].shifted)
8653 if (inst.size_req == 4)
8659 inst.instruction = THUMB_OP16 (inst.instruction);
8660 inst.instruction |= Rd;
8661 inst.instruction |= Rn << 3;
8665 /* If we get here, it can't be done in 16 bits. */
8666 constraint (inst.operands[2].shifted
8667 && inst.operands[2].immisreg,
8668 _("shift must be constant"));
8669 inst.instruction = THUMB_OP32 (inst.instruction);
8670 inst.instruction |= Rd << 8;
8671 inst.instruction |= Rs << 16;
8672 encode_thumb32_shifted_operand (2);
8677 /* On its face this is a lie - the instruction does set the
8678 flags. However, the only supported mnemonic in this mode
8680 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8682 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8683 _("unshifted register required"));
8684 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8685 constraint (Rd != Rs,
8686 _("dest and source1 must be the same register"));
8688 inst.instruction = THUMB_OP16 (inst.instruction);
8689 inst.instruction |= Rd;
8690 inst.instruction |= Rn << 3;
8694 /* Similarly, but for instructions where the arithmetic operation is
8695 commutative, so we can allow either of them to be different from
8696 the destination operand in a 16-bit instruction. For instance, all
8697 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8704 Rd = inst.operands[0].reg;
8705 Rs = (inst.operands[1].present
8706 ? inst.operands[1].reg /* Rd, Rs, foo */
8707 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8708 Rn = inst.operands[2].reg;
8712 if (!inst.operands[2].isreg)
8714 /* For an immediate, we always generate a 32-bit opcode;
8715 section relaxation will shrink it later if possible. */
8716 inst.instruction = THUMB_OP32 (inst.instruction);
8717 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8718 inst.instruction |= Rd << 8;
8719 inst.instruction |= Rs << 16;
8720 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8726 /* See if we can do this with a 16-bit instruction. */
8727 if (THUMB_SETS_FLAGS (inst.instruction))
8728 narrow = current_it_mask == 0;
8730 narrow = current_it_mask != 0;
8732 if (Rd > 7 || Rn > 7 || Rs > 7)
8734 if (inst.operands[2].shifted)
8736 if (inst.size_req == 4)
8743 inst.instruction = THUMB_OP16 (inst.instruction);
8744 inst.instruction |= Rd;
8745 inst.instruction |= Rn << 3;
8750 inst.instruction = THUMB_OP16 (inst.instruction);
8751 inst.instruction |= Rd;
8752 inst.instruction |= Rs << 3;
8757 /* If we get here, it can't be done in 16 bits. */
8758 constraint (inst.operands[2].shifted
8759 && inst.operands[2].immisreg,
8760 _("shift must be constant"));
8761 inst.instruction = THUMB_OP32 (inst.instruction);
8762 inst.instruction |= Rd << 8;
8763 inst.instruction |= Rs << 16;
8764 encode_thumb32_shifted_operand (2);
8769 /* On its face this is a lie - the instruction does set the
8770 flags. However, the only supported mnemonic in this mode
8772 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8774 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8775 _("unshifted register required"));
8776 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8778 inst.instruction = THUMB_OP16 (inst.instruction);
8779 inst.instruction |= Rd;
8782 inst.instruction |= Rn << 3;
8784 inst.instruction |= Rs << 3;
8786 constraint (1, _("dest must overlap one source register"));
8793 if (inst.operands[0].present)
8795 constraint ((inst.instruction & 0xf0) != 0x40
8796 && inst.operands[0].imm != 0xf,
8797 "bad barrier type");
8798 inst.instruction |= inst.operands[0].imm;
8801 inst.instruction |= 0xf;
8807 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8808 constraint (msb > 32, _("bit-field extends past end of register"));
8809 /* The instruction encoding stores the LSB and MSB,
8810 not the LSB and width. */
8811 inst.instruction |= inst.operands[0].reg << 8;
8812 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
8813 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
8814 inst.instruction |= msb - 1;
8822 /* #0 in second position is alternative syntax for bfc, which is
8823 the same instruction but with REG_PC in the Rm field. */
8824 if (!inst.operands[1].isreg)
8825 inst.operands[1].reg = REG_PC;
8827 msb = inst.operands[2].imm + inst.operands[3].imm;
8828 constraint (msb > 32, _("bit-field extends past end of register"));
8829 /* The instruction encoding stores the LSB and MSB,
8830 not the LSB and width. */
8831 inst.instruction |= inst.operands[0].reg << 8;
8832 inst.instruction |= inst.operands[1].reg << 16;
8833 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8834 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8835 inst.instruction |= msb - 1;
8841 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8842 _("bit-field extends past end of register"));
8843 inst.instruction |= inst.operands[0].reg << 8;
8844 inst.instruction |= inst.operands[1].reg << 16;
8845 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8846 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8847 inst.instruction |= inst.operands[3].imm - 1;
8850 /* ARM V5 Thumb BLX (argument parse)
8851 BLX <target_addr> which is BLX(1)
8852 BLX <Rm> which is BLX(2)
8853 Unfortunately, there are two different opcodes for this mnemonic.
8854 So, the insns[].value is not used, and the code here zaps values
8855 into inst.instruction.
8857 ??? How to take advantage of the additional two bits of displacement
8858 available in Thumb32 mode? Need new relocation? */
8863 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8864 if (inst.operands[0].isreg)
8865 /* We have a register, so this is BLX(2). */
8866 inst.instruction |= inst.operands[0].reg << 3;
8869 /* No register. This must be BLX(1). */
8870 inst.instruction = 0xf000e800;
8872 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8873 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8876 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
8877 inst.reloc.pc_rel = 1;
8887 if (current_it_mask)
8889 /* Conditional branches inside IT blocks are encoded as unconditional
8892 /* A branch must be the last instruction in an IT block. */
8893 constraint (current_it_mask != 0x10, BAD_BRANCH);
8898 if (cond != COND_ALWAYS)
8899 opcode = T_MNEM_bcond;
8901 opcode = inst.instruction;
8903 if (unified_syntax && inst.size_req == 4)
8905 inst.instruction = THUMB_OP32(opcode);
8906 if (cond == COND_ALWAYS)
8907 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
8910 assert (cond != 0xF);
8911 inst.instruction |= cond << 22;
8912 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
8917 inst.instruction = THUMB_OP16(opcode);
8918 if (cond == COND_ALWAYS)
8919 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
8922 inst.instruction |= cond << 8;
8923 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
8925 /* Allow section relaxation. */
8926 if (unified_syntax && inst.size_req != 2)
8927 inst.relax = opcode;
8930 inst.reloc.pc_rel = 1;
8936 constraint (inst.cond != COND_ALWAYS,
8937 _("instruction is always unconditional"));
8938 if (inst.operands[0].present)
8940 constraint (inst.operands[0].imm > 255,
8941 _("immediate value out of range"));
8942 inst.instruction |= inst.operands[0].imm;
8947 do_t_branch23 (void)
8949 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8950 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8951 inst.reloc.pc_rel = 1;
8953 /* If the destination of the branch is a defined symbol which does not have
8954 the THUMB_FUNC attribute, then we must be calling a function which has
8955 the (interfacearm) attribute. We look for the Thumb entry point to that
8956 function and change the branch to refer to that function instead. */
8957 if ( inst.reloc.exp.X_op == O_symbol
8958 && inst.reloc.exp.X_add_symbol != NULL
8959 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8960 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8961 inst.reloc.exp.X_add_symbol =
8962 find_real_start (inst.reloc.exp.X_add_symbol);
8968 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8969 inst.instruction |= inst.operands[0].reg << 3;
8970 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8971 should cause the alignment to be checked once it is known. This is
8972 because BX PC only works if the instruction is word aligned. */
8978 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8979 if (inst.operands[0].reg == REG_PC)
8980 as_tsktsk (_("use of r15 in bxj is not really useful"));
8982 inst.instruction |= inst.operands[0].reg << 16;
8988 inst.instruction |= inst.operands[0].reg << 8;
8989 inst.instruction |= inst.operands[1].reg << 16;
8990 inst.instruction |= inst.operands[1].reg;
8996 constraint (current_it_mask, BAD_NOT_IT);
8997 inst.instruction |= inst.operands[0].imm;
9003 constraint (current_it_mask, BAD_NOT_IT);
9005 && (inst.operands[1].present || inst.size_req == 4)
9006 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
9008 unsigned int imod = (inst.instruction & 0x0030) >> 4;
9009 inst.instruction = 0xf3af8000;
9010 inst.instruction |= imod << 9;
9011 inst.instruction |= inst.operands[0].imm << 5;
9012 if (inst.operands[1].present)
9013 inst.instruction |= 0x100 | inst.operands[1].imm;
9017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
9018 && (inst.operands[0].imm & 4),
9019 _("selected processor does not support 'A' form "
9020 "of this instruction"));
9021 constraint (inst.operands[1].present || inst.size_req == 4,
9022 _("Thumb does not support the 2-argument "
9023 "form of this instruction"));
9024 inst.instruction |= inst.operands[0].imm;
9028 /* THUMB CPY instruction (argument parse). */
9033 if (inst.size_req == 4)
9035 inst.instruction = THUMB_OP32 (T_MNEM_mov);
9036 inst.instruction |= inst.operands[0].reg << 8;
9037 inst.instruction |= inst.operands[1].reg;
9041 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9042 inst.instruction |= (inst.operands[0].reg & 0x7);
9043 inst.instruction |= inst.operands[1].reg << 3;
9050 constraint (current_it_mask, BAD_NOT_IT);
9051 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9052 inst.instruction |= inst.operands[0].reg;
9053 inst.reloc.pc_rel = 1;
9054 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
9060 inst.instruction |= inst.operands[0].imm;
9066 if (!inst.operands[1].present)
9067 inst.operands[1].reg = inst.operands[0].reg;
9068 inst.instruction |= inst.operands[0].reg << 8;
9069 inst.instruction |= inst.operands[1].reg << 16;
9070 inst.instruction |= inst.operands[2].reg;
9076 if (unified_syntax && inst.size_req == 4)
9077 inst.instruction = THUMB_OP32 (inst.instruction);
9079 inst.instruction = THUMB_OP16 (inst.instruction);
9085 unsigned int cond = inst.operands[0].imm;
9087 constraint (current_it_mask, BAD_NOT_IT);
9088 current_it_mask = (inst.instruction & 0xf) | 0x10;
9091 /* If the condition is a negative condition, invert the mask. */
9092 if ((cond & 0x1) == 0x0)
9094 unsigned int mask = inst.instruction & 0x000f;
9096 if ((mask & 0x7) == 0)
9097 /* no conversion needed */;
9098 else if ((mask & 0x3) == 0)
9100 else if ((mask & 0x1) == 0)
9105 inst.instruction &= 0xfff0;
9106 inst.instruction |= mask;
9109 inst.instruction |= cond << 4;
9112 /* Helper function used for both push/pop and ldm/stm. */
9114 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
9118 load = (inst.instruction & (1 << 20)) != 0;
9120 if (mask & (1 << 13))
9121 inst.error = _("SP not allowed in register list");
9124 if (mask & (1 << 14)
9125 && mask & (1 << 15))
9126 inst.error = _("LR and PC should not both be in register list");
9128 if ((mask & (1 << base)) != 0
9130 as_warn (_("base register should not be in register list "
9131 "when written back"));
9135 if (mask & (1 << 15))
9136 inst.error = _("PC not allowed in register list");
9138 if (mask & (1 << base))
9139 as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
9142 if ((mask & (mask - 1)) == 0)
9144 /* Single register transfers implemented as str/ldr. */
9147 if (inst.instruction & (1 << 23))
9148 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
9150 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
9154 if (inst.instruction & (1 << 23))
9155 inst.instruction = 0x00800000; /* ia -> [base] */
9157 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
9160 inst.instruction |= 0xf8400000;
9162 inst.instruction |= 0x00100000;
9164 mask = ffs(mask) - 1;
9168 inst.instruction |= WRITE_BACK;
9170 inst.instruction |= mask;
9171 inst.instruction |= base << 16;
9177 /* This really doesn't seem worth it. */
9178 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9179 _("expression too complex"));
9180 constraint (inst.operands[1].writeback,
9181 _("Thumb load/store multiple does not support {reglist}^"));
9189 /* See if we can use a 16-bit instruction. */
9190 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
9191 && inst.size_req != 4
9192 && !(inst.operands[1].imm & ~0xff))
9194 mask = 1 << inst.operands[0].reg;
9196 if (inst.operands[0].reg <= 7
9197 && (inst.instruction == T_MNEM_stmia
9198 ? inst.operands[0].writeback
9199 : (inst.operands[0].writeback
9200 == !(inst.operands[1].imm & mask))))
9202 if (inst.instruction == T_MNEM_stmia
9203 && (inst.operands[1].imm & mask)
9204 && (inst.operands[1].imm & (mask - 1)))
9205 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9206 inst.operands[0].reg);
9208 inst.instruction = THUMB_OP16 (inst.instruction);
9209 inst.instruction |= inst.operands[0].reg << 8;
9210 inst.instruction |= inst.operands[1].imm;
9213 else if (inst.operands[0] .reg == REG_SP
9214 && inst.operands[0].writeback)
9216 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
9217 ? T_MNEM_push : T_MNEM_pop);
9218 inst.instruction |= inst.operands[1].imm;
9225 if (inst.instruction < 0xffff)
9226 inst.instruction = THUMB_OP32 (inst.instruction);
9228 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
9229 inst.operands[0].writeback);
9234 constraint (inst.operands[0].reg > 7
9235 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
9236 constraint (inst.instruction != T_MNEM_ldmia
9237 && inst.instruction != T_MNEM_stmia,
9238 _("Thumb-2 instruction only valid in unified syntax"));
9239 if (inst.instruction == T_MNEM_stmia)
9241 if (!inst.operands[0].writeback)
9242 as_warn (_("this instruction will write back the base register"));
9243 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9244 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9245 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9246 inst.operands[0].reg);
9250 if (!inst.operands[0].writeback
9251 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9252 as_warn (_("this instruction will write back the base register"));
9253 else if (inst.operands[0].writeback
9254 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9255 as_warn (_("this instruction will not write back the base register"));
9258 inst.instruction = THUMB_OP16 (inst.instruction);
9259 inst.instruction |= inst.operands[0].reg << 8;
9260 inst.instruction |= inst.operands[1].imm;
9267 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9268 || inst.operands[1].postind || inst.operands[1].writeback
9269 || inst.operands[1].immisreg || inst.operands[1].shifted
9270 || inst.operands[1].negative,
9273 inst.instruction |= inst.operands[0].reg << 12;
9274 inst.instruction |= inst.operands[1].reg << 16;
9275 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
9281 if (!inst.operands[1].present)
9283 constraint (inst.operands[0].reg == REG_LR,
9284 _("r14 not allowed as first register "
9285 "when second register is omitted"));
9286 inst.operands[1].reg = inst.operands[0].reg + 1;
9288 constraint (inst.operands[0].reg == inst.operands[1].reg,
9291 inst.instruction |= inst.operands[0].reg << 12;
9292 inst.instruction |= inst.operands[1].reg << 8;
9293 inst.instruction |= inst.operands[2].reg << 16;
9299 unsigned long opcode;
9302 opcode = inst.instruction;
9305 if (!inst.operands[1].isreg)
9307 if (opcode <= 0xffff)
9308 inst.instruction = THUMB_OP32 (opcode);
9309 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9312 if (inst.operands[1].isreg
9313 && !inst.operands[1].writeback
9314 && !inst.operands[1].shifted && !inst.operands[1].postind
9315 && !inst.operands[1].negative && inst.operands[0].reg <= 7
9317 && inst.size_req != 4)
9319 /* Insn may have a 16-bit form. */
9320 Rn = inst.operands[1].reg;
9321 if (inst.operands[1].immisreg)
9323 inst.instruction = THUMB_OP16 (opcode);
9325 if (Rn <= 7 && inst.operands[1].imm <= 7)
9328 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
9329 && opcode != T_MNEM_ldrsb)
9330 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
9331 || (Rn == REG_SP && opcode == T_MNEM_str))
9338 if (inst.reloc.pc_rel)
9339 opcode = T_MNEM_ldr_pc2;
9341 opcode = T_MNEM_ldr_pc;
9345 if (opcode == T_MNEM_ldr)
9346 opcode = T_MNEM_ldr_sp;
9348 opcode = T_MNEM_str_sp;
9350 inst.instruction = inst.operands[0].reg << 8;
9354 inst.instruction = inst.operands[0].reg;
9355 inst.instruction |= inst.operands[1].reg << 3;
9357 inst.instruction |= THUMB_OP16 (opcode);
9358 if (inst.size_req == 2)
9359 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9361 inst.relax = opcode;
9365 /* Definitely a 32-bit variant. */
9366 inst.instruction = THUMB_OP32 (opcode);
9367 inst.instruction |= inst.operands[0].reg << 12;
9368 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
9372 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9374 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
9376 /* Only [Rn,Rm] is acceptable. */
9377 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9378 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
9379 || inst.operands[1].postind || inst.operands[1].shifted
9380 || inst.operands[1].negative,
9381 _("Thumb does not support this addressing mode"));
9382 inst.instruction = THUMB_OP16 (inst.instruction);
9386 inst.instruction = THUMB_OP16 (inst.instruction);
9387 if (!inst.operands[1].isreg)
9388 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9391 constraint (!inst.operands[1].preind
9392 || inst.operands[1].shifted
9393 || inst.operands[1].writeback,
9394 _("Thumb does not support this addressing mode"));
9395 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
9397 constraint (inst.instruction & 0x0600,
9398 _("byte or halfword not valid for base register"));
9399 constraint (inst.operands[1].reg == REG_PC
9400 && !(inst.instruction & THUMB_LOAD_BIT),
9401 _("r15 based store not allowed"));
9402 constraint (inst.operands[1].immisreg,
9403 _("invalid base register for register offset"));
9405 if (inst.operands[1].reg == REG_PC)
9406 inst.instruction = T_OPCODE_LDR_PC;
9407 else if (inst.instruction & THUMB_LOAD_BIT)
9408 inst.instruction = T_OPCODE_LDR_SP;
9410 inst.instruction = T_OPCODE_STR_SP;
9412 inst.instruction |= inst.operands[0].reg << 8;
9413 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9417 constraint (inst.operands[1].reg > 7, BAD_HIREG);
9418 if (!inst.operands[1].immisreg)
9420 /* Immediate offset. */
9421 inst.instruction |= inst.operands[0].reg;
9422 inst.instruction |= inst.operands[1].reg << 3;
9423 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9427 /* Register offset. */
9428 constraint (inst.operands[1].imm > 7, BAD_HIREG);
9429 constraint (inst.operands[1].negative,
9430 _("Thumb does not support this addressing mode"));
9433 switch (inst.instruction)
9435 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
9436 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
9437 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
9438 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
9439 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
9440 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
9441 case 0x5600 /* ldrsb */:
9442 case 0x5e00 /* ldrsh */: break;
9446 inst.instruction |= inst.operands[0].reg;
9447 inst.instruction |= inst.operands[1].reg << 3;
9448 inst.instruction |= inst.operands[1].imm << 6;
9454 if (!inst.operands[1].present)
9456 inst.operands[1].reg = inst.operands[0].reg + 1;
9457 constraint (inst.operands[0].reg == REG_LR,
9458 _("r14 not allowed here"));
9460 inst.instruction |= inst.operands[0].reg << 12;
9461 inst.instruction |= inst.operands[1].reg << 8;
9462 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
9469 inst.instruction |= inst.operands[0].reg << 12;
9470 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
9476 inst.instruction |= inst.operands[0].reg << 8;
9477 inst.instruction |= inst.operands[1].reg << 16;
9478 inst.instruction |= inst.operands[2].reg;
9479 inst.instruction |= inst.operands[3].reg << 12;
9485 inst.instruction |= inst.operands[0].reg << 12;
9486 inst.instruction |= inst.operands[1].reg << 8;
9487 inst.instruction |= inst.operands[2].reg << 16;
9488 inst.instruction |= inst.operands[3].reg;
9496 int r0off = (inst.instruction == T_MNEM_mov
9497 || inst.instruction == T_MNEM_movs) ? 8 : 16;
9498 unsigned long opcode;
9500 bfd_boolean low_regs;
9502 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
9503 opcode = inst.instruction;
9504 if (current_it_mask)
9505 narrow = opcode != T_MNEM_movs;
9507 narrow = opcode != T_MNEM_movs || low_regs;
9508 if (inst.size_req == 4
9509 || inst.operands[1].shifted)
9512 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9513 if (opcode == T_MNEM_movs && inst.operands[1].isreg
9514 && !inst.operands[1].shifted
9515 && inst.operands[0].reg == REG_PC
9516 && inst.operands[1].reg == REG_LR)
9518 inst.instruction = T2_SUBS_PC_LR;
9522 if (!inst.operands[1].isreg)
9524 /* Immediate operand. */
9525 if (current_it_mask == 0 && opcode == T_MNEM_mov)
9527 if (low_regs && narrow)
9529 inst.instruction = THUMB_OP16 (opcode);
9530 inst.instruction |= inst.operands[0].reg << 8;
9531 if (inst.size_req == 2)
9532 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9534 inst.relax = opcode;
9538 inst.instruction = THUMB_OP32 (inst.instruction);
9539 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9540 inst.instruction |= inst.operands[0].reg << r0off;
9541 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9544 else if (inst.operands[1].shifted && inst.operands[1].immisreg
9545 && (inst.instruction == T_MNEM_mov
9546 || inst.instruction == T_MNEM_movs))
9548 /* Register shifts are encoded as separate shift instructions. */
9549 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
9551 if (current_it_mask)
9556 if (inst.size_req == 4)
9559 if (!low_regs || inst.operands[1].imm > 7)
9562 if (inst.operands[0].reg != inst.operands[1].reg)
9565 switch (inst.operands[1].shift_kind)
9568 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
9571 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
9574 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
9577 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
9583 inst.instruction = opcode;
9586 inst.instruction |= inst.operands[0].reg;
9587 inst.instruction |= inst.operands[1].imm << 3;
9592 inst.instruction |= CONDS_BIT;
9594 inst.instruction |= inst.operands[0].reg << 8;
9595 inst.instruction |= inst.operands[1].reg << 16;
9596 inst.instruction |= inst.operands[1].imm;
9601 /* Some mov with immediate shift have narrow variants.
9602 Register shifts are handled above. */
9603 if (low_regs && inst.operands[1].shifted
9604 && (inst.instruction == T_MNEM_mov
9605 || inst.instruction == T_MNEM_movs))
9607 if (current_it_mask)
9608 narrow = (inst.instruction == T_MNEM_mov);
9610 narrow = (inst.instruction == T_MNEM_movs);
9615 switch (inst.operands[1].shift_kind)
9617 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
9618 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
9619 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
9620 default: narrow = FALSE; break;
9626 inst.instruction |= inst.operands[0].reg;
9627 inst.instruction |= inst.operands[1].reg << 3;
9628 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
9632 inst.instruction = THUMB_OP32 (inst.instruction);
9633 inst.instruction |= inst.operands[0].reg << r0off;
9634 encode_thumb32_shifted_operand (1);
9638 switch (inst.instruction)
9641 inst.instruction = T_OPCODE_MOV_HR;
9642 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9643 inst.instruction |= (inst.operands[0].reg & 0x7);
9644 inst.instruction |= inst.operands[1].reg << 3;
9648 /* We know we have low registers at this point.
9649 Generate ADD Rd, Rs, #0. */
9650 inst.instruction = T_OPCODE_ADD_I3;
9651 inst.instruction |= inst.operands[0].reg;
9652 inst.instruction |= inst.operands[1].reg << 3;
9658 inst.instruction = T_OPCODE_CMP_LR;
9659 inst.instruction |= inst.operands[0].reg;
9660 inst.instruction |= inst.operands[1].reg << 3;
9664 inst.instruction = T_OPCODE_CMP_HR;
9665 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9666 inst.instruction |= (inst.operands[0].reg & 0x7);
9667 inst.instruction |= inst.operands[1].reg << 3;
9674 inst.instruction = THUMB_OP16 (inst.instruction);
9675 if (inst.operands[1].isreg)
9677 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
9679 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9680 since a MOV instruction produces unpredictable results. */
9681 if (inst.instruction == T_OPCODE_MOV_I8)
9682 inst.instruction = T_OPCODE_ADD_I3;
9684 inst.instruction = T_OPCODE_CMP_LR;
9686 inst.instruction |= inst.operands[0].reg;
9687 inst.instruction |= inst.operands[1].reg << 3;
9691 if (inst.instruction == T_OPCODE_MOV_I8)
9692 inst.instruction = T_OPCODE_MOV_HR;
9694 inst.instruction = T_OPCODE_CMP_HR;
9700 constraint (inst.operands[0].reg > 7,
9701 _("only lo regs allowed with immediate"));
9702 inst.instruction |= inst.operands[0].reg << 8;
9703 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9713 top = (inst.instruction & 0x00800000) != 0;
9714 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
9716 constraint (top, _(":lower16: not allowed this instruction"));
9717 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
9719 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
9721 constraint (!top, _(":upper16: not allowed this instruction"));
9722 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
9725 inst.instruction |= inst.operands[0].reg << 8;
9726 if (inst.reloc.type == BFD_RELOC_UNUSED)
9728 imm = inst.reloc.exp.X_add_number;
9729 inst.instruction |= (imm & 0xf000) << 4;
9730 inst.instruction |= (imm & 0x0800) << 15;
9731 inst.instruction |= (imm & 0x0700) << 4;
9732 inst.instruction |= (imm & 0x00ff);
9741 int r0off = (inst.instruction == T_MNEM_mvn
9742 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
9745 if (inst.size_req == 4
9746 || inst.instruction > 0xffff
9747 || inst.operands[1].shifted
9748 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9750 else if (inst.instruction == T_MNEM_cmn)
9752 else if (THUMB_SETS_FLAGS (inst.instruction))
9753 narrow = (current_it_mask == 0);
9755 narrow = (current_it_mask != 0);
9757 if (!inst.operands[1].isreg)
9759 /* For an immediate, we always generate a 32-bit opcode;
9760 section relaxation will shrink it later if possible. */
9761 if (inst.instruction < 0xffff)
9762 inst.instruction = THUMB_OP32 (inst.instruction);
9763 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9764 inst.instruction |= inst.operands[0].reg << r0off;
9765 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9769 /* See if we can do this with a 16-bit instruction. */
9772 inst.instruction = THUMB_OP16 (inst.instruction);
9773 inst.instruction |= inst.operands[0].reg;
9774 inst.instruction |= inst.operands[1].reg << 3;
9778 constraint (inst.operands[1].shifted
9779 && inst.operands[1].immisreg,
9780 _("shift must be constant"));
9781 if (inst.instruction < 0xffff)
9782 inst.instruction = THUMB_OP32 (inst.instruction);
9783 inst.instruction |= inst.operands[0].reg << r0off;
9784 encode_thumb32_shifted_operand (1);
9790 constraint (inst.instruction > 0xffff
9791 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
9792 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
9793 _("unshifted register required"));
9794 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9797 inst.instruction = THUMB_OP16 (inst.instruction);
9798 inst.instruction |= inst.operands[0].reg;
9799 inst.instruction |= inst.operands[1].reg << 3;
9808 if (do_vfp_nsyn_mrs () == SUCCESS)
9811 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
9814 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9815 _("selected processor does not support "
9816 "requested special purpose register"));
9820 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9821 _("selected processor does not support "
9822 "requested special purpose register %x"));
9823 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9824 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
9825 _("'CPSR' or 'SPSR' expected"));
9828 inst.instruction |= inst.operands[0].reg << 8;
9829 inst.instruction |= (flags & SPSR_BIT) >> 2;
9830 inst.instruction |= inst.operands[1].imm & 0xff;
9838 if (do_vfp_nsyn_msr () == SUCCESS)
9841 constraint (!inst.operands[1].isreg,
9842 _("Thumb encoding does not support an immediate here"));
9843 flags = inst.operands[0].imm;
9846 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9847 _("selected processor does not support "
9848 "requested special purpose register"));
9852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9853 _("selected processor does not support "
9854 "requested special purpose register"));
9857 inst.instruction |= (flags & SPSR_BIT) >> 2;
9858 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
9859 inst.instruction |= (flags & 0xff);
9860 inst.instruction |= inst.operands[1].reg << 16;
9866 if (!inst.operands[2].present)
9867 inst.operands[2].reg = inst.operands[0].reg;
9869 /* There is no 32-bit MULS and no 16-bit MUL. */
9870 if (unified_syntax && inst.instruction == T_MNEM_mul)
9872 inst.instruction = THUMB_OP32 (inst.instruction);
9873 inst.instruction |= inst.operands[0].reg << 8;
9874 inst.instruction |= inst.operands[1].reg << 16;
9875 inst.instruction |= inst.operands[2].reg << 0;
9879 constraint (!unified_syntax
9880 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
9881 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9884 inst.instruction = THUMB_OP16 (inst.instruction);
9885 inst.instruction |= inst.operands[0].reg;
9887 if (inst.operands[0].reg == inst.operands[1].reg)
9888 inst.instruction |= inst.operands[2].reg << 3;
9889 else if (inst.operands[0].reg == inst.operands[2].reg)
9890 inst.instruction |= inst.operands[1].reg << 3;
9892 constraint (1, _("dest must overlap one source register"));
9899 inst.instruction |= inst.operands[0].reg << 12;
9900 inst.instruction |= inst.operands[1].reg << 8;
9901 inst.instruction |= inst.operands[2].reg << 16;
9902 inst.instruction |= inst.operands[3].reg;
9904 if (inst.operands[0].reg == inst.operands[1].reg)
9905 as_tsktsk (_("rdhi and rdlo must be different"));
9913 if (inst.size_req == 4 || inst.operands[0].imm > 15)
9915 inst.instruction = THUMB_OP32 (inst.instruction);
9916 inst.instruction |= inst.operands[0].imm;
9920 inst.instruction = THUMB_OP16 (inst.instruction);
9921 inst.instruction |= inst.operands[0].imm << 4;
9926 constraint (inst.operands[0].present,
9927 _("Thumb does not support NOP with hints"));
9928 inst.instruction = 0x46c0;
9939 if (THUMB_SETS_FLAGS (inst.instruction))
9940 narrow = (current_it_mask == 0);
9942 narrow = (current_it_mask != 0);
9943 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9945 if (inst.size_req == 4)
9950 inst.instruction = THUMB_OP32 (inst.instruction);
9951 inst.instruction |= inst.operands[0].reg << 8;
9952 inst.instruction |= inst.operands[1].reg << 16;
9956 inst.instruction = THUMB_OP16 (inst.instruction);
9957 inst.instruction |= inst.operands[0].reg;
9958 inst.instruction |= inst.operands[1].reg << 3;
9963 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9965 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9967 inst.instruction = THUMB_OP16 (inst.instruction);
9968 inst.instruction |= inst.operands[0].reg;
9969 inst.instruction |= inst.operands[1].reg << 3;
9976 inst.instruction |= inst.operands[0].reg << 8;
9977 inst.instruction |= inst.operands[1].reg << 16;
9978 inst.instruction |= inst.operands[2].reg;
9979 if (inst.operands[3].present)
9981 unsigned int val = inst.reloc.exp.X_add_number;
9982 constraint (inst.reloc.exp.X_op != O_constant,
9983 _("expression too complex"));
9984 inst.instruction |= (val & 0x1c) << 10;
9985 inst.instruction |= (val & 0x03) << 6;
9992 if (!inst.operands[3].present)
9993 inst.instruction &= ~0x00000020;
10000 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
10004 do_t_push_pop (void)
10008 constraint (inst.operands[0].writeback,
10009 _("push/pop do not support {reglist}^"));
10010 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10011 _("expression too complex"));
10013 mask = inst.operands[0].imm;
10014 if ((mask & ~0xff) == 0)
10015 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
10016 else if ((inst.instruction == T_MNEM_push
10017 && (mask & ~0xff) == 1 << REG_LR)
10018 || (inst.instruction == T_MNEM_pop
10019 && (mask & ~0xff) == 1 << REG_PC))
10021 inst.instruction = THUMB_OP16 (inst.instruction);
10022 inst.instruction |= THUMB_PP_PC_LR;
10023 inst.instruction |= mask & 0xff;
10025 else if (unified_syntax)
10027 inst.instruction = THUMB_OP32 (inst.instruction);
10028 encode_thumb2_ldmstm(13, mask, TRUE);
10032 inst.error = _("invalid register list to push/pop instruction");
10040 inst.instruction |= inst.operands[0].reg << 8;
10041 inst.instruction |= inst.operands[1].reg << 16;
10047 inst.instruction |= inst.operands[0].reg << 8;
10048 inst.instruction |= inst.operands[1].reg;
10054 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10055 && inst.size_req != 4)
10057 inst.instruction = THUMB_OP16 (inst.instruction);
10058 inst.instruction |= inst.operands[0].reg;
10059 inst.instruction |= inst.operands[1].reg << 3;
10061 else if (unified_syntax)
10063 inst.instruction = THUMB_OP32 (inst.instruction);
10064 inst.instruction |= inst.operands[0].reg << 8;
10065 inst.instruction |= inst.operands[1].reg << 16;
10066 inst.instruction |= inst.operands[1].reg;
10069 inst.error = BAD_HIREG;
10077 Rd = inst.operands[0].reg;
10078 Rs = (inst.operands[1].present
10079 ? inst.operands[1].reg /* Rd, Rs, foo */
10080 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10082 inst.instruction |= Rd << 8;
10083 inst.instruction |= Rs << 16;
10084 if (!inst.operands[2].isreg)
10086 bfd_boolean narrow;
10088 if ((inst.instruction & 0x00100000) != 0)
10089 narrow = (current_it_mask == 0);
10091 narrow = (current_it_mask != 0);
10093 if (Rd > 7 || Rs > 7)
10096 if (inst.size_req == 4 || !unified_syntax)
10099 if (inst.reloc.exp.X_op != O_constant
10100 || inst.reloc.exp.X_add_number != 0)
10103 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10104 relaxation, but it doesn't seem worth the hassle. */
10107 inst.reloc.type = BFD_RELOC_UNUSED;
10108 inst.instruction = THUMB_OP16 (T_MNEM_negs);
10109 inst.instruction |= Rs << 3;
10110 inst.instruction |= Rd;
10114 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10115 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10119 encode_thumb32_shifted_operand (2);
10125 constraint (current_it_mask, BAD_NOT_IT);
10126 if (inst.operands[0].imm)
10127 inst.instruction |= 0x8;
10133 if (!inst.operands[1].present)
10134 inst.operands[1].reg = inst.operands[0].reg;
10136 if (unified_syntax)
10138 bfd_boolean narrow;
10141 switch (inst.instruction)
10144 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
10146 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
10148 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
10150 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
10154 if (THUMB_SETS_FLAGS (inst.instruction))
10155 narrow = (current_it_mask == 0);
10157 narrow = (current_it_mask != 0);
10158 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10160 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
10162 if (inst.operands[2].isreg
10163 && (inst.operands[1].reg != inst.operands[0].reg
10164 || inst.operands[2].reg > 7))
10166 if (inst.size_req == 4)
10171 if (inst.operands[2].isreg)
10173 inst.instruction = THUMB_OP32 (inst.instruction);
10174 inst.instruction |= inst.operands[0].reg << 8;
10175 inst.instruction |= inst.operands[1].reg << 16;
10176 inst.instruction |= inst.operands[2].reg;
10180 inst.operands[1].shifted = 1;
10181 inst.operands[1].shift_kind = shift_kind;
10182 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
10183 ? T_MNEM_movs : T_MNEM_mov);
10184 inst.instruction |= inst.operands[0].reg << 8;
10185 encode_thumb32_shifted_operand (1);
10186 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10187 inst.reloc.type = BFD_RELOC_UNUSED;
10192 if (inst.operands[2].isreg)
10194 switch (shift_kind)
10196 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
10197 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
10198 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
10199 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
10203 inst.instruction |= inst.operands[0].reg;
10204 inst.instruction |= inst.operands[2].reg << 3;
10208 switch (shift_kind)
10210 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10211 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10212 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10215 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10216 inst.instruction |= inst.operands[0].reg;
10217 inst.instruction |= inst.operands[1].reg << 3;
10223 constraint (inst.operands[0].reg > 7
10224 || inst.operands[1].reg > 7, BAD_HIREG);
10225 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10227 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
10229 constraint (inst.operands[2].reg > 7, BAD_HIREG);
10230 constraint (inst.operands[0].reg != inst.operands[1].reg,
10231 _("source1 and dest must be same register"));
10233 switch (inst.instruction)
10235 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
10236 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
10237 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
10238 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
10242 inst.instruction |= inst.operands[0].reg;
10243 inst.instruction |= inst.operands[2].reg << 3;
10247 switch (inst.instruction)
10249 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
10250 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
10251 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
10252 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
10255 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10256 inst.instruction |= inst.operands[0].reg;
10257 inst.instruction |= inst.operands[1].reg << 3;
10265 inst.instruction |= inst.operands[0].reg << 8;
10266 inst.instruction |= inst.operands[1].reg << 16;
10267 inst.instruction |= inst.operands[2].reg;
10273 unsigned int value = inst.reloc.exp.X_add_number;
10274 constraint (inst.reloc.exp.X_op != O_constant,
10275 _("expression too complex"));
10276 inst.reloc.type = BFD_RELOC_UNUSED;
10277 inst.instruction |= (value & 0xf000) >> 12;
10278 inst.instruction |= (value & 0x0ff0);
10279 inst.instruction |= (value & 0x000f) << 16;
10285 inst.instruction |= inst.operands[0].reg << 8;
10286 inst.instruction |= inst.operands[1].imm - 1;
10287 inst.instruction |= inst.operands[2].reg << 16;
10289 if (inst.operands[3].present)
10291 constraint (inst.reloc.exp.X_op != O_constant,
10292 _("expression too complex"));
10294 if (inst.reloc.exp.X_add_number != 0)
10296 if (inst.operands[3].shift_kind == SHIFT_ASR)
10297 inst.instruction |= 0x00200000; /* sh bit */
10298 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10299 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10301 inst.reloc.type = BFD_RELOC_UNUSED;
10308 inst.instruction |= inst.operands[0].reg << 8;
10309 inst.instruction |= inst.operands[1].imm - 1;
10310 inst.instruction |= inst.operands[2].reg << 16;
10316 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10317 || inst.operands[2].postind || inst.operands[2].writeback
10318 || inst.operands[2].immisreg || inst.operands[2].shifted
10319 || inst.operands[2].negative,
10322 inst.instruction |= inst.operands[0].reg << 8;
10323 inst.instruction |= inst.operands[1].reg << 12;
10324 inst.instruction |= inst.operands[2].reg << 16;
10325 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10331 if (!inst.operands[2].present)
10332 inst.operands[2].reg = inst.operands[1].reg + 1;
10334 constraint (inst.operands[0].reg == inst.operands[1].reg
10335 || inst.operands[0].reg == inst.operands[2].reg
10336 || inst.operands[0].reg == inst.operands[3].reg
10337 || inst.operands[1].reg == inst.operands[2].reg,
10340 inst.instruction |= inst.operands[0].reg;
10341 inst.instruction |= inst.operands[1].reg << 12;
10342 inst.instruction |= inst.operands[2].reg << 8;
10343 inst.instruction |= inst.operands[3].reg << 16;
10349 inst.instruction |= inst.operands[0].reg << 8;
10350 inst.instruction |= inst.operands[1].reg << 16;
10351 inst.instruction |= inst.operands[2].reg;
10352 inst.instruction |= inst.operands[3].imm << 4;
10358 if (inst.instruction <= 0xffff && inst.size_req != 4
10359 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10360 && (!inst.operands[2].present || inst.operands[2].imm == 0))
10362 inst.instruction = THUMB_OP16 (inst.instruction);
10363 inst.instruction |= inst.operands[0].reg;
10364 inst.instruction |= inst.operands[1].reg << 3;
10366 else if (unified_syntax)
10368 if (inst.instruction <= 0xffff)
10369 inst.instruction = THUMB_OP32 (inst.instruction);
10370 inst.instruction |= inst.operands[0].reg << 8;
10371 inst.instruction |= inst.operands[1].reg;
10372 inst.instruction |= inst.operands[2].imm << 4;
10376 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
10377 _("Thumb encoding does not support rotation"));
10378 constraint (1, BAD_HIREG);
10385 inst.reloc.type = BFD_RELOC_ARM_SWI;
10393 half = (inst.instruction & 0x10) != 0;
10394 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
10395 constraint (inst.operands[0].immisreg,
10396 _("instruction requires register index"));
10397 constraint (inst.operands[0].imm == 15,
10398 _("PC is not a valid index register"));
10399 constraint (!half && inst.operands[0].shifted,
10400 _("instruction does not allow shifted index"));
10401 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10407 inst.instruction |= inst.operands[0].reg << 8;
10408 inst.instruction |= inst.operands[1].imm;
10409 inst.instruction |= inst.operands[2].reg << 16;
10411 if (inst.operands[3].present)
10413 constraint (inst.reloc.exp.X_op != O_constant,
10414 _("expression too complex"));
10415 if (inst.reloc.exp.X_add_number != 0)
10417 if (inst.operands[3].shift_kind == SHIFT_ASR)
10418 inst.instruction |= 0x00200000; /* sh bit */
10420 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10421 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10423 inst.reloc.type = BFD_RELOC_UNUSED;
10430 inst.instruction |= inst.operands[0].reg << 8;
10431 inst.instruction |= inst.operands[1].imm;
10432 inst.instruction |= inst.operands[2].reg << 16;
10435 /* Neon instruction encoder helpers. */
10437 /* Encodings for the different types for various Neon opcodes. */
10439 /* An "invalid" code for the following tables. */
10442 struct neon_tab_entry
10445 unsigned float_or_poly;
10446 unsigned scalar_or_imm;
10449 /* Map overloaded Neon opcodes to their respective encodings. */
10450 #define NEON_ENC_TAB \
10451 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10452 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10453 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10454 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10455 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10456 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10457 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10458 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10459 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10460 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10461 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10462 /* Register variants of the following two instructions are encoded as
10463 vcge / vcgt with the operands reversed. */ \
10464 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10465 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10466 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10467 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10468 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10469 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10470 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10471 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10472 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10473 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10474 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10475 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10476 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10477 X(vshl, 0x0000400, N_INV, 0x0800510), \
10478 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10479 X(vand, 0x0000110, N_INV, 0x0800030), \
10480 X(vbic, 0x0100110, N_INV, 0x0800030), \
10481 X(veor, 0x1000110, N_INV, N_INV), \
10482 X(vorn, 0x0300110, N_INV, 0x0800010), \
10483 X(vorr, 0x0200110, N_INV, 0x0800010), \
10484 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10485 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10486 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10487 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10488 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10489 X(vst1, 0x0000000, 0x0800000, N_INV), \
10490 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10491 X(vst2, 0x0000100, 0x0800100, N_INV), \
10492 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10493 X(vst3, 0x0000200, 0x0800200, N_INV), \
10494 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10495 X(vst4, 0x0000300, 0x0800300, N_INV), \
10496 X(vmovn, 0x1b20200, N_INV, N_INV), \
10497 X(vtrn, 0x1b20080, N_INV, N_INV), \
10498 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10499 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10500 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10501 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10502 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10503 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10504 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10505 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10506 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10510 #define X(OPC,I,F,S) N_MNEM_##OPC
10515 static const struct neon_tab_entry neon_enc_tab[] =
10517 #define X(OPC,I,F,S) { (I), (F), (S) }
10522 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10523 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10524 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10525 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10526 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10527 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10528 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10529 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10530 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10531 #define NEON_ENC_SINGLE(X) \
10532 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10533 #define NEON_ENC_DOUBLE(X) \
10534 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10536 /* Define shapes for instruction operands. The following mnemonic characters
10537 are used in this table:
10539 F - VFP S<n> register
10540 D - Neon D<n> register
10541 Q - Neon Q<n> register
10545 L - D<n> register list
10547 This table is used to generate various data:
10548 - enumerations of the form NS_DDR to be used as arguments to
10550 - a table classifying shapes into single, double, quad, mixed.
10551 - a table used to drive neon_select_shape.
10554 #define NEON_SHAPE_DEF \
10555 X(3, (D, D, D), DOUBLE), \
10556 X(3, (Q, Q, Q), QUAD), \
10557 X(3, (D, D, I), DOUBLE), \
10558 X(3, (Q, Q, I), QUAD), \
10559 X(3, (D, D, S), DOUBLE), \
10560 X(3, (Q, Q, S), QUAD), \
10561 X(2, (D, D), DOUBLE), \
10562 X(2, (Q, Q), QUAD), \
10563 X(2, (D, S), DOUBLE), \
10564 X(2, (Q, S), QUAD), \
10565 X(2, (D, R), DOUBLE), \
10566 X(2, (Q, R), QUAD), \
10567 X(2, (D, I), DOUBLE), \
10568 X(2, (Q, I), QUAD), \
10569 X(3, (D, L, D), DOUBLE), \
10570 X(2, (D, Q), MIXED), \
10571 X(2, (Q, D), MIXED), \
10572 X(3, (D, Q, I), MIXED), \
10573 X(3, (Q, D, I), MIXED), \
10574 X(3, (Q, D, D), MIXED), \
10575 X(3, (D, Q, Q), MIXED), \
10576 X(3, (Q, Q, D), MIXED), \
10577 X(3, (Q, D, S), MIXED), \
10578 X(3, (D, Q, S), MIXED), \
10579 X(4, (D, D, D, I), DOUBLE), \
10580 X(4, (Q, Q, Q, I), QUAD), \
10581 X(2, (F, F), SINGLE), \
10582 X(3, (F, F, F), SINGLE), \
10583 X(2, (F, I), SINGLE), \
10584 X(2, (F, D), MIXED), \
10585 X(2, (D, F), MIXED), \
10586 X(3, (F, F, I), MIXED), \
10587 X(4, (R, R, F, F), SINGLE), \
10588 X(4, (F, F, R, R), SINGLE), \
10589 X(3, (D, R, R), DOUBLE), \
10590 X(3, (R, R, D), DOUBLE), \
10591 X(2, (S, R), SINGLE), \
10592 X(2, (R, S), SINGLE), \
10593 X(2, (F, R), SINGLE), \
10594 X(2, (R, F), SINGLE)
10596 #define S2(A,B) NS_##A##B
10597 #define S3(A,B,C) NS_##A##B##C
10598 #define S4(A,B,C,D) NS_##A##B##C##D
10600 #define X(N, L, C) S##N L
10613 enum neon_shape_class
10621 #define X(N, L, C) SC_##C
10623 static enum neon_shape_class neon_shape_class[] =
10641 /* Register widths of above. */
10642 static unsigned neon_shape_el_size[] =
10653 struct neon_shape_info
10656 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
10659 #define S2(A,B) { SE_##A, SE_##B }
10660 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10661 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10663 #define X(N, L, C) { N, S##N L }
10665 static struct neon_shape_info neon_shape_tab[] =
10675 /* Bit masks used in type checking given instructions.
10676 'N_EQK' means the type must be the same as (or based on in some way) the key
10677 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10678 set, various other bits can be set as well in order to modify the meaning of
10679 the type constraint. */
10681 enum neon_type_mask
10703 N_KEY = 0x100000, /* key element (main type specifier). */
10704 N_EQK = 0x200000, /* given operand has the same type & size as the key. */
10705 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */
10706 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */
10707 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */
10708 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */
10709 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10710 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */
10711 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */
10712 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10714 N_MAX_NONSPECIAL = N_F64
10717 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10719 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10720 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10721 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10722 #define N_SUF_32 (N_SU_32 | N_F32)
10723 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10724 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10726 /* Pass this as the first type argument to neon_check_type to ignore types
10728 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10730 /* Select a "shape" for the current instruction (describing register types or
10731 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10732 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10733 function of operand parsing, so this function doesn't need to be called.
10734 Shapes should be listed in order of decreasing length. */
10736 static enum neon_shape
10737 neon_select_shape (enum neon_shape shape, ...)
10740 enum neon_shape first_shape = shape;
10742 /* Fix missing optional operands. FIXME: we don't know at this point how
10743 many arguments we should have, so this makes the assumption that we have
10744 > 1. This is true of all current Neon opcodes, I think, but may not be
10745 true in the future. */
10746 if (!inst.operands[1].present)
10747 inst.operands[1] = inst.operands[0];
10749 va_start (ap, shape);
10751 for (; shape != NS_NULL; shape = va_arg (ap, int))
10756 for (j = 0; j < neon_shape_tab[shape].els; j++)
10758 if (!inst.operands[j].present)
10764 switch (neon_shape_tab[shape].el[j])
10767 if (!(inst.operands[j].isreg
10768 && inst.operands[j].isvec
10769 && inst.operands[j].issingle
10770 && !inst.operands[j].isquad))
10775 if (!(inst.operands[j].isreg
10776 && inst.operands[j].isvec
10777 && !inst.operands[j].isquad
10778 && !inst.operands[j].issingle))
10783 if (!(inst.operands[j].isreg
10784 && !inst.operands[j].isvec))
10789 if (!(inst.operands[j].isreg
10790 && inst.operands[j].isvec
10791 && inst.operands[j].isquad
10792 && !inst.operands[j].issingle))
10797 if (!(!inst.operands[j].isreg
10798 && !inst.operands[j].isscalar))
10803 if (!(!inst.operands[j].isreg
10804 && inst.operands[j].isscalar))
10818 if (shape == NS_NULL && first_shape != NS_NULL)
10819 first_error (_("invalid instruction shape"));
10824 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10825 means the Q bit should be set). */
10828 neon_quad (enum neon_shape shape)
10830 return neon_shape_class[shape] == SC_QUAD;
10834 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
10837 /* Allow modification to be made to types which are constrained to be
10838 based on the key element, based on bits set alongside N_EQK. */
10839 if ((typebits & N_EQK) != 0)
10841 if ((typebits & N_HLF) != 0)
10843 else if ((typebits & N_DBL) != 0)
10845 if ((typebits & N_SGN) != 0)
10846 *g_type = NT_signed;
10847 else if ((typebits & N_UNS) != 0)
10848 *g_type = NT_unsigned;
10849 else if ((typebits & N_INT) != 0)
10850 *g_type = NT_integer;
10851 else if ((typebits & N_FLT) != 0)
10852 *g_type = NT_float;
10853 else if ((typebits & N_SIZ) != 0)
10854 *g_type = NT_untyped;
10858 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10859 operand type, i.e. the single type specified in a Neon instruction when it
10860 is the only one given. */
10862 static struct neon_type_el
10863 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
10865 struct neon_type_el dest = *key;
10867 assert ((thisarg & N_EQK) != 0);
10869 neon_modify_type_size (thisarg, &dest.type, &dest.size);
10874 /* Convert Neon type and size into compact bitmask representation. */
10876 static enum neon_type_mask
10877 type_chk_of_el_type (enum neon_el_type type, unsigned size)
10884 case 8: return N_8;
10885 case 16: return N_16;
10886 case 32: return N_32;
10887 case 64: return N_64;
10895 case 8: return N_I8;
10896 case 16: return N_I16;
10897 case 32: return N_I32;
10898 case 64: return N_I64;
10906 case 32: return N_F32;
10907 case 64: return N_F64;
10915 case 8: return N_P8;
10916 case 16: return N_P16;
10924 case 8: return N_S8;
10925 case 16: return N_S16;
10926 case 32: return N_S32;
10927 case 64: return N_S64;
10935 case 8: return N_U8;
10936 case 16: return N_U16;
10937 case 32: return N_U32;
10938 case 64: return N_U64;
10949 /* Convert compact Neon bitmask type representation to a type and size. Only
10950 handles the case where a single bit is set in the mask. */
10953 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
10954 enum neon_type_mask mask)
10956 if ((mask & N_EQK) != 0)
10959 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
10961 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
10963 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
10965 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
10970 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
10972 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
10973 *type = NT_unsigned;
10974 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
10975 *type = NT_integer;
10976 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
10977 *type = NT_untyped;
10978 else if ((mask & (N_P8 | N_P16)) != 0)
10980 else if ((mask & (N_F32 | N_F64)) != 0)
10988 /* Modify a bitmask of allowed types. This is only needed for type
10992 modify_types_allowed (unsigned allowed, unsigned mods)
10995 enum neon_el_type type;
11001 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
11003 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
11005 neon_modify_type_size (mods, &type, &size);
11006 destmask |= type_chk_of_el_type (type, size);
11013 /* Check type and return type classification.
11014 The manual states (paraphrase): If one datatype is given, it indicates the
11016 - the second operand, if there is one
11017 - the operand, if there is no second operand
11018 - the result, if there are no operands.
11019 This isn't quite good enough though, so we use a concept of a "key" datatype
11020 which is set on a per-instruction basis, which is the one which matters when
11021 only one data type is written.
11022 Note: this function has side-effects (e.g. filling in missing operands). All
11023 Neon instructions should call it before performing bit encoding. */
11025 static struct neon_type_el
11026 neon_check_type (unsigned els, enum neon_shape ns, ...)
11029 unsigned i, pass, key_el = 0;
11030 unsigned types[NEON_MAX_TYPE_ELS];
11031 enum neon_el_type k_type = NT_invtype;
11032 unsigned k_size = -1u;
11033 struct neon_type_el badtype = {NT_invtype, -1};
11034 unsigned key_allowed = 0;
11036 /* Optional registers in Neon instructions are always (not) in operand 1.
11037 Fill in the missing operand here, if it was omitted. */
11038 if (els > 1 && !inst.operands[1].present)
11039 inst.operands[1] = inst.operands[0];
11041 /* Suck up all the varargs. */
11043 for (i = 0; i < els; i++)
11045 unsigned thisarg = va_arg (ap, unsigned);
11046 if (thisarg == N_IGNORE_TYPE)
11051 types[i] = thisarg;
11052 if ((thisarg & N_KEY) != 0)
11057 if (inst.vectype.elems > 0)
11058 for (i = 0; i < els; i++)
11059 if (inst.operands[i].vectype.type != NT_invtype)
11061 first_error (_("types specified in both the mnemonic and operands"));
11065 /* Duplicate inst.vectype elements here as necessary.
11066 FIXME: No idea if this is exactly the same as the ARM assembler,
11067 particularly when an insn takes one register and one non-register
11069 if (inst.vectype.elems == 1 && els > 1)
11072 inst.vectype.elems = els;
11073 inst.vectype.el[key_el] = inst.vectype.el[0];
11074 for (j = 0; j < els; j++)
11076 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11079 else if (inst.vectype.elems == 0 && els > 0)
11082 /* No types were given after the mnemonic, so look for types specified
11083 after each operand. We allow some flexibility here; as long as the
11084 "key" operand has a type, we can infer the others. */
11085 for (j = 0; j < els; j++)
11086 if (inst.operands[j].vectype.type != NT_invtype)
11087 inst.vectype.el[j] = inst.operands[j].vectype;
11089 if (inst.operands[key_el].vectype.type != NT_invtype)
11091 for (j = 0; j < els; j++)
11092 if (inst.operands[j].vectype.type == NT_invtype)
11093 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11098 first_error (_("operand types can't be inferred"));
11102 else if (inst.vectype.elems != els)
11104 first_error (_("type specifier has the wrong number of parts"));
11108 for (pass = 0; pass < 2; pass++)
11110 for (i = 0; i < els; i++)
11112 unsigned thisarg = types[i];
11113 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
11114 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
11115 enum neon_el_type g_type = inst.vectype.el[i].type;
11116 unsigned g_size = inst.vectype.el[i].size;
11118 /* Decay more-specific signed & unsigned types to sign-insensitive
11119 integer types if sign-specific variants are unavailable. */
11120 if ((g_type == NT_signed || g_type == NT_unsigned)
11121 && (types_allowed & N_SU_ALL) == 0)
11122 g_type = NT_integer;
11124 /* If only untyped args are allowed, decay any more specific types to
11125 them. Some instructions only care about signs for some element
11126 sizes, so handle that properly. */
11127 if ((g_size == 8 && (types_allowed & N_8) != 0)
11128 || (g_size == 16 && (types_allowed & N_16) != 0)
11129 || (g_size == 32 && (types_allowed & N_32) != 0)
11130 || (g_size == 64 && (types_allowed & N_64) != 0))
11131 g_type = NT_untyped;
11135 if ((thisarg & N_KEY) != 0)
11139 key_allowed = thisarg & ~N_KEY;
11144 if ((thisarg & N_VFP) != 0)
11146 enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
11147 unsigned regwidth = neon_shape_el_size[regshape], match;
11149 /* In VFP mode, operands must match register widths. If we
11150 have a key operand, use its width, else use the width of
11151 the current operand. */
11157 if (regwidth != match)
11159 first_error (_("operand size must match register width"));
11164 if ((thisarg & N_EQK) == 0)
11166 unsigned given_type = type_chk_of_el_type (g_type, g_size);
11168 if ((given_type & types_allowed) == 0)
11170 first_error (_("bad type in Neon instruction"));
11176 enum neon_el_type mod_k_type = k_type;
11177 unsigned mod_k_size = k_size;
11178 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
11179 if (g_type != mod_k_type || g_size != mod_k_size)
11181 first_error (_("inconsistent types in Neon instruction"));
11189 return inst.vectype.el[key_el];
11192 /* Neon-style VFP instruction forwarding. */
11194 /* Thumb VFP instructions have 0xE in the condition field. */
11197 do_vfp_cond_or_thumb (void)
11200 inst.instruction |= 0xe0000000;
11202 inst.instruction |= inst.cond << 28;
11205 /* Look up and encode a simple mnemonic, for use as a helper function for the
11206 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11207 etc. It is assumed that operand parsing has already been done, and that the
11208 operands are in the form expected by the given opcode (this isn't necessarily
11209 the same as the form in which they were parsed, hence some massaging must
11210 take place before this function is called).
11211 Checks current arch version against that in the looked-up opcode. */
11214 do_vfp_nsyn_opcode (const char *opname)
11216 const struct asm_opcode *opcode;
11218 opcode = hash_find (arm_ops_hsh, opname);
11223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
11224 thumb_mode ? *opcode->tvariant : *opcode->avariant),
11229 inst.instruction = opcode->tvalue;
11230 opcode->tencode ();
11234 inst.instruction = (inst.cond << 28) | opcode->avalue;
11235 opcode->aencode ();
11240 do_vfp_nsyn_add_sub (enum neon_shape rs)
11242 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
11247 do_vfp_nsyn_opcode ("fadds");
11249 do_vfp_nsyn_opcode ("fsubs");
11254 do_vfp_nsyn_opcode ("faddd");
11256 do_vfp_nsyn_opcode ("fsubd");
11260 /* Check operand types to see if this is a VFP instruction, and if so call
11264 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
11266 enum neon_shape rs;
11267 struct neon_type_el et;
11272 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11273 et = neon_check_type (2, rs,
11274 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11278 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11279 et = neon_check_type (3, rs,
11280 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11287 if (et.type != NT_invtype)
11299 do_vfp_nsyn_mla_mls (enum neon_shape rs)
11301 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
11306 do_vfp_nsyn_opcode ("fmacs");
11308 do_vfp_nsyn_opcode ("fmscs");
11313 do_vfp_nsyn_opcode ("fmacd");
11315 do_vfp_nsyn_opcode ("fmscd");
11320 do_vfp_nsyn_mul (enum neon_shape rs)
11323 do_vfp_nsyn_opcode ("fmuls");
11325 do_vfp_nsyn_opcode ("fmuld");
11329 do_vfp_nsyn_abs_neg (enum neon_shape rs)
11331 int is_neg = (inst.instruction & 0x80) != 0;
11332 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
11337 do_vfp_nsyn_opcode ("fnegs");
11339 do_vfp_nsyn_opcode ("fabss");
11344 do_vfp_nsyn_opcode ("fnegd");
11346 do_vfp_nsyn_opcode ("fabsd");
11350 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11351 insns belong to Neon, and are handled elsewhere. */
11354 do_vfp_nsyn_ldm_stm (int is_dbmode)
11356 int is_ldm = (inst.instruction & (1 << 20)) != 0;
11360 do_vfp_nsyn_opcode ("fldmdbs");
11362 do_vfp_nsyn_opcode ("fldmias");
11367 do_vfp_nsyn_opcode ("fstmdbs");
11369 do_vfp_nsyn_opcode ("fstmias");
11374 do_vfp_nsyn_sqrt (void)
11376 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11377 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11380 do_vfp_nsyn_opcode ("fsqrts");
11382 do_vfp_nsyn_opcode ("fsqrtd");
11386 do_vfp_nsyn_div (void)
11388 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11389 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11390 N_F32 | N_F64 | N_KEY | N_VFP);
11393 do_vfp_nsyn_opcode ("fdivs");
11395 do_vfp_nsyn_opcode ("fdivd");
11399 do_vfp_nsyn_nmul (void)
11401 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11402 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11403 N_F32 | N_F64 | N_KEY | N_VFP);
11407 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11408 do_vfp_sp_dyadic ();
11412 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11413 do_vfp_dp_rd_rn_rm ();
11415 do_vfp_cond_or_thumb ();
11419 do_vfp_nsyn_cmp (void)
11421 if (inst.operands[1].isreg)
11423 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11424 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11428 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11429 do_vfp_sp_monadic ();
11433 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11434 do_vfp_dp_rd_rm ();
11439 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
11440 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
11442 switch (inst.instruction & 0x0fffffff)
11445 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
11448 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
11456 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11457 do_vfp_sp_compare_z ();
11461 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11465 do_vfp_cond_or_thumb ();
11469 nsyn_insert_sp (void)
11471 inst.operands[1] = inst.operands[0];
11472 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
11473 inst.operands[0].reg = 13;
11474 inst.operands[0].isreg = 1;
11475 inst.operands[0].writeback = 1;
11476 inst.operands[0].present = 1;
11480 do_vfp_nsyn_push (void)
11483 if (inst.operands[1].issingle)
11484 do_vfp_nsyn_opcode ("fstmdbs");
11486 do_vfp_nsyn_opcode ("fstmdbd");
11490 do_vfp_nsyn_pop (void)
11493 if (inst.operands[1].issingle)
11494 do_vfp_nsyn_opcode ("fldmias");
11496 do_vfp_nsyn_opcode ("fldmiad");
11499 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11500 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11503 neon_dp_fixup (unsigned i)
11507 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11521 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11525 neon_logbits (unsigned x)
11527 return ffs (x) - 4;
11530 #define LOW4(R) ((R) & 0xf)
11531 #define HI1(R) (((R) >> 4) & 1)
11533 /* Encode insns with bit pattern:
11535 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11536 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11538 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11539 different meaning for some instruction. */
11542 neon_three_same (int isquad, int ubit, int size)
11544 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11545 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11546 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
11547 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
11548 inst.instruction |= LOW4 (inst.operands[2].reg);
11549 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
11550 inst.instruction |= (isquad != 0) << 6;
11551 inst.instruction |= (ubit != 0) << 24;
11553 inst.instruction |= neon_logbits (size) << 20;
11555 inst.instruction = neon_dp_fixup (inst.instruction);
11558 /* Encode instructions of the form:
11560 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11561 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11563 Don't write size if SIZE == -1. */
11566 neon_two_same (int qbit, int ubit, int size)
11568 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11569 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11570 inst.instruction |= LOW4 (inst.operands[1].reg);
11571 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11572 inst.instruction |= (qbit != 0) << 6;
11573 inst.instruction |= (ubit != 0) << 24;
11576 inst.instruction |= neon_logbits (size) << 18;
11578 inst.instruction = neon_dp_fixup (inst.instruction);
11581 /* Neon instruction encoders, in approximate order of appearance. */
11584 do_neon_dyadic_i_su (void)
11586 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11587 struct neon_type_el et = neon_check_type (3, rs,
11588 N_EQK, N_EQK, N_SU_32 | N_KEY);
11589 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11593 do_neon_dyadic_i64_su (void)
11595 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11596 struct neon_type_el et = neon_check_type (3, rs,
11597 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11598 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11602 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
11605 unsigned size = et.size >> 3;
11606 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11607 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11608 inst.instruction |= LOW4 (inst.operands[1].reg);
11609 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11610 inst.instruction |= (isquad != 0) << 6;
11611 inst.instruction |= immbits << 16;
11612 inst.instruction |= (size >> 3) << 7;
11613 inst.instruction |= (size & 0x7) << 19;
11615 inst.instruction |= (uval != 0) << 24;
11617 inst.instruction = neon_dp_fixup (inst.instruction);
11621 do_neon_shl_imm (void)
11623 if (!inst.operands[2].isreg)
11625 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11626 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
11627 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11628 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
11632 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11633 struct neon_type_el et = neon_check_type (3, rs,
11634 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11637 /* VSHL/VQSHL 3-register variants have syntax such as:
11639 whereas other 3-register operations encoded by neon_three_same have
11642 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11644 tmp = inst.operands[2].reg;
11645 inst.operands[2].reg = inst.operands[1].reg;
11646 inst.operands[1].reg = tmp;
11647 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11648 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11653 do_neon_qshl_imm (void)
11655 if (!inst.operands[2].isreg)
11657 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11658 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
11660 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11661 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
11662 inst.operands[2].imm);
11666 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11667 struct neon_type_el et = neon_check_type (3, rs,
11668 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11671 /* See note in do_neon_shl_imm. */
11672 tmp = inst.operands[2].reg;
11673 inst.operands[2].reg = inst.operands[1].reg;
11674 inst.operands[1].reg = tmp;
11675 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11676 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11681 do_neon_rshl (void)
11683 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11684 struct neon_type_el et = neon_check_type (3, rs,
11685 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11688 tmp = inst.operands[2].reg;
11689 inst.operands[2].reg = inst.operands[1].reg;
11690 inst.operands[1].reg = tmp;
11691 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11695 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
11697 /* Handle .I8 pseudo-instructions. */
11700 /* Unfortunately, this will make everything apart from zero out-of-range.
11701 FIXME is this the intended semantics? There doesn't seem much point in
11702 accepting .I8 if so. */
11703 immediate |= immediate << 8;
11709 if (immediate == (immediate & 0x000000ff))
11711 *immbits = immediate;
11714 else if (immediate == (immediate & 0x0000ff00))
11716 *immbits = immediate >> 8;
11719 else if (immediate == (immediate & 0x00ff0000))
11721 *immbits = immediate >> 16;
11724 else if (immediate == (immediate & 0xff000000))
11726 *immbits = immediate >> 24;
11729 if ((immediate & 0xffff) != (immediate >> 16))
11730 goto bad_immediate;
11731 immediate &= 0xffff;
11734 if (immediate == (immediate & 0x000000ff))
11736 *immbits = immediate;
11739 else if (immediate == (immediate & 0x0000ff00))
11741 *immbits = immediate >> 8;
11746 first_error (_("immediate value out of range"));
11750 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11754 neon_bits_same_in_bytes (unsigned imm)
11756 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
11757 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
11758 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
11759 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
11762 /* For immediate of above form, return 0bABCD. */
11765 neon_squash_bits (unsigned imm)
11767 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
11768 | ((imm & 0x01000000) >> 21);
11771 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11774 neon_qfloat_bits (unsigned imm)
11776 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
11779 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11780 the instruction. *OP is passed as the initial value of the op field, and
11781 may be set to a different value depending on the constant (i.e.
11782 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11783 MVN). If the immediate looks like a repeated parttern then also
11784 try smaller element sizes. */
11787 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
11788 unsigned *immbits, int *op, int size,
11789 enum neon_el_type type)
11791 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11793 if (type == NT_float && !float_p)
11796 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
11798 if (size != 32 || *op == 1)
11800 *immbits = neon_qfloat_bits (immlo);
11806 if (neon_bits_same_in_bytes (immhi)
11807 && neon_bits_same_in_bytes (immlo))
11811 *immbits = (neon_squash_bits (immhi) << 4)
11812 | neon_squash_bits (immlo);
11817 if (immhi != immlo)
11823 if (immlo == (immlo & 0x000000ff))
11828 else if (immlo == (immlo & 0x0000ff00))
11830 *immbits = immlo >> 8;
11833 else if (immlo == (immlo & 0x00ff0000))
11835 *immbits = immlo >> 16;
11838 else if (immlo == (immlo & 0xff000000))
11840 *immbits = immlo >> 24;
11843 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
11845 *immbits = (immlo >> 8) & 0xff;
11848 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
11850 *immbits = (immlo >> 16) & 0xff;
11854 if ((immlo & 0xffff) != (immlo >> 16))
11861 if (immlo == (immlo & 0x000000ff))
11866 else if (immlo == (immlo & 0x0000ff00))
11868 *immbits = immlo >> 8;
11872 if ((immlo & 0xff) != (immlo >> 8))
11877 if (immlo == (immlo & 0x000000ff))
11879 /* Don't allow MVN with 8-bit immediate. */
11889 /* Write immediate bits [7:0] to the following locations:
11891 |28/24|23 19|18 16|15 4|3 0|
11892 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11894 This function is used by VMOV/VMVN/VORR/VBIC. */
11897 neon_write_immbits (unsigned immbits)
11899 inst.instruction |= immbits & 0xf;
11900 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
11901 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
11904 /* Invert low-order SIZE bits of XHI:XLO. */
11907 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
11909 unsigned immlo = xlo ? *xlo : 0;
11910 unsigned immhi = xhi ? *xhi : 0;
11915 immlo = (~immlo) & 0xff;
11919 immlo = (~immlo) & 0xffff;
11923 immhi = (~immhi) & 0xffffffff;
11924 /* fall through. */
11927 immlo = (~immlo) & 0xffffffff;
11942 do_neon_logic (void)
11944 if (inst.operands[2].present && inst.operands[2].isreg)
11946 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11947 neon_check_type (3, rs, N_IGNORE_TYPE);
11948 /* U bit and size field were set as part of the bitmask. */
11949 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11950 neon_three_same (neon_quad (rs), 0, -1);
11954 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
11955 struct neon_type_el et = neon_check_type (2, rs,
11956 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
11957 enum neon_opc opcode = inst.instruction & 0x0fffffff;
11961 if (et.type == NT_invtype)
11964 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11966 immbits = inst.operands[1].imm;
11969 /* .i64 is a pseudo-op, so the immediate must be a repeating
11971 if (immbits != (inst.operands[1].regisimm ?
11972 inst.operands[1].reg : 0))
11974 /* Set immbits to an invalid constant. */
11975 immbits = 0xdeadbeef;
11982 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11986 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11990 /* Pseudo-instruction for VBIC. */
11991 neon_invert_size (&immbits, 0, et.size);
11992 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11996 /* Pseudo-instruction for VORR. */
11997 neon_invert_size (&immbits, 0, et.size);
11998 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12008 inst.instruction |= neon_quad (rs) << 6;
12009 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12010 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12011 inst.instruction |= cmode << 8;
12012 neon_write_immbits (immbits);
12014 inst.instruction = neon_dp_fixup (inst.instruction);
12019 do_neon_bitfield (void)
12021 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12022 neon_check_type (3, rs, N_IGNORE_TYPE);
12023 neon_three_same (neon_quad (rs), 0, -1);
12027 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
12030 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12031 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
12033 if (et.type == NT_float)
12035 inst.instruction = NEON_ENC_FLOAT (inst.instruction);
12036 neon_three_same (neon_quad (rs), 0, -1);
12040 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12041 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
12046 do_neon_dyadic_if_su (void)
12048 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
12052 do_neon_dyadic_if_su_d (void)
12054 /* This version only allow D registers, but that constraint is enforced during
12055 operand parsing so we don't need to do anything extra here. */
12056 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
12060 do_neon_dyadic_if_i_d (void)
12062 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12063 affected if we specify unsigned args. */
12064 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12067 enum vfp_or_neon_is_neon_bits
12070 NEON_CHECK_ARCH = 2
12073 /* Call this function if an instruction which may have belonged to the VFP or
12074 Neon instruction sets, but turned out to be a Neon instruction (due to the
12075 operand types involved, etc.). We have to check and/or fix-up a couple of
12078 - Make sure the user hasn't attempted to make a Neon instruction
12080 - Alter the value in the condition code field if necessary.
12081 - Make sure that the arch supports Neon instructions.
12083 Which of these operations take place depends on bits from enum
12084 vfp_or_neon_is_neon_bits.
12086 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12087 current instruction's condition is COND_ALWAYS, the condition field is
12088 changed to inst.uncond_value. This is necessary because instructions shared
12089 between VFP and Neon may be conditional for the VFP variants only, and the
12090 unconditional Neon version must have, e.g., 0xF in the condition field. */
12093 vfp_or_neon_is_neon (unsigned check)
12095 /* Conditions are always legal in Thumb mode (IT blocks). */
12096 if (!thumb_mode && (check & NEON_CHECK_CC))
12098 if (inst.cond != COND_ALWAYS)
12100 first_error (_(BAD_COND));
12103 if (inst.uncond_value != -1)
12104 inst.instruction |= inst.uncond_value << 28;
12107 if ((check & NEON_CHECK_ARCH)
12108 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
12110 first_error (_(BAD_FPU));
12118 do_neon_addsub_if_i (void)
12120 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
12123 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12126 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12127 affected if we specify unsigned args. */
12128 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
12131 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12133 V<op> A,B (A is operand 0, B is operand 2)
12138 so handle that case specially. */
12141 neon_exchange_operands (void)
12143 void *scratch = alloca (sizeof (inst.operands[0]));
12144 if (inst.operands[1].present)
12146 /* Swap operands[1] and operands[2]. */
12147 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
12148 inst.operands[1] = inst.operands[2];
12149 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
12153 inst.operands[1] = inst.operands[2];
12154 inst.operands[2] = inst.operands[0];
12159 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
12161 if (inst.operands[2].isreg)
12164 neon_exchange_operands ();
12165 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
12169 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12170 struct neon_type_el et = neon_check_type (2, rs,
12171 N_EQK | N_SIZ, immtypes | N_KEY);
12173 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12174 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12175 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12176 inst.instruction |= LOW4 (inst.operands[1].reg);
12177 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12178 inst.instruction |= neon_quad (rs) << 6;
12179 inst.instruction |= (et.type == NT_float) << 10;
12180 inst.instruction |= neon_logbits (et.size) << 18;
12182 inst.instruction = neon_dp_fixup (inst.instruction);
12189 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
12193 do_neon_cmp_inv (void)
12195 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
12201 neon_compare (N_IF_32, N_IF_32, FALSE);
12204 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12205 scalars, which are encoded in 5 bits, M : Rm.
12206 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12207 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12211 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
12213 unsigned regno = NEON_SCALAR_REG (scalar);
12214 unsigned elno = NEON_SCALAR_INDEX (scalar);
12219 if (regno > 7 || elno > 3)
12221 return regno | (elno << 3);
12224 if (regno > 15 || elno > 1)
12226 return regno | (elno << 4);
12230 first_error (_("scalar out of range for multiply instruction"));
12236 /* Encode multiply / multiply-accumulate scalar instructions. */
12239 neon_mul_mac (struct neon_type_el et, int ubit)
12243 /* Give a more helpful error message if we have an invalid type. */
12244 if (et.type == NT_invtype)
12247 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
12248 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12249 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12250 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12251 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12252 inst.instruction |= LOW4 (scalar);
12253 inst.instruction |= HI1 (scalar) << 5;
12254 inst.instruction |= (et.type == NT_float) << 8;
12255 inst.instruction |= neon_logbits (et.size) << 20;
12256 inst.instruction |= (ubit != 0) << 24;
12258 inst.instruction = neon_dp_fixup (inst.instruction);
12262 do_neon_mac_maybe_scalar (void)
12264 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
12267 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12270 if (inst.operands[2].isscalar)
12272 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12273 struct neon_type_el et = neon_check_type (3, rs,
12274 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
12275 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12276 neon_mul_mac (et, neon_quad (rs));
12280 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12281 affected if we specify unsigned args. */
12282 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12289 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12290 struct neon_type_el et = neon_check_type (3, rs,
12291 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
12292 neon_three_same (neon_quad (rs), 0, et.size);
12295 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12296 same types as the MAC equivalents. The polynomial type for this instruction
12297 is encoded the same as the integer type. */
12302 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
12305 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12308 if (inst.operands[2].isscalar)
12309 do_neon_mac_maybe_scalar ();
12311 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
12315 do_neon_qdmulh (void)
12317 if (inst.operands[2].isscalar)
12319 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12320 struct neon_type_el et = neon_check_type (3, rs,
12321 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12322 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12323 neon_mul_mac (et, neon_quad (rs));
12327 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12328 struct neon_type_el et = neon_check_type (3, rs,
12329 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12330 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12331 /* The U bit (rounding) comes from bit mask. */
12332 neon_three_same (neon_quad (rs), 0, et.size);
12337 do_neon_fcmp_absolute (void)
12339 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12340 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12341 /* Size field comes from bit mask. */
12342 neon_three_same (neon_quad (rs), 1, -1);
12346 do_neon_fcmp_absolute_inv (void)
12348 neon_exchange_operands ();
12349 do_neon_fcmp_absolute ();
12353 do_neon_step (void)
12355 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12356 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12357 neon_three_same (neon_quad (rs), 0, -1);
12361 do_neon_abs_neg (void)
12363 enum neon_shape rs;
12364 struct neon_type_el et;
12366 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
12369 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12372 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12373 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
12375 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12376 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12377 inst.instruction |= LOW4 (inst.operands[1].reg);
12378 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12379 inst.instruction |= neon_quad (rs) << 6;
12380 inst.instruction |= (et.type == NT_float) << 10;
12381 inst.instruction |= neon_logbits (et.size) << 18;
12383 inst.instruction = neon_dp_fixup (inst.instruction);
12389 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12390 struct neon_type_el et = neon_check_type (2, rs,
12391 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12392 int imm = inst.operands[2].imm;
12393 constraint (imm < 0 || (unsigned)imm >= et.size,
12394 _("immediate out of range for insert"));
12395 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12401 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12402 struct neon_type_el et = neon_check_type (2, rs,
12403 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12404 int imm = inst.operands[2].imm;
12405 constraint (imm < 1 || (unsigned)imm > et.size,
12406 _("immediate out of range for insert"));
12407 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
12411 do_neon_qshlu_imm (void)
12413 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12414 struct neon_type_el et = neon_check_type (2, rs,
12415 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
12416 int imm = inst.operands[2].imm;
12417 constraint (imm < 0 || (unsigned)imm >= et.size,
12418 _("immediate out of range for shift"));
12419 /* Only encodes the 'U present' variant of the instruction.
12420 In this case, signed types have OP (bit 8) set to 0.
12421 Unsigned types have OP set to 1. */
12422 inst.instruction |= (et.type == NT_unsigned) << 8;
12423 /* The rest of the bits are the same as other immediate shifts. */
12424 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12428 do_neon_qmovn (void)
12430 struct neon_type_el et = neon_check_type (2, NS_DQ,
12431 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12432 /* Saturating move where operands can be signed or unsigned, and the
12433 destination has the same signedness. */
12434 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12435 if (et.type == NT_unsigned)
12436 inst.instruction |= 0xc0;
12438 inst.instruction |= 0x80;
12439 neon_two_same (0, 1, et.size / 2);
12443 do_neon_qmovun (void)
12445 struct neon_type_el et = neon_check_type (2, NS_DQ,
12446 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12447 /* Saturating move with unsigned results. Operands must be signed. */
12448 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12449 neon_two_same (0, 1, et.size / 2);
12453 do_neon_rshift_sat_narrow (void)
12455 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12456 or unsigned. If operands are unsigned, results must also be unsigned. */
12457 struct neon_type_el et = neon_check_type (2, NS_DQI,
12458 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12459 int imm = inst.operands[2].imm;
12460 /* This gets the bounds check, size encoding and immediate bits calculation
12464 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12465 VQMOVN.I<size> <Dd>, <Qm>. */
12468 inst.operands[2].present = 0;
12469 inst.instruction = N_MNEM_vqmovn;
12474 constraint (imm < 1 || (unsigned)imm > et.size,
12475 _("immediate out of range"));
12476 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
12480 do_neon_rshift_sat_narrow_u (void)
12482 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12483 or unsigned. If operands are unsigned, results must also be unsigned. */
12484 struct neon_type_el et = neon_check_type (2, NS_DQI,
12485 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12486 int imm = inst.operands[2].imm;
12487 /* This gets the bounds check, size encoding and immediate bits calculation
12491 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12492 VQMOVUN.I<size> <Dd>, <Qm>. */
12495 inst.operands[2].present = 0;
12496 inst.instruction = N_MNEM_vqmovun;
12501 constraint (imm < 1 || (unsigned)imm > et.size,
12502 _("immediate out of range"));
12503 /* FIXME: The manual is kind of unclear about what value U should have in
12504 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12506 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
12510 do_neon_movn (void)
12512 struct neon_type_el et = neon_check_type (2, NS_DQ,
12513 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12514 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12515 neon_two_same (0, 1, et.size / 2);
12519 do_neon_rshift_narrow (void)
12521 struct neon_type_el et = neon_check_type (2, NS_DQI,
12522 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12523 int imm = inst.operands[2].imm;
12524 /* This gets the bounds check, size encoding and immediate bits calculation
12528 /* If immediate is zero then we are a pseudo-instruction for
12529 VMOVN.I<size> <Dd>, <Qm> */
12532 inst.operands[2].present = 0;
12533 inst.instruction = N_MNEM_vmovn;
12538 constraint (imm < 1 || (unsigned)imm > et.size,
12539 _("immediate out of range for narrowing operation"));
12540 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
12544 do_neon_shll (void)
12546 /* FIXME: Type checking when lengthening. */
12547 struct neon_type_el et = neon_check_type (2, NS_QDI,
12548 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
12549 unsigned imm = inst.operands[2].imm;
12551 if (imm == et.size)
12553 /* Maximum shift variant. */
12554 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12555 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12556 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12557 inst.instruction |= LOW4 (inst.operands[1].reg);
12558 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12559 inst.instruction |= neon_logbits (et.size) << 18;
12561 inst.instruction = neon_dp_fixup (inst.instruction);
12565 /* A more-specific type check for non-max versions. */
12566 et = neon_check_type (2, NS_QDI,
12567 N_EQK | N_DBL, N_SU_32 | N_KEY);
12568 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12569 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
12573 /* Check the various types for the VCVT instruction, and return which version
12574 the current instruction is. */
12577 neon_cvt_flavour (enum neon_shape rs)
12579 #define CVT_VAR(C,X,Y) \
12580 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12581 if (et.type != NT_invtype) \
12583 inst.error = NULL; \
12586 struct neon_type_el et;
12587 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
12588 || rs == NS_FF) ? N_VFP : 0;
12589 /* The instruction versions which take an immediate take one register
12590 argument, which is extended to the width of the full register. Thus the
12591 "source" and "destination" registers must have the same width. Hack that
12592 here by making the size equal to the key (wider, in this case) operand. */
12593 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
12595 CVT_VAR (0, N_S32, N_F32);
12596 CVT_VAR (1, N_U32, N_F32);
12597 CVT_VAR (2, N_F32, N_S32);
12598 CVT_VAR (3, N_F32, N_U32);
12602 /* VFP instructions. */
12603 CVT_VAR (4, N_F32, N_F64);
12604 CVT_VAR (5, N_F64, N_F32);
12605 CVT_VAR (6, N_S32, N_F64 | key);
12606 CVT_VAR (7, N_U32, N_F64 | key);
12607 CVT_VAR (8, N_F64 | key, N_S32);
12608 CVT_VAR (9, N_F64 | key, N_U32);
12609 /* VFP instructions with bitshift. */
12610 CVT_VAR (10, N_F32 | key, N_S16);
12611 CVT_VAR (11, N_F32 | key, N_U16);
12612 CVT_VAR (12, N_F64 | key, N_S16);
12613 CVT_VAR (13, N_F64 | key, N_U16);
12614 CVT_VAR (14, N_S16, N_F32 | key);
12615 CVT_VAR (15, N_U16, N_F32 | key);
12616 CVT_VAR (16, N_S16, N_F64 | key);
12617 CVT_VAR (17, N_U16, N_F64 | key);
12623 /* Neon-syntax VFP conversions. */
12626 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
12628 const char *opname = 0;
12630 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
12632 /* Conversions with immediate bitshift. */
12633 const char *enc[] =
12655 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12657 opname = enc[flavour];
12658 constraint (inst.operands[0].reg != inst.operands[1].reg,
12659 _("operands 0 and 1 must be the same register"));
12660 inst.operands[1] = inst.operands[2];
12661 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
12666 /* Conversions without bitshift. */
12667 const char *enc[] =
12681 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12682 opname = enc[flavour];
12686 do_vfp_nsyn_opcode (opname);
12690 do_vfp_nsyn_cvtz (void)
12692 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
12693 int flavour = neon_cvt_flavour (rs);
12694 const char *enc[] =
12706 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
12707 do_vfp_nsyn_opcode (enc[flavour]);
12713 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
12714 NS_FD, NS_DF, NS_FF, NS_NULL);
12715 int flavour = neon_cvt_flavour (rs);
12717 /* VFP rather than Neon conversions. */
12720 do_vfp_nsyn_cvt (rs, flavour);
12729 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12732 /* Fixed-point conversion with #0 immediate is encoded as an
12733 integer conversion. */
12734 if (inst.operands[2].present && inst.operands[2].imm == 0)
12736 unsigned immbits = 32 - inst.operands[2].imm;
12737 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12738 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12740 inst.instruction |= enctab[flavour];
12741 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12742 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12743 inst.instruction |= LOW4 (inst.operands[1].reg);
12744 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12745 inst.instruction |= neon_quad (rs) << 6;
12746 inst.instruction |= 1 << 21;
12747 inst.instruction |= immbits << 16;
12749 inst.instruction = neon_dp_fixup (inst.instruction);
12757 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
12759 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12761 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12765 inst.instruction |= enctab[flavour];
12767 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12768 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12769 inst.instruction |= LOW4 (inst.operands[1].reg);
12770 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12771 inst.instruction |= neon_quad (rs) << 6;
12772 inst.instruction |= 2 << 18;
12774 inst.instruction = neon_dp_fixup (inst.instruction);
12779 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12780 do_vfp_nsyn_cvt (rs, flavour);
12785 neon_move_immediate (void)
12787 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
12788 struct neon_type_el et = neon_check_type (2, rs,
12789 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
12790 unsigned immlo, immhi = 0, immbits;
12791 int op, cmode, float_p;
12793 constraint (et.type == NT_invtype,
12794 _("operand size must be specified for immediate VMOV"));
12796 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12797 op = (inst.instruction & (1 << 5)) != 0;
12799 immlo = inst.operands[1].imm;
12800 if (inst.operands[1].regisimm)
12801 immhi = inst.operands[1].reg;
12803 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
12804 _("immediate has bits set outside the operand size"));
12806 float_p = inst.operands[1].immisfloat;
12808 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
12809 et.size, et.type)) == FAIL)
12811 /* Invert relevant bits only. */
12812 neon_invert_size (&immlo, &immhi, et.size);
12813 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12814 with one or the other; those cases are caught by
12815 neon_cmode_for_move_imm. */
12817 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
12818 &op, et.size, et.type)) == FAIL)
12820 first_error (_("immediate out of range"));
12825 inst.instruction &= ~(1 << 5);
12826 inst.instruction |= op << 5;
12828 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12829 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12830 inst.instruction |= neon_quad (rs) << 6;
12831 inst.instruction |= cmode << 8;
12833 neon_write_immbits (immbits);
12839 if (inst.operands[1].isreg)
12841 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12843 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12844 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12845 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12846 inst.instruction |= LOW4 (inst.operands[1].reg);
12847 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12848 inst.instruction |= neon_quad (rs) << 6;
12852 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12853 neon_move_immediate ();
12856 inst.instruction = neon_dp_fixup (inst.instruction);
12859 /* Encode instructions of form:
12861 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12862 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12867 neon_mixed_length (struct neon_type_el et, unsigned size)
12869 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12870 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12871 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12872 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12873 inst.instruction |= LOW4 (inst.operands[2].reg);
12874 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12875 inst.instruction |= (et.type == NT_unsigned) << 24;
12876 inst.instruction |= neon_logbits (size) << 20;
12878 inst.instruction = neon_dp_fixup (inst.instruction);
12882 do_neon_dyadic_long (void)
12884 /* FIXME: Type checking for lengthening op. */
12885 struct neon_type_el et = neon_check_type (3, NS_QDD,
12886 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
12887 neon_mixed_length (et, et.size);
12891 do_neon_abal (void)
12893 struct neon_type_el et = neon_check_type (3, NS_QDD,
12894 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
12895 neon_mixed_length (et, et.size);
12899 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
12901 if (inst.operands[2].isscalar)
12903 struct neon_type_el et = neon_check_type (3, NS_QDS,
12904 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
12905 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12906 neon_mul_mac (et, et.type == NT_unsigned);
12910 struct neon_type_el et = neon_check_type (3, NS_QDD,
12911 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
12912 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12913 neon_mixed_length (et, et.size);
12918 do_neon_mac_maybe_scalar_long (void)
12920 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
12924 do_neon_dyadic_wide (void)
12926 struct neon_type_el et = neon_check_type (3, NS_QQD,
12927 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
12928 neon_mixed_length (et, et.size);
12932 do_neon_dyadic_narrow (void)
12934 struct neon_type_el et = neon_check_type (3, NS_QDD,
12935 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
12936 /* Operand sign is unimportant, and the U bit is part of the opcode,
12937 so force the operand type to integer. */
12938 et.type = NT_integer;
12939 neon_mixed_length (et, et.size / 2);
12943 do_neon_mul_sat_scalar_long (void)
12945 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
12949 do_neon_vmull (void)
12951 if (inst.operands[2].isscalar)
12952 do_neon_mac_maybe_scalar_long ();
12955 struct neon_type_el et = neon_check_type (3, NS_QDD,
12956 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
12957 if (et.type == NT_poly)
12958 inst.instruction = NEON_ENC_POLY (inst.instruction);
12960 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12961 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12962 zero. Should be OK as-is. */
12963 neon_mixed_length (et, et.size);
12970 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
12971 struct neon_type_el et = neon_check_type (3, rs,
12972 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12973 unsigned imm = (inst.operands[3].imm * et.size) / 8;
12974 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
12975 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12976 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12977 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12978 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12979 inst.instruction |= LOW4 (inst.operands[2].reg);
12980 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12981 inst.instruction |= neon_quad (rs) << 6;
12982 inst.instruction |= imm << 8;
12984 inst.instruction = neon_dp_fixup (inst.instruction);
12990 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12991 struct neon_type_el et = neon_check_type (2, rs,
12992 N_EQK, N_8 | N_16 | N_32 | N_KEY);
12993 unsigned op = (inst.instruction >> 7) & 3;
12994 /* N (width of reversed regions) is encoded as part of the bitmask. We
12995 extract it here to check the elements to be reversed are smaller.
12996 Otherwise we'd get a reserved instruction. */
12997 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
12998 assert (elsize != 0);
12999 constraint (et.size >= elsize,
13000 _("elements must be smaller than reversal region"));
13001 neon_two_same (neon_quad (rs), 1, et.size);
13007 if (inst.operands[1].isscalar)
13009 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
13010 struct neon_type_el et = neon_check_type (2, rs,
13011 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13012 unsigned sizebits = et.size >> 3;
13013 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
13014 int logsize = neon_logbits (et.size);
13015 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
13017 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
13020 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
13021 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13022 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13023 inst.instruction |= LOW4 (dm);
13024 inst.instruction |= HI1 (dm) << 5;
13025 inst.instruction |= neon_quad (rs) << 6;
13026 inst.instruction |= x << 17;
13027 inst.instruction |= sizebits << 16;
13029 inst.instruction = neon_dp_fixup (inst.instruction);
13033 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
13034 struct neon_type_el et = neon_check_type (2, rs,
13035 N_8 | N_16 | N_32 | N_KEY, N_EQK);
13036 /* Duplicate ARM register to lanes of vector. */
13037 inst.instruction = NEON_ENC_ARMREG (inst.instruction);
13040 case 8: inst.instruction |= 0x400000; break;
13041 case 16: inst.instruction |= 0x000020; break;
13042 case 32: inst.instruction |= 0x000000; break;
13045 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13046 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
13047 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
13048 inst.instruction |= neon_quad (rs) << 21;
13049 /* The encoding for this instruction is identical for the ARM and Thumb
13050 variants, except for the condition field. */
13051 do_vfp_cond_or_thumb ();
13055 /* VMOV has particularly many variations. It can be one of:
13056 0. VMOV<c><q> <Qd>, <Qm>
13057 1. VMOV<c><q> <Dd>, <Dm>
13058 (Register operations, which are VORR with Rm = Rn.)
13059 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13060 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13062 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13063 (ARM register to scalar.)
13064 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13065 (Two ARM registers to vector.)
13066 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13067 (Scalar to ARM register.)
13068 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13069 (Vector to two ARM registers.)
13070 8. VMOV.F32 <Sd>, <Sm>
13071 9. VMOV.F64 <Dd>, <Dm>
13072 (VFP register moves.)
13073 10. VMOV.F32 <Sd>, #imm
13074 11. VMOV.F64 <Dd>, #imm
13075 (VFP float immediate load.)
13076 12. VMOV <Rd>, <Sm>
13077 (VFP single to ARM reg.)
13078 13. VMOV <Sd>, <Rm>
13079 (ARM reg to VFP single.)
13080 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13081 (Two ARM regs to two VFP singles.)
13082 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13083 (Two VFP singles to two ARM regs.)
13085 These cases can be disambiguated using neon_select_shape, except cases 1/9
13086 and 3/11 which depend on the operand type too.
13088 All the encoded bits are hardcoded by this function.
13090 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13091 Cases 5, 7 may be used with VFPv2 and above.
13093 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13094 can specify a type where it doesn't make sense to, and is ignored).
13100 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
13101 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
13103 struct neon_type_el et;
13104 const char *ldconst = 0;
13108 case NS_DD: /* case 1/9. */
13109 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13110 /* It is not an error here if no type is given. */
13112 if (et.type == NT_float && et.size == 64)
13114 do_vfp_nsyn_opcode ("fcpyd");
13117 /* fall through. */
13119 case NS_QQ: /* case 0/1. */
13121 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13123 /* The architecture manual I have doesn't explicitly state which
13124 value the U bit should have for register->register moves, but
13125 the equivalent VORR instruction has U = 0, so do that. */
13126 inst.instruction = 0x0200110;
13127 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13128 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13129 inst.instruction |= LOW4 (inst.operands[1].reg);
13130 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13131 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13132 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13133 inst.instruction |= neon_quad (rs) << 6;
13135 inst.instruction = neon_dp_fixup (inst.instruction);
13139 case NS_DI: /* case 3/11. */
13140 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13142 if (et.type == NT_float && et.size == 64)
13144 /* case 11 (fconstd). */
13145 ldconst = "fconstd";
13146 goto encode_fconstd;
13148 /* fall through. */
13150 case NS_QI: /* case 2/3. */
13151 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13153 inst.instruction = 0x0800010;
13154 neon_move_immediate ();
13155 inst.instruction = neon_dp_fixup (inst.instruction);
13158 case NS_SR: /* case 4. */
13160 unsigned bcdebits = 0;
13161 struct neon_type_el et = neon_check_type (2, NS_NULL,
13162 N_8 | N_16 | N_32 | N_KEY, N_EQK);
13163 int logsize = neon_logbits (et.size);
13164 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
13165 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
13167 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13169 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13170 && et.size != 32, _(BAD_FPU));
13171 constraint (et.type == NT_invtype, _("bad type for scalar"));
13172 constraint (x >= 64 / et.size, _("scalar index out of range"));
13176 case 8: bcdebits = 0x8; break;
13177 case 16: bcdebits = 0x1; break;
13178 case 32: bcdebits = 0x0; break;
13182 bcdebits |= x << logsize;
13184 inst.instruction = 0xe000b10;
13185 do_vfp_cond_or_thumb ();
13186 inst.instruction |= LOW4 (dn) << 16;
13187 inst.instruction |= HI1 (dn) << 7;
13188 inst.instruction |= inst.operands[1].reg << 12;
13189 inst.instruction |= (bcdebits & 3) << 5;
13190 inst.instruction |= (bcdebits >> 2) << 21;
13194 case NS_DRR: /* case 5 (fmdrr). */
13195 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13198 inst.instruction = 0xc400b10;
13199 do_vfp_cond_or_thumb ();
13200 inst.instruction |= LOW4 (inst.operands[0].reg);
13201 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
13202 inst.instruction |= inst.operands[1].reg << 12;
13203 inst.instruction |= inst.operands[2].reg << 16;
13206 case NS_RS: /* case 6. */
13208 struct neon_type_el et = neon_check_type (2, NS_NULL,
13209 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
13210 unsigned logsize = neon_logbits (et.size);
13211 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
13212 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
13213 unsigned abcdebits = 0;
13215 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13217 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13218 && et.size != 32, _(BAD_FPU));
13219 constraint (et.type == NT_invtype, _("bad type for scalar"));
13220 constraint (x >= 64 / et.size, _("scalar index out of range"));
13224 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
13225 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
13226 case 32: abcdebits = 0x00; break;
13230 abcdebits |= x << logsize;
13231 inst.instruction = 0xe100b10;
13232 do_vfp_cond_or_thumb ();
13233 inst.instruction |= LOW4 (dn) << 16;
13234 inst.instruction |= HI1 (dn) << 7;
13235 inst.instruction |= inst.operands[0].reg << 12;
13236 inst.instruction |= (abcdebits & 3) << 5;
13237 inst.instruction |= (abcdebits >> 2) << 21;
13241 case NS_RRD: /* case 7 (fmrrd). */
13242 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13245 inst.instruction = 0xc500b10;
13246 do_vfp_cond_or_thumb ();
13247 inst.instruction |= inst.operands[0].reg << 12;
13248 inst.instruction |= inst.operands[1].reg << 16;
13249 inst.instruction |= LOW4 (inst.operands[2].reg);
13250 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13253 case NS_FF: /* case 8 (fcpys). */
13254 do_vfp_nsyn_opcode ("fcpys");
13257 case NS_FI: /* case 10 (fconsts). */
13258 ldconst = "fconsts";
13260 if (is_quarter_float (inst.operands[1].imm))
13262 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
13263 do_vfp_nsyn_opcode (ldconst);
13266 first_error (_("immediate out of range"));
13269 case NS_RF: /* case 12 (fmrs). */
13270 do_vfp_nsyn_opcode ("fmrs");
13273 case NS_FR: /* case 13 (fmsr). */
13274 do_vfp_nsyn_opcode ("fmsr");
13277 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13278 (one of which is a list), but we have parsed four. Do some fiddling to
13279 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13281 case NS_RRFF: /* case 14 (fmrrs). */
13282 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
13283 _("VFP registers must be adjacent"));
13284 inst.operands[2].imm = 2;
13285 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13286 do_vfp_nsyn_opcode ("fmrrs");
13289 case NS_FFRR: /* case 15 (fmsrr). */
13290 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
13291 _("VFP registers must be adjacent"));
13292 inst.operands[1] = inst.operands[2];
13293 inst.operands[2] = inst.operands[3];
13294 inst.operands[0].imm = 2;
13295 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13296 do_vfp_nsyn_opcode ("fmsrr");
13305 do_neon_rshift_round_imm (void)
13307 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13308 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13309 int imm = inst.operands[2].imm;
13311 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13314 inst.operands[2].present = 0;
13319 constraint (imm < 1 || (unsigned)imm > et.size,
13320 _("immediate out of range for shift"));
13321 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13326 do_neon_movl (void)
13328 struct neon_type_el et = neon_check_type (2, NS_QD,
13329 N_EQK | N_DBL, N_SU_32 | N_KEY);
13330 unsigned sizebits = et.size >> 3;
13331 inst.instruction |= sizebits << 19;
13332 neon_two_same (0, et.type == NT_unsigned, -1);
13338 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13339 struct neon_type_el et = neon_check_type (2, rs,
13340 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13341 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
13342 neon_two_same (neon_quad (rs), 1, et.size);
13346 do_neon_zip_uzp (void)
13348 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13349 struct neon_type_el et = neon_check_type (2, rs,
13350 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13351 if (rs == NS_DD && et.size == 32)
13353 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13354 inst.instruction = N_MNEM_vtrn;
13358 neon_two_same (neon_quad (rs), 1, et.size);
13362 do_neon_sat_abs_neg (void)
13364 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13365 struct neon_type_el et = neon_check_type (2, rs,
13366 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13367 neon_two_same (neon_quad (rs), 1, et.size);
13371 do_neon_pair_long (void)
13373 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13374 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
13375 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13376 inst.instruction |= (et.type == NT_unsigned) << 7;
13377 neon_two_same (neon_quad (rs), 1, et.size);
13381 do_neon_recip_est (void)
13383 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13384 struct neon_type_el et = neon_check_type (2, rs,
13385 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
13386 inst.instruction |= (et.type == NT_float) << 8;
13387 neon_two_same (neon_quad (rs), 1, et.size);
13393 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13394 struct neon_type_el et = neon_check_type (2, rs,
13395 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13396 neon_two_same (neon_quad (rs), 1, et.size);
13402 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13403 struct neon_type_el et = neon_check_type (2, rs,
13404 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
13405 neon_two_same (neon_quad (rs), 1, et.size);
13411 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13412 struct neon_type_el et = neon_check_type (2, rs,
13413 N_EQK | N_INT, N_8 | N_KEY);
13414 neon_two_same (neon_quad (rs), 1, et.size);
13420 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13421 neon_two_same (neon_quad (rs), 1, -1);
13425 do_neon_tbl_tbx (void)
13427 unsigned listlenbits;
13428 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
13430 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
13432 first_error (_("bad list length for table lookup"));
13436 listlenbits = inst.operands[1].imm - 1;
13437 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13438 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13439 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13440 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13441 inst.instruction |= LOW4 (inst.operands[2].reg);
13442 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13443 inst.instruction |= listlenbits << 8;
13445 inst.instruction = neon_dp_fixup (inst.instruction);
13449 do_neon_ldm_stm (void)
13451 /* P, U and L bits are part of bitmask. */
13452 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
13453 unsigned offsetbits = inst.operands[1].imm * 2;
13455 if (inst.operands[1].issingle)
13457 do_vfp_nsyn_ldm_stm (is_dbmode);
13461 constraint (is_dbmode && !inst.operands[0].writeback,
13462 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13464 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
13465 _("register list must contain at least 1 and at most 16 "
13468 inst.instruction |= inst.operands[0].reg << 16;
13469 inst.instruction |= inst.operands[0].writeback << 21;
13470 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13471 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
13473 inst.instruction |= offsetbits;
13475 do_vfp_cond_or_thumb ();
13479 do_neon_ldr_str (void)
13481 int is_ldr = (inst.instruction & (1 << 20)) != 0;
13483 if (inst.operands[0].issingle)
13486 do_vfp_nsyn_opcode ("flds");
13488 do_vfp_nsyn_opcode ("fsts");
13493 do_vfp_nsyn_opcode ("fldd");
13495 do_vfp_nsyn_opcode ("fstd");
13499 /* "interleave" version also handles non-interleaving register VLD1/VST1
13503 do_neon_ld_st_interleave (void)
13505 struct neon_type_el et = neon_check_type (1, NS_NULL,
13506 N_8 | N_16 | N_32 | N_64);
13507 unsigned alignbits = 0;
13509 /* The bits in this table go:
13510 0: register stride of one (0) or two (1)
13511 1,2: register list length, minus one (1, 2, 3, 4).
13512 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13513 We use -1 for invalid entries. */
13514 const int typetable[] =
13516 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13517 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13518 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13519 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13523 if (et.type == NT_invtype)
13526 if (inst.operands[1].immisalign)
13527 switch (inst.operands[1].imm >> 8)
13529 case 64: alignbits = 1; break;
13531 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13532 goto bad_alignment;
13536 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13537 goto bad_alignment;
13542 first_error (_("bad alignment"));
13546 inst.instruction |= alignbits << 4;
13547 inst.instruction |= neon_logbits (et.size) << 6;
13549 /* Bits [4:6] of the immediate in a list specifier encode register stride
13550 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13551 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13552 up the right value for "type" in a table based on this value and the given
13553 list style, then stick it back. */
13554 idx = ((inst.operands[0].imm >> 4) & 7)
13555 | (((inst.instruction >> 8) & 3) << 3);
13557 typebits = typetable[idx];
13559 constraint (typebits == -1, _("bad list type for instruction"));
13561 inst.instruction &= ~0xf00;
13562 inst.instruction |= typebits << 8;
13565 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13566 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13567 otherwise. The variable arguments are a list of pairs of legal (size, align)
13568 values, terminated with -1. */
13571 neon_alignment_bit (int size, int align, int *do_align, ...)
13574 int result = FAIL, thissize, thisalign;
13576 if (!inst.operands[1].immisalign)
13582 va_start (ap, do_align);
13586 thissize = va_arg (ap, int);
13587 if (thissize == -1)
13589 thisalign = va_arg (ap, int);
13591 if (size == thissize && align == thisalign)
13594 while (result != SUCCESS);
13598 if (result == SUCCESS)
13601 first_error (_("unsupported alignment for instruction"));
13607 do_neon_ld_st_lane (void)
13609 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13610 int align_good, do_align = 0;
13611 int logsize = neon_logbits (et.size);
13612 int align = inst.operands[1].imm >> 8;
13613 int n = (inst.instruction >> 8) & 3;
13614 int max_el = 64 / et.size;
13616 if (et.type == NT_invtype)
13619 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
13620 _("bad list length"));
13621 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
13622 _("scalar index out of range"));
13623 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
13625 _("stride of 2 unavailable when element size is 8"));
13629 case 0: /* VLD1 / VST1. */
13630 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
13632 if (align_good == FAIL)
13636 unsigned alignbits = 0;
13639 case 16: alignbits = 0x1; break;
13640 case 32: alignbits = 0x3; break;
13643 inst.instruction |= alignbits << 4;
13647 case 1: /* VLD2 / VST2. */
13648 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
13650 if (align_good == FAIL)
13653 inst.instruction |= 1 << 4;
13656 case 2: /* VLD3 / VST3. */
13657 constraint (inst.operands[1].immisalign,
13658 _("can't use alignment with this instruction"));
13661 case 3: /* VLD4 / VST4. */
13662 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13663 16, 64, 32, 64, 32, 128, -1);
13664 if (align_good == FAIL)
13668 unsigned alignbits = 0;
13671 case 8: alignbits = 0x1; break;
13672 case 16: alignbits = 0x1; break;
13673 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
13676 inst.instruction |= alignbits << 4;
13683 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13684 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13685 inst.instruction |= 1 << (4 + logsize);
13687 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
13688 inst.instruction |= logsize << 10;
13691 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13694 do_neon_ld_dup (void)
13696 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13697 int align_good, do_align = 0;
13699 if (et.type == NT_invtype)
13702 switch ((inst.instruction >> 8) & 3)
13704 case 0: /* VLD1. */
13705 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
13706 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13707 &do_align, 16, 16, 32, 32, -1);
13708 if (align_good == FAIL)
13710 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
13713 case 2: inst.instruction |= 1 << 5; break;
13714 default: first_error (_("bad list length")); return;
13716 inst.instruction |= neon_logbits (et.size) << 6;
13719 case 1: /* VLD2. */
13720 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13721 &do_align, 8, 16, 16, 32, 32, 64, -1);
13722 if (align_good == FAIL)
13724 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
13725 _("bad list length"));
13726 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13727 inst.instruction |= 1 << 5;
13728 inst.instruction |= neon_logbits (et.size) << 6;
13731 case 2: /* VLD3. */
13732 constraint (inst.operands[1].immisalign,
13733 _("can't use alignment with this instruction"));
13734 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
13735 _("bad list length"));
13736 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13737 inst.instruction |= 1 << 5;
13738 inst.instruction |= neon_logbits (et.size) << 6;
13741 case 3: /* VLD4. */
13743 int align = inst.operands[1].imm >> 8;
13744 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13745 16, 64, 32, 64, 32, 128, -1);
13746 if (align_good == FAIL)
13748 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
13749 _("bad list length"));
13750 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13751 inst.instruction |= 1 << 5;
13752 if (et.size == 32 && align == 128)
13753 inst.instruction |= 0x3 << 6;
13755 inst.instruction |= neon_logbits (et.size) << 6;
13762 inst.instruction |= do_align << 4;
13765 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13766 apart from bits [11:4]. */
13769 do_neon_ldx_stx (void)
13771 switch (NEON_LANE (inst.operands[0].imm))
13773 case NEON_INTERLEAVE_LANES:
13774 inst.instruction = NEON_ENC_INTERLV (inst.instruction);
13775 do_neon_ld_st_interleave ();
13778 case NEON_ALL_LANES:
13779 inst.instruction = NEON_ENC_DUP (inst.instruction);
13784 inst.instruction = NEON_ENC_LANE (inst.instruction);
13785 do_neon_ld_st_lane ();
13788 /* L bit comes from bit mask. */
13789 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13790 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13791 inst.instruction |= inst.operands[1].reg << 16;
13793 if (inst.operands[1].postind)
13795 int postreg = inst.operands[1].imm & 0xf;
13796 constraint (!inst.operands[1].immisreg,
13797 _("post-index must be a register"));
13798 constraint (postreg == 0xd || postreg == 0xf,
13799 _("bad register for post-index"));
13800 inst.instruction |= postreg;
13802 else if (inst.operands[1].writeback)
13804 inst.instruction |= 0xd;
13807 inst.instruction |= 0xf;
13810 inst.instruction |= 0xf9000000;
13812 inst.instruction |= 0xf4000000;
13816 /* Overall per-instruction processing. */
13818 /* We need to be able to fix up arbitrary expressions in some statements.
13819 This is so that we can handle symbols that are an arbitrary distance from
13820 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13821 which returns part of an address in a form which will be valid for
13822 a data instruction. We do this by pushing the expression into a symbol
13823 in the expr_section, and creating a fix for that. */
13826 fix_new_arm (fragS * frag,
13841 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
13845 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
13850 /* Mark whether the fix is to a THUMB instruction, or an ARM
13852 new_fix->tc_fix_data = thumb_mode;
13855 /* Create a frg for an instruction requiring relaxation. */
13857 output_relax_insn (void)
13863 /* The size of the instruction is unknown, so tie the debug info to the
13864 start of the instruction. */
13865 dwarf2_emit_insn (0);
13867 switch (inst.reloc.exp.X_op)
13870 sym = inst.reloc.exp.X_add_symbol;
13871 offset = inst.reloc.exp.X_add_number;
13875 offset = inst.reloc.exp.X_add_number;
13878 sym = make_expr_symbol (&inst.reloc.exp);
13882 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
13883 inst.relax, sym, offset, NULL/*offset, opcode*/);
13884 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
13887 /* Write a 32-bit thumb instruction to buf. */
13889 put_thumb32_insn (char * buf, unsigned long insn)
13891 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
13892 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
13896 output_inst (const char * str)
13902 as_bad ("%s -- `%s'", inst.error, str);
13906 output_relax_insn();
13909 if (inst.size == 0)
13912 to = frag_more (inst.size);
13914 if (thumb_mode && (inst.size > THUMB_SIZE))
13916 assert (inst.size == (2 * THUMB_SIZE));
13917 put_thumb32_insn (to, inst.instruction);
13919 else if (inst.size > INSN_SIZE)
13921 assert (inst.size == (2 * INSN_SIZE));
13922 md_number_to_chars (to, inst.instruction, INSN_SIZE);
13923 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
13926 md_number_to_chars (to, inst.instruction, inst.size);
13928 if (inst.reloc.type != BFD_RELOC_UNUSED)
13929 fix_new_arm (frag_now, to - frag_now->fr_literal,
13930 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
13933 dwarf2_emit_insn (inst.size);
13936 /* Tag values used in struct asm_opcode's tag field. */
13939 OT_unconditional, /* Instruction cannot be conditionalized.
13940 The ARM condition field is still 0xE. */
13941 OT_unconditionalF, /* Instruction cannot be conditionalized
13942 and carries 0xF in its ARM condition field. */
13943 OT_csuffix, /* Instruction takes a conditional suffix. */
13944 OT_csuffixF, /* Some forms of the instruction take a conditional
13945 suffix, others place 0xF where the condition field
13947 OT_cinfix3, /* Instruction takes a conditional infix,
13948 beginning at character index 3. (In
13949 unified mode, it becomes a suffix.) */
13950 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
13951 tsts, cmps, cmns, and teqs. */
13952 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
13953 character index 3, even in unified mode. Used for
13954 legacy instructions where suffix and infix forms
13955 may be ambiguous. */
13956 OT_csuf_or_in3, /* Instruction takes either a conditional
13957 suffix or an infix at character index 3. */
13958 OT_odd_infix_unc, /* This is the unconditional variant of an
13959 instruction that takes a conditional infix
13960 at an unusual position. In unified mode,
13961 this variant will accept a suffix. */
13962 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
13963 are the conditional variants of instructions that
13964 take conditional infixes in unusual positions.
13965 The infix appears at character index
13966 (tag - OT_odd_infix_0). These are not accepted
13967 in unified mode. */
13970 /* Subroutine of md_assemble, responsible for looking up the primary
13971 opcode from the mnemonic the user wrote. STR points to the
13972 beginning of the mnemonic.
13974 This is not simply a hash table lookup, because of conditional
13975 variants. Most instructions have conditional variants, which are
13976 expressed with a _conditional affix_ to the mnemonic. If we were
13977 to encode each conditional variant as a literal string in the opcode
13978 table, it would have approximately 20,000 entries.
13980 Most mnemonics take this affix as a suffix, and in unified syntax,
13981 'most' is upgraded to 'all'. However, in the divided syntax, some
13982 instructions take the affix as an infix, notably the s-variants of
13983 the arithmetic instructions. Of those instructions, all but six
13984 have the infix appear after the third character of the mnemonic.
13986 Accordingly, the algorithm for looking up primary opcodes given
13989 1. Look up the identifier in the opcode table.
13990 If we find a match, go to step U.
13992 2. Look up the last two characters of the identifier in the
13993 conditions table. If we find a match, look up the first N-2
13994 characters of the identifier in the opcode table. If we
13995 find a match, go to step CE.
13997 3. Look up the fourth and fifth characters of the identifier in
13998 the conditions table. If we find a match, extract those
13999 characters from the identifier, and look up the remaining
14000 characters in the opcode table. If we find a match, go
14005 U. Examine the tag field of the opcode structure, in case this is
14006 one of the six instructions with its conditional infix in an
14007 unusual place. If it is, the tag tells us where to find the
14008 infix; look it up in the conditions table and set inst.cond
14009 accordingly. Otherwise, this is an unconditional instruction.
14010 Again set inst.cond accordingly. Return the opcode structure.
14012 CE. Examine the tag field to make sure this is an instruction that
14013 should receive a conditional suffix. If it is not, fail.
14014 Otherwise, set inst.cond from the suffix we already looked up,
14015 and return the opcode structure.
14017 CM. Examine the tag field to make sure this is an instruction that
14018 should receive a conditional infix after the third character.
14019 If it is not, fail. Otherwise, undo the edits to the current
14020 line of input and proceed as for case CE. */
14022 static const struct asm_opcode *
14023 opcode_lookup (char **str)
14027 const struct asm_opcode *opcode;
14028 const struct asm_cond *cond;
14030 bfd_boolean neon_supported;
14032 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
14034 /* Scan up to the end of the mnemonic, which must end in white space,
14035 '.' (in unified mode, or for Neon instructions), or end of string. */
14036 for (base = end = *str; *end != '\0'; end++)
14037 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
14043 /* Handle a possible width suffix and/or Neon type suffix. */
14048 /* The .w and .n suffixes are only valid if the unified syntax is in
14050 if (unified_syntax && end[1] == 'w')
14052 else if (unified_syntax && end[1] == 'n')
14057 inst.vectype.elems = 0;
14059 *str = end + offset;
14061 if (end[offset] == '.')
14063 /* See if we have a Neon type suffix (possible in either unified or
14064 non-unified ARM syntax mode). */
14065 if (parse_neon_type (&inst.vectype, str) == FAIL)
14068 else if (end[offset] != '\0' && end[offset] != ' ')
14074 /* Look for unaffixed or special-case affixed mnemonic. */
14075 opcode = hash_find_n (arm_ops_hsh, base, end - base);
14079 if (opcode->tag < OT_odd_infix_0)
14081 inst.cond = COND_ALWAYS;
14085 if (unified_syntax)
14086 as_warn (_("conditional infixes are deprecated in unified syntax"));
14087 affix = base + (opcode->tag - OT_odd_infix_0);
14088 cond = hash_find_n (arm_cond_hsh, affix, 2);
14091 inst.cond = cond->value;
14095 /* Cannot have a conditional suffix on a mnemonic of less than two
14097 if (end - base < 3)
14100 /* Look for suffixed mnemonic. */
14102 cond = hash_find_n (arm_cond_hsh, affix, 2);
14103 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
14104 if (opcode && cond)
14107 switch (opcode->tag)
14109 case OT_cinfix3_legacy:
14110 /* Ignore conditional suffixes matched on infix only mnemonics. */
14114 case OT_cinfix3_deprecated:
14115 case OT_odd_infix_unc:
14116 if (!unified_syntax)
14118 /* else fall through */
14122 case OT_csuf_or_in3:
14123 inst.cond = cond->value;
14126 case OT_unconditional:
14127 case OT_unconditionalF:
14130 inst.cond = cond->value;
14134 /* delayed diagnostic */
14135 inst.error = BAD_COND;
14136 inst.cond = COND_ALWAYS;
14145 /* Cannot have a usual-position infix on a mnemonic of less than
14146 six characters (five would be a suffix). */
14147 if (end - base < 6)
14150 /* Look for infixed mnemonic in the usual position. */
14152 cond = hash_find_n (arm_cond_hsh, affix, 2);
14156 memcpy (save, affix, 2);
14157 memmove (affix, affix + 2, (end - affix) - 2);
14158 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
14159 memmove (affix + 2, affix, (end - affix) - 2);
14160 memcpy (affix, save, 2);
14163 && (opcode->tag == OT_cinfix3
14164 || opcode->tag == OT_cinfix3_deprecated
14165 || opcode->tag == OT_csuf_or_in3
14166 || opcode->tag == OT_cinfix3_legacy))
14170 && (opcode->tag == OT_cinfix3
14171 || opcode->tag == OT_cinfix3_deprecated))
14172 as_warn (_("conditional infixes are deprecated in unified syntax"));
14174 inst.cond = cond->value;
14182 md_assemble (char *str)
14185 const struct asm_opcode * opcode;
14187 /* Align the previous label if needed. */
14188 if (last_label_seen != NULL)
14190 symbol_set_frag (last_label_seen, frag_now);
14191 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
14192 S_SET_SEGMENT (last_label_seen, now_seg);
14195 memset (&inst, '\0', sizeof (inst));
14196 inst.reloc.type = BFD_RELOC_UNUSED;
14198 opcode = opcode_lookup (&p);
14201 /* It wasn't an instruction, but it might be a register alias of
14202 the form alias .req reg, or a Neon .dn/.qn directive. */
14203 if (!create_register_alias (str, p)
14204 && !create_neon_reg_alias (str, p))
14205 as_bad (_("bad instruction `%s'"), str);
14210 if (opcode->tag == OT_cinfix3_deprecated)
14211 as_warn (_("s suffix on comparison instruction is deprecated"));
14213 /* The value which unconditional instructions should have in place of the
14214 condition field. */
14215 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
14219 arm_feature_set variant;
14221 variant = cpu_variant;
14222 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14223 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
14224 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
14225 /* Check that this instruction is supported for this CPU. */
14226 if (!opcode->tvariant
14227 || (thumb_mode == 1
14228 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
14230 as_bad (_("selected processor does not support `%s'"), str);
14233 if (inst.cond != COND_ALWAYS && !unified_syntax
14234 && opcode->tencode != do_t_branch)
14236 as_bad (_("Thumb does not support conditional execution"));
14240 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
14242 /* Implicit require narrow instructions on Thumb-1. This avoids
14243 relaxation accidentally introducing Thumb-2 instructions. */
14244 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
14248 /* Check conditional suffixes. */
14249 if (current_it_mask)
14252 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
14253 current_it_mask <<= 1;
14254 current_it_mask &= 0x1f;
14255 /* The BKPT instruction is unconditional even in an IT block. */
14257 && cond != inst.cond && opcode->tencode != do_t_bkpt)
14259 as_bad (_("incorrect condition in IT block"));
14263 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
14265 as_bad (_("thumb conditional instrunction not in IT block"));
14269 mapping_state (MAP_THUMB);
14270 inst.instruction = opcode->tvalue;
14272 if (!parse_operands (p, opcode->operands))
14273 opcode->tencode ();
14275 /* Clear current_it_mask at the end of an IT block. */
14276 if (current_it_mask == 0x10)
14277 current_it_mask = 0;
14279 if (!(inst.error || inst.relax))
14281 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
14282 inst.size = (inst.instruction > 0xffff ? 4 : 2);
14283 if (inst.size_req && inst.size_req != inst.size)
14285 as_bad (_("cannot honor width suffix -- `%s'"), str);
14290 /* Something has gone badly wrong if we try to relax a fixed size
14292 assert (inst.size_req == 0 || !inst.relax);
14294 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14295 *opcode->tvariant);
14296 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14297 set those bits when Thumb-2 32-bit instructions are seen. ie.
14298 anything other than bl/blx.
14299 This is overly pessimistic for relaxable instructions. */
14300 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
14302 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14305 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
14307 /* Check that this instruction is supported for this CPU. */
14308 if (!opcode->avariant ||
14309 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
14311 as_bad (_("selected processor does not support `%s'"), str);
14316 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
14320 mapping_state (MAP_ARM);
14321 inst.instruction = opcode->avalue;
14322 if (opcode->tag == OT_unconditionalF)
14323 inst.instruction |= 0xF << 28;
14325 inst.instruction |= inst.cond << 28;
14326 inst.size = INSN_SIZE;
14327 if (!parse_operands (p, opcode->operands))
14328 opcode->aencode ();
14329 /* Arm mode bx is marked as both v4T and v5 because it's still required
14330 on a hypothetical non-thumb v5 core. */
14331 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
14332 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
14333 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
14335 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
14336 *opcode->avariant);
14340 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14347 /* Various frobbings of labels and their addresses. */
14350 arm_start_line_hook (void)
14352 last_label_seen = NULL;
14356 arm_frob_label (symbolS * sym)
14358 last_label_seen = sym;
14360 ARM_SET_THUMB (sym, thumb_mode);
14362 #if defined OBJ_COFF || defined OBJ_ELF
14363 ARM_SET_INTERWORK (sym, support_interwork);
14366 /* Note - do not allow local symbols (.Lxxx) to be labeled
14367 as Thumb functions. This is because these labels, whilst
14368 they exist inside Thumb code, are not the entry points for
14369 possible ARM->Thumb calls. Also, these labels can be used
14370 as part of a computed goto or switch statement. eg gcc
14371 can generate code that looks like this:
14373 ldr r2, [pc, .Laaa]
14383 The first instruction loads the address of the jump table.
14384 The second instruction converts a table index into a byte offset.
14385 The third instruction gets the jump address out of the table.
14386 The fourth instruction performs the jump.
14388 If the address stored at .Laaa is that of a symbol which has the
14389 Thumb_Func bit set, then the linker will arrange for this address
14390 to have the bottom bit set, which in turn would mean that the
14391 address computation performed by the third instruction would end
14392 up with the bottom bit set. Since the ARM is capable of unaligned
14393 word loads, the instruction would then load the incorrect address
14394 out of the jump table, and chaos would ensue. */
14395 if (label_is_thumb_function_name
14396 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
14397 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
14399 /* When the address of a Thumb function is taken the bottom
14400 bit of that address should be set. This will allow
14401 interworking between Arm and Thumb functions to work
14404 THUMB_SET_FUNC (sym, 1);
14406 label_is_thumb_function_name = FALSE;
14409 dwarf2_emit_label (sym);
14413 arm_data_in_code (void)
14415 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
14417 *input_line_pointer = '/';
14418 input_line_pointer += 5;
14419 *input_line_pointer = 0;
14427 arm_canonicalize_symbol_name (char * name)
14431 if (thumb_mode && (len = strlen (name)) > 5
14432 && streq (name + len - 5, "/data"))
14433 *(name + len - 5) = 0;
14438 /* Table of all register names defined by default. The user can
14439 define additional names with .req. Note that all register names
14440 should appear in both upper and lowercase variants. Some registers
14441 also have mixed-case names. */
14443 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14444 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14445 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14446 #define REGSET(p,t) \
14447 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14448 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14449 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14450 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14451 #define REGSETH(p,t) \
14452 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14453 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14454 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14455 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14456 #define REGSET2(p,t) \
14457 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14458 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14459 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14460 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14462 static const struct reg_entry reg_names[] =
14464 /* ARM integer registers. */
14465 REGSET(r, RN), REGSET(R, RN),
14467 /* ATPCS synonyms. */
14468 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
14469 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
14470 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
14472 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
14473 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
14474 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
14476 /* Well-known aliases. */
14477 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
14478 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
14480 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
14481 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
14483 /* Coprocessor numbers. */
14484 REGSET(p, CP), REGSET(P, CP),
14486 /* Coprocessor register numbers. The "cr" variants are for backward
14488 REGSET(c, CN), REGSET(C, CN),
14489 REGSET(cr, CN), REGSET(CR, CN),
14491 /* FPA registers. */
14492 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
14493 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
14495 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
14496 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
14498 /* VFP SP registers. */
14499 REGSET(s,VFS), REGSET(S,VFS),
14500 REGSETH(s,VFS), REGSETH(S,VFS),
14502 /* VFP DP Registers. */
14503 REGSET(d,VFD), REGSET(D,VFD),
14504 /* Extra Neon DP registers. */
14505 REGSETH(d,VFD), REGSETH(D,VFD),
14507 /* Neon QP registers. */
14508 REGSET2(q,NQ), REGSET2(Q,NQ),
14510 /* VFP control registers. */
14511 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
14512 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
14513 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
14514 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
14515 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
14516 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
14518 /* Maverick DSP coprocessor registers. */
14519 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
14520 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
14522 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
14523 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
14524 REGDEF(dspsc,0,DSPSC),
14526 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
14527 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
14528 REGDEF(DSPSC,0,DSPSC),
14530 /* iWMMXt data registers - p0, c0-15. */
14531 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
14533 /* iWMMXt control registers - p1, c0-3. */
14534 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
14535 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
14536 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
14537 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
14539 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14540 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
14541 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
14542 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
14543 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
14545 /* XScale accumulator registers. */
14546 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
14552 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14553 within psr_required_here. */
14554 static const struct asm_psr psrs[] =
14556 /* Backward compatibility notation. Note that "all" is no longer
14557 truly all possible PSR bits. */
14558 {"all", PSR_c | PSR_f},
14562 /* Individual flags. */
14567 /* Combinations of flags. */
14568 {"fs", PSR_f | PSR_s},
14569 {"fx", PSR_f | PSR_x},
14570 {"fc", PSR_f | PSR_c},
14571 {"sf", PSR_s | PSR_f},
14572 {"sx", PSR_s | PSR_x},
14573 {"sc", PSR_s | PSR_c},
14574 {"xf", PSR_x | PSR_f},
14575 {"xs", PSR_x | PSR_s},
14576 {"xc", PSR_x | PSR_c},
14577 {"cf", PSR_c | PSR_f},
14578 {"cs", PSR_c | PSR_s},
14579 {"cx", PSR_c | PSR_x},
14580 {"fsx", PSR_f | PSR_s | PSR_x},
14581 {"fsc", PSR_f | PSR_s | PSR_c},
14582 {"fxs", PSR_f | PSR_x | PSR_s},
14583 {"fxc", PSR_f | PSR_x | PSR_c},
14584 {"fcs", PSR_f | PSR_c | PSR_s},
14585 {"fcx", PSR_f | PSR_c | PSR_x},
14586 {"sfx", PSR_s | PSR_f | PSR_x},
14587 {"sfc", PSR_s | PSR_f | PSR_c},
14588 {"sxf", PSR_s | PSR_x | PSR_f},
14589 {"sxc", PSR_s | PSR_x | PSR_c},
14590 {"scf", PSR_s | PSR_c | PSR_f},
14591 {"scx", PSR_s | PSR_c | PSR_x},
14592 {"xfs", PSR_x | PSR_f | PSR_s},
14593 {"xfc", PSR_x | PSR_f | PSR_c},
14594 {"xsf", PSR_x | PSR_s | PSR_f},
14595 {"xsc", PSR_x | PSR_s | PSR_c},
14596 {"xcf", PSR_x | PSR_c | PSR_f},
14597 {"xcs", PSR_x | PSR_c | PSR_s},
14598 {"cfs", PSR_c | PSR_f | PSR_s},
14599 {"cfx", PSR_c | PSR_f | PSR_x},
14600 {"csf", PSR_c | PSR_s | PSR_f},
14601 {"csx", PSR_c | PSR_s | PSR_x},
14602 {"cxf", PSR_c | PSR_x | PSR_f},
14603 {"cxs", PSR_c | PSR_x | PSR_s},
14604 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
14605 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
14606 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
14607 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
14608 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
14609 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
14610 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
14611 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
14612 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
14613 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
14614 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
14615 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
14616 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
14617 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
14618 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
14619 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
14620 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
14621 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
14622 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
14623 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
14624 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
14625 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
14626 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
14627 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
14630 /* Table of V7M psr names. */
14631 static const struct asm_psr v7m_psrs[] =
14633 {"apsr", 0 }, {"APSR", 0 },
14634 {"iapsr", 1 }, {"IAPSR", 1 },
14635 {"eapsr", 2 }, {"EAPSR", 2 },
14636 {"psr", 3 }, {"PSR", 3 },
14637 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14638 {"ipsr", 5 }, {"IPSR", 5 },
14639 {"epsr", 6 }, {"EPSR", 6 },
14640 {"iepsr", 7 }, {"IEPSR", 7 },
14641 {"msp", 8 }, {"MSP", 8 },
14642 {"psp", 9 }, {"PSP", 9 },
14643 {"primask", 16}, {"PRIMASK", 16},
14644 {"basepri", 17}, {"BASEPRI", 17},
14645 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14646 {"faultmask", 19}, {"FAULTMASK", 19},
14647 {"control", 20}, {"CONTROL", 20}
14650 /* Table of all shift-in-operand names. */
14651 static const struct asm_shift_name shift_names [] =
14653 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
14654 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
14655 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
14656 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
14657 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
14658 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
14661 /* Table of all explicit relocation names. */
14663 static struct reloc_entry reloc_names[] =
14665 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
14666 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
14667 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
14668 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
14669 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
14670 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
14671 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
14672 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
14673 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
14674 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
14675 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
14679 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14680 static const struct asm_cond conds[] =
14684 {"cs", 0x2}, {"hs", 0x2},
14685 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14699 static struct asm_barrier_opt barrier_opt_names[] =
14707 /* Table of ARM-format instructions. */
14709 /* Macros for gluing together operand strings. N.B. In all cases
14710 other than OPS0, the trailing OP_stop comes from default
14711 zero-initialization of the unspecified elements of the array. */
14712 #define OPS0() { OP_stop, }
14713 #define OPS1(a) { OP_##a, }
14714 #define OPS2(a,b) { OP_##a,OP_##b, }
14715 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14716 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14717 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14718 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14720 /* These macros abstract out the exact format of the mnemonic table and
14721 save some repeated characters. */
14723 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14724 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14725 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14726 THUMB_VARIANT, do_##ae, do_##te }
14728 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14729 a T_MNEM_xyz enumerator. */
14730 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14731 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14732 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14733 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14735 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14736 infix after the third character. */
14737 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14738 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14739 THUMB_VARIANT, do_##ae, do_##te }
14740 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14741 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14742 THUMB_VARIANT, do_##ae, do_##te }
14743 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14744 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14745 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14746 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14747 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14748 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14749 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14750 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14752 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14753 appear in the condition table. */
14754 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14755 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14756 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14758 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14759 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14760 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14761 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14762 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14763 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14764 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14765 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14766 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14767 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14768 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14769 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14770 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14771 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14772 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14773 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14774 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14775 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14776 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14777 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14779 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14780 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14781 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14782 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14784 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14785 field is still 0xE. Many of the Thumb variants can be executed
14786 conditionally, so this is checked separately. */
14787 #define TUE(mnem, op, top, nops, ops, ae, te) \
14788 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14789 THUMB_VARIANT, do_##ae, do_##te }
14791 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14792 condition code field. */
14793 #define TUF(mnem, op, top, nops, ops, ae, te) \
14794 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14795 THUMB_VARIANT, do_##ae, do_##te }
14797 /* ARM-only variants of all the above. */
14798 #define CE(mnem, op, nops, ops, ae) \
14799 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14801 #define C3(mnem, op, nops, ops, ae) \
14802 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14804 /* Legacy mnemonics that always have conditional infix after the third
14806 #define CL(mnem, op, nops, ops, ae) \
14807 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14808 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14810 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14811 #define cCE(mnem, op, nops, ops, ae) \
14812 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14814 /* Legacy coprocessor instructions where conditional infix and conditional
14815 suffix are ambiguous. For consistency this includes all FPA instructions,
14816 not just the potentially ambiguous ones. */
14817 #define cCL(mnem, op, nops, ops, ae) \
14818 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14819 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14821 /* Coprocessor, takes either a suffix or a position-3 infix
14822 (for an FPA corner case). */
14823 #define C3E(mnem, op, nops, ops, ae) \
14824 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14825 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14827 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14828 { #m1 #m2 #m3, OPS##nops ops, \
14829 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14830 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14832 #define CM(m1, m2, op, nops, ops, ae) \
14833 xCM_(m1, , m2, op, nops, ops, ae), \
14834 xCM_(m1, eq, m2, op, nops, ops, ae), \
14835 xCM_(m1, ne, m2, op, nops, ops, ae), \
14836 xCM_(m1, cs, m2, op, nops, ops, ae), \
14837 xCM_(m1, hs, m2, op, nops, ops, ae), \
14838 xCM_(m1, cc, m2, op, nops, ops, ae), \
14839 xCM_(m1, ul, m2, op, nops, ops, ae), \
14840 xCM_(m1, lo, m2, op, nops, ops, ae), \
14841 xCM_(m1, mi, m2, op, nops, ops, ae), \
14842 xCM_(m1, pl, m2, op, nops, ops, ae), \
14843 xCM_(m1, vs, m2, op, nops, ops, ae), \
14844 xCM_(m1, vc, m2, op, nops, ops, ae), \
14845 xCM_(m1, hi, m2, op, nops, ops, ae), \
14846 xCM_(m1, ls, m2, op, nops, ops, ae), \
14847 xCM_(m1, ge, m2, op, nops, ops, ae), \
14848 xCM_(m1, lt, m2, op, nops, ops, ae), \
14849 xCM_(m1, gt, m2, op, nops, ops, ae), \
14850 xCM_(m1, le, m2, op, nops, ops, ae), \
14851 xCM_(m1, al, m2, op, nops, ops, ae)
14853 #define UE(mnem, op, nops, ops, ae) \
14854 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14856 #define UF(mnem, op, nops, ops, ae) \
14857 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14859 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14860 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14861 use the same encoding function for each. */
14862 #define NUF(mnem, op, nops, ops, enc) \
14863 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14864 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14866 /* Neon data processing, version which indirects through neon_enc_tab for
14867 the various overloaded versions of opcodes. */
14868 #define nUF(mnem, op, nops, ops, enc) \
14869 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14870 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14872 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14874 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14875 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14876 THUMB_VARIANT, do_##enc, do_##enc }
14878 #define NCE(mnem, op, nops, ops, enc) \
14879 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14881 #define NCEF(mnem, op, nops, ops, enc) \
14882 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14884 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14885 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14886 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14887 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14889 #define nCE(mnem, op, nops, ops, enc) \
14890 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14892 #define nCEF(mnem, op, nops, ops, enc) \
14893 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14897 /* Thumb-only, unconditional. */
14898 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14900 static const struct asm_opcode insns[] =
14902 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14903 #define THUMB_VARIANT &arm_ext_v4t
14904 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
14905 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
14906 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
14907 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
14908 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
14909 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
14910 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub),
14911 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub),
14912 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
14913 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
14914 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
14915 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
14916 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
14917 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
14918 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
14919 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
14921 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14922 for setting PSR flag bits. They are obsolete in V6 and do not
14923 have Thumb equivalents. */
14924 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14925 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14926 CL(tstp, 110f000, 2, (RR, SH), cmp),
14927 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14928 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14929 CL(cmpp, 150f000, 2, (RR, SH), cmp),
14930 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14931 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14932 CL(cmnp, 170f000, 2, (RR, SH), cmp),
14934 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
14935 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
14936 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
14937 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
14939 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
14940 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14941 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst),
14942 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14944 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14945 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14946 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14947 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14948 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14949 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14951 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
14952 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi),
14953 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
14954 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
14957 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
14958 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
14959 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
14961 /* Thumb-compatibility pseudo ops. */
14962 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
14963 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
14964 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
14965 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
14966 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
14967 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
14968 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
14969 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
14970 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
14971 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
14972 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
14973 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
14975 /* These may simplify to neg. */
14976 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
14977 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
14979 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14980 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14982 #undef THUMB_VARIANT
14983 #define THUMB_VARIANT &arm_ext_v6
14984 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
14986 /* V1 instructions with no Thumb analogue prior to V6T2. */
14987 #undef THUMB_VARIANT
14988 #define THUMB_VARIANT &arm_ext_v6t2
14989 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14990 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14991 CL(teqp, 130f000, 2, (RR, SH), cmp),
14993 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
14994 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt),
14995 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
14996 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt),
14998 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14999 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15001 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15002 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
15004 /* V1 instructions with no Thumb analogue at all. */
15005 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
15006 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
15008 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
15009 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
15010 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
15011 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
15012 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
15013 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
15014 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
15015 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
15018 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15019 #undef THUMB_VARIANT
15020 #define THUMB_VARIANT &arm_ext_v4t
15021 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
15022 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
15024 #undef THUMB_VARIANT
15025 #define THUMB_VARIANT &arm_ext_v6t2
15026 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15027 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
15029 /* Generic coprocessor instructions. */
15030 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
15031 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15032 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15033 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15034 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15035 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15036 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
15039 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15040 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15041 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15044 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15045 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
15046 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
15049 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15050 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15051 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15052 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15053 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15054 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15055 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15056 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15057 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15060 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15061 #undef THUMB_VARIANT
15062 #define THUMB_VARIANT &arm_ext_v4t
15063 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15064 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15065 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15066 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15067 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15068 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15071 #define ARM_VARIANT &arm_ext_v4t_5
15072 /* ARM Architecture 4T. */
15073 /* Note: bx (and blx) are required on V5, even if the processor does
15074 not support Thumb. */
15075 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
15078 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15079 #undef THUMB_VARIANT
15080 #define THUMB_VARIANT &arm_ext_v5t
15081 /* Note: blx has 2 variants; the .value coded here is for
15082 BLX(2). Only this variant has conditional execution. */
15083 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
15084 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
15086 #undef THUMB_VARIANT
15087 #define THUMB_VARIANT &arm_ext_v6t2
15088 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
15089 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15090 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15091 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15092 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15093 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
15094 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15095 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
15098 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15099 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15100 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15101 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15102 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15104 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15105 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15107 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15108 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15109 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15110 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15112 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15113 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15114 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15115 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15117 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15118 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15120 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15121 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15122 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15123 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15126 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15127 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
15128 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15129 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15131 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15132 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15135 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15136 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
15139 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15140 #undef THUMB_VARIANT
15141 #define THUMB_VARIANT &arm_ext_v6
15142 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
15143 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
15144 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15145 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15146 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15147 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15148 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15149 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15150 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15151 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
15153 #undef THUMB_VARIANT
15154 #define THUMB_VARIANT &arm_ext_v6t2
15155 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
15156 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
15157 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15158 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15160 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
15161 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
15163 /* ARM V6 not included in V7M (eg. integer SIMD). */
15164 #undef THUMB_VARIANT
15165 #define THUMB_VARIANT &arm_ext_v6_notm
15166 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps),
15167 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
15168 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
15169 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15170 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15171 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15172 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15173 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15174 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15175 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15176 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15177 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15178 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15179 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15180 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15181 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15182 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15183 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15184 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15185 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15186 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15187 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15188 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15189 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15190 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15191 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15192 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15193 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15194 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15195 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15196 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15197 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15198 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15199 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15200 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15201 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15202 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15203 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15204 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15205 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15206 UF(rfeib, 9900a00, 1, (RRw), rfe),
15207 UF(rfeda, 8100a00, 1, (RRw), rfe),
15208 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15209 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15210 UF(rfefa, 9900a00, 1, (RRw), rfe),
15211 UF(rfeea, 8100a00, 1, (RRw), rfe),
15212 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15213 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15214 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15215 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15216 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15217 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15218 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15219 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15220 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15221 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15222 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15223 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15224 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15225 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15226 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15227 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15228 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15229 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15230 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15231 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15232 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15233 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15234 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15235 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15236 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15237 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15238 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15239 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15240 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
15241 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
15242 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
15243 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
15244 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
15245 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
15246 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15247 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15248 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
15251 #define ARM_VARIANT &arm_ext_v6k
15252 #undef THUMB_VARIANT
15253 #define THUMB_VARIANT &arm_ext_v6k
15254 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
15255 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
15256 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
15257 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
15259 #undef THUMB_VARIANT
15260 #define THUMB_VARIANT &arm_ext_v6_notm
15261 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
15262 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
15264 #undef THUMB_VARIANT
15265 #define THUMB_VARIANT &arm_ext_v6t2
15266 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15267 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15268 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15269 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15270 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
15273 #define ARM_VARIANT &arm_ext_v6z
15274 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
15277 #define ARM_VARIANT &arm_ext_v6t2
15278 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
15279 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
15280 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15281 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15283 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15284 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
15285 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
15286 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
15288 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15289 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15290 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15291 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15293 UT(cbnz, b900, 2, (RR, EXP), t_cbz),
15294 UT(cbz, b100, 2, (RR, EXP), t_cbz),
15295 /* ARM does not really have an IT instruction, so always allow it. */
15297 #define ARM_VARIANT &arm_ext_v1
15298 TUE(it, 0, bf08, 1, (COND), it, t_it),
15299 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
15300 TUE(ite, 0, bf04, 1, (COND), it, t_it),
15301 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
15302 TUE(itet, 0, bf06, 1, (COND), it, t_it),
15303 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
15304 TUE(itee, 0, bf02, 1, (COND), it, t_it),
15305 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
15306 TUE(itett, 0, bf07, 1, (COND), it, t_it),
15307 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
15308 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
15309 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
15310 TUE(itete, 0, bf05, 1, (COND), it, t_it),
15311 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
15312 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
15314 /* Thumb2 only instructions. */
15316 #define ARM_VARIANT NULL
15318 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15319 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15320 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
15321 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
15323 /* Thumb-2 hardware division instructions (R and M profiles only). */
15324 #undef THUMB_VARIANT
15325 #define THUMB_VARIANT &arm_ext_div
15326 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
15327 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
15329 /* ARM V7 instructions. */
15331 #define ARM_VARIANT &arm_ext_v7
15332 #undef THUMB_VARIANT
15333 #define THUMB_VARIANT &arm_ext_v7
15334 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
15335 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
15336 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
15337 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
15338 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
15341 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15342 cCE(wfs, e200110, 1, (RR), rd),
15343 cCE(rfs, e300110, 1, (RR), rd),
15344 cCE(wfc, e400110, 1, (RR), rd),
15345 cCE(rfc, e500110, 1, (RR), rd),
15347 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
15348 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
15349 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
15350 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
15352 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
15353 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
15354 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
15355 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
15357 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
15358 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
15359 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
15360 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
15361 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
15362 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
15363 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
15364 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
15365 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
15366 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
15367 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
15368 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
15370 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
15371 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
15372 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
15373 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
15374 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
15375 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
15376 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
15377 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
15378 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
15379 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
15380 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
15381 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
15383 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
15384 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
15385 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
15386 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
15387 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
15388 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
15389 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
15390 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
15391 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
15392 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
15393 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
15394 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
15396 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
15397 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
15398 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
15399 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
15400 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
15401 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
15402 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
15403 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
15404 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
15405 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
15406 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
15407 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
15409 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
15410 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
15411 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
15412 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
15413 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
15414 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
15415 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
15416 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
15417 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
15418 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
15419 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
15420 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
15422 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
15423 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
15424 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
15425 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
15426 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
15427 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
15428 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
15429 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
15430 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
15431 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
15432 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
15433 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
15435 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
15436 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
15437 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
15438 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
15439 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
15440 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
15441 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
15442 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
15443 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
15444 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
15445 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
15446 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
15448 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
15449 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
15450 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
15451 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
15452 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
15453 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
15454 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
15455 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
15456 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
15457 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
15458 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
15459 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
15461 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
15462 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
15463 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
15464 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
15465 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
15466 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
15467 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
15468 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
15469 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
15470 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
15471 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
15472 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
15474 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
15475 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
15476 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
15477 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
15478 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
15479 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
15480 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
15481 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
15482 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
15483 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
15484 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
15485 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
15487 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
15488 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
15489 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
15490 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
15491 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
15492 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
15493 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
15494 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
15495 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
15496 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
15497 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
15498 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
15500 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
15501 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
15502 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
15503 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
15504 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
15505 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
15506 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
15507 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
15508 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
15509 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
15510 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
15511 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
15513 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
15514 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
15515 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
15516 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
15517 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
15518 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
15519 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
15520 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
15521 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
15522 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
15523 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
15524 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
15526 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
15527 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
15528 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
15529 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
15530 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
15531 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
15532 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
15533 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
15534 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
15535 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
15536 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
15537 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
15539 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
15540 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
15541 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
15542 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
15543 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
15544 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
15545 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
15546 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
15547 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
15548 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
15549 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
15550 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
15552 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
15553 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
15554 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
15555 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
15556 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
15557 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
15558 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
15559 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
15560 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
15561 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
15562 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
15563 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
15565 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
15566 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
15567 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
15568 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
15569 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
15570 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15571 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15572 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15573 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
15574 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
15575 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
15576 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
15578 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
15579 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
15580 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
15581 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
15582 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
15583 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15584 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15585 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15586 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
15587 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
15588 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
15589 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
15591 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
15592 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
15593 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
15594 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
15595 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
15596 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15597 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15598 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15599 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
15600 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
15601 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
15602 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
15604 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
15605 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
15606 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
15607 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
15608 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
15609 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15610 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15611 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15612 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
15613 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
15614 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
15615 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
15617 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
15618 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
15619 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
15620 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
15621 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
15622 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15623 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15624 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15625 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
15626 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
15627 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
15628 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
15630 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
15631 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
15632 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
15633 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
15634 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
15635 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15636 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15637 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15638 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
15639 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
15640 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
15641 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
15643 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
15644 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
15645 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
15646 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
15647 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
15648 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15649 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15650 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15651 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
15652 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
15653 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
15654 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
15656 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
15657 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
15658 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
15659 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
15660 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
15661 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15662 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15663 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15664 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
15665 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
15666 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
15667 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
15669 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
15670 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
15671 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
15672 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
15673 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
15674 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15675 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15676 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15677 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
15678 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
15679 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
15680 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
15682 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
15683 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
15684 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
15685 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
15686 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
15687 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15688 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15689 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15690 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
15691 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
15692 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
15693 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
15695 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15696 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15697 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15698 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15699 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15700 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15701 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15702 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15703 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15704 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15705 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15706 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15708 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15709 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15710 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15711 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15712 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15713 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15714 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15715 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15716 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15717 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15718 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15719 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15721 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15722 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15723 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15724 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15725 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15726 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15727 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15728 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15729 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15730 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15731 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15732 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15734 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
15735 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
15736 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
15737 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
15739 cCL(flts, e000110, 2, (RF, RR), rn_rd),
15740 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
15741 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
15742 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
15743 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
15744 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
15745 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
15746 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
15747 cCL(flte, e080110, 2, (RF, RR), rn_rd),
15748 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
15749 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
15750 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
15752 /* The implementation of the FIX instruction is broken on some
15753 assemblers, in that it accepts a precision specifier as well as a
15754 rounding specifier, despite the fact that this is meaningless.
15755 To be more compatible, we accept it as well, though of course it
15756 does not set any bits. */
15757 cCE(fix, e100110, 2, (RR, RF), rd_rm),
15758 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
15759 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
15760 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
15761 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
15762 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
15763 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
15764 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
15765 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
15766 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
15767 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
15768 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
15769 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
15771 /* Instructions that were new with the real FPA, call them V2. */
15773 #define ARM_VARIANT &fpu_fpa_ext_v2
15774 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15775 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15776 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15777 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15778 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15779 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15782 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15783 /* Moves and type conversions. */
15784 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
15785 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
15786 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
15787 cCE(fmstat, ef1fa10, 0, (), noargs),
15788 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
15789 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
15790 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
15791 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15792 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
15793 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15794 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
15795 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
15796 cCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vfp_vmrs),
15797 cCE(vmsr, ee00a10, 2, (RVC, RR), vfp_vmsr),
15799 /* Memory operations. */
15800 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15801 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15802 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15803 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15804 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15805 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15806 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15807 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15808 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15809 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15810 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15811 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15812 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15813 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15814 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15815 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15816 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15817 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15819 /* Monadic operations. */
15820 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
15821 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
15822 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
15824 /* Dyadic operations. */
15825 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15826 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15827 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15828 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15829 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15830 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15831 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15832 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15833 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15836 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
15837 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
15838 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
15839 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
15842 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15843 /* Moves and type conversions. */
15844 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15845 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15846 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15847 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
15848 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
15849 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
15850 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
15851 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15852 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
15853 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15854 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15855 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15856 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15858 /* Memory operations. */
15859 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15860 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15861 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15862 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15863 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15864 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15865 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15866 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15867 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15868 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15870 /* Monadic operations. */
15871 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15872 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15873 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15875 /* Dyadic operations. */
15876 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15877 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15878 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15879 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15880 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15881 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15882 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15883 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15884 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15887 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15888 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd),
15889 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15890 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd),
15893 #define ARM_VARIANT &fpu_vfp_ext_v2
15894 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
15895 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
15896 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
15897 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
15899 /* Instructions which may belong to either the Neon or VFP instruction sets.
15900 Individual encoder functions perform additional architecture checks. */
15902 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15903 #undef THUMB_VARIANT
15904 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15905 /* These mnemonics are unique to VFP. */
15906 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
15907 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
15908 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15909 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15910 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15911 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15912 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15913 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
15914 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
15915 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
15917 /* Mnemonics shared by Neon and VFP. */
15918 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
15919 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15920 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15922 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15923 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15925 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15926 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15928 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15929 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15930 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15931 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15932 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15933 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15934 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15935 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15937 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
15939 /* NOTE: All VMOV encoding is special-cased! */
15940 NCE(vmov, 0, 1, (VMOV), neon_mov),
15941 NCE(vmovq, 0, 1, (VMOV), neon_mov),
15943 #undef THUMB_VARIANT
15944 #define THUMB_VARIANT &fpu_neon_ext_v1
15946 #define ARM_VARIANT &fpu_neon_ext_v1
15947 /* Data processing with three registers of the same length. */
15948 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15949 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
15950 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
15951 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15952 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15953 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15954 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15955 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15956 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15957 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15958 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15959 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15960 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15961 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15962 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15963 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15964 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15965 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15966 /* If not immediate, fall back to neon_dyadic_i64_su.
15967 shl_imm should accept I8 I16 I32 I64,
15968 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15969 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
15970 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
15971 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
15972 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
15973 /* Logic ops, types optional & ignored. */
15974 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic),
15975 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic),
15976 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic),
15977 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic),
15978 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic),
15979 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic),
15980 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic),
15981 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic),
15982 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
15983 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
15984 /* Bitfield ops, untyped. */
15985 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15986 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15987 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15988 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15989 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15990 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15991 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15992 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15993 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15994 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15995 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15996 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15997 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15998 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15999 back to neon_dyadic_if_su. */
16000 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
16001 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
16002 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
16003 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
16004 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
16005 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
16006 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
16007 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
16008 /* Comparison. Type I8 I16 I32 F32. */
16009 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
16010 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
16011 /* As above, D registers only. */
16012 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
16013 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
16014 /* Int and float variants, signedness unimportant. */
16015 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
16016 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
16017 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
16018 /* Add/sub take types I8 I16 I32 I64 F32. */
16019 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
16020 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
16021 /* vtst takes sizes 8, 16, 32. */
16022 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
16023 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
16024 /* VMUL takes I8 I16 I32 F32 P8. */
16025 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
16026 /* VQD{R}MULH takes S16 S32. */
16027 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16028 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
16029 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16030 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
16031 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16032 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
16033 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16034 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
16035 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16036 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
16037 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16038 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
16039 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
16040 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
16041 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
16042 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
16044 /* Two address, int/float. Types S8 S16 S32 F32. */
16045 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
16046 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
16048 /* Data processing with two registers and a shift amount. */
16049 /* Right shifts, and variants with rounding.
16050 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16051 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16052 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
16053 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16054 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
16055 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
16056 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
16057 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
16058 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
16059 /* Shift and insert. Sizes accepted 8 16 32 64. */
16060 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
16061 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
16062 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
16063 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
16064 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16065 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
16066 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
16067 /* Right shift immediate, saturating & narrowing, with rounding variants.
16068 Types accepted S16 S32 S64 U16 U32 U64. */
16069 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16070 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16071 /* As above, unsigned. Types accepted S16 S32 S64. */
16072 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16073 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16074 /* Right shift narrowing. Types accepted I16 I32 I64. */
16075 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16076 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16077 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16078 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll),
16079 /* CVT with optional immediate for fixed-point variant. */
16080 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
16082 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn),
16083 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn),
16085 /* Data processing, three registers of different lengths. */
16086 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16087 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
16088 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
16089 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
16090 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
16091 /* If not scalar, fall back to neon_dyadic_long.
16092 Vector types as above, scalar types S16 S32 U16 U32. */
16093 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16094 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16095 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16096 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16097 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16098 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16099 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16100 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16101 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16102 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16103 /* Saturating doubling multiplies. Types S16 S32. */
16104 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16105 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16106 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16107 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16108 S16 S32 U16 U32. */
16109 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
16111 /* Extract. Size 8. */
16112 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
16113 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
16115 /* Two registers, miscellaneous. */
16116 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16117 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
16118 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
16119 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
16120 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
16121 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
16122 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
16123 /* Vector replicate. Sizes 8 16 32. */
16124 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup),
16125 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup),
16126 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16127 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
16128 /* VMOVN. Types I16 I32 I64. */
16129 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn),
16130 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16131 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn),
16132 /* VQMOVUN. Types S16 S32 S64. */
16133 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun),
16134 /* VZIP / VUZP. Sizes 8 16 32. */
16135 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
16136 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
16137 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
16138 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
16139 /* VQABS / VQNEG. Types S8 S16 S32. */
16140 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16141 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
16142 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16143 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
16144 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16145 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
16146 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
16147 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
16148 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
16149 /* Reciprocal estimates. Types U32 F32. */
16150 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
16151 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
16152 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
16153 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
16154 /* VCLS. Types S8 S16 S32. */
16155 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
16156 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
16157 /* VCLZ. Types I8 I16 I32. */
16158 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
16159 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
16160 /* VCNT. Size 8. */
16161 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
16162 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
16163 /* Two address, untyped. */
16164 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
16165 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
16166 /* VTRN. Sizes 8 16 32. */
16167 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn),
16168 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn),
16170 /* Table lookup. Size 8. */
16171 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16172 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16174 #undef THUMB_VARIANT
16175 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16177 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16178 /* Neon element/structure load/store. */
16179 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16180 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16181 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16182 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16183 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16184 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16185 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16186 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16188 #undef THUMB_VARIANT
16189 #define THUMB_VARIANT &fpu_vfp_ext_v3
16191 #define ARM_VARIANT &fpu_vfp_ext_v3
16192 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const),
16193 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const),
16194 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16195 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16196 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16197 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16198 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16199 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16200 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16201 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16202 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16203 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16204 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16205 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16206 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16207 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16208 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16209 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16211 #undef THUMB_VARIANT
16213 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16214 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16215 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16216 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16217 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16218 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16219 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16220 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
16221 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
16224 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16225 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
16226 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
16227 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
16228 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
16229 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
16230 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
16231 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
16232 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
16233 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
16234 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16235 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16236 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16237 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16238 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16239 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16240 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16241 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16242 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16243 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd),
16244 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
16245 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16246 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16247 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16248 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16249 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16250 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16251 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
16252 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
16253 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
16254 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn),
16255 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
16256 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
16257 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
16258 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
16259 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
16260 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
16261 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
16262 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16263 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16264 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16265 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16266 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16267 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16268 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16269 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16270 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16271 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
16272 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16273 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16274 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16275 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16276 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16277 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16278 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16279 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16280 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16281 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16282 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16283 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16284 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16285 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16286 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16287 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16288 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16289 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16290 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16291 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16292 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16293 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16294 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16295 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16296 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16297 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16298 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16299 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16300 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16301 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16302 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16303 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16304 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16305 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16306 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16307 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16308 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16309 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16310 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16311 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16312 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16313 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
16314 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16315 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16316 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16317 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16318 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16319 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16320 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16321 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16322 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16323 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16324 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16325 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16326 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16327 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16328 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16329 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16330 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16331 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16332 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16333 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16334 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16335 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
16336 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16337 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16338 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16339 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16340 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16341 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16342 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16343 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16344 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16345 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16346 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16347 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16348 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16349 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16350 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16351 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16352 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16353 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16354 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16355 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16356 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16357 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16358 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16359 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16360 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16361 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16362 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16363 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16364 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16365 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16366 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16367 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
16368 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
16369 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
16370 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
16371 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
16372 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
16373 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16374 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16375 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16376 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
16377 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
16378 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
16379 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
16380 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
16381 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
16382 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16383 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16384 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16385 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16386 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
16389 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16390 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc),
16391 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc),
16392 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc),
16393 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn),
16394 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn),
16395 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn),
16396 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16397 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16398 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16399 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16400 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16401 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16402 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16403 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16404 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16405 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16406 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16407 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16408 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16409 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16410 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
16411 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16412 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16413 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16414 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16415 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16416 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16417 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16418 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16419 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16420 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16421 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16422 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16423 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16424 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16425 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16426 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16427 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16428 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16429 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16430 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16431 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16432 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16433 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16434 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16435 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16436 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16437 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16438 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16439 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16440 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16441 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16442 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16443 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16444 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16445 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16446 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16449 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16450 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16451 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16452 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16453 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16454 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16455 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16456 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16457 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16458 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
16459 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
16460 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
16461 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
16462 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
16463 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
16464 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
16465 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
16466 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
16467 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
16468 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
16469 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
16470 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
16471 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
16472 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
16473 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
16474 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
16475 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
16476 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
16477 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
16478 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
16479 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
16480 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
16481 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
16482 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
16483 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
16484 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
16485 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
16486 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
16487 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
16488 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
16489 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
16490 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
16491 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
16492 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
16493 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
16494 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
16495 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
16496 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
16497 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
16498 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
16499 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
16500 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
16501 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
16502 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
16503 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
16504 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
16505 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
16506 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
16507 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
16508 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
16509 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
16510 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
16511 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
16512 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
16513 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
16514 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16515 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16516 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16517 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16518 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16519 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16520 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16521 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16522 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16523 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16524 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16525 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16528 #undef THUMB_VARIANT
16555 /* MD interface: bits in the object file. */
16557 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16558 for use in the a.out file, and stores them in the array pointed to by buf.
16559 This knows about the endian-ness of the target machine and does
16560 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16561 2 (short) and 4 (long) Floating numbers are put out as a series of
16562 LITTLENUMS (shorts, here at least). */
16565 md_number_to_chars (char * buf, valueT val, int n)
16567 if (target_big_endian)
16568 number_to_chars_bigendian (buf, val, n);
16570 number_to_chars_littleendian (buf, val, n);
16574 md_chars_to_number (char * buf, int n)
16577 unsigned char * where = (unsigned char *) buf;
16579 if (target_big_endian)
16584 result |= (*where++ & 255);
16592 result |= (where[n] & 255);
16599 /* MD interface: Sections. */
16601 /* Estimate the size of a frag before relaxing. Assume everything fits in
16605 md_estimate_size_before_relax (fragS * fragp,
16606 segT segtype ATTRIBUTE_UNUSED)
16612 /* Convert a machine dependent frag. */
16615 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
16617 unsigned long insn;
16618 unsigned long old_op;
16626 buf = fragp->fr_literal + fragp->fr_fix;
16628 old_op = bfd_get_16(abfd, buf);
16629 if (fragp->fr_symbol) {
16630 exp.X_op = O_symbol;
16631 exp.X_add_symbol = fragp->fr_symbol;
16633 exp.X_op = O_constant;
16635 exp.X_add_number = fragp->fr_offset;
16636 opcode = fragp->fr_subtype;
16639 case T_MNEM_ldr_pc:
16640 case T_MNEM_ldr_pc2:
16641 case T_MNEM_ldr_sp:
16642 case T_MNEM_str_sp:
16649 if (fragp->fr_var == 4)
16651 insn = THUMB_OP32(opcode);
16652 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
16654 insn |= (old_op & 0x700) << 4;
16658 insn |= (old_op & 7) << 12;
16659 insn |= (old_op & 0x38) << 13;
16661 insn |= 0x00000c00;
16662 put_thumb32_insn (buf, insn);
16663 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
16667 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
16669 pc_rel = (opcode == T_MNEM_ldr_pc2);
16672 if (fragp->fr_var == 4)
16674 insn = THUMB_OP32 (opcode);
16675 insn |= (old_op & 0xf0) << 4;
16676 put_thumb32_insn (buf, insn);
16677 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
16681 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16682 exp.X_add_number -= 4;
16690 if (fragp->fr_var == 4)
16692 int r0off = (opcode == T_MNEM_mov
16693 || opcode == T_MNEM_movs) ? 0 : 8;
16694 insn = THUMB_OP32 (opcode);
16695 insn = (insn & 0xe1ffffff) | 0x10000000;
16696 insn |= (old_op & 0x700) << r0off;
16697 put_thumb32_insn (buf, insn);
16698 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16702 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
16707 if (fragp->fr_var == 4)
16709 insn = THUMB_OP32(opcode);
16710 put_thumb32_insn (buf, insn);
16711 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
16714 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
16718 if (fragp->fr_var == 4)
16720 insn = THUMB_OP32(opcode);
16721 insn |= (old_op & 0xf00) << 14;
16722 put_thumb32_insn (buf, insn);
16723 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
16726 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
16729 case T_MNEM_add_sp:
16730 case T_MNEM_add_pc:
16731 case T_MNEM_inc_sp:
16732 case T_MNEM_dec_sp:
16733 if (fragp->fr_var == 4)
16735 /* ??? Choose between add and addw. */
16736 insn = THUMB_OP32 (opcode);
16737 insn |= (old_op & 0xf0) << 4;
16738 put_thumb32_insn (buf, insn);
16739 if (opcode == T_MNEM_add_pc)
16740 reloc_type = BFD_RELOC_ARM_T32_IMM12;
16742 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16745 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16753 if (fragp->fr_var == 4)
16755 insn = THUMB_OP32 (opcode);
16756 insn |= (old_op & 0xf0) << 4;
16757 insn |= (old_op & 0xf) << 16;
16758 put_thumb32_insn (buf, insn);
16759 if (insn & (1 << 20))
16760 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16762 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16765 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16771 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
16773 fixp->fx_file = fragp->fr_file;
16774 fixp->fx_line = fragp->fr_line;
16775 fragp->fr_fix += fragp->fr_var;
16778 /* Return the size of a relaxable immediate operand instruction.
16779 SHIFT and SIZE specify the form of the allowable immediate. */
16781 relax_immediate (fragS *fragp, int size, int shift)
16787 /* ??? Should be able to do better than this. */
16788 if (fragp->fr_symbol)
16791 low = (1 << shift) - 1;
16792 mask = (1 << (shift + size)) - (1 << shift);
16793 offset = fragp->fr_offset;
16794 /* Force misaligned offsets to 32-bit variant. */
16797 if (offset & ~mask)
16802 /* Get the address of a symbol during relaxation. */
16804 relaxed_symbol_addr(fragS *fragp, long stretch)
16810 sym = fragp->fr_symbol;
16811 sym_frag = symbol_get_frag (sym);
16812 know (S_GET_SEGMENT (sym) != absolute_section
16813 || sym_frag == &zero_address_frag);
16814 addr = S_GET_VALUE (sym) + fragp->fr_offset;
16816 /* If frag has yet to be reached on this pass, assume it will
16817 move by STRETCH just as we did. If this is not so, it will
16818 be because some frag between grows, and that will force
16822 && sym_frag->relax_marker != fragp->relax_marker)
16828 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16831 relax_adr (fragS *fragp, asection *sec, long stretch)
16836 /* Assume worst case for symbols not known to be in the same section. */
16837 if (!S_IS_DEFINED(fragp->fr_symbol)
16838 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16841 val = relaxed_symbol_addr(fragp, stretch);
16842 addr = fragp->fr_address + fragp->fr_fix;
16843 addr = (addr + 4) & ~3;
16844 /* Force misaligned targets to 32-bit variant. */
16848 if (val < 0 || val > 1020)
16853 /* Return the size of a relaxable add/sub immediate instruction. */
16855 relax_addsub (fragS *fragp, asection *sec)
16860 buf = fragp->fr_literal + fragp->fr_fix;
16861 op = bfd_get_16(sec->owner, buf);
16862 if ((op & 0xf) == ((op >> 4) & 0xf))
16863 return relax_immediate (fragp, 8, 0);
16865 return relax_immediate (fragp, 3, 0);
16869 /* Return the size of a relaxable branch instruction. BITS is the
16870 size of the offset field in the narrow instruction. */
16873 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
16879 /* Assume worst case for symbols not known to be in the same section. */
16880 if (!S_IS_DEFINED(fragp->fr_symbol)
16881 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16884 val = relaxed_symbol_addr(fragp, stretch);
16885 addr = fragp->fr_address + fragp->fr_fix + 4;
16888 /* Offset is a signed value *2 */
16890 if (val >= limit || val < -limit)
16896 /* Relax a machine dependent frag. This returns the amount by which
16897 the current size of the frag should change. */
16900 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
16905 oldsize = fragp->fr_var;
16906 switch (fragp->fr_subtype)
16908 case T_MNEM_ldr_pc2:
16909 newsize = relax_adr(fragp, sec, stretch);
16911 case T_MNEM_ldr_pc:
16912 case T_MNEM_ldr_sp:
16913 case T_MNEM_str_sp:
16914 newsize = relax_immediate(fragp, 8, 2);
16918 newsize = relax_immediate(fragp, 5, 2);
16922 newsize = relax_immediate(fragp, 5, 1);
16926 newsize = relax_immediate(fragp, 5, 0);
16929 newsize = relax_adr(fragp, sec, stretch);
16935 newsize = relax_immediate(fragp, 8, 0);
16938 newsize = relax_branch(fragp, sec, 11, stretch);
16941 newsize = relax_branch(fragp, sec, 8, stretch);
16943 case T_MNEM_add_sp:
16944 case T_MNEM_add_pc:
16945 newsize = relax_immediate (fragp, 8, 2);
16947 case T_MNEM_inc_sp:
16948 case T_MNEM_dec_sp:
16949 newsize = relax_immediate (fragp, 7, 2);
16955 newsize = relax_addsub (fragp, sec);
16961 fragp->fr_var = newsize;
16962 /* Freeze wide instructions that are at or before the same location as
16963 in the previous pass. This avoids infinite loops.
16964 Don't freeze them unconditionally because targets may be artificialy
16965 misaligned by the expansion of preceeding frags. */
16966 if (stretch <= 0 && newsize > 2)
16968 md_convert_frag (sec->owner, sec, fragp);
16972 return newsize - oldsize;
16975 /* Round up a section size to the appropriate boundary. */
16978 md_section_align (segT segment ATTRIBUTE_UNUSED,
16981 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16982 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
16984 /* For a.out, force the section size to be aligned. If we don't do
16985 this, BFD will align it for us, but it will not write out the
16986 final bytes of the section. This may be a bug in BFD, but it is
16987 easier to fix it here since that is how the other a.out targets
16991 align = bfd_get_section_alignment (stdoutput, segment);
16992 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
16999 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17000 of an rs_align_code fragment. */
17003 arm_handle_align (fragS * fragP)
17005 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17006 static char const thumb_noop[2] = { 0xc0, 0x46 };
17007 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17008 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
17010 int bytes, fix, noop_size;
17014 if (fragP->fr_type != rs_align_code)
17017 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
17018 p = fragP->fr_literal + fragP->fr_fix;
17021 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
17022 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
17024 if (fragP->tc_frag_data)
17026 if (target_big_endian)
17027 noop = thumb_bigend_noop;
17030 noop_size = sizeof (thumb_noop);
17034 if (target_big_endian)
17035 noop = arm_bigend_noop;
17038 noop_size = sizeof (arm_noop);
17041 if (bytes & (noop_size - 1))
17043 fix = bytes & (noop_size - 1);
17044 memset (p, 0, fix);
17049 while (bytes >= noop_size)
17051 memcpy (p, noop, noop_size);
17053 bytes -= noop_size;
17057 fragP->fr_fix += fix;
17058 fragP->fr_var = noop_size;
17061 /* Called from md_do_align. Used to create an alignment
17062 frag in a code section. */
17065 arm_frag_align_code (int n, int max)
17069 /* We assume that there will never be a requirement
17070 to support alignments greater than 32 bytes. */
17071 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
17072 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17074 p = frag_var (rs_align_code,
17075 MAX_MEM_FOR_RS_ALIGN_CODE,
17077 (relax_substateT) max,
17084 /* Perform target specific initialisation of a frag. */
17087 arm_init_frag (fragS * fragP)
17089 /* Record whether this frag is in an ARM or a THUMB area. */
17090 fragP->tc_frag_data = thumb_mode;
17094 /* When we change sections we need to issue a new mapping symbol. */
17097 arm_elf_change_section (void)
17100 segment_info_type *seginfo;
17102 /* Link an unlinked unwind index table section to the .text section. */
17103 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
17104 && elf_linked_to_section (now_seg) == NULL)
17105 elf_linked_to_section (now_seg) = text_section;
17107 if (!SEG_NORMAL (now_seg))
17110 flags = bfd_get_section_flags (stdoutput, now_seg);
17112 /* We can ignore sections that only contain debug info. */
17113 if ((flags & SEC_ALLOC) == 0)
17116 seginfo = seg_info (now_seg);
17117 mapstate = seginfo->tc_segment_info_data.mapstate;
17118 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
17122 arm_elf_section_type (const char * str, size_t len)
17124 if (len == 5 && strncmp (str, "exidx", 5) == 0)
17125 return SHT_ARM_EXIDX;
17130 /* Code to deal with unwinding tables. */
17132 static void add_unwind_adjustsp (offsetT);
17134 /* Cenerate and deferred unwind frame offset. */
17137 flush_pending_unwind (void)
17141 offset = unwind.pending_offset;
17142 unwind.pending_offset = 0;
17144 add_unwind_adjustsp (offset);
17147 /* Add an opcode to this list for this function. Two-byte opcodes should
17148 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17152 add_unwind_opcode (valueT op, int length)
17154 /* Add any deferred stack adjustment. */
17155 if (unwind.pending_offset)
17156 flush_pending_unwind ();
17158 unwind.sp_restored = 0;
17160 if (unwind.opcode_count + length > unwind.opcode_alloc)
17162 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
17163 if (unwind.opcodes)
17164 unwind.opcodes = xrealloc (unwind.opcodes,
17165 unwind.opcode_alloc);
17167 unwind.opcodes = xmalloc (unwind.opcode_alloc);
17172 unwind.opcodes[unwind.opcode_count] = op & 0xff;
17174 unwind.opcode_count++;
17178 /* Add unwind opcodes to adjust the stack pointer. */
17181 add_unwind_adjustsp (offsetT offset)
17185 if (offset > 0x200)
17187 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17192 /* Long form: 0xb2, uleb128. */
17193 /* This might not fit in a word so add the individual bytes,
17194 remembering the list is built in reverse order. */
17195 o = (valueT) ((offset - 0x204) >> 2);
17197 add_unwind_opcode (0, 1);
17199 /* Calculate the uleb128 encoding of the offset. */
17203 bytes[n] = o & 0x7f;
17209 /* Add the insn. */
17211 add_unwind_opcode (bytes[n - 1], 1);
17212 add_unwind_opcode (0xb2, 1);
17214 else if (offset > 0x100)
17216 /* Two short opcodes. */
17217 add_unwind_opcode (0x3f, 1);
17218 op = (offset - 0x104) >> 2;
17219 add_unwind_opcode (op, 1);
17221 else if (offset > 0)
17223 /* Short opcode. */
17224 op = (offset - 4) >> 2;
17225 add_unwind_opcode (op, 1);
17227 else if (offset < 0)
17230 while (offset > 0x100)
17232 add_unwind_opcode (0x7f, 1);
17235 op = ((offset - 4) >> 2) | 0x40;
17236 add_unwind_opcode (op, 1);
17240 /* Finish the list of unwind opcodes for this function. */
17242 finish_unwind_opcodes (void)
17246 if (unwind.fp_used)
17248 /* Adjust sp as necessary. */
17249 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
17250 flush_pending_unwind ();
17252 /* After restoring sp from the frame pointer. */
17253 op = 0x90 | unwind.fp_reg;
17254 add_unwind_opcode (op, 1);
17257 flush_pending_unwind ();
17261 /* Start an exception table entry. If idx is nonzero this is an index table
17265 start_unwind_section (const segT text_seg, int idx)
17267 const char * text_name;
17268 const char * prefix;
17269 const char * prefix_once;
17270 const char * group_name;
17274 size_t sec_name_len;
17281 prefix = ELF_STRING_ARM_unwind;
17282 prefix_once = ELF_STRING_ARM_unwind_once;
17283 type = SHT_ARM_EXIDX;
17287 prefix = ELF_STRING_ARM_unwind_info;
17288 prefix_once = ELF_STRING_ARM_unwind_info_once;
17289 type = SHT_PROGBITS;
17292 text_name = segment_name (text_seg);
17293 if (streq (text_name, ".text"))
17296 if (strncmp (text_name, ".gnu.linkonce.t.",
17297 strlen (".gnu.linkonce.t.")) == 0)
17299 prefix = prefix_once;
17300 text_name += strlen (".gnu.linkonce.t.");
17303 prefix_len = strlen (prefix);
17304 text_len = strlen (text_name);
17305 sec_name_len = prefix_len + text_len;
17306 sec_name = xmalloc (sec_name_len + 1);
17307 memcpy (sec_name, prefix, prefix_len);
17308 memcpy (sec_name + prefix_len, text_name, text_len);
17309 sec_name[prefix_len + text_len] = '\0';
17315 /* Handle COMDAT group. */
17316 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
17318 group_name = elf_group_name (text_seg);
17319 if (group_name == NULL)
17321 as_bad ("Group section `%s' has no group signature",
17322 segment_name (text_seg));
17323 ignore_rest_of_line ();
17326 flags |= SHF_GROUP;
17330 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
17332 /* Set the setion link for index tables. */
17334 elf_linked_to_section (now_seg) = text_seg;
17338 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17339 personality routine data. Returns zero, or the index table value for
17340 and inline entry. */
17343 create_unwind_entry (int have_data)
17348 /* The current word of data. */
17350 /* The number of bytes left in this word. */
17353 finish_unwind_opcodes ();
17355 /* Remember the current text section. */
17356 unwind.saved_seg = now_seg;
17357 unwind.saved_subseg = now_subseg;
17359 start_unwind_section (now_seg, 0);
17361 if (unwind.personality_routine == NULL)
17363 if (unwind.personality_index == -2)
17366 as_bad (_("handerdata in cantunwind frame"));
17367 return 1; /* EXIDX_CANTUNWIND. */
17370 /* Use a default personality routine if none is specified. */
17371 if (unwind.personality_index == -1)
17373 if (unwind.opcode_count > 3)
17374 unwind.personality_index = 1;
17376 unwind.personality_index = 0;
17379 /* Space for the personality routine entry. */
17380 if (unwind.personality_index == 0)
17382 if (unwind.opcode_count > 3)
17383 as_bad (_("too many unwind opcodes for personality routine 0"));
17387 /* All the data is inline in the index table. */
17390 while (unwind.opcode_count > 0)
17392 unwind.opcode_count--;
17393 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17397 /* Pad with "finish" opcodes. */
17399 data = (data << 8) | 0xb0;
17406 /* We get two opcodes "free" in the first word. */
17407 size = unwind.opcode_count - 2;
17410 /* An extra byte is required for the opcode count. */
17411 size = unwind.opcode_count + 1;
17413 size = (size + 3) >> 2;
17415 as_bad (_("too many unwind opcodes"));
17417 frag_align (2, 0, 0);
17418 record_alignment (now_seg, 2);
17419 unwind.table_entry = expr_build_dot ();
17421 /* Allocate the table entry. */
17422 ptr = frag_more ((size << 2) + 4);
17423 memset(ptr, 0, (size << 2) + 4);
17424 where = frag_now_fix () - ((size << 2) + 4);
17426 switch (unwind.personality_index)
17429 /* ??? Should this be a PLT generating relocation? */
17430 /* Custom personality routine. */
17431 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
17432 BFD_RELOC_ARM_PREL31);
17437 /* Set the first byte to the number of additional words. */
17442 /* ABI defined personality routines. */
17444 /* Three opcodes bytes are packed into the first word. */
17451 /* The size and first two opcode bytes go in the first word. */
17452 data = ((0x80 + unwind.personality_index) << 8) | size;
17457 /* Should never happen. */
17461 /* Pack the opcodes into words (MSB first), reversing the list at the same
17463 while (unwind.opcode_count > 0)
17467 md_number_to_chars (ptr, data, 4);
17472 unwind.opcode_count--;
17474 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17477 /* Finish off the last word. */
17480 /* Pad with "finish" opcodes. */
17482 data = (data << 8) | 0xb0;
17484 md_number_to_chars (ptr, data, 4);
17489 /* Add an empty descriptor if there is no user-specified data. */
17490 ptr = frag_more (4);
17491 md_number_to_chars (ptr, 0, 4);
17498 /* Initialize the DWARF-2 unwind information for this procedure. */
17501 tc_arm_frame_initial_instructions (void)
17503 cfi_add_CFA_def_cfa (REG_SP, 0);
17505 #endif /* OBJ_ELF */
17507 /* Convert REGNAME to a DWARF-2 register number. */
17510 tc_arm_regname_to_dw2regnum (char *regname)
17512 int reg = arm_reg_parse (®name, REG_TYPE_RN);
17522 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
17526 expr.X_op = O_secrel;
17527 expr.X_add_symbol = symbol;
17528 expr.X_add_number = 0;
17529 emit_expr (&expr, size);
17533 /* MD interface: Symbol and relocation handling. */
17535 /* Return the address within the segment that a PC-relative fixup is
17536 relative to. For ARM, PC-relative fixups applied to instructions
17537 are generally relative to the location of the fixup plus 8 bytes.
17538 Thumb branches are offset by 4, and Thumb loads relative to PC
17539 require special handling. */
17542 md_pcrel_from_section (fixS * fixP, segT seg)
17544 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
17546 /* If this is pc-relative and we are going to emit a relocation
17547 then we just want to put out any pipeline compensation that the linker
17548 will need. Otherwise we want to use the calculated base.
17549 For WinCE we skip the bias for externals as well, since this
17550 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17552 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
17553 || (arm_force_relocation (fixP)
17555 && !S_IS_EXTERNAL (fixP->fx_addsy)
17560 switch (fixP->fx_r_type)
17562 /* PC relative addressing on the Thumb is slightly odd as the
17563 bottom two bits of the PC are forced to zero for the
17564 calculation. This happens *after* application of the
17565 pipeline offset. However, Thumb adrl already adjusts for
17566 this, so we need not do it again. */
17567 case BFD_RELOC_ARM_THUMB_ADD:
17570 case BFD_RELOC_ARM_THUMB_OFFSET:
17571 case BFD_RELOC_ARM_T32_OFFSET_IMM:
17572 case BFD_RELOC_ARM_T32_ADD_PC12:
17573 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
17574 return (base + 4) & ~3;
17576 /* Thumb branches are simply offset by +4. */
17577 case BFD_RELOC_THUMB_PCREL_BRANCH7:
17578 case BFD_RELOC_THUMB_PCREL_BRANCH9:
17579 case BFD_RELOC_THUMB_PCREL_BRANCH12:
17580 case BFD_RELOC_THUMB_PCREL_BRANCH20:
17581 case BFD_RELOC_THUMB_PCREL_BRANCH23:
17582 case BFD_RELOC_THUMB_PCREL_BRANCH25:
17583 case BFD_RELOC_THUMB_PCREL_BLX:
17586 /* ARM mode branches are offset by +8. However, the Windows CE
17587 loader expects the relocation not to take this into account. */
17588 case BFD_RELOC_ARM_PCREL_BRANCH:
17589 case BFD_RELOC_ARM_PCREL_CALL:
17590 case BFD_RELOC_ARM_PCREL_JUMP:
17591 case BFD_RELOC_ARM_PCREL_BLX:
17592 case BFD_RELOC_ARM_PLT32:
17594 /* When handling fixups immediately, because we have already
17595 discovered the value of a symbol, or the address of the frag involved
17596 we must account for the offset by +8, as the OS loader will never see the reloc.
17597 see fixup_segment() in write.c
17598 The S_IS_EXTERNAL test handles the case of global symbols.
17599 Those need the calculated base, not just the pipe compensation the linker will need. */
17601 && fixP->fx_addsy != NULL
17602 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
17603 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
17610 /* ARM mode loads relative to PC are also offset by +8. Unlike
17611 branches, the Windows CE loader *does* expect the relocation
17612 to take this into account. */
17613 case BFD_RELOC_ARM_OFFSET_IMM:
17614 case BFD_RELOC_ARM_OFFSET_IMM8:
17615 case BFD_RELOC_ARM_HWLITERAL:
17616 case BFD_RELOC_ARM_LITERAL:
17617 case BFD_RELOC_ARM_CP_OFF_IMM:
17621 /* Other PC-relative relocations are un-offset. */
17627 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17628 Otherwise we have no need to default values of symbols. */
17631 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
17634 if (name[0] == '_' && name[1] == 'G'
17635 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
17639 if (symbol_find (name))
17640 as_bad ("GOT already in the symbol table");
17642 GOT_symbol = symbol_new (name, undefined_section,
17643 (valueT) 0, & zero_address_frag);
17653 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17654 computed as two separate immediate values, added together. We
17655 already know that this value cannot be computed by just one ARM
17658 static unsigned int
17659 validate_immediate_twopart (unsigned int val,
17660 unsigned int * highpart)
17665 for (i = 0; i < 32; i += 2)
17666 if (((a = rotate_left (val, i)) & 0xff) != 0)
17672 * highpart = (a >> 8) | ((i + 24) << 7);
17674 else if (a & 0xff0000)
17676 if (a & 0xff000000)
17678 * highpart = (a >> 16) | ((i + 16) << 7);
17682 assert (a & 0xff000000);
17683 * highpart = (a >> 24) | ((i + 8) << 7);
17686 return (a & 0xff) | (i << 7);
17693 validate_offset_imm (unsigned int val, int hwse)
17695 if ((hwse && val > 255) || val > 4095)
17700 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17701 negative immediate constant by altering the instruction. A bit of
17706 by inverting the second operand, and
17709 by negating the second operand. */
17712 negate_data_op (unsigned long * instruction,
17713 unsigned long value)
17716 unsigned long negated, inverted;
17718 negated = encode_arm_immediate (-value);
17719 inverted = encode_arm_immediate (~value);
17721 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
17724 /* First negates. */
17725 case OPCODE_SUB: /* ADD <-> SUB */
17726 new_inst = OPCODE_ADD;
17731 new_inst = OPCODE_SUB;
17735 case OPCODE_CMP: /* CMP <-> CMN */
17736 new_inst = OPCODE_CMN;
17741 new_inst = OPCODE_CMP;
17745 /* Now Inverted ops. */
17746 case OPCODE_MOV: /* MOV <-> MVN */
17747 new_inst = OPCODE_MVN;
17752 new_inst = OPCODE_MOV;
17756 case OPCODE_AND: /* AND <-> BIC */
17757 new_inst = OPCODE_BIC;
17762 new_inst = OPCODE_AND;
17766 case OPCODE_ADC: /* ADC <-> SBC */
17767 new_inst = OPCODE_SBC;
17772 new_inst = OPCODE_ADC;
17776 /* We cannot do anything. */
17781 if (value == (unsigned) FAIL)
17784 *instruction &= OPCODE_MASK;
17785 *instruction |= new_inst << DATA_OP_SHIFT;
17789 /* Like negate_data_op, but for Thumb-2. */
17791 static unsigned int
17792 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
17796 unsigned int negated, inverted;
17798 negated = encode_thumb32_immediate (-value);
17799 inverted = encode_thumb32_immediate (~value);
17801 rd = (*instruction >> 8) & 0xf;
17802 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
17805 /* ADD <-> SUB. Includes CMP <-> CMN. */
17806 case T2_OPCODE_SUB:
17807 new_inst = T2_OPCODE_ADD;
17811 case T2_OPCODE_ADD:
17812 new_inst = T2_OPCODE_SUB;
17816 /* ORR <-> ORN. Includes MOV <-> MVN. */
17817 case T2_OPCODE_ORR:
17818 new_inst = T2_OPCODE_ORN;
17822 case T2_OPCODE_ORN:
17823 new_inst = T2_OPCODE_ORR;
17827 /* AND <-> BIC. TST has no inverted equivalent. */
17828 case T2_OPCODE_AND:
17829 new_inst = T2_OPCODE_BIC;
17836 case T2_OPCODE_BIC:
17837 new_inst = T2_OPCODE_AND;
17842 case T2_OPCODE_ADC:
17843 new_inst = T2_OPCODE_SBC;
17847 case T2_OPCODE_SBC:
17848 new_inst = T2_OPCODE_ADC;
17852 /* We cannot do anything. */
17857 if (value == (unsigned int)FAIL)
17860 *instruction &= T2_OPCODE_MASK;
17861 *instruction |= new_inst << T2_DATA_OP_SHIFT;
17865 /* Read a 32-bit thumb instruction from buf. */
17866 static unsigned long
17867 get_thumb32_insn (char * buf)
17869 unsigned long insn;
17870 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
17871 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
17877 /* We usually want to set the low bit on the address of thumb function
17878 symbols. In particular .word foo - . should have the low bit set.
17879 Generic code tries to fold the difference of two symbols to
17880 a constant. Prevent this and force a relocation when the first symbols
17881 is a thumb function. */
17883 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
17885 if (op == O_subtract
17886 && l->X_op == O_symbol
17887 && r->X_op == O_symbol
17888 && THUMB_IS_FUNC (l->X_add_symbol))
17890 l->X_op = O_subtract;
17891 l->X_op_symbol = r->X_add_symbol;
17892 l->X_add_number -= r->X_add_number;
17895 /* Process as normal. */
17900 md_apply_fix (fixS * fixP,
17904 offsetT value = * valP;
17906 unsigned int newimm;
17907 unsigned long temp;
17909 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
17911 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
17913 /* Note whether this will delete the relocation. */
17915 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
17918 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17919 consistency with the behavior on 32-bit hosts. Remember value
17921 value &= 0xffffffff;
17922 value ^= 0x80000000;
17923 value -= 0x80000000;
17926 fixP->fx_addnumber = value;
17928 /* Same treatment for fixP->fx_offset. */
17929 fixP->fx_offset &= 0xffffffff;
17930 fixP->fx_offset ^= 0x80000000;
17931 fixP->fx_offset -= 0x80000000;
17933 switch (fixP->fx_r_type)
17935 case BFD_RELOC_NONE:
17936 /* This will need to go in the object file. */
17940 case BFD_RELOC_ARM_IMMEDIATE:
17941 /* We claim that this fixup has been processed here,
17942 even if in fact we generate an error because we do
17943 not have a reloc for it, so tc_gen_reloc will reject it. */
17947 && ! S_IS_DEFINED (fixP->fx_addsy))
17949 as_bad_where (fixP->fx_file, fixP->fx_line,
17950 _("undefined symbol %s used as an immediate value"),
17951 S_GET_NAME (fixP->fx_addsy));
17955 newimm = encode_arm_immediate (value);
17956 temp = md_chars_to_number (buf, INSN_SIZE);
17958 /* If the instruction will fail, see if we can fix things up by
17959 changing the opcode. */
17960 if (newimm == (unsigned int) FAIL
17961 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
17963 as_bad_where (fixP->fx_file, fixP->fx_line,
17964 _("invalid constant (%lx) after fixup"),
17965 (unsigned long) value);
17969 newimm |= (temp & 0xfffff000);
17970 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
17973 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
17975 unsigned int highpart = 0;
17976 unsigned int newinsn = 0xe1a00000; /* nop. */
17978 newimm = encode_arm_immediate (value);
17979 temp = md_chars_to_number (buf, INSN_SIZE);
17981 /* If the instruction will fail, see if we can fix things up by
17982 changing the opcode. */
17983 if (newimm == (unsigned int) FAIL
17984 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
17986 /* No ? OK - try using two ADD instructions to generate
17988 newimm = validate_immediate_twopart (value, & highpart);
17990 /* Yes - then make sure that the second instruction is
17992 if (newimm != (unsigned int) FAIL)
17994 /* Still No ? Try using a negated value. */
17995 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
17996 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
17997 /* Otherwise - give up. */
18000 as_bad_where (fixP->fx_file, fixP->fx_line,
18001 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18006 /* Replace the first operand in the 2nd instruction (which
18007 is the PC) with the destination register. We have
18008 already added in the PC in the first instruction and we
18009 do not want to do it again. */
18010 newinsn &= ~ 0xf0000;
18011 newinsn |= ((newinsn & 0x0f000) << 4);
18014 newimm |= (temp & 0xfffff000);
18015 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
18017 highpart |= (newinsn & 0xfffff000);
18018 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
18022 case BFD_RELOC_ARM_OFFSET_IMM:
18023 if (!fixP->fx_done && seg->use_rela_p)
18026 case BFD_RELOC_ARM_LITERAL:
18032 if (validate_offset_imm (value, 0) == FAIL)
18034 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
18035 as_bad_where (fixP->fx_file, fixP->fx_line,
18036 _("invalid literal constant: pool needs to be closer"));
18038 as_bad_where (fixP->fx_file, fixP->fx_line,
18039 _("bad immediate value for offset (%ld)"),
18044 newval = md_chars_to_number (buf, INSN_SIZE);
18045 newval &= 0xff7ff000;
18046 newval |= value | (sign ? INDEX_UP : 0);
18047 md_number_to_chars (buf, newval, INSN_SIZE);
18050 case BFD_RELOC_ARM_OFFSET_IMM8:
18051 case BFD_RELOC_ARM_HWLITERAL:
18057 if (validate_offset_imm (value, 1) == FAIL)
18059 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
18060 as_bad_where (fixP->fx_file, fixP->fx_line,
18061 _("invalid literal constant: pool needs to be closer"));
18063 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18068 newval = md_chars_to_number (buf, INSN_SIZE);
18069 newval &= 0xff7ff0f0;
18070 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
18071 md_number_to_chars (buf, newval, INSN_SIZE);
18074 case BFD_RELOC_ARM_T32_OFFSET_U8:
18075 if (value < 0 || value > 1020 || value % 4 != 0)
18076 as_bad_where (fixP->fx_file, fixP->fx_line,
18077 _("bad immediate value for offset (%ld)"), (long) value);
18080 newval = md_chars_to_number (buf+2, THUMB_SIZE);
18082 md_number_to_chars (buf+2, newval, THUMB_SIZE);
18085 case BFD_RELOC_ARM_T32_OFFSET_IMM:
18086 /* This is a complicated relocation used for all varieties of Thumb32
18087 load/store instruction with immediate offset:
18089 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18090 *4, optional writeback(W)
18091 (doubleword load/store)
18093 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18094 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18095 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18096 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18097 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18099 Uppercase letters indicate bits that are already encoded at
18100 this point. Lowercase letters are our problem. For the
18101 second block of instructions, the secondary opcode nybble
18102 (bits 8..11) is present, and bit 23 is zero, even if this is
18103 a PC-relative operation. */
18104 newval = md_chars_to_number (buf, THUMB_SIZE);
18106 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
18108 if ((newval & 0xf0000000) == 0xe0000000)
18110 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18112 newval |= (1 << 23);
18115 if (value % 4 != 0)
18117 as_bad_where (fixP->fx_file, fixP->fx_line,
18118 _("offset not a multiple of 4"));
18124 as_bad_where (fixP->fx_file, fixP->fx_line,
18125 _("offset out of range"));
18130 else if ((newval & 0x000f0000) == 0x000f0000)
18132 /* PC-relative, 12-bit offset. */
18134 newval |= (1 << 23);
18139 as_bad_where (fixP->fx_file, fixP->fx_line,
18140 _("offset out of range"));
18145 else if ((newval & 0x00000100) == 0x00000100)
18147 /* Writeback: 8-bit, +/- offset. */
18149 newval |= (1 << 9);
18154 as_bad_where (fixP->fx_file, fixP->fx_line,
18155 _("offset out of range"));
18160 else if ((newval & 0x00000f00) == 0x00000e00)
18162 /* T-instruction: positive 8-bit offset. */
18163 if (value < 0 || value > 0xff)
18165 as_bad_where (fixP->fx_file, fixP->fx_line,
18166 _("offset out of range"));
18174 /* Positive 12-bit or negative 8-bit offset. */
18178 newval |= (1 << 23);
18188 as_bad_where (fixP->fx_file, fixP->fx_line,
18189 _("offset out of range"));
18196 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
18197 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
18200 case BFD_RELOC_ARM_SHIFT_IMM:
18201 newval = md_chars_to_number (buf, INSN_SIZE);
18202 if (((unsigned long) value) > 32
18204 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
18206 as_bad_where (fixP->fx_file, fixP->fx_line,
18207 _("shift expression is too large"));
18212 /* Shifts of zero must be done as lsl. */
18214 else if (value == 32)
18216 newval &= 0xfffff07f;
18217 newval |= (value & 0x1f) << 7;
18218 md_number_to_chars (buf, newval, INSN_SIZE);
18221 case BFD_RELOC_ARM_T32_IMMEDIATE:
18222 case BFD_RELOC_ARM_T32_ADD_IMM:
18223 case BFD_RELOC_ARM_T32_IMM12:
18224 case BFD_RELOC_ARM_T32_ADD_PC12:
18225 /* We claim that this fixup has been processed here,
18226 even if in fact we generate an error because we do
18227 not have a reloc for it, so tc_gen_reloc will reject it. */
18231 && ! S_IS_DEFINED (fixP->fx_addsy))
18233 as_bad_where (fixP->fx_file, fixP->fx_line,
18234 _("undefined symbol %s used as an immediate value"),
18235 S_GET_NAME (fixP->fx_addsy));
18239 newval = md_chars_to_number (buf, THUMB_SIZE);
18241 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
18244 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
18245 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18247 newimm = encode_thumb32_immediate (value);
18248 if (newimm == (unsigned int) FAIL)
18249 newimm = thumb32_negate_data_op (&newval, value);
18251 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
18252 && newimm == (unsigned int) FAIL)
18254 /* Turn add/sum into addw/subw. */
18255 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18256 newval = (newval & 0xfeffffff) | 0x02000000;
18258 /* 12 bit immediate for addw/subw. */
18262 newval ^= 0x00a00000;
18265 newimm = (unsigned int) FAIL;
18270 if (newimm == (unsigned int)FAIL)
18272 as_bad_where (fixP->fx_file, fixP->fx_line,
18273 _("invalid constant (%lx) after fixup"),
18274 (unsigned long) value);
18278 newval |= (newimm & 0x800) << 15;
18279 newval |= (newimm & 0x700) << 4;
18280 newval |= (newimm & 0x0ff);
18282 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
18283 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
18286 case BFD_RELOC_ARM_SMC:
18287 if (((unsigned long) value) > 0xffff)
18288 as_bad_where (fixP->fx_file, fixP->fx_line,
18289 _("invalid smc expression"));
18290 newval = md_chars_to_number (buf, INSN_SIZE);
18291 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
18292 md_number_to_chars (buf, newval, INSN_SIZE);
18295 case BFD_RELOC_ARM_SWI:
18296 if (fixP->tc_fix_data != 0)
18298 if (((unsigned long) value) > 0xff)
18299 as_bad_where (fixP->fx_file, fixP->fx_line,
18300 _("invalid swi expression"));
18301 newval = md_chars_to_number (buf, THUMB_SIZE);
18303 md_number_to_chars (buf, newval, THUMB_SIZE);
18307 if (((unsigned long) value) > 0x00ffffff)
18308 as_bad_where (fixP->fx_file, fixP->fx_line,
18309 _("invalid swi expression"));
18310 newval = md_chars_to_number (buf, INSN_SIZE);
18312 md_number_to_chars (buf, newval, INSN_SIZE);
18316 case BFD_RELOC_ARM_MULTI:
18317 if (((unsigned long) value) > 0xffff)
18318 as_bad_where (fixP->fx_file, fixP->fx_line,
18319 _("invalid expression in load/store multiple"));
18320 newval = value | md_chars_to_number (buf, INSN_SIZE);
18321 md_number_to_chars (buf, newval, INSN_SIZE);
18325 case BFD_RELOC_ARM_PCREL_CALL:
18326 newval = md_chars_to_number (buf, INSN_SIZE);
18327 if ((newval & 0xf0000000) == 0xf0000000)
18331 goto arm_branch_common;
18333 case BFD_RELOC_ARM_PCREL_JUMP:
18334 case BFD_RELOC_ARM_PLT32:
18336 case BFD_RELOC_ARM_PCREL_BRANCH:
18338 goto arm_branch_common;
18340 case BFD_RELOC_ARM_PCREL_BLX:
18343 /* We are going to store value (shifted right by two) in the
18344 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18345 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18346 also be be clear. */
18348 as_bad_where (fixP->fx_file, fixP->fx_line,
18349 _("misaligned branch destination"));
18350 if ((value & (offsetT)0xfe000000) != (offsetT)0
18351 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
18352 as_bad_where (fixP->fx_file, fixP->fx_line,
18353 _("branch out of range"));
18355 if (fixP->fx_done || !seg->use_rela_p)
18357 newval = md_chars_to_number (buf, INSN_SIZE);
18358 newval |= (value >> 2) & 0x00ffffff;
18359 /* Set the H bit on BLX instructions. */
18363 newval |= 0x01000000;
18365 newval &= ~0x01000000;
18367 md_number_to_chars (buf, newval, INSN_SIZE);
18371 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
18372 /* CBZ can only branch forward. */
18374 /* Attempts to use CBZ to branch to the next instruction
18375 (which, strictly speaking, are prohibited) will be turned into
18378 FIXME: It may be better to remove the instruction completely and
18379 perform relaxation. */
18382 newval = md_chars_to_number (buf, THUMB_SIZE);
18383 newval = 0xbf00; /* NOP encoding T1 */
18384 md_number_to_chars (buf, newval, THUMB_SIZE);
18389 as_bad_where (fixP->fx_file, fixP->fx_line,
18390 _("branch out of range"));
18392 if (fixP->fx_done || !seg->use_rela_p)
18394 newval = md_chars_to_number (buf, THUMB_SIZE);
18395 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
18396 md_number_to_chars (buf, newval, THUMB_SIZE);
18401 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
18402 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
18403 as_bad_where (fixP->fx_file, fixP->fx_line,
18404 _("branch out of range"));
18406 if (fixP->fx_done || !seg->use_rela_p)
18408 newval = md_chars_to_number (buf, THUMB_SIZE);
18409 newval |= (value & 0x1ff) >> 1;
18410 md_number_to_chars (buf, newval, THUMB_SIZE);
18414 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
18415 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
18416 as_bad_where (fixP->fx_file, fixP->fx_line,
18417 _("branch out of range"));
18419 if (fixP->fx_done || !seg->use_rela_p)
18421 newval = md_chars_to_number (buf, THUMB_SIZE);
18422 newval |= (value & 0xfff) >> 1;
18423 md_number_to_chars (buf, newval, THUMB_SIZE);
18427 case BFD_RELOC_THUMB_PCREL_BRANCH20:
18428 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
18429 as_bad_where (fixP->fx_file, fixP->fx_line,
18430 _("conditional branch out of range"));
18432 if (fixP->fx_done || !seg->use_rela_p)
18435 addressT S, J1, J2, lo, hi;
18437 S = (value & 0x00100000) >> 20;
18438 J2 = (value & 0x00080000) >> 19;
18439 J1 = (value & 0x00040000) >> 18;
18440 hi = (value & 0x0003f000) >> 12;
18441 lo = (value & 0x00000ffe) >> 1;
18443 newval = md_chars_to_number (buf, THUMB_SIZE);
18444 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18445 newval |= (S << 10) | hi;
18446 newval2 |= (J1 << 13) | (J2 << 11) | lo;
18447 md_number_to_chars (buf, newval, THUMB_SIZE);
18448 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18452 case BFD_RELOC_THUMB_PCREL_BLX:
18453 case BFD_RELOC_THUMB_PCREL_BRANCH23:
18454 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
18455 as_bad_where (fixP->fx_file, fixP->fx_line,
18456 _("branch out of range"));
18458 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
18459 /* For a BLX instruction, make sure that the relocation is rounded up
18460 to a word boundary. This follows the semantics of the instruction
18461 which specifies that bit 1 of the target address will come from bit
18462 1 of the base address. */
18463 value = (value + 1) & ~ 1;
18465 if (fixP->fx_done || !seg->use_rela_p)
18469 newval = md_chars_to_number (buf, THUMB_SIZE);
18470 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18471 newval |= (value & 0x7fffff) >> 12;
18472 newval2 |= (value & 0xfff) >> 1;
18473 md_number_to_chars (buf, newval, THUMB_SIZE);
18474 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18478 case BFD_RELOC_THUMB_PCREL_BRANCH25:
18479 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
18480 as_bad_where (fixP->fx_file, fixP->fx_line,
18481 _("branch out of range"));
18483 if (fixP->fx_done || !seg->use_rela_p)
18486 addressT S, I1, I2, lo, hi;
18488 S = (value & 0x01000000) >> 24;
18489 I1 = (value & 0x00800000) >> 23;
18490 I2 = (value & 0x00400000) >> 22;
18491 hi = (value & 0x003ff000) >> 12;
18492 lo = (value & 0x00000ffe) >> 1;
18497 newval = md_chars_to_number (buf, THUMB_SIZE);
18498 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18499 newval |= (S << 10) | hi;
18500 newval2 |= (I1 << 13) | (I2 << 11) | lo;
18501 md_number_to_chars (buf, newval, THUMB_SIZE);
18502 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18507 if (fixP->fx_done || !seg->use_rela_p)
18508 md_number_to_chars (buf, value, 1);
18512 if (fixP->fx_done || !seg->use_rela_p)
18513 md_number_to_chars (buf, value, 2);
18517 case BFD_RELOC_ARM_TLS_GD32:
18518 case BFD_RELOC_ARM_TLS_LE32:
18519 case BFD_RELOC_ARM_TLS_IE32:
18520 case BFD_RELOC_ARM_TLS_LDM32:
18521 case BFD_RELOC_ARM_TLS_LDO32:
18522 S_SET_THREAD_LOCAL (fixP->fx_addsy);
18525 case BFD_RELOC_ARM_GOT32:
18526 case BFD_RELOC_ARM_GOTOFF:
18527 case BFD_RELOC_ARM_TARGET2:
18528 if (fixP->fx_done || !seg->use_rela_p)
18529 md_number_to_chars (buf, 0, 4);
18533 case BFD_RELOC_RVA:
18535 case BFD_RELOC_ARM_TARGET1:
18536 case BFD_RELOC_ARM_ROSEGREL32:
18537 case BFD_RELOC_ARM_SBREL32:
18538 case BFD_RELOC_32_PCREL:
18540 case BFD_RELOC_32_SECREL:
18542 if (fixP->fx_done || !seg->use_rela_p)
18544 /* For WinCE we only do this for pcrel fixups. */
18545 if (fixP->fx_done || fixP->fx_pcrel)
18547 md_number_to_chars (buf, value, 4);
18551 case BFD_RELOC_ARM_PREL31:
18552 if (fixP->fx_done || !seg->use_rela_p)
18554 newval = md_chars_to_number (buf, 4) & 0x80000000;
18555 if ((value ^ (value >> 1)) & 0x40000000)
18557 as_bad_where (fixP->fx_file, fixP->fx_line,
18558 _("rel31 relocation overflow"));
18560 newval |= value & 0x7fffffff;
18561 md_number_to_chars (buf, newval, 4);
18566 case BFD_RELOC_ARM_CP_OFF_IMM:
18567 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
18568 if (value < -1023 || value > 1023 || (value & 3))
18569 as_bad_where (fixP->fx_file, fixP->fx_line,
18570 _("co-processor offset out of range"));
18575 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18576 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18577 newval = md_chars_to_number (buf, INSN_SIZE);
18579 newval = get_thumb32_insn (buf);
18580 newval &= 0xff7fff00;
18581 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
18582 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18583 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18584 md_number_to_chars (buf, newval, INSN_SIZE);
18586 put_thumb32_insn (buf, newval);
18589 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
18590 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
18591 if (value < -255 || value > 255)
18592 as_bad_where (fixP->fx_file, fixP->fx_line,
18593 _("co-processor offset out of range"));
18595 goto cp_off_common;
18597 case BFD_RELOC_ARM_THUMB_OFFSET:
18598 newval = md_chars_to_number (buf, THUMB_SIZE);
18599 /* Exactly what ranges, and where the offset is inserted depends
18600 on the type of instruction, we can establish this from the
18602 switch (newval >> 12)
18604 case 4: /* PC load. */
18605 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18606 forced to zero for these loads; md_pcrel_from has already
18607 compensated for this. */
18609 as_bad_where (fixP->fx_file, fixP->fx_line,
18610 _("invalid offset, target not word aligned (0x%08lX)"),
18611 (((unsigned long) fixP->fx_frag->fr_address
18612 + (unsigned long) fixP->fx_where) & ~3)
18613 + (unsigned long) value);
18615 if (value & ~0x3fc)
18616 as_bad_where (fixP->fx_file, fixP->fx_line,
18617 _("invalid offset, value too big (0x%08lX)"),
18620 newval |= value >> 2;
18623 case 9: /* SP load/store. */
18624 if (value & ~0x3fc)
18625 as_bad_where (fixP->fx_file, fixP->fx_line,
18626 _("invalid offset, value too big (0x%08lX)"),
18628 newval |= value >> 2;
18631 case 6: /* Word load/store. */
18633 as_bad_where (fixP->fx_file, fixP->fx_line,
18634 _("invalid offset, value too big (0x%08lX)"),
18636 newval |= value << 4; /* 6 - 2. */
18639 case 7: /* Byte load/store. */
18641 as_bad_where (fixP->fx_file, fixP->fx_line,
18642 _("invalid offset, value too big (0x%08lX)"),
18644 newval |= value << 6;
18647 case 8: /* Halfword load/store. */
18649 as_bad_where (fixP->fx_file, fixP->fx_line,
18650 _("invalid offset, value too big (0x%08lX)"),
18652 newval |= value << 5; /* 6 - 1. */
18656 as_bad_where (fixP->fx_file, fixP->fx_line,
18657 "Unable to process relocation for thumb opcode: %lx",
18658 (unsigned long) newval);
18661 md_number_to_chars (buf, newval, THUMB_SIZE);
18664 case BFD_RELOC_ARM_THUMB_ADD:
18665 /* This is a complicated relocation, since we use it for all of
18666 the following immediate relocations:
18670 9bit ADD/SUB SP word-aligned
18671 10bit ADD PC/SP word-aligned
18673 The type of instruction being processed is encoded in the
18680 newval = md_chars_to_number (buf, THUMB_SIZE);
18682 int rd = (newval >> 4) & 0xf;
18683 int rs = newval & 0xf;
18684 int subtract = !!(newval & 0x8000);
18686 /* Check for HI regs, only very restricted cases allowed:
18687 Adjusting SP, and using PC or SP to get an address. */
18688 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
18689 || (rs > 7 && rs != REG_SP && rs != REG_PC))
18690 as_bad_where (fixP->fx_file, fixP->fx_line,
18691 _("invalid Hi register with immediate"));
18693 /* If value is negative, choose the opposite instruction. */
18697 subtract = !subtract;
18699 as_bad_where (fixP->fx_file, fixP->fx_line,
18700 _("immediate value out of range"));
18705 if (value & ~0x1fc)
18706 as_bad_where (fixP->fx_file, fixP->fx_line,
18707 _("invalid immediate for stack address calculation"));
18708 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
18709 newval |= value >> 2;
18711 else if (rs == REG_PC || rs == REG_SP)
18713 if (subtract || value & ~0x3fc)
18714 as_bad_where (fixP->fx_file, fixP->fx_line,
18715 _("invalid immediate for address calculation (value = 0x%08lX)"),
18716 (unsigned long) value);
18717 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
18719 newval |= value >> 2;
18724 as_bad_where (fixP->fx_file, fixP->fx_line,
18725 _("immediate value out of range"));
18726 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
18727 newval |= (rd << 8) | value;
18732 as_bad_where (fixP->fx_file, fixP->fx_line,
18733 _("immediate value out of range"));
18734 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
18735 newval |= rd | (rs << 3) | (value << 6);
18738 md_number_to_chars (buf, newval, THUMB_SIZE);
18741 case BFD_RELOC_ARM_THUMB_IMM:
18742 newval = md_chars_to_number (buf, THUMB_SIZE);
18743 if (value < 0 || value > 255)
18744 as_bad_where (fixP->fx_file, fixP->fx_line,
18745 _("invalid immediate: %ld is too large"),
18748 md_number_to_chars (buf, newval, THUMB_SIZE);
18751 case BFD_RELOC_ARM_THUMB_SHIFT:
18752 /* 5bit shift value (0..32). LSL cannot take 32. */
18753 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
18754 temp = newval & 0xf800;
18755 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
18756 as_bad_where (fixP->fx_file, fixP->fx_line,
18757 _("invalid shift value: %ld"), (long) value);
18758 /* Shifts of zero must be encoded as LSL. */
18760 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
18761 /* Shifts of 32 are encoded as zero. */
18762 else if (value == 32)
18764 newval |= value << 6;
18765 md_number_to_chars (buf, newval, THUMB_SIZE);
18768 case BFD_RELOC_VTABLE_INHERIT:
18769 case BFD_RELOC_VTABLE_ENTRY:
18773 case BFD_RELOC_ARM_MOVW:
18774 case BFD_RELOC_ARM_MOVT:
18775 case BFD_RELOC_ARM_THUMB_MOVW:
18776 case BFD_RELOC_ARM_THUMB_MOVT:
18777 if (fixP->fx_done || !seg->use_rela_p)
18779 /* REL format relocations are limited to a 16-bit addend. */
18780 if (!fixP->fx_done)
18782 if (value < -0x1000 || value > 0xffff)
18783 as_bad_where (fixP->fx_file, fixP->fx_line,
18784 _("offset too big"));
18786 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
18787 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18792 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
18793 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18795 newval = get_thumb32_insn (buf);
18796 newval &= 0xfbf08f00;
18797 newval |= (value & 0xf000) << 4;
18798 newval |= (value & 0x0800) << 15;
18799 newval |= (value & 0x0700) << 4;
18800 newval |= (value & 0x00ff);
18801 put_thumb32_insn (buf, newval);
18805 newval = md_chars_to_number (buf, 4);
18806 newval &= 0xfff0f000;
18807 newval |= value & 0x0fff;
18808 newval |= (value & 0xf000) << 4;
18809 md_number_to_chars (buf, newval, 4);
18814 case BFD_RELOC_ARM_ALU_PC_G0_NC:
18815 case BFD_RELOC_ARM_ALU_PC_G0:
18816 case BFD_RELOC_ARM_ALU_PC_G1_NC:
18817 case BFD_RELOC_ARM_ALU_PC_G1:
18818 case BFD_RELOC_ARM_ALU_PC_G2:
18819 case BFD_RELOC_ARM_ALU_SB_G0_NC:
18820 case BFD_RELOC_ARM_ALU_SB_G0:
18821 case BFD_RELOC_ARM_ALU_SB_G1_NC:
18822 case BFD_RELOC_ARM_ALU_SB_G1:
18823 case BFD_RELOC_ARM_ALU_SB_G2:
18824 assert (!fixP->fx_done);
18825 if (!seg->use_rela_p)
18828 bfd_vma encoded_addend;
18829 bfd_vma addend_abs = abs (value);
18831 /* Check that the absolute value of the addend can be
18832 expressed as an 8-bit constant plus a rotation. */
18833 encoded_addend = encode_arm_immediate (addend_abs);
18834 if (encoded_addend == (unsigned int) FAIL)
18835 as_bad_where (fixP->fx_file, fixP->fx_line,
18836 _("the offset 0x%08lX is not representable"),
18837 (unsigned long) addend_abs);
18839 /* Extract the instruction. */
18840 insn = md_chars_to_number (buf, INSN_SIZE);
18842 /* If the addend is positive, use an ADD instruction.
18843 Otherwise use a SUB. Take care not to destroy the S bit. */
18844 insn &= 0xff1fffff;
18850 /* Place the encoded addend into the first 12 bits of the
18852 insn &= 0xfffff000;
18853 insn |= encoded_addend;
18855 /* Update the instruction. */
18856 md_number_to_chars (buf, insn, INSN_SIZE);
18860 case BFD_RELOC_ARM_LDR_PC_G0:
18861 case BFD_RELOC_ARM_LDR_PC_G1:
18862 case BFD_RELOC_ARM_LDR_PC_G2:
18863 case BFD_RELOC_ARM_LDR_SB_G0:
18864 case BFD_RELOC_ARM_LDR_SB_G1:
18865 case BFD_RELOC_ARM_LDR_SB_G2:
18866 assert (!fixP->fx_done);
18867 if (!seg->use_rela_p)
18870 bfd_vma addend_abs = abs (value);
18872 /* Check that the absolute value of the addend can be
18873 encoded in 12 bits. */
18874 if (addend_abs >= 0x1000)
18875 as_bad_where (fixP->fx_file, fixP->fx_line,
18876 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18877 (unsigned long) addend_abs);
18879 /* Extract the instruction. */
18880 insn = md_chars_to_number (buf, INSN_SIZE);
18882 /* If the addend is negative, clear bit 23 of the instruction.
18883 Otherwise set it. */
18885 insn &= ~(1 << 23);
18889 /* Place the absolute value of the addend into the first 12 bits
18890 of the instruction. */
18891 insn &= 0xfffff000;
18892 insn |= addend_abs;
18894 /* Update the instruction. */
18895 md_number_to_chars (buf, insn, INSN_SIZE);
18899 case BFD_RELOC_ARM_LDRS_PC_G0:
18900 case BFD_RELOC_ARM_LDRS_PC_G1:
18901 case BFD_RELOC_ARM_LDRS_PC_G2:
18902 case BFD_RELOC_ARM_LDRS_SB_G0:
18903 case BFD_RELOC_ARM_LDRS_SB_G1:
18904 case BFD_RELOC_ARM_LDRS_SB_G2:
18905 assert (!fixP->fx_done);
18906 if (!seg->use_rela_p)
18909 bfd_vma addend_abs = abs (value);
18911 /* Check that the absolute value of the addend can be
18912 encoded in 8 bits. */
18913 if (addend_abs >= 0x100)
18914 as_bad_where (fixP->fx_file, fixP->fx_line,
18915 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18916 (unsigned long) addend_abs);
18918 /* Extract the instruction. */
18919 insn = md_chars_to_number (buf, INSN_SIZE);
18921 /* If the addend is negative, clear bit 23 of the instruction.
18922 Otherwise set it. */
18924 insn &= ~(1 << 23);
18928 /* Place the first four bits of the absolute value of the addend
18929 into the first 4 bits of the instruction, and the remaining
18930 four into bits 8 .. 11. */
18931 insn &= 0xfffff0f0;
18932 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
18934 /* Update the instruction. */
18935 md_number_to_chars (buf, insn, INSN_SIZE);
18939 case BFD_RELOC_ARM_LDC_PC_G0:
18940 case BFD_RELOC_ARM_LDC_PC_G1:
18941 case BFD_RELOC_ARM_LDC_PC_G2:
18942 case BFD_RELOC_ARM_LDC_SB_G0:
18943 case BFD_RELOC_ARM_LDC_SB_G1:
18944 case BFD_RELOC_ARM_LDC_SB_G2:
18945 assert (!fixP->fx_done);
18946 if (!seg->use_rela_p)
18949 bfd_vma addend_abs = abs (value);
18951 /* Check that the absolute value of the addend is a multiple of
18952 four and, when divided by four, fits in 8 bits. */
18953 if (addend_abs & 0x3)
18954 as_bad_where (fixP->fx_file, fixP->fx_line,
18955 _("bad offset 0x%08lX (must be word-aligned)"),
18956 (unsigned long) addend_abs);
18958 if ((addend_abs >> 2) > 0xff)
18959 as_bad_where (fixP->fx_file, fixP->fx_line,
18960 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18961 (unsigned long) addend_abs);
18963 /* Extract the instruction. */
18964 insn = md_chars_to_number (buf, INSN_SIZE);
18966 /* If the addend is negative, clear bit 23 of the instruction.
18967 Otherwise set it. */
18969 insn &= ~(1 << 23);
18973 /* Place the addend (divided by four) into the first eight
18974 bits of the instruction. */
18975 insn &= 0xfffffff0;
18976 insn |= addend_abs >> 2;
18978 /* Update the instruction. */
18979 md_number_to_chars (buf, insn, INSN_SIZE);
18983 case BFD_RELOC_UNUSED:
18985 as_bad_where (fixP->fx_file, fixP->fx_line,
18986 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
18990 /* Translate internal representation of relocation info to BFD target
18994 tc_gen_reloc (asection *section, fixS *fixp)
18997 bfd_reloc_code_real_type code;
18999 reloc = xmalloc (sizeof (arelent));
19001 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
19002 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
19003 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
19005 if (fixp->fx_pcrel)
19007 if (section->use_rela_p)
19008 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
19010 fixp->fx_offset = reloc->address;
19012 reloc->addend = fixp->fx_offset;
19014 switch (fixp->fx_r_type)
19017 if (fixp->fx_pcrel)
19019 code = BFD_RELOC_8_PCREL;
19024 if (fixp->fx_pcrel)
19026 code = BFD_RELOC_16_PCREL;
19031 if (fixp->fx_pcrel)
19033 code = BFD_RELOC_32_PCREL;
19037 case BFD_RELOC_ARM_MOVW:
19038 if (fixp->fx_pcrel)
19040 code = BFD_RELOC_ARM_MOVW_PCREL;
19044 case BFD_RELOC_ARM_MOVT:
19045 if (fixp->fx_pcrel)
19047 code = BFD_RELOC_ARM_MOVT_PCREL;
19051 case BFD_RELOC_ARM_THUMB_MOVW:
19052 if (fixp->fx_pcrel)
19054 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
19058 case BFD_RELOC_ARM_THUMB_MOVT:
19059 if (fixp->fx_pcrel)
19061 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
19065 case BFD_RELOC_NONE:
19066 case BFD_RELOC_ARM_PCREL_BRANCH:
19067 case BFD_RELOC_ARM_PCREL_BLX:
19068 case BFD_RELOC_RVA:
19069 case BFD_RELOC_THUMB_PCREL_BRANCH7:
19070 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19071 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19072 case BFD_RELOC_THUMB_PCREL_BRANCH20:
19073 case BFD_RELOC_THUMB_PCREL_BRANCH23:
19074 case BFD_RELOC_THUMB_PCREL_BRANCH25:
19075 case BFD_RELOC_THUMB_PCREL_BLX:
19076 case BFD_RELOC_VTABLE_ENTRY:
19077 case BFD_RELOC_VTABLE_INHERIT:
19079 case BFD_RELOC_32_SECREL:
19081 code = fixp->fx_r_type;
19084 case BFD_RELOC_ARM_LITERAL:
19085 case BFD_RELOC_ARM_HWLITERAL:
19086 /* If this is called then the a literal has
19087 been referenced across a section boundary. */
19088 as_bad_where (fixp->fx_file, fixp->fx_line,
19089 _("literal referenced across section boundary"));
19093 case BFD_RELOC_ARM_GOT32:
19094 case BFD_RELOC_ARM_GOTOFF:
19095 case BFD_RELOC_ARM_PLT32:
19096 case BFD_RELOC_ARM_TARGET1:
19097 case BFD_RELOC_ARM_ROSEGREL32:
19098 case BFD_RELOC_ARM_SBREL32:
19099 case BFD_RELOC_ARM_PREL31:
19100 case BFD_RELOC_ARM_TARGET2:
19101 case BFD_RELOC_ARM_TLS_LE32:
19102 case BFD_RELOC_ARM_TLS_LDO32:
19103 case BFD_RELOC_ARM_PCREL_CALL:
19104 case BFD_RELOC_ARM_PCREL_JUMP:
19105 case BFD_RELOC_ARM_ALU_PC_G0_NC:
19106 case BFD_RELOC_ARM_ALU_PC_G0:
19107 case BFD_RELOC_ARM_ALU_PC_G1_NC:
19108 case BFD_RELOC_ARM_ALU_PC_G1:
19109 case BFD_RELOC_ARM_ALU_PC_G2:
19110 case BFD_RELOC_ARM_LDR_PC_G0:
19111 case BFD_RELOC_ARM_LDR_PC_G1:
19112 case BFD_RELOC_ARM_LDR_PC_G2:
19113 case BFD_RELOC_ARM_LDRS_PC_G0:
19114 case BFD_RELOC_ARM_LDRS_PC_G1:
19115 case BFD_RELOC_ARM_LDRS_PC_G2:
19116 case BFD_RELOC_ARM_LDC_PC_G0:
19117 case BFD_RELOC_ARM_LDC_PC_G1:
19118 case BFD_RELOC_ARM_LDC_PC_G2:
19119 case BFD_RELOC_ARM_ALU_SB_G0_NC:
19120 case BFD_RELOC_ARM_ALU_SB_G0:
19121 case BFD_RELOC_ARM_ALU_SB_G1_NC:
19122 case BFD_RELOC_ARM_ALU_SB_G1:
19123 case BFD_RELOC_ARM_ALU_SB_G2:
19124 case BFD_RELOC_ARM_LDR_SB_G0:
19125 case BFD_RELOC_ARM_LDR_SB_G1:
19126 case BFD_RELOC_ARM_LDR_SB_G2:
19127 case BFD_RELOC_ARM_LDRS_SB_G0:
19128 case BFD_RELOC_ARM_LDRS_SB_G1:
19129 case BFD_RELOC_ARM_LDRS_SB_G2:
19130 case BFD_RELOC_ARM_LDC_SB_G0:
19131 case BFD_RELOC_ARM_LDC_SB_G1:
19132 case BFD_RELOC_ARM_LDC_SB_G2:
19133 code = fixp->fx_r_type;
19136 case BFD_RELOC_ARM_TLS_GD32:
19137 case BFD_RELOC_ARM_TLS_IE32:
19138 case BFD_RELOC_ARM_TLS_LDM32:
19139 /* BFD will include the symbol's address in the addend.
19140 But we don't want that, so subtract it out again here. */
19141 if (!S_IS_COMMON (fixp->fx_addsy))
19142 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
19143 code = fixp->fx_r_type;
19147 case BFD_RELOC_ARM_IMMEDIATE:
19148 as_bad_where (fixp->fx_file, fixp->fx_line,
19149 _("internal relocation (type: IMMEDIATE) not fixed up"));
19152 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
19153 as_bad_where (fixp->fx_file, fixp->fx_line,
19154 _("ADRL used for a symbol not defined in the same file"));
19157 case BFD_RELOC_ARM_OFFSET_IMM:
19158 if (section->use_rela_p)
19160 code = fixp->fx_r_type;
19164 if (fixp->fx_addsy != NULL
19165 && !S_IS_DEFINED (fixp->fx_addsy)
19166 && S_IS_LOCAL (fixp->fx_addsy))
19168 as_bad_where (fixp->fx_file, fixp->fx_line,
19169 _("undefined local label `%s'"),
19170 S_GET_NAME (fixp->fx_addsy));
19174 as_bad_where (fixp->fx_file, fixp->fx_line,
19175 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19182 switch (fixp->fx_r_type)
19184 case BFD_RELOC_NONE: type = "NONE"; break;
19185 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
19186 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
19187 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
19188 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
19189 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
19190 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
19191 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
19192 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
19193 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
19194 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
19195 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
19196 default: type = _("<unknown>"); break;
19198 as_bad_where (fixp->fx_file, fixp->fx_line,
19199 _("cannot represent %s relocation in this object file format"),
19206 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
19208 && fixp->fx_addsy == GOT_symbol)
19210 code = BFD_RELOC_ARM_GOTPC;
19211 reloc->addend = fixp->fx_offset = reloc->address;
19215 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
19217 if (reloc->howto == NULL)
19219 as_bad_where (fixp->fx_file, fixp->fx_line,
19220 _("cannot represent %s relocation in this object file format"),
19221 bfd_get_reloc_code_name (code));
19225 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19226 vtable entry to be used in the relocation's section offset. */
19227 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19228 reloc->address = fixp->fx_offset;
19233 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19236 cons_fix_new_arm (fragS * frag,
19241 bfd_reloc_code_real_type type;
19245 FIXME: @@ Should look at CPU word size. */
19249 type = BFD_RELOC_8;
19252 type = BFD_RELOC_16;
19256 type = BFD_RELOC_32;
19259 type = BFD_RELOC_64;
19264 if (exp->X_op == O_secrel)
19266 exp->X_op = O_symbol;
19267 type = BFD_RELOC_32_SECREL;
19271 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
19274 #if defined OBJ_COFF || defined OBJ_ELF
19276 arm_validate_fix (fixS * fixP)
19278 /* If the destination of the branch is a defined symbol which does not have
19279 the THUMB_FUNC attribute, then we must be calling a function which has
19280 the (interfacearm) attribute. We look for the Thumb entry point to that
19281 function and change the branch to refer to that function instead. */
19282 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
19283 && fixP->fx_addsy != NULL
19284 && S_IS_DEFINED (fixP->fx_addsy)
19285 && ! THUMB_IS_FUNC (fixP->fx_addsy))
19287 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
19293 arm_force_relocation (struct fix * fixp)
19295 #if defined (OBJ_COFF) && defined (TE_PE)
19296 if (fixp->fx_r_type == BFD_RELOC_RVA)
19300 /* Resolve these relocations even if the symbol is extern or weak. */
19301 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
19302 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
19303 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
19304 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
19305 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
19306 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
19307 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
19310 /* Always leave these relocations for the linker. */
19311 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19312 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19313 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19316 /* Always generate relocations against function symbols. */
19317 if (fixp->fx_r_type == BFD_RELOC_32
19319 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
19322 return generic_force_reloc (fixp);
19325 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19326 /* Relocations against function names must be left unadjusted,
19327 so that the linker can use this information to generate interworking
19328 stubs. The MIPS version of this function
19329 also prevents relocations that are mips-16 specific, but I do not
19330 know why it does this.
19333 There is one other problem that ought to be addressed here, but
19334 which currently is not: Taking the address of a label (rather
19335 than a function) and then later jumping to that address. Such
19336 addresses also ought to have their bottom bit set (assuming that
19337 they reside in Thumb code), but at the moment they will not. */
19340 arm_fix_adjustable (fixS * fixP)
19342 if (fixP->fx_addsy == NULL)
19345 /* Preserve relocations against symbols with function type. */
19346 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
19349 if (THUMB_IS_FUNC (fixP->fx_addsy)
19350 && fixP->fx_subsy == NULL)
19353 /* We need the symbol name for the VTABLE entries. */
19354 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
19355 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19358 /* Don't allow symbols to be discarded on GOT related relocs. */
19359 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
19360 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
19361 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
19362 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
19363 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
19364 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
19365 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
19366 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
19367 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
19370 /* Similarly for group relocations. */
19371 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19372 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19373 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19376 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
19377 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
19378 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
19379 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
19384 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19389 elf32_arm_target_format (void)
19392 return (target_big_endian
19393 ? "elf32-bigarm-symbian"
19394 : "elf32-littlearm-symbian");
19395 #elif defined (TE_VXWORKS)
19396 return (target_big_endian
19397 ? "elf32-bigarm-vxworks"
19398 : "elf32-littlearm-vxworks");
19400 if (target_big_endian)
19401 return "elf32-bigarm";
19403 return "elf32-littlearm";
19408 armelf_frob_symbol (symbolS * symp,
19411 elf_frob_symbol (symp, puntp);
19415 /* MD interface: Finalization. */
19417 /* A good place to do this, although this was probably not intended
19418 for this kind of use. We need to dump the literal pool before
19419 references are made to a null symbol pointer. */
19424 literal_pool * pool;
19426 for (pool = list_of_pools; pool; pool = pool->next)
19428 /* Put it at the end of the relevent section. */
19429 subseg_set (pool->section, pool->sub_section);
19431 arm_elf_change_section ();
19437 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19441 arm_adjust_symtab (void)
19446 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19448 if (ARM_IS_THUMB (sym))
19450 if (THUMB_IS_FUNC (sym))
19452 /* Mark the symbol as a Thumb function. */
19453 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
19454 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
19455 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
19457 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
19458 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
19460 as_bad (_("%s: unexpected function type: %d"),
19461 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
19463 else switch (S_GET_STORAGE_CLASS (sym))
19466 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
19469 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
19472 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
19480 if (ARM_IS_INTERWORK (sym))
19481 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
19488 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19490 if (ARM_IS_THUMB (sym))
19492 elf_symbol_type * elf_sym;
19494 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
19495 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
19497 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
19498 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
19500 /* If it's a .thumb_func, declare it as so,
19501 otherwise tag label as .code 16. */
19502 if (THUMB_IS_FUNC (sym))
19503 elf_sym->internal_elf_sym.st_info =
19504 ELF_ST_INFO (bind, STT_ARM_TFUNC);
19505 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
19506 elf_sym->internal_elf_sym.st_info =
19507 ELF_ST_INFO (bind, STT_ARM_16BIT);
19514 /* MD interface: Initialization. */
19517 set_constant_flonums (void)
19521 for (i = 0; i < NUM_FLOAT_VALS; i++)
19522 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
19526 /* Auto-select Thumb mode if it's the only available instruction set for the
19527 given architecture. */
19530 autoselect_thumb_from_cpu_variant (void)
19532 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
19533 opcode_select (16);
19542 if ( (arm_ops_hsh = hash_new ()) == NULL
19543 || (arm_cond_hsh = hash_new ()) == NULL
19544 || (arm_shift_hsh = hash_new ()) == NULL
19545 || (arm_psr_hsh = hash_new ()) == NULL
19546 || (arm_v7m_psr_hsh = hash_new ()) == NULL
19547 || (arm_reg_hsh = hash_new ()) == NULL
19548 || (arm_reloc_hsh = hash_new ()) == NULL
19549 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
19550 as_fatal (_("virtual memory exhausted"));
19552 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
19553 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
19554 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
19555 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
19556 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
19557 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
19558 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
19559 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
19560 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
19561 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
19562 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
19563 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
19565 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
19567 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
19568 (PTR) (barrier_opt_names + i));
19570 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
19571 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
19574 set_constant_flonums ();
19576 /* Set the cpu variant based on the command-line options. We prefer
19577 -mcpu= over -march= if both are set (as for GCC); and we prefer
19578 -mfpu= over any other way of setting the floating point unit.
19579 Use of legacy options with new options are faulted. */
19582 if (mcpu_cpu_opt || march_cpu_opt)
19583 as_bad (_("use of old and new-style options to set CPU type"));
19585 mcpu_cpu_opt = legacy_cpu;
19587 else if (!mcpu_cpu_opt)
19588 mcpu_cpu_opt = march_cpu_opt;
19593 as_bad (_("use of old and new-style options to set FPU type"));
19595 mfpu_opt = legacy_fpu;
19597 else if (!mfpu_opt)
19599 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19600 /* Some environments specify a default FPU. If they don't, infer it
19601 from the processor. */
19603 mfpu_opt = mcpu_fpu_opt;
19605 mfpu_opt = march_fpu_opt;
19607 mfpu_opt = &fpu_default;
19613 if (mcpu_cpu_opt != NULL)
19614 mfpu_opt = &fpu_default;
19615 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
19616 mfpu_opt = &fpu_arch_vfp_v2;
19618 mfpu_opt = &fpu_arch_fpa;
19624 mcpu_cpu_opt = &cpu_default;
19625 selected_cpu = cpu_default;
19629 selected_cpu = *mcpu_cpu_opt;
19631 mcpu_cpu_opt = &arm_arch_any;
19634 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
19636 autoselect_thumb_from_cpu_variant ();
19638 arm_arch_used = thumb_arch_used = arm_arch_none;
19640 #if defined OBJ_COFF || defined OBJ_ELF
19642 unsigned int flags = 0;
19644 #if defined OBJ_ELF
19645 flags = meabi_flags;
19647 switch (meabi_flags)
19649 case EF_ARM_EABI_UNKNOWN:
19651 /* Set the flags in the private structure. */
19652 if (uses_apcs_26) flags |= F_APCS26;
19653 if (support_interwork) flags |= F_INTERWORK;
19654 if (uses_apcs_float) flags |= F_APCS_FLOAT;
19655 if (pic_code) flags |= F_PIC;
19656 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
19657 flags |= F_SOFT_FLOAT;
19659 switch (mfloat_abi_opt)
19661 case ARM_FLOAT_ABI_SOFT:
19662 case ARM_FLOAT_ABI_SOFTFP:
19663 flags |= F_SOFT_FLOAT;
19666 case ARM_FLOAT_ABI_HARD:
19667 if (flags & F_SOFT_FLOAT)
19668 as_bad (_("hard-float conflicts with specified fpu"));
19672 /* Using pure-endian doubles (even if soft-float). */
19673 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
19674 flags |= F_VFP_FLOAT;
19676 #if defined OBJ_ELF
19677 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
19678 flags |= EF_ARM_MAVERICK_FLOAT;
19681 case EF_ARM_EABI_VER4:
19682 case EF_ARM_EABI_VER5:
19683 /* No additional flags to set. */
19690 bfd_set_private_flags (stdoutput, flags);
19692 /* We have run out flags in the COFF header to encode the
19693 status of ATPCS support, so instead we create a dummy,
19694 empty, debug section called .arm.atpcs. */
19699 sec = bfd_make_section (stdoutput, ".arm.atpcs");
19703 bfd_set_section_flags
19704 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
19705 bfd_set_section_size (stdoutput, sec, 0);
19706 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
19712 /* Record the CPU type as well. */
19713 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
19714 mach = bfd_mach_arm_iWMMXt2;
19715 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
19716 mach = bfd_mach_arm_iWMMXt;
19717 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
19718 mach = bfd_mach_arm_XScale;
19719 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
19720 mach = bfd_mach_arm_ep9312;
19721 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
19722 mach = bfd_mach_arm_5TE;
19723 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
19725 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19726 mach = bfd_mach_arm_5T;
19728 mach = bfd_mach_arm_5;
19730 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
19732 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19733 mach = bfd_mach_arm_4T;
19735 mach = bfd_mach_arm_4;
19737 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
19738 mach = bfd_mach_arm_3M;
19739 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
19740 mach = bfd_mach_arm_3;
19741 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
19742 mach = bfd_mach_arm_2a;
19743 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
19744 mach = bfd_mach_arm_2;
19746 mach = bfd_mach_arm_unknown;
19748 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
19751 /* Command line processing. */
19754 Invocation line includes a switch not recognized by the base assembler.
19755 See if it's a processor-specific option.
19757 This routine is somewhat complicated by the need for backwards
19758 compatibility (since older releases of gcc can't be changed).
19759 The new options try to make the interface as compatible as
19762 New options (supported) are:
19764 -mcpu=<cpu name> Assemble for selected processor
19765 -march=<architecture name> Assemble for selected architecture
19766 -mfpu=<fpu architecture> Assemble for selected FPU.
19767 -EB/-mbig-endian Big-endian
19768 -EL/-mlittle-endian Little-endian
19769 -k Generate PIC code
19770 -mthumb Start in Thumb mode
19771 -mthumb-interwork Code supports ARM/Thumb interworking
19773 For now we will also provide support for:
19775 -mapcs-32 32-bit Program counter
19776 -mapcs-26 26-bit Program counter
19777 -macps-float Floats passed in FP registers
19778 -mapcs-reentrant Reentrant code
19780 (sometime these will probably be replaced with -mapcs=<list of options>
19781 and -matpcs=<list of options>)
19783 The remaining options are only supported for back-wards compatibility.
19784 Cpu variants, the arm part is optional:
19785 -m[arm]1 Currently not supported.
19786 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19787 -m[arm]3 Arm 3 processor
19788 -m[arm]6[xx], Arm 6 processors
19789 -m[arm]7[xx][t][[d]m] Arm 7 processors
19790 -m[arm]8[10] Arm 8 processors
19791 -m[arm]9[20][tdmi] Arm 9 processors
19792 -mstrongarm[110[0]] StrongARM processors
19793 -mxscale XScale processors
19794 -m[arm]v[2345[t[e]]] Arm architectures
19795 -mall All (except the ARM1)
19797 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19798 -mfpe-old (No float load/store multiples)
19799 -mvfpxd VFP Single precision
19801 -mno-fpu Disable all floating point instructions
19803 The following CPU names are recognized:
19804 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19805 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19806 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19807 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19808 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19809 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19810 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19814 const char * md_shortopts = "m:k";
19816 #ifdef ARM_BI_ENDIAN
19817 #define OPTION_EB (OPTION_MD_BASE + 0)
19818 #define OPTION_EL (OPTION_MD_BASE + 1)
19820 #if TARGET_BYTES_BIG_ENDIAN
19821 #define OPTION_EB (OPTION_MD_BASE + 0)
19823 #define OPTION_EL (OPTION_MD_BASE + 1)
19827 struct option md_longopts[] =
19830 {"EB", no_argument, NULL, OPTION_EB},
19833 {"EL", no_argument, NULL, OPTION_EL},
19835 {NULL, no_argument, NULL, 0}
19838 size_t md_longopts_size = sizeof (md_longopts);
19840 struct arm_option_table
19842 char *option; /* Option name to match. */
19843 char *help; /* Help information. */
19844 int *var; /* Variable to change. */
19845 int value; /* What to change it to. */
19846 char *deprecated; /* If non-null, print this message. */
19849 struct arm_option_table arm_opts[] =
19851 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
19852 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
19853 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19854 &support_interwork, 1, NULL},
19855 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
19856 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
19857 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
19859 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
19860 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
19861 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
19862 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
19865 /* These are recognized by the assembler, but have no affect on code. */
19866 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
19867 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
19868 {NULL, NULL, NULL, 0, NULL}
19871 struct arm_legacy_option_table
19873 char *option; /* Option name to match. */
19874 const arm_feature_set **var; /* Variable to change. */
19875 const arm_feature_set value; /* What to change it to. */
19876 char *deprecated; /* If non-null, print this message. */
19879 const struct arm_legacy_option_table arm_legacy_opts[] =
19881 /* DON'T add any new processors to this list -- we want the whole list
19882 to go away... Add them to the processors table instead. */
19883 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19884 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19885 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19886 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19887 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19888 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19889 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19890 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19891 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19892 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19893 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19894 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19895 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19896 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19897 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19898 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19899 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19900 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19901 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19902 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19903 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19904 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19905 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19906 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19907 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19908 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19909 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19910 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19911 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19912 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19913 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19914 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19915 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19916 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19917 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19918 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19919 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19920 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19921 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19922 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19923 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19924 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19925 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19926 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19927 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19928 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19929 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19930 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19931 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19932 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19933 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19934 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19935 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19936 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19937 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19938 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19939 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19940 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19941 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19942 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19943 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19944 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19945 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19946 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19947 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19948 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19949 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19950 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19951 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
19952 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
19953 N_("use -mcpu=strongarm110")},
19954 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
19955 N_("use -mcpu=strongarm1100")},
19956 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
19957 N_("use -mcpu=strongarm1110")},
19958 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
19959 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
19960 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
19962 /* Architecture variants -- don't add any more to this list either. */
19963 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19964 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19965 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19966 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19967 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19968 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19969 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19970 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19971 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19972 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19973 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19974 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19975 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19976 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19977 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19978 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19979 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19980 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19982 /* Floating point variants -- don't add any more to this list either. */
19983 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
19984 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
19985 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
19986 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
19987 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19989 {NULL, NULL, ARM_ARCH_NONE, NULL}
19992 struct arm_cpu_option_table
19995 const arm_feature_set value;
19996 /* For some CPUs we assume an FPU unless the user explicitly sets
19998 const arm_feature_set default_fpu;
19999 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20001 const char *canonical_name;
20004 /* This list should, at a minimum, contain all the cpu names
20005 recognized by GCC. */
20006 static const struct arm_cpu_option_table arm_cpus[] =
20008 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
20009 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
20010 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
20011 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
20012 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
20013 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20014 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20015 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20016 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20017 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20018 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20019 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20020 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20021 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20022 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20023 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20024 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20025 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20026 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20027 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20028 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20029 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20030 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20031 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20032 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20033 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20034 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20035 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20036 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20037 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20038 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20039 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20040 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20041 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20042 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20043 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20044 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20045 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20046 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20047 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
20048 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20049 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20050 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20051 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20052 /* For V5 or later processors we default to using VFP; but the user
20053 should really set the FPU type explicitly. */
20054 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20055 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20056 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20057 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20058 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
20059 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20060 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
20061 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20062 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20063 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
20064 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20065 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20066 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20067 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20068 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20069 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
20070 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20071 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20072 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20073 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
20074 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
20075 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
20076 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
20077 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
20078 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
20079 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
20080 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
20081 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
20082 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
20083 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
20084 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
20085 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20086 | FPU_NEON_EXT_V1),
20088 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20089 | FPU_NEON_EXT_V1),
20091 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL},
20092 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL},
20093 /* ??? XSCALE is really an architecture. */
20094 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
20095 /* ??? iwmmxt is not a processor. */
20096 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
20097 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
20098 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
20100 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
20101 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
20104 struct arm_arch_option_table
20107 const arm_feature_set value;
20108 const arm_feature_set default_fpu;
20111 /* This list should, at a minimum, contain all the architecture names
20112 recognized by GCC. */
20113 static const struct arm_arch_option_table arm_archs[] =
20115 {"all", ARM_ANY, FPU_ARCH_FPA},
20116 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
20117 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
20118 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
20119 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
20120 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
20121 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
20122 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
20123 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
20124 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
20125 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
20126 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
20127 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
20128 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
20129 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
20130 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
20131 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
20132 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
20133 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
20134 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
20135 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
20136 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
20137 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
20138 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
20139 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
20140 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
20141 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
20142 /* The official spelling of the ARMv7 profile variants is the dashed form.
20143 Accept the non-dashed form for compatibility with old toolchains. */
20144 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
20145 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
20146 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
20147 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
20148 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
20149 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
20150 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
20151 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
20152 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
20153 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
20156 /* ISA extensions in the co-processor space. */
20157 struct arm_option_cpu_value_table
20160 const arm_feature_set value;
20163 static const struct arm_option_cpu_value_table arm_extensions[] =
20165 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
20166 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
20167 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
20168 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
20169 {"sec", ARM_FEATURE (ARM_EXT_V6Z, 0)},
20170 {NULL, ARM_ARCH_NONE}
20173 /* This list should, at a minimum, contain all the fpu names
20174 recognized by GCC. */
20175 static const struct arm_option_cpu_value_table arm_fpus[] =
20177 {"softfpa", FPU_NONE},
20178 {"fpe", FPU_ARCH_FPE},
20179 {"fpe2", FPU_ARCH_FPE},
20180 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
20181 {"fpa", FPU_ARCH_FPA},
20182 {"fpa10", FPU_ARCH_FPA},
20183 {"fpa11", FPU_ARCH_FPA},
20184 {"arm7500fe", FPU_ARCH_FPA},
20185 {"softvfp", FPU_ARCH_VFP},
20186 {"softvfp+vfp", FPU_ARCH_VFP_V2},
20187 {"vfp", FPU_ARCH_VFP_V2},
20188 {"vfpv2", FPU_ARCH_VFP_V2},
20189 {"vfp9", FPU_ARCH_VFP_V2},
20190 {"vfp3", FPU_ARCH_VFP_V3},
20191 {"vfpv3", FPU_ARCH_VFP_V3},
20192 {"vfp10", FPU_ARCH_VFP_V2},
20193 {"vfp10-r0", FPU_ARCH_VFP_V1},
20194 {"vfpxd", FPU_ARCH_VFP_V1xD},
20195 {"arm1020t", FPU_ARCH_VFP_V1},
20196 {"arm1020e", FPU_ARCH_VFP_V2},
20197 {"arm1136jfs", FPU_ARCH_VFP_V2},
20198 {"arm1136jf-s", FPU_ARCH_VFP_V2},
20199 {"maverick", FPU_ARCH_MAVERICK},
20200 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
20201 {NULL, ARM_ARCH_NONE}
20204 struct arm_option_value_table
20210 static const struct arm_option_value_table arm_float_abis[] =
20212 {"hard", ARM_FLOAT_ABI_HARD},
20213 {"softfp", ARM_FLOAT_ABI_SOFTFP},
20214 {"soft", ARM_FLOAT_ABI_SOFT},
20219 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20220 static const struct arm_option_value_table arm_eabis[] =
20222 {"gnu", EF_ARM_EABI_UNKNOWN},
20223 {"4", EF_ARM_EABI_VER4},
20224 {"5", EF_ARM_EABI_VER5},
20229 struct arm_long_option_table
20231 char * option; /* Substring to match. */
20232 char * help; /* Help information. */
20233 int (* func) (char * subopt); /* Function to decode sub-option. */
20234 char * deprecated; /* If non-null, print this message. */
20238 arm_parse_extension (char * str, const arm_feature_set **opt_p)
20240 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
20242 /* Copy the feature set, so that we can modify it. */
20243 *ext_set = **opt_p;
20246 while (str != NULL && *str != 0)
20248 const struct arm_option_cpu_value_table * opt;
20254 as_bad (_("invalid architectural extension"));
20259 ext = strchr (str, '+');
20262 optlen = ext - str;
20264 optlen = strlen (str);
20268 as_bad (_("missing architectural extension"));
20272 for (opt = arm_extensions; opt->name != NULL; opt++)
20273 if (strncmp (opt->name, str, optlen) == 0)
20275 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
20279 if (opt->name == NULL)
20281 as_bad (_("unknown architectural extnsion `%s'"), str);
20292 arm_parse_cpu (char * str)
20294 const struct arm_cpu_option_table * opt;
20295 char * ext = strchr (str, '+');
20299 optlen = ext - str;
20301 optlen = strlen (str);
20305 as_bad (_("missing cpu name `%s'"), str);
20309 for (opt = arm_cpus; opt->name != NULL; opt++)
20310 if (strncmp (opt->name, str, optlen) == 0)
20312 mcpu_cpu_opt = &opt->value;
20313 mcpu_fpu_opt = &opt->default_fpu;
20314 if (opt->canonical_name)
20315 strcpy(selected_cpu_name, opt->canonical_name);
20319 for (i = 0; i < optlen; i++)
20320 selected_cpu_name[i] = TOUPPER (opt->name[i]);
20321 selected_cpu_name[i] = 0;
20325 return arm_parse_extension (ext, &mcpu_cpu_opt);
20330 as_bad (_("unknown cpu `%s'"), str);
20335 arm_parse_arch (char * str)
20337 const struct arm_arch_option_table *opt;
20338 char *ext = strchr (str, '+');
20342 optlen = ext - str;
20344 optlen = strlen (str);
20348 as_bad (_("missing architecture name `%s'"), str);
20352 for (opt = arm_archs; opt->name != NULL; opt++)
20353 if (strncmp (opt->name, str, optlen) == 0)
20355 march_cpu_opt = &opt->value;
20356 march_fpu_opt = &opt->default_fpu;
20357 strcpy(selected_cpu_name, opt->name);
20360 return arm_parse_extension (ext, &march_cpu_opt);
20365 as_bad (_("unknown architecture `%s'\n"), str);
20370 arm_parse_fpu (char * str)
20372 const struct arm_option_cpu_value_table * opt;
20374 for (opt = arm_fpus; opt->name != NULL; opt++)
20375 if (streq (opt->name, str))
20377 mfpu_opt = &opt->value;
20381 as_bad (_("unknown floating point format `%s'\n"), str);
20386 arm_parse_float_abi (char * str)
20388 const struct arm_option_value_table * opt;
20390 for (opt = arm_float_abis; opt->name != NULL; opt++)
20391 if (streq (opt->name, str))
20393 mfloat_abi_opt = opt->value;
20397 as_bad (_("unknown floating point abi `%s'\n"), str);
20403 arm_parse_eabi (char * str)
20405 const struct arm_option_value_table *opt;
20407 for (opt = arm_eabis; opt->name != NULL; opt++)
20408 if (streq (opt->name, str))
20410 meabi_flags = opt->value;
20413 as_bad (_("unknown EABI `%s'\n"), str);
20418 struct arm_long_option_table arm_long_opts[] =
20420 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20421 arm_parse_cpu, NULL},
20422 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20423 arm_parse_arch, NULL},
20424 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20425 arm_parse_fpu, NULL},
20426 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20427 arm_parse_float_abi, NULL},
20429 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20430 arm_parse_eabi, NULL},
20432 {NULL, NULL, 0, NULL}
20436 md_parse_option (int c, char * arg)
20438 struct arm_option_table *opt;
20439 const struct arm_legacy_option_table *fopt;
20440 struct arm_long_option_table *lopt;
20446 target_big_endian = 1;
20452 target_big_endian = 0;
20457 /* Listing option. Just ignore these, we don't support additional
20462 for (opt = arm_opts; opt->option != NULL; opt++)
20464 if (c == opt->option[0]
20465 && ((arg == NULL && opt->option[1] == 0)
20466 || streq (arg, opt->option + 1)))
20468 #if WARN_DEPRECATED
20469 /* If the option is deprecated, tell the user. */
20470 if (opt->deprecated != NULL)
20471 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20472 arg ? arg : "", _(opt->deprecated));
20475 if (opt->var != NULL)
20476 *opt->var = opt->value;
20482 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
20484 if (c == fopt->option[0]
20485 && ((arg == NULL && fopt->option[1] == 0)
20486 || streq (arg, fopt->option + 1)))
20488 #if WARN_DEPRECATED
20489 /* If the option is deprecated, tell the user. */
20490 if (fopt->deprecated != NULL)
20491 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20492 arg ? arg : "", _(fopt->deprecated));
20495 if (fopt->var != NULL)
20496 *fopt->var = &fopt->value;
20502 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20504 /* These options are expected to have an argument. */
20505 if (c == lopt->option[0]
20507 && strncmp (arg, lopt->option + 1,
20508 strlen (lopt->option + 1)) == 0)
20510 #if WARN_DEPRECATED
20511 /* If the option is deprecated, tell the user. */
20512 if (lopt->deprecated != NULL)
20513 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
20514 _(lopt->deprecated));
20517 /* Call the sup-option parser. */
20518 return lopt->func (arg + strlen (lopt->option) - 1);
20529 md_show_usage (FILE * fp)
20531 struct arm_option_table *opt;
20532 struct arm_long_option_table *lopt;
20534 fprintf (fp, _(" ARM-specific assembler options:\n"));
20536 for (opt = arm_opts; opt->option != NULL; opt++)
20537 if (opt->help != NULL)
20538 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
20540 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20541 if (lopt->help != NULL)
20542 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
20546 -EB assemble code for a big-endian cpu\n"));
20551 -EL assemble code for a little-endian cpu\n"));
20560 arm_feature_set flags;
20561 } cpu_arch_ver_table;
20563 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20564 least features first. */
20565 static const cpu_arch_ver_table cpu_arch_ver[] =
20570 {4, ARM_ARCH_V5TE},
20571 {5, ARM_ARCH_V5TEJ},
20575 {9, ARM_ARCH_V6T2},
20576 {10, ARM_ARCH_V7A},
20577 {10, ARM_ARCH_V7R},
20578 {10, ARM_ARCH_V7M},
20582 /* Set the public EABI object attributes. */
20584 aeabi_set_public_attributes (void)
20587 arm_feature_set flags;
20588 arm_feature_set tmp;
20589 const cpu_arch_ver_table *p;
20591 /* Choose the architecture based on the capabilities of the requested cpu
20592 (if any) and/or the instructions actually used. */
20593 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
20594 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
20595 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
20596 /*Allow the user to override the reported architecture. */
20599 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
20600 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
20605 for (p = cpu_arch_ver; p->val; p++)
20607 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
20610 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
20614 /* Tag_CPU_name. */
20615 if (selected_cpu_name[0])
20619 p = selected_cpu_name;
20620 if (strncmp(p, "armv", 4) == 0)
20625 for (i = 0; p[i]; i++)
20626 p[i] = TOUPPER (p[i]);
20628 bfd_elf_add_proc_attr_string (stdoutput, 5, p);
20630 /* Tag_CPU_arch. */
20631 bfd_elf_add_proc_attr_int (stdoutput, 6, arch);
20632 /* Tag_CPU_arch_profile. */
20633 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
20634 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');
20635 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
20636 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');
20637 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
20638 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');
20639 /* Tag_ARM_ISA_use. */
20640 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
20641 bfd_elf_add_proc_attr_int (stdoutput, 8, 1);
20642 /* Tag_THUMB_ISA_use. */
20643 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
20644 bfd_elf_add_proc_attr_int (stdoutput, 9,
20645 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
20646 /* Tag_VFP_arch. */
20647 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
20648 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
20649 bfd_elf_add_proc_attr_int (stdoutput, 10, 3);
20650 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
20651 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))
20652 bfd_elf_add_proc_attr_int (stdoutput, 10, 2);
20653 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
20654 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
20655 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
20656 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))
20657 bfd_elf_add_proc_attr_int (stdoutput, 10, 1);
20658 /* Tag_WMMX_arch. */
20659 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
20660 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
20661 bfd_elf_add_proc_attr_int (stdoutput, 11, 1);
20662 /* Tag_NEON_arch. */
20663 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1)
20664 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1))
20665 bfd_elf_add_proc_attr_int (stdoutput, 12, 1);
20668 /* Add the default contents for the .ARM.attributes section. */
20672 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
20675 aeabi_set_public_attributes ();
20677 #endif /* OBJ_ELF */
20680 /* Parse a .cpu directive. */
20683 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
20685 const struct arm_cpu_option_table *opt;
20689 name = input_line_pointer;
20690 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20691 input_line_pointer++;
20692 saved_char = *input_line_pointer;
20693 *input_line_pointer = 0;
20695 /* Skip the first "all" entry. */
20696 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
20697 if (streq (opt->name, name))
20699 mcpu_cpu_opt = &opt->value;
20700 selected_cpu = opt->value;
20701 if (opt->canonical_name)
20702 strcpy(selected_cpu_name, opt->canonical_name);
20706 for (i = 0; opt->name[i]; i++)
20707 selected_cpu_name[i] = TOUPPER (opt->name[i]);
20708 selected_cpu_name[i] = 0;
20710 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20711 *input_line_pointer = saved_char;
20712 demand_empty_rest_of_line ();
20715 as_bad (_("unknown cpu `%s'"), name);
20716 *input_line_pointer = saved_char;
20717 ignore_rest_of_line ();
20721 /* Parse a .arch directive. */
20724 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
20726 const struct arm_arch_option_table *opt;
20730 name = input_line_pointer;
20731 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20732 input_line_pointer++;
20733 saved_char = *input_line_pointer;
20734 *input_line_pointer = 0;
20736 /* Skip the first "all" entry. */
20737 for (opt = arm_archs + 1; opt->name != NULL; opt++)
20738 if (streq (opt->name, name))
20740 mcpu_cpu_opt = &opt->value;
20741 selected_cpu = opt->value;
20742 strcpy(selected_cpu_name, opt->name);
20743 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20744 *input_line_pointer = saved_char;
20745 demand_empty_rest_of_line ();
20749 as_bad (_("unknown architecture `%s'\n"), name);
20750 *input_line_pointer = saved_char;
20751 ignore_rest_of_line ();
20754 /* Parse a .arch_extension directive. */
20757 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
20759 const struct arm_option_cpu_value_table *opt;
20763 name = input_line_pointer;
20764 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20765 input_line_pointer++;
20766 saved_char = *input_line_pointer;
20767 *input_line_pointer = 0;
20769 for (opt = arm_extensions; opt->name != NULL; opt++)
20770 if (streq (opt->name, name))
20772 ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, opt->value);
20773 *input_line_pointer = saved_char;
20774 demand_empty_rest_of_line ();
20778 as_bad (_("unknown architecture `%s'\n"), name);
20779 *input_line_pointer = saved_char;
20780 ignore_rest_of_line ();
20783 /* Parse a .object_arch directive. */
20786 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
20788 const struct arm_arch_option_table *opt;
20792 name = input_line_pointer;
20793 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20794 input_line_pointer++;
20795 saved_char = *input_line_pointer;
20796 *input_line_pointer = 0;
20798 /* Skip the first "all" entry. */
20799 for (opt = arm_archs + 1; opt->name != NULL; opt++)
20800 if (streq (opt->name, name))
20802 object_arch = &opt->value;
20803 *input_line_pointer = saved_char;
20804 demand_empty_rest_of_line ();
20808 as_bad (_("unknown architecture `%s'\n"), name);
20809 *input_line_pointer = saved_char;
20810 ignore_rest_of_line ();
20814 /* Parse a .fpu directive. */
20817 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
20819 const struct arm_option_cpu_value_table *opt;
20823 name = input_line_pointer;
20824 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20825 input_line_pointer++;
20826 saved_char = *input_line_pointer;
20827 *input_line_pointer = 0;
20829 for (opt = arm_fpus; opt->name != NULL; opt++)
20830 if (streq (opt->name, name))
20832 mfpu_opt = &opt->value;
20833 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20834 *input_line_pointer = saved_char;
20835 demand_empty_rest_of_line ();
20839 as_bad (_("unknown floating point format `%s'\n"), name);
20840 *input_line_pointer = saved_char;
20841 ignore_rest_of_line ();
20844 /* Copy symbol information. */
20846 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
20848 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);