1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
27 #include "opcode/mips.h"
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
41 /* Mips instructions are at maximum this many bytes long. */
44 /* Generate Octeon/MIPS unaligned load and store instructions. */
45 #ifdef INCLUDE_OCTEON_USEUN
46 int octeon_use_unalign = 1;
48 int octeon_use_unalign = 0;
52 /* FIXME: These should be shared with gdb somehow. */
54 struct mips_cp0sel_name
58 const char * const name;
61 /* The mips16 registers. */
62 static const unsigned int mips16_to_32_reg_map[] =
64 16, 17, 2, 3, 4, 5, 6, 7
67 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
70 static const char * const mips_gpr_names_numeric[32] =
72 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
73 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
74 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
75 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
78 static const char * const mips_gpr_names_oldabi[32] =
80 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
81 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
82 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
83 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
86 static const char * const mips_gpr_names_newabi[32] =
88 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
89 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
90 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
91 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
94 static const char * const mips_fpr_names_numeric[32] =
96 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
97 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
98 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
99 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
102 static const char * const mips_fpr_names_32[32] =
104 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
105 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
106 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
107 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
110 static const char * const mips_fpr_names_n32[32] =
112 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
113 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
114 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
115 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
118 static const char * const mips_fpr_names_64[32] =
120 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
121 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
122 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
123 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
126 static const char * const mips_cp0_names_numeric[32] =
128 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
129 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
130 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
131 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
134 static const char * const mips_cp0_names_mips3264[32] =
136 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
137 "c0_context", "c0_pagemask", "c0_wired", "$7",
138 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
139 "c0_status", "c0_cause", "c0_epc", "c0_prid",
140 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
141 "c0_xcontext", "$21", "$22", "c0_debug",
142 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
143 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
146 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
148 { 16, 1, "c0_config1" },
149 { 16, 2, "c0_config2" },
150 { 16, 3, "c0_config3" },
151 { 18, 1, "c0_watchlo,1" },
152 { 18, 2, "c0_watchlo,2" },
153 { 18, 3, "c0_watchlo,3" },
154 { 18, 4, "c0_watchlo,4" },
155 { 18, 5, "c0_watchlo,5" },
156 { 18, 6, "c0_watchlo,6" },
157 { 18, 7, "c0_watchlo,7" },
158 { 19, 1, "c0_watchhi,1" },
159 { 19, 2, "c0_watchhi,2" },
160 { 19, 3, "c0_watchhi,3" },
161 { 19, 4, "c0_watchhi,4" },
162 { 19, 5, "c0_watchhi,5" },
163 { 19, 6, "c0_watchhi,6" },
164 { 19, 7, "c0_watchhi,7" },
165 { 25, 1, "c0_perfcnt,1" },
166 { 25, 2, "c0_perfcnt,2" },
167 { 25, 3, "c0_perfcnt,3" },
168 { 25, 4, "c0_perfcnt,4" },
169 { 25, 5, "c0_perfcnt,5" },
170 { 25, 6, "c0_perfcnt,6" },
171 { 25, 7, "c0_perfcnt,7" },
172 { 27, 1, "c0_cacheerr,1" },
173 { 27, 2, "c0_cacheerr,2" },
174 { 27, 3, "c0_cacheerr,3" },
175 { 28, 1, "c0_datalo" },
176 { 29, 1, "c0_datahi" }
179 static const char * const mips_cp0_names_mips3264r2[32] =
181 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
182 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
183 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
184 "c0_status", "c0_cause", "c0_epc", "c0_prid",
185 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
186 "c0_xcontext", "$21", "$22", "c0_debug",
187 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
188 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
191 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
193 { 4, 1, "c0_contextconfig" },
194 { 0, 1, "c0_mvpcontrol" },
195 { 0, 2, "c0_mvpconf0" },
196 { 0, 3, "c0_mvpconf1" },
197 { 1, 1, "c0_vpecontrol" },
198 { 1, 2, "c0_vpeconf0" },
199 { 1, 3, "c0_vpeconf1" },
200 { 1, 4, "c0_yqmask" },
201 { 1, 5, "c0_vpeschedule" },
202 { 1, 6, "c0_vpeschefback" },
203 { 2, 1, "c0_tcstatus" },
204 { 2, 2, "c0_tcbind" },
205 { 2, 3, "c0_tcrestart" },
206 { 2, 4, "c0_tchalt" },
207 { 2, 5, "c0_tccontext" },
208 { 2, 6, "c0_tcschedule" },
209 { 2, 7, "c0_tcschefback" },
210 { 5, 1, "c0_pagegrain" },
211 { 6, 1, "c0_srsconf0" },
212 { 6, 2, "c0_srsconf1" },
213 { 6, 3, "c0_srsconf2" },
214 { 6, 4, "c0_srsconf3" },
215 { 6, 5, "c0_srsconf4" },
216 { 12, 1, "c0_intctl" },
217 { 12, 2, "c0_srsctl" },
218 { 12, 3, "c0_srsmap" },
219 { 15, 1, "c0_ebase" },
220 { 16, 1, "c0_config1" },
221 { 16, 2, "c0_config2" },
222 { 16, 3, "c0_config3" },
223 { 18, 1, "c0_watchlo,1" },
224 { 18, 2, "c0_watchlo,2" },
225 { 18, 3, "c0_watchlo,3" },
226 { 18, 4, "c0_watchlo,4" },
227 { 18, 5, "c0_watchlo,5" },
228 { 18, 6, "c0_watchlo,6" },
229 { 18, 7, "c0_watchlo,7" },
230 { 19, 1, "c0_watchhi,1" },
231 { 19, 2, "c0_watchhi,2" },
232 { 19, 3, "c0_watchhi,3" },
233 { 19, 4, "c0_watchhi,4" },
234 { 19, 5, "c0_watchhi,5" },
235 { 19, 6, "c0_watchhi,6" },
236 { 19, 7, "c0_watchhi,7" },
237 { 23, 1, "c0_tracecontrol" },
238 { 23, 2, "c0_tracecontrol2" },
239 { 23, 3, "c0_usertracedata" },
240 { 23, 4, "c0_tracebpc" },
241 { 25, 1, "c0_perfcnt,1" },
242 { 25, 2, "c0_perfcnt,2" },
243 { 25, 3, "c0_perfcnt,3" },
244 { 25, 4, "c0_perfcnt,4" },
245 { 25, 5, "c0_perfcnt,5" },
246 { 25, 6, "c0_perfcnt,6" },
247 { 25, 7, "c0_perfcnt,7" },
248 { 27, 1, "c0_cacheerr,1" },
249 { 27, 2, "c0_cacheerr,2" },
250 { 27, 3, "c0_cacheerr,3" },
251 { 28, 1, "c0_datalo" },
252 { 28, 2, "c0_taglo1" },
253 { 28, 3, "c0_datalo1" },
254 { 28, 4, "c0_taglo2" },
255 { 28, 5, "c0_datalo2" },
256 { 28, 6, "c0_taglo3" },
257 { 28, 7, "c0_datalo3" },
258 { 29, 1, "c0_datahi" },
259 { 29, 2, "c0_taghi1" },
260 { 29, 3, "c0_datahi1" },
261 { 29, 4, "c0_taghi2" },
262 { 29, 5, "c0_datahi2" },
263 { 29, 6, "c0_taghi3" },
264 { 29, 7, "c0_datahi3" },
267 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
268 static const char * const mips_cp0_names_sb1[32] =
270 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
271 "c0_context", "c0_pagemask", "c0_wired", "$7",
272 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
273 "c0_status", "c0_cause", "c0_epc", "c0_prid",
274 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
275 "c0_xcontext", "$21", "$22", "c0_debug",
276 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
277 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
280 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
282 { 16, 1, "c0_config1" },
283 { 18, 1, "c0_watchlo,1" },
284 { 19, 1, "c0_watchhi,1" },
285 { 22, 0, "c0_perftrace" },
286 { 23, 3, "c0_edebug" },
287 { 25, 1, "c0_perfcnt,1" },
288 { 25, 2, "c0_perfcnt,2" },
289 { 25, 3, "c0_perfcnt,3" },
290 { 25, 4, "c0_perfcnt,4" },
291 { 25, 5, "c0_perfcnt,5" },
292 { 25, 6, "c0_perfcnt,6" },
293 { 25, 7, "c0_perfcnt,7" },
294 { 26, 1, "c0_buserr_pa" },
295 { 27, 1, "c0_cacheerr_d" },
296 { 27, 3, "c0_cacheerr_d_pa" },
297 { 28, 1, "c0_datalo_i" },
298 { 28, 2, "c0_taglo_d" },
299 { 28, 3, "c0_datalo_d" },
300 { 29, 1, "c0_datahi_i" },
301 { 29, 2, "c0_taghi_d" },
302 { 29, 3, "c0_datahi_d" },
305 static const char * const mips_cp0_names_octeon[32] = {
306 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
307 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
308 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
309 "c0_status", "c0_cause", "c0_epc", "c0_prid",
310 "c0_config", "$17", "c0_watchlo", "c0_watchhi",
311 "c0_xcontext", "$21", "c0_mdebug", "c0_debug",
312 "c0_depc", "c0_perfcnt", "$26", "c0_cacheerr",
313 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
316 static const struct mips_cp0sel_name mips_cp0sel_names_octeon[] = {
317 { 5, 1, "c0_pagegrain" },
318 { 9, 6, "c0_cvmcount" },
319 { 9, 7, "c0_cvmctl" },
320 { 11, 7, "c0_cvmmemctl" },
321 { 12, 1, "c0_intctl" },
322 { 12, 2, "c0_srsctl" },
323 { 15, 1, "c0_ebase" },
324 { 16, 1, "c0_config1", },
325 { 16, 2, "c0_config2", },
326 { 16, 3, "c0_config3", },
327 { 18, 1, "c0_watchlo,1" },
328 { 19, 1, "c0_watchhi,1" },
329 { 25, 2, "c0_perfcnt,2" },
330 { 27, 1, "c0_cacheerr,1" },
331 { 28, 3, "c0_datalo" },
332 { 29, 3, "c0_datahi" },
335 static const char * const mips_hwr_names_numeric[32] =
337 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
338 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
339 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
340 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
343 static const char * const mips_hwr_names_mips3264r2[32] =
345 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
346 "$4", "$5", "$6", "$7",
347 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
348 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
349 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
352 struct mips_abi_choice
355 const char * const *gpr_names;
356 const char * const *fpr_names;
359 struct mips_abi_choice mips_abi_choices[] =
361 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
362 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
363 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
364 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
367 struct mips_arch_choice
371 unsigned long bfd_mach;
374 const char * const *cp0_names;
375 const struct mips_cp0sel_name *cp0sel_names;
376 unsigned int cp0sel_names_len;
377 const char * const *hwr_names;
380 const struct mips_arch_choice mips_arch_choices[] =
382 { "numeric", 0, 0, 0, 0,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
385 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
386 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
387 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
388 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
389 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
390 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
391 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
392 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
393 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
394 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
395 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
396 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
397 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
398 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
399 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
400 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
401 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
402 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
403 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
404 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
405 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
406 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
407 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
408 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
409 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
410 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
411 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
412 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
413 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
414 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
415 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
416 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
417 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
418 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
419 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
420 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
421 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
422 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
423 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
424 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
425 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
426 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
428 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
429 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
430 _MIPS32 Architecture For Programmers Volume I: Introduction to the
431 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
433 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
434 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
435 mips_cp0_names_mips3264,
436 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
437 mips_hwr_names_numeric },
439 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
440 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
441 | INSN_MIPS3D | INSN_MT),
442 mips_cp0_names_mips3264r2,
443 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
444 mips_hwr_names_mips3264r2 },
446 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
447 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
448 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
449 mips_cp0_names_mips3264,
450 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
451 mips_hwr_names_numeric },
453 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
454 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
455 | INSN_DSP64 | INSN_MT | INSN_MDMX),
456 mips_cp0_names_mips3264r2,
457 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
458 mips_hwr_names_mips3264r2 },
460 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
461 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
463 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
464 mips_hwr_names_numeric },
466 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
467 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_octeon,
468 mips_cp0sel_names_octeon, ARRAY_SIZE (mips_cp0sel_names_octeon),
469 mips_hwr_names_numeric },
471 /* This entry, mips16, is here only for ISA/processor selection; do
472 not print its name. */
473 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
474 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
477 /* ISA and processor type to disassemble for, and register names to use.
478 set_default_mips_dis_options and parse_mips_dis_options fill in these
480 static int mips_processor;
482 static const char * const *mips_gpr_names;
483 static const char * const *mips_fpr_names;
484 static const char * const *mips_cp0_names;
485 static const struct mips_cp0sel_name *mips_cp0sel_names;
486 static int mips_cp0sel_names_len;
487 static const char * const *mips_hwr_names;
490 static int no_aliases; /* If set disassemble as most general inst. */
492 static const struct mips_abi_choice *
493 choose_abi_by_name (const char *name, unsigned int namelen)
495 const struct mips_abi_choice *c;
498 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
499 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
500 && strlen (mips_abi_choices[i].name) == namelen)
501 c = &mips_abi_choices[i];
506 static const struct mips_arch_choice *
507 choose_arch_by_name (const char *name, unsigned int namelen)
509 const struct mips_arch_choice *c = NULL;
512 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
513 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
514 && strlen (mips_arch_choices[i].name) == namelen)
515 c = &mips_arch_choices[i];
520 static const struct mips_arch_choice *
521 choose_arch_by_number (unsigned long mach)
523 static unsigned long hint_bfd_mach;
524 static const struct mips_arch_choice *hint_arch_choice;
525 const struct mips_arch_choice *c;
528 /* We optimize this because even if the user specifies no
529 flags, this will be done for every instruction! */
530 if (hint_bfd_mach == mach
531 && hint_arch_choice != NULL
532 && hint_arch_choice->bfd_mach == hint_bfd_mach)
533 return hint_arch_choice;
535 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
537 if (mips_arch_choices[i].bfd_mach_valid
538 && mips_arch_choices[i].bfd_mach == mach)
540 c = &mips_arch_choices[i];
541 hint_bfd_mach = mach;
542 hint_arch_choice = c;
548 /* Check if the object uses NewABI conventions. */
551 is_newabi (Elf_Internal_Ehdr *header)
553 /* There are no old-style ABIs which use 64-bit ELF. */
554 if (header->e_ident[EI_CLASS] == ELFCLASS64)
557 /* If a 32-bit ELF file, n32 is a new-style ABI. */
558 if ((header->e_flags & EF_MIPS_ABI2) != 0)
565 set_default_mips_dis_options (struct disassemble_info *info)
567 const struct mips_arch_choice *chosen_arch;
569 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
570 and numeric FPR, CP0 register, and HWR names. */
571 mips_isa = ISA_MIPS3;
572 mips_processor = CPU_R3000;
573 mips_gpr_names = mips_gpr_names_oldabi;
574 mips_fpr_names = mips_fpr_names_numeric;
575 mips_cp0_names = mips_cp0_names_numeric;
576 mips_cp0sel_names = NULL;
577 mips_cp0sel_names_len = 0;
578 mips_hwr_names = mips_hwr_names_numeric;
581 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
582 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
584 Elf_Internal_Ehdr *header;
586 header = elf_elfheader (info->section->owner);
587 if (is_newabi (header))
588 mips_gpr_names = mips_gpr_names_newabi;
591 /* Set ISA, architecture, and cp0 register names as best we can. */
592 #if ! SYMTAB_AVAILABLE
593 /* This is running out on a target machine, not in a host tool.
594 FIXME: Where does mips_target_info come from? */
595 target_processor = mips_target_info.processor;
596 mips_isa = mips_target_info.isa;
598 chosen_arch = choose_arch_by_number (info->mach);
599 if (chosen_arch != NULL)
601 mips_processor = chosen_arch->processor;
602 mips_isa = chosen_arch->isa;
603 mips_cp0_names = chosen_arch->cp0_names;
604 mips_cp0sel_names = chosen_arch->cp0sel_names;
605 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
606 mips_hwr_names = chosen_arch->hwr_names;
612 parse_mips_dis_option (const char *option, unsigned int len)
614 unsigned int i, optionlen, vallen;
616 const struct mips_abi_choice *chosen_abi;
617 const struct mips_arch_choice *chosen_arch;
619 if (strcmp ("octeon-useun", option) == 0)
621 octeon_use_unalign = 1;
624 if (strcmp ("no-octeon-useun", option) == 0)
626 octeon_use_unalign = 0;
630 /* Try to match options that are simple flags */
631 if (CONST_STRNEQ (option, "no-aliases"))
637 /* Look for the = that delimits the end of the option name. */
638 for (i = 0; i < len; i++)
639 if (option[i] == '=')
642 if (i == 0) /* Invalid option: no name before '='. */
644 if (i == len) /* Invalid option: no '='. */
646 if (i == (len - 1)) /* Invalid option: no value after '='. */
650 val = option + (optionlen + 1);
651 vallen = len - (optionlen + 1);
653 if (strncmp ("gpr-names", option, optionlen) == 0
654 && strlen ("gpr-names") == optionlen)
656 chosen_abi = choose_abi_by_name (val, vallen);
657 if (chosen_abi != NULL)
658 mips_gpr_names = chosen_abi->gpr_names;
662 if (strncmp ("fpr-names", option, optionlen) == 0
663 && strlen ("fpr-names") == optionlen)
665 chosen_abi = choose_abi_by_name (val, vallen);
666 if (chosen_abi != NULL)
667 mips_fpr_names = chosen_abi->fpr_names;
671 if (strncmp ("cp0-names", option, optionlen) == 0
672 && strlen ("cp0-names") == optionlen)
674 chosen_arch = choose_arch_by_name (val, vallen);
675 if (chosen_arch != NULL)
677 mips_cp0_names = chosen_arch->cp0_names;
678 mips_cp0sel_names = chosen_arch->cp0sel_names;
679 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
684 if (strncmp ("hwr-names", option, optionlen) == 0
685 && strlen ("hwr-names") == optionlen)
687 chosen_arch = choose_arch_by_name (val, vallen);
688 if (chosen_arch != NULL)
689 mips_hwr_names = chosen_arch->hwr_names;
693 if (strncmp ("reg-names", option, optionlen) == 0
694 && strlen ("reg-names") == optionlen)
696 /* We check both ABI and ARCH here unconditionally, so
697 that "numeric" will do the desirable thing: select
698 numeric register names for all registers. Other than
699 that, a given name probably won't match both. */
700 chosen_abi = choose_abi_by_name (val, vallen);
701 if (chosen_abi != NULL)
703 mips_gpr_names = chosen_abi->gpr_names;
704 mips_fpr_names = chosen_abi->fpr_names;
706 chosen_arch = choose_arch_by_name (val, vallen);
707 if (chosen_arch != NULL)
709 mips_cp0_names = chosen_arch->cp0_names;
710 mips_cp0sel_names = chosen_arch->cp0sel_names;
711 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
712 mips_hwr_names = chosen_arch->hwr_names;
717 /* Invalid option. */
721 parse_mips_dis_options (const char *options)
723 const char *option_end;
728 while (*options != '\0')
730 /* Skip empty options. */
737 /* We know that *options is neither NUL or a comma. */
738 option_end = options + 1;
739 while (*option_end != ',' && *option_end != '\0')
742 parse_mips_dis_option (options, option_end - options);
744 /* Go on to the next one. If option_end points to a comma, it
745 will be skipped above. */
746 options = option_end;
750 static const struct mips_cp0sel_name *
751 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
758 for (i = 0; i < len; i++)
759 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
764 /* Print insn arguments for 32/64-bit code. */
767 print_insn_args (const char *d,
768 register unsigned long int l,
770 struct disassemble_info *info,
771 const struct mips_opcode *opp)
774 unsigned int lsb, msb, msbd;
778 for (; *d != '\0'; d++)
787 (*info->fprintf_func) (info->stream, "%c", *d);
791 /* Extension character; switch for second char. */
796 /* xgettext:c-format */
797 (*info->fprintf_func) (info->stream,
798 _("# internal error, incomplete extension sequence (+)"));
802 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
803 (*info->fprintf_func) (info->stream, "0x%x", lsb);
807 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
808 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
812 (*info->fprintf_func) (info->stream, "0x%lx",
813 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
817 (*info->fprintf_func) (info->stream, "0x%lx",
818 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
822 (*info->fprintf_func) (info->stream, "0x%lx",
823 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
827 (*info->fprintf_func) (info->stream, "0x%lx",
828 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
833 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
834 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
839 const struct mips_cp0sel_name *n;
840 unsigned int cp0reg, sel;
842 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
843 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
845 /* CP0 register including 'sel' code for mtcN (et al.), to be
846 printed textually if known. If not known, print both
847 CP0 register name and sel numerically since CP0 register
848 with sel 0 may have a name unrelated to register being
850 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
851 mips_cp0sel_names_len, cp0reg, sel);
853 (*info->fprintf_func) (info->stream, "%s", n->name);
855 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
860 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
861 (*info->fprintf_func) (info->stream, "0x%x", lsb);
865 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
866 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
870 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
871 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
874 case 't': /* Coprocessor 0 reg name */
875 (*info->fprintf_func) (info->stream, "%s",
876 mips_cp0_names[(l >> OP_SH_RT) &
880 case 'T': /* Coprocessor 0 reg name */
882 const struct mips_cp0sel_name *n;
883 unsigned int cp0reg, sel;
885 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
886 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
888 /* CP0 register including 'sel' code for mftc0, to be
889 printed textually if known. If not known, print both
890 CP0 register name and sel numerically since CP0 register
891 with sel 0 may have a name unrelated to register being
893 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
894 mips_cp0sel_names_len, cp0reg, sel);
896 (*info->fprintf_func) (info->stream, "%s", n->name);
898 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
903 /* xgettext:c-format */
904 (*info->fprintf_func) (info->stream,
905 _("# internal error, undefined extension sequence (+%c)"),
912 (*info->fprintf_func) (info->stream, "0x%lx",
913 (l >> OP_SH_BP) & OP_MASK_BP);
917 (*info->fprintf_func) (info->stream, "0x%lx",
918 (l >> OP_SH_SA3) & OP_MASK_SA3);
922 (*info->fprintf_func) (info->stream, "0x%lx",
923 (l >> OP_SH_SA4) & OP_MASK_SA4);
927 (*info->fprintf_func) (info->stream, "0x%lx",
928 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
932 (*info->fprintf_func) (info->stream, "0x%lx",
933 (l >> OP_SH_RS) & OP_MASK_RS);
937 (*info->fprintf_func) (info->stream, "$ac%ld",
938 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
942 (*info->fprintf_func) (info->stream, "0x%lx",
943 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
947 (*info->fprintf_func) (info->stream, "$ac%ld",
948 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
951 case '0': /* dsp 6-bit signed immediate in bit 20 */
952 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
953 if (delta & 0x20) /* test sign bit */
954 delta |= ~OP_MASK_DSPSFT;
955 (*info->fprintf_func) (info->stream, "%d", delta);
958 case ':': /* dsp 7-bit signed immediate in bit 19 */
959 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
960 if (delta & 0x40) /* test sign bit */
961 delta |= ~OP_MASK_DSPSFT_7;
962 (*info->fprintf_func) (info->stream, "%d", delta);
966 (*info->fprintf_func) (info->stream, "0x%lx",
967 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
970 case '@': /* dsp 10-bit signed immediate in bit 16 */
971 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
972 if (delta & 0x200) /* test sign bit */
973 delta |= ~OP_MASK_IMM10;
974 (*info->fprintf_func) (info->stream, "%d", delta);
978 (*info->fprintf_func) (info->stream, "%ld",
979 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
983 (*info->fprintf_func) (info->stream, "%ld",
984 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
988 (*info->fprintf_func) (info->stream, "$ac%ld",
989 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
993 (*info->fprintf_func) (info->stream, "$ac%ld",
994 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
998 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
999 (*info->fprintf_func) (info->stream, "$%ld",
1000 (l >> OP_SH_RD) & OP_MASK_RD);
1007 (*info->fprintf_func) (info->stream, "%s",
1008 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1013 (*info->fprintf_func) (info->stream, "%s",
1014 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1019 (*info->fprintf_func) (info->stream, "0x%lx",
1020 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1023 case 'j': /* Same as i, but sign-extended. */
1025 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1028 (*info->fprintf_func) (info->stream, "%d",
1033 (*info->fprintf_func) (info->stream, "0x%x",
1034 (unsigned int) ((l >> OP_SH_PREFX)
1039 (*info->fprintf_func) (info->stream, "0x%x",
1040 (unsigned int) ((l >> OP_SH_CACHE)
1045 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1046 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1047 /* For gdb disassembler, force odd address on jalx. */
1048 if (info->flavour == bfd_target_unknown_flavour
1049 && strcmp (opp->name, "jalx") == 0)
1051 (*info->print_address_func) (info->target, info);
1055 /* Sign extend the displacement. */
1056 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1059 info->target = (delta << 2) + pc + INSNLEN;
1060 (*info->print_address_func) (info->target, info);
1064 (*info->fprintf_func) (info->stream, "%s",
1065 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1070 /* First check for both rd and rt being equal. */
1071 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1072 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1073 (*info->fprintf_func) (info->stream, "%s",
1074 mips_gpr_names[reg]);
1077 /* If one is zero use the other. */
1079 (*info->fprintf_func) (info->stream, "%s",
1080 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1081 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1082 (*info->fprintf_func) (info->stream, "%s",
1083 mips_gpr_names[reg]);
1084 else /* Bogus, result depends on processor. */
1085 (*info->fprintf_func) (info->stream, "%s or %s",
1086 mips_gpr_names[reg],
1087 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1093 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1097 (*info->fprintf_func) (info->stream, "0x%lx",
1098 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1102 (*info->fprintf_func) (info->stream, "0x%lx",
1103 (l >> OP_SH_CODE) & OP_MASK_CODE);
1107 (*info->fprintf_func) (info->stream, "0x%lx",
1108 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1111 /* Display 5 bits of bbit0/1 bit index amount. */
1113 (*info->fprintf_func) (info->stream, "0x%lx",
1114 (l >> OP_SH_BITIND) & OP_MASK_BITIND);
1117 /* Display 10 bits signed constant from seqi/snei instruction. */
1120 int imm = (l >> OP_SH_CODE2) & OP_MASK_CODE2;
1123 (*info->fprintf_func) (info->stream, "%d", imm);
1128 (*info->fprintf_func) (info->stream, "0x%lx",
1129 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1133 (*info->fprintf_func) (info->stream, "0x%lx",
1135 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1139 (*info->fprintf_func) (info->stream, "0x%lx",
1140 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1145 (*info->fprintf_func) (info->stream, "%s",
1146 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1151 (*info->fprintf_func) (info->stream, "%s",
1152 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1156 (*info->fprintf_func) (info->stream, "%s",
1157 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1161 (*info->fprintf_func) (info->stream, "%s",
1162 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1166 /* Coprocessor register for lwcN instructions, et al.
1168 Note that there is no load/store cp0 instructions, and
1169 that FPU (cp1) instructions disassemble this field using
1170 'T' format. Therefore, until we gain understanding of
1171 cp2 register names, we can simply print the register
1173 (*info->fprintf_func) (info->stream, "$%ld",
1174 (l >> OP_SH_RT) & OP_MASK_RT);
1178 /* Coprocessor register for mtcN instructions, et al. Note
1179 that FPU (cp1) instructions disassemble this field using
1180 'S' format. Therefore, we only need to worry about cp0,
1182 op = (l >> OP_SH_OP) & OP_MASK_OP;
1183 if (op == OP_OP_COP0)
1184 (*info->fprintf_func) (info->stream, "%s",
1185 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1187 (*info->fprintf_func) (info->stream, "$%ld",
1188 (l >> OP_SH_RD) & OP_MASK_RD);
1192 (*info->fprintf_func) (info->stream, "%s",
1193 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1197 (*info->fprintf_func) (info->stream,
1198 ((opp->pinfo & (FP_D | FP_S)) != 0
1199 ? "$fcc%ld" : "$cc%ld"),
1200 (l >> OP_SH_BCC) & OP_MASK_BCC);
1204 (*info->fprintf_func) (info->stream, "$fcc%ld",
1205 (l >> OP_SH_CCC) & OP_MASK_CCC);
1209 (*info->fprintf_func) (info->stream, "%ld",
1210 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1214 (*info->fprintf_func) (info->stream, "%ld",
1215 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1219 (*info->fprintf_func) (info->stream, "%ld",
1220 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1224 (*info->fprintf_func) (info->stream, "%ld",
1225 (l >> OP_SH_SEL) & OP_MASK_SEL);
1229 (*info->fprintf_func) (info->stream, "%ld",
1230 (l >> OP_SH_ALN) & OP_MASK_ALN);
1235 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1237 if ((vsel & 0x10) == 0)
1242 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1243 if ((vsel & 1) == 0)
1245 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1246 (l >> OP_SH_FT) & OP_MASK_FT,
1249 else if ((vsel & 0x08) == 0)
1251 (*info->fprintf_func) (info->stream, "$v%ld",
1252 (l >> OP_SH_FT) & OP_MASK_FT);
1256 (*info->fprintf_func) (info->stream, "0x%lx",
1257 (l >> OP_SH_FT) & OP_MASK_FT);
1263 (*info->fprintf_func) (info->stream, "$v%ld",
1264 (l >> OP_SH_FD) & OP_MASK_FD);
1268 (*info->fprintf_func) (info->stream, "$v%ld",
1269 (l >> OP_SH_FS) & OP_MASK_FS);
1273 (*info->fprintf_func) (info->stream, "$v%ld",
1274 (l >> OP_SH_FT) & OP_MASK_FT);
1278 /* xgettext:c-format */
1279 (*info->fprintf_func) (info->stream,
1280 _("# internal error, undefined modifier(%c)"),
1287 /* Print the mips instruction at address MEMADDR in debugged memory,
1288 on using INFO. Returns length of the instruction, in bytes, which is
1289 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1290 this is little-endian code. */
1293 print_insn_mips (bfd_vma memaddr,
1294 unsigned long int word,
1295 struct disassemble_info *info)
1297 const struct mips_opcode *op;
1298 static bfd_boolean init = 0;
1299 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1301 /* Build a hash table to shorten the search time. */
1306 for (i = 0; i <= OP_MASK_OP; i++)
1308 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1310 if (op->pinfo == INSN_MACRO
1311 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1313 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1324 info->bytes_per_chunk = INSNLEN;
1325 info->display_endian = info->endian;
1326 info->insn_info_valid = 1;
1327 info->branch_delay_insns = 0;
1328 info->data_size = 0;
1329 info->insn_type = dis_nonbranch;
1333 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1336 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1338 if (op->pinfo != INSN_MACRO
1339 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1340 && (word & op->mask) == op->match)
1344 /* We always allow to disassemble the jalx instruction. */
1345 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1346 && strcmp (op->name, "jalx"))
1349 if (info->mach == CPU_OCTEON && octeon_use_unalign)
1351 if (strcmp (op->name, "lwl") == 0
1352 || strcmp (op->name, "ldl") == 0
1353 || strcmp (op->name, "swl") == 0
1354 || strcmp (op->name, "sdl") == 0
1355 || strcmp (op->name, "lcache") == 0
1356 || strcmp (op->name, "scache") == 0
1357 || strcmp (op->name, "flush") == 0)
1360 if (strcmp (op->name, "ldr") == 0
1361 || strcmp (op->name, "lwr") == 0
1362 || strcmp (op->name, "swr") == 0
1363 || strcmp (op->name, "sdr") == 0)
1365 (*info->fprintf_func) (info->stream, "nop");
1370 /* Figure out instruction type and branch delay information. */
1371 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1373 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1374 info->insn_type = dis_jsr;
1376 info->insn_type = dis_branch;
1377 info->branch_delay_insns = 1;
1379 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1380 | INSN_COND_BRANCH_LIKELY)) != 0)
1382 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1383 info->insn_type = dis_condjsr;
1385 info->insn_type = dis_condbranch;
1386 info->branch_delay_insns = 1;
1388 else if ((op->pinfo & (INSN_STORE_MEMORY
1389 | INSN_LOAD_MEMORY_DELAY)) != 0)
1390 info->insn_type = dis_dref;
1392 (*info->fprintf_func) (info->stream, "%s", op->name);
1395 if (d != NULL && *d != '\0')
1397 (*info->fprintf_func) (info->stream, "\t");
1398 print_insn_args (d, word, memaddr, info, op);
1406 /* Handle undefined instructions. */
1407 info->insn_type = dis_noninsn;
1408 (*info->fprintf_func) (info->stream, "0x%lx", word);
1412 /* Disassemble an operand for a mips16 instruction. */
1415 print_mips16_insn_arg (char type,
1416 const struct mips_opcode *op,
1418 bfd_boolean use_extend,
1421 struct disassemble_info *info)
1428 (*info->fprintf_func) (info->stream, "%c", type);
1433 (*info->fprintf_func) (info->stream, "%s",
1434 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1435 & MIPS16OP_MASK_RY)));
1440 (*info->fprintf_func) (info->stream, "%s",
1441 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1442 & MIPS16OP_MASK_RX)));
1446 (*info->fprintf_func) (info->stream, "%s",
1447 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1448 & MIPS16OP_MASK_RZ)));
1452 (*info->fprintf_func) (info->stream, "%s",
1453 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1454 & MIPS16OP_MASK_MOVE32Z)));
1458 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1462 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1466 (*info->fprintf_func) (info->stream, "$pc");
1470 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1474 (*info->fprintf_func) (info->stream, "%s",
1475 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1476 & MIPS16OP_MASK_REGR32)]);
1480 (*info->fprintf_func) (info->stream, "%s",
1481 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1507 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1519 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1525 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1531 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1537 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1543 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1549 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1550 info->insn_type = dis_dref;
1551 info->data_size = 1;
1556 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1557 info->insn_type = dis_dref;
1558 info->data_size = 2;
1563 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1564 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1565 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1567 info->insn_type = dis_dref;
1568 info->data_size = 4;
1574 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1575 info->insn_type = dis_dref;
1576 info->data_size = 8;
1580 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1585 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1589 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1594 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1595 /* FIXME: This might be lw, or it might be addiu to $sp or
1596 $pc. We assume it's load. */
1597 info->insn_type = dis_dref;
1598 info->data_size = 4;
1603 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1604 info->insn_type = dis_dref;
1605 info->data_size = 8;
1609 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1614 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1620 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1625 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1629 info->insn_type = dis_condbranch;
1633 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1637 info->insn_type = dis_branch;
1642 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1644 /* FIXME: This can be lw or la. We assume it is lw. */
1645 info->insn_type = dis_dref;
1646 info->data_size = 4;
1651 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1653 info->insn_type = dis_dref;
1654 info->data_size = 8;
1659 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1668 if (signedp && immed >= (1 << (nbits - 1)))
1669 immed -= 1 << nbits;
1671 if ((type == '<' || type == '>' || type == '[' || type == ']')
1678 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1679 else if (extbits == 15)
1680 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1682 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1683 immed &= (1 << extbits) - 1;
1684 if (! extu && immed >= (1 << (extbits - 1)))
1685 immed -= 1 << extbits;
1689 (*info->fprintf_func) (info->stream, "%d", immed);
1697 baseaddr = memaddr + 2;
1699 else if (use_extend)
1700 baseaddr = memaddr - 2;
1708 /* If this instruction is in the delay slot of a jr
1709 instruction, the base address is the address of the
1710 jr instruction. If it is in the delay slot of jalr
1711 instruction, the base address is the address of the
1712 jalr instruction. This test is unreliable: we have
1713 no way of knowing whether the previous word is
1714 instruction or data. */
1715 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1718 && (((info->endian == BFD_ENDIAN_BIG
1719 ? bfd_getb16 (buffer)
1720 : bfd_getl16 (buffer))
1721 & 0xf800) == 0x1800))
1722 baseaddr = memaddr - 4;
1725 status = (*info->read_memory_func) (memaddr - 2, buffer,
1728 && (((info->endian == BFD_ENDIAN_BIG
1729 ? bfd_getb16 (buffer)
1730 : bfd_getl16 (buffer))
1731 & 0xf81f) == 0xe800))
1732 baseaddr = memaddr - 2;
1735 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1737 && info->flavour == bfd_target_unknown_flavour)
1738 /* For gdb disassembler, maintain odd address. */
1740 (*info->print_address_func) (info->target, info);
1747 int jalx = l & 0x400;
1751 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1752 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1753 /* For gdb disassembler, maintain odd address. */
1756 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1757 (*info->print_address_func) (info->target, info);
1758 info->insn_type = dis_jsr;
1759 info->branch_delay_insns = 1;
1765 int need_comma, amask, smask;
1769 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1771 amask = (l >> 3) & 7;
1773 if (amask > 0 && amask < 5)
1775 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1777 (*info->fprintf_func) (info->stream, "-%s",
1778 mips_gpr_names[amask + 3]);
1782 smask = (l >> 1) & 3;
1785 (*info->fprintf_func) (info->stream, "%s??",
1786 need_comma ? "," : "");
1791 (*info->fprintf_func) (info->stream, "%s%s",
1792 need_comma ? "," : "",
1793 mips_gpr_names[16]);
1795 (*info->fprintf_func) (info->stream, "-%s",
1796 mips_gpr_names[smask + 15]);
1802 (*info->fprintf_func) (info->stream, "%s%s",
1803 need_comma ? "," : "",
1804 mips_gpr_names[31]);
1808 if (amask == 5 || amask == 6)
1810 (*info->fprintf_func) (info->stream, "%s$f0",
1811 need_comma ? "," : "");
1813 (*info->fprintf_func) (info->stream, "-$f1");
1820 /* MIPS16e save/restore. */
1823 int amask, args, statics;
1832 amask = (l >> 16) & 0xf;
1833 if (amask == MIPS16_ALL_ARGS)
1838 else if (amask == MIPS16_ALL_STATICS)
1846 statics = amask & 3;
1850 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1852 (*info->fprintf_func) (info->stream, "-%s",
1853 mips_gpr_names[4 + args - 1]);
1857 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1858 if (framesz == 0 && !use_extend)
1861 (*info->fprintf_func) (info->stream, "%s%d",
1862 need_comma ? "," : "",
1865 if (l & 0x40) /* $ra */
1866 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1868 nsreg = (l >> 24) & 0x7;
1870 if (l & 0x20) /* $s0 */
1872 if (l & 0x10) /* $s1 */
1874 if (nsreg > 0) /* $s2-$s8 */
1875 smask |= ((1 << nsreg) - 1) << 2;
1877 /* Find first set static reg bit. */
1878 for (i = 0; i < 9; i++)
1880 if (smask & (1 << i))
1882 (*info->fprintf_func) (info->stream, ",%s",
1883 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1884 /* Skip over string of set bits. */
1885 for (j = i; smask & (2 << j); j++)
1888 (*info->fprintf_func) (info->stream, "-%s",
1889 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1894 /* Statics $ax - $a3. */
1896 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1897 else if (statics > 0)
1898 (*info->fprintf_func) (info->stream, ",%s-%s",
1899 mips_gpr_names[7 - statics + 1],
1905 /* xgettext:c-format */
1906 (*info->fprintf_func)
1908 _("# internal disassembler error, unrecognised modifier (%c)"),
1914 /* Disassemble mips16 instructions. */
1917 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1923 bfd_boolean use_extend;
1925 const struct mips_opcode *op, *opend;
1927 info->bytes_per_chunk = 2;
1928 info->display_endian = info->endian;
1929 info->insn_info_valid = 1;
1930 info->branch_delay_insns = 0;
1931 info->data_size = 0;
1932 info->insn_type = dis_nonbranch;
1936 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1939 (*info->memory_error_func) (status, memaddr, info);
1945 if (info->endian == BFD_ENDIAN_BIG)
1946 insn = bfd_getb16 (buffer);
1948 insn = bfd_getl16 (buffer);
1950 /* Handle the extend opcode specially. */
1952 if ((insn & 0xf800) == 0xf000)
1955 extend = insn & 0x7ff;
1959 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1962 (*info->fprintf_func) (info->stream, "extend 0x%x",
1963 (unsigned int) extend);
1964 (*info->memory_error_func) (status, memaddr, info);
1968 if (info->endian == BFD_ENDIAN_BIG)
1969 insn = bfd_getb16 (buffer);
1971 insn = bfd_getl16 (buffer);
1973 /* Check for an extend opcode followed by an extend opcode. */
1974 if ((insn & 0xf800) == 0xf000)
1976 (*info->fprintf_func) (info->stream, "extend 0x%x",
1977 (unsigned int) extend);
1978 info->insn_type = dis_noninsn;
1985 /* FIXME: Should probably use a hash table on the major opcode here. */
1987 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1988 for (op = mips16_opcodes; op < opend; op++)
1990 if (op->pinfo != INSN_MACRO
1991 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1992 && (insn & op->mask) == op->match)
1996 if (strchr (op->args, 'a') != NULL)
2000 (*info->fprintf_func) (info->stream, "extend 0x%x",
2001 (unsigned int) extend);
2002 info->insn_type = dis_noninsn;
2010 status = (*info->read_memory_func) (memaddr, buffer, 2,
2015 if (info->endian == BFD_ENDIAN_BIG)
2016 extend = bfd_getb16 (buffer);
2018 extend = bfd_getl16 (buffer);
2023 (*info->fprintf_func) (info->stream, "%s", op->name);
2024 if (op->args[0] != '\0')
2025 (*info->fprintf_func) (info->stream, "\t");
2027 for (s = op->args; *s != '\0'; s++)
2031 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2032 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2034 /* Skip the register and the comma. */
2040 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2041 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2043 /* Skip the register and the comma. */
2047 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2051 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2053 info->branch_delay_insns = 1;
2054 if (info->insn_type != dis_jsr)
2055 info->insn_type = dis_branch;
2063 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2064 (*info->fprintf_func) (info->stream, "0x%x", insn);
2065 info->insn_type = dis_noninsn;
2070 /* In an environment where we do not know the symbol type of the
2071 instruction we are forced to assume that the low order bit of the
2072 instructions' address may mark it as a mips16 instruction. If we
2073 are single stepping, or the pc is within the disassembled function,
2074 this works. Otherwise, we need a clue. Sometimes. */
2077 _print_insn_mips (bfd_vma memaddr,
2078 struct disassemble_info *info,
2079 enum bfd_endian endianness)
2081 bfd_byte buffer[INSNLEN];
2084 set_default_mips_dis_options (info);
2085 parse_mips_dis_options (info->disassembler_options);
2088 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2089 /* Only a few tools will work this way. */
2091 return print_insn_mips16 (memaddr, info);
2094 #if SYMTAB_AVAILABLE
2095 if (info->mach == bfd_mach_mips16
2096 || (info->flavour == bfd_target_elf_flavour
2097 && info->symbols != NULL
2098 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
2100 return print_insn_mips16 (memaddr, info);
2103 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2108 if (endianness == BFD_ENDIAN_BIG)
2109 insn = (unsigned long) bfd_getb32 (buffer);
2111 insn = (unsigned long) bfd_getl32 (buffer);
2113 return print_insn_mips (memaddr, insn, info);
2117 (*info->memory_error_func) (status, memaddr, info);
2123 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2125 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2129 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2131 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2135 print_mips_disassembler_options (FILE *stream)
2139 fprintf (stream, _("\n\
2140 The following MIPS specific disassembler options are supported for use\n\
2141 with the -M switch (multiple options should be separated by commas):\n"));
2143 fprintf (stream, _("\n\
2144 octeon-useun Disassemble Octeon unaligned load/store instructions.\n"));
2146 fprintf (stream, _("\n\
2147 no-octeon-useun Disassemble mips unaligned load/store instructions.\n"));
2149 fprintf (stream, _("\n\
2150 gpr-names=ABI Print GPR names according to specified ABI.\n\
2151 Default: based on binary being disassembled.\n"));
2153 fprintf (stream, _("\n\
2154 fpr-names=ABI Print FPR names according to specified ABI.\n\
2155 Default: numeric.\n"));
2157 fprintf (stream, _("\n\
2158 cp0-names=ARCH Print CP0 register names according to\n\
2159 specified architecture.\n\
2160 Default: based on binary being disassembled.\n"));
2162 fprintf (stream, _("\n\
2163 hwr-names=ARCH Print HWR names according to specified \n\
2165 Default: based on binary being disassembled.\n"));
2167 fprintf (stream, _("\n\
2168 reg-names=ABI Print GPR and FPR names according to\n\
2169 specified ABI.\n"));
2171 fprintf (stream, _("\n\
2172 reg-names=ARCH Print CP0 register and HWR names according to\n\
2173 specified architecture.\n"));
2175 fprintf (stream, _("\n\
2176 For the options above, the following values are supported for \"ABI\":\n\
2178 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2179 fprintf (stream, " %s", mips_abi_choices[i].name);
2180 fprintf (stream, _("\n"));
2182 fprintf (stream, _("\n\
2183 For the options above, The following values are supported for \"ARCH\":\n\
2185 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2186 if (*mips_arch_choices[i].name != '\0')
2187 fprintf (stream, " %s", mips_arch_choices[i].name);
2188 fprintf (stream, _("\n"));
2190 fprintf (stream, _("\n"));