1 2007-08-08 Andrew Haley <aph@redhat.com> (r128087)
3 * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New.
4 * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New.
5 * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New.
7 2007-07-12 Geoffrey Keating <geoffk@apple.com> (r126588)
9 * builtins.c (get_pointer_alignment): Honor DECL_ALIGN on a
11 * tree.c (build_decl_stat): Move code from here...
12 (make_node_stat): ... to here. Don't uselessly clear DECL_USER_ALIGN.
13 (expr_align): Honor DECL_ALIGN on a FUNCTION_DECL. Add comment
14 about using DECL_ALIGN of LABEL_DECL and CONST_DECL.
15 * tree.h (DECL_USER_ALIGN): Fix misplaced comment.
16 * varasm.c (assemble_start_function): Use DECL_ALIGN instead of
19 2007-07-09 Geoffrey Keating <geoffk@apple.com> (r126529)
22 * c-common.c (c_alignof_expr): Look at DECL_ALIGN of
24 (handle_aligned_attribute): Allow use on FUNCTION_DECLs.
25 * varasm.c (assemble_start_function): Honor DECL_ALIGN
26 for FUNCTION_DECLs. Don't use align_functions_log if
28 * print-tree.c (print_node): Print DECL_ALIGN and DECL_USER_ALIGN
29 even for FUNCTION_DECLs.
30 * c-decl.c (merge_decls): Propagate DECL_ALIGN even for
32 * tree.h (DECL_ALIGN): Update for new location of 'align'.
33 (DECL_FUNCTION_CODE): Update for new location and name of
35 (DECL_OFFSET_ALIGN): Update for new location of 'off_align'.
36 (struct tree_decl_common): Move 'align' and 'off_align' out
37 of union, ensure they're still on a 32-bit boundary. Remove
38 other fields in union 'u1'.
39 (struct tree_function_decl): Add field 'function_code' replacing
40 'u1.f' in tree_decl_common.
41 * tree.c (build_decl_stat): Set initial value of DECL_ALIGN.
42 * doc/extend.texi (Function Attributes): Add 'aligned' attribute.
43 (Variable Attributes): Cross-reference 'aligned' attribute
44 to Function Attributes.
45 * flags.h (force_align_functions_log): Delete.
46 * toplev.c (force_align_functions_log): Delete.
48 2007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346)
51 * doc/extend.texi: Document the 0b-prefixed binary integer
54 2007-05-27 Eric Christopher <echristo@apple.com> (r125116)
56 * config/rs6000/rs6000.c (rs6000_emit_prologue): Update
57 sp_offset depending on stack size. Save r12 depending
58 on registers we're saving later.
59 (rs6000_emit_epilogue): Update sp_offset depending only
62 2007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037)
64 * postreload-gcse.c (reg_changed_after_insn_p): New function.
65 (oprs_unchanged_p): Use it to check all registers in a REG.
66 (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE.
67 (reg_set_between_after_reload_p): Delete.
68 (reg_used_between_after_reload_p): Likewise.
69 (reg_set_or_used_since_bb_start): Likewise.
70 (eliminate_partially_redundant_load): Use reg_changed_after_insn_p
71 and reg_used_between_p instead of reg_set_or_used_since_bb_start.
72 Use reg_set_between_p instead of reg_set_between_after_reload_p.
73 * rtlanal.c (reg_set_p): Check whether REG overlaps
74 regs_invalidated_by_call, rather than just checking the
75 membership of REGNO (REG).
77 2007-05-16 Eric Christopher <echristo@apple.com> (r124763)
79 * config/rs6000/rs6000.c (rs6000_emit_prologue): Move altivec register
80 saving after stack push. Set sp_offset whenever we push.
81 (rs6000_emit_epilogue): Move altivec register restore before stack push.
83 2007-05-03 Ian Lance Taylor <iant@google.com> (r124381)
85 * config/rs6000/rs6000.c (rs6000_override_options): Don't set
86 MASK_PPC_GFXOPT for 8540 or 8548.
88 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341)
90 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
93 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
95 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
96 and athlon64-sse3 as improved versions of k8, opteron and athlon64
97 with SSE3 instruction set support.
98 * doc/invoke.texi: Likewise.
100 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330)
102 * config/i386/i386.c (override_options): Tuning 32-byte loop
103 alignment for amdfam10 architecture. Increasing the max loop
104 alignment to 24 bytes.
106 2007-04-16 Lawrence Crowl <crowl@google.com> (r123909)
108 * doc/invoke.texi (Debugging Options): Add documentation for the
109 -femit-struct-debug options -femit-struct-debug-baseonly,
110 -femit-struct-debug-reduced, and
111 -femit-struct-debug-detailed[=...].
113 * c-opts.c (c_common_handle_option): Add
114 OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced,
115 and OPT_femit_struct_debug_detailed_.
116 * c.opt: Add specifications for
117 -femit-struct-debug-baseonly, -femit-struct-debug-reduced,
118 and -femit-struct-debug-detailed[=...].
119 * opts.c (set_struct_debug_option): Parse the
120 -femit-struct-debug-... options.
121 * opts.c (matches_main_base, main_input_basename,
122 main_input_baselength, base_of_path, matches_main_base): Add
123 variables and functions to compare header base name to compilation
125 * opts.c (should_emit_struct_debug): Add to determine to emit a
126 structure based on the option.
127 (dump_struct_debug) Also disabled function to debug this
129 * opts.c (handle_options): Save the base name of the
132 * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define.
133 (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add.
134 This hook indicates if a type is generic. Set it by default
136 * langhooks.h (struct lang_hooks_for_types): Add a new hook
137 to determine if a struct type is generic or not.
138 * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook.
139 * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook.
140 * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook
143 * flags.h (enum debug_info_usage): Add an enumeration to describe
144 a program's use of a structure type.
145 * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter
146 to indicate the program's usage of the type. Filter structs based
147 on the -femit-struct-debug-... specification.
148 (gen_type_die): Split into two routines, gen_type_die and
149 gen_type_die_with_usage. gen_type_die is now a wrapper
150 that assumes direct usage.
151 (gen_type_die_with_usage): Replace calls to gen_type_die
152 with gen_type_die_with_usage adding the program usage of
154 (dwarf2out_imported_module_or_decl): Suppress struct debug
155 information using should_emit_struct_debug when appropriate.
157 2007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
159 PR tree-optimization/24689
160 PR tree-optimization/31307
161 * fold-const.c (operand_equal_p): Compare INTEGER_CST array
163 * gimplify.c (canonicalize_addr_expr): To be consistent with
164 gimplify_compound_lval only set operands two and three of
165 ARRAY_REFs if they are not gimple_min_invariant. This makes
166 it never at this place.
167 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
169 2007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
171 * config/i386/i386.c (ix86_handle_option): Handle SSSE3.
173 2007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313)
175 * config.gcc: Accept barcelona as a variant of amdfam10.
176 * config/i386/i386.c (override_options): Likewise.
177 * doc/invoke.texi: Likewise.
179 2007-03-12 Seongbae Park <seongbae.park@gmail.com> (r122851)
181 * c-decl.c (warn_variable_length_array): New function.
182 Refactored from grokdeclarator to handle warn_vla
183 and handle unnamed array case.
184 (grokdeclarator): Refactored VLA warning case.
185 * c.opt (Wvla): New flag.
187 2007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial)
189 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and
190 the *_DIV_EXPR codes correctly with overflow infinities.
192 2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763)
194 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
197 2007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
199 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h
200 conditional to __SSE2__.
201 (Entries below should have been added to first ChangeLog
202 entry for amdfam10 dated 2007-02-05)
203 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not
205 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
207 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
210 2007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
212 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
214 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
216 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8,
217 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov,
218 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul,
219 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn,
220 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8,
221 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load,
222 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8,
223 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10.
225 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
227 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse,
228 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387,
229 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse,
230 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse,
231 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed,
232 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse,
233 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1,
234 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn,
235 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn,
236 umuldi3_highpart_rex64, umulsi3_highpart_insn,
237 umulsi3_highpart_zext, smuldi3_highpart_rex64,
238 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld,
239 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse,
240 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387,
241 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387,
242 sqrtextenddfxf2_i387): Added amdfam10_decode.
244 * config/i386/athlon.md (athlon_idirect_amdfam10,
245 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10,
246 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10,
247 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10,
248 athlon_ivector_store_amdfam10): New define_insn_reservation.
249 (athlon_idirect_loadmov, athlon_idirect_movstore): Added
252 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
254 * config/i386/athlon.md (athlon_call_amdfam10,
255 athlon_pop_amdfam10, athlon_lea_amdfam10): New
256 define_insn_reservation.
257 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8,
258 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI,
259 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10.
261 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
263 * config/i386/athlon.md (athlon_sseld_amdfam10,
264 athlon_mmxld_amdfam10, athlon_ssest_amdfam10,
265 athlon_mmxssest_short_amdfam10): New define_insn_reservation.
267 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
269 * config/i386/athlon.md (athlon_sseins_amdfam10): New
270 define_insn_reservation.
271 * config/i386/i386.md (sseins): Added sseins to define_attr type
272 and define_attr unit.
273 * config/i386/sse.md: Set type attribute to sseins for insertq
276 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
278 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10,
279 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10,
280 ssecomi_load_amdfam10, ssecomi_amdfam10,
281 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New
282 define_insn_reservation.
283 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10.
285 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
287 * config/i386/athlon.md (cvtss2sd_load_amdfam10,
288 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10,
289 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10,
290 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10,
291 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10,
292 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New
293 define_insn_reservation.
295 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si,
296 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq,
297 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq,
298 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd,
299 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute.
301 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
303 * config/i386/athlon.md (athlon_ssedivvector_amdfam10,
304 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10,
305 athlon_ssemulvector_load_amdfam10): New define_insn_reservation.
306 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul,
307 athlon_ssemul_load_k8): Added amdfam10.
309 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
311 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro.
312 (x86_sse_unaligned_move_optimal): New variable.
314 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for
316 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups
317 for unaligned vector SSE double/single precision loads for AMDFAM10.
319 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
321 * config/i386/i386.h (TARGET_AMDFAM10): New macro.
322 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10.
323 Define TARGET_CPU_DEFAULT_amdfam10.
324 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10.
325 (processor_type): Add PROCESSOR_AMDFAM10.
327 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match
328 processor_type in config/i386/i386.h.
329 Enable imul peepholes for TARGET_AMDFAM10.
331 * config.gcc: Add support for --with-cpu option for amdfam10.
333 * config/i386/i386.c (amdfam10_cost): New variable.
334 (m_AMDFAM10): New macro.
335 (m_ATHLON_K8_AMDFAM10): New macro.
336 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
337 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop,
338 x86_promote_QImode, x86_integer_DFmode_moves,
339 x86_partial_reg_dependency, x86_memory_mismatch_stall,
340 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387,
341 x86_sse_partial_reg_dependency, x86_sse_typeless_stores,
342 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit,
343 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns):
344 Enable/disable for amdfam10.
345 (override_options): Add amdfam10_cost to processor_target_table.
346 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in
347 processor_alias_table.
348 (ix86_issue_rate): Add PROCESSOR_AMDFAM10.
349 (ix86_adjust_cost): Add code for amdfam10.
351 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
353 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm)
354 instruction set feature flag. Add new (-mpopcnt) flag for popcnt
355 instruction. Add new SSE4A (-msse4a) instruction set feature flag.
356 * config/i386/i386.h: Add builtin definition for SSE4A.
357 * config/i386/i386.md: Add support for ABM instructions
359 * config/i386/sse.md: Add support for SSE4A instructions
360 (movntss, movntsd, extrq, insertq).
361 * config/i386/i386.c: Add support for ABM and SSE4A builtins.
362 Add -march=amdfam10 flag.
363 * config/i386/ammintrin.h: Add support for SSE4A intrinsics.
364 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt
366 * doc/extend.texi: Add documentation for SSE4A builtins.
368 2007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140)
370 * config/i386/i386.h (x86_cmpxchg16b): Remove const.
371 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b.
372 * config/i386/i386.c (x86_cmpxchg16b): Remove const.
373 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b
374 for CPUs that have PTA_CX16 set.
376 2007-01-17 Eric Christopher <echristo@apple.com> (r120846)
378 * config.gcc: Support core2 processor.
380 2007-01-05 Manuel Lopez-Ibanez <manu@gcc.gnu.org> (r120505)
383 * tree.h (TREE_OVERFLOW_P): New.
384 * c-typeck.c (parser_build_unary_op): Warn only if result
385 overflowed and operands did not.
386 (parser_build_binary_op): Likewise.
387 (convert_for_assignment): Remove redundant overflow_warning.
388 * c-common.c (overflow_warning): Don't check or set TREE_OVERFLOW.
390 2006-12-13 Ian Lance Taylor <iant@google.com> (r119855)
394 * c-typeck.c (parser_build_binary_op): Move parentheses warnings
395 to warn_about_parentheses in c-common.c.
396 * c-common.c (warn_about_parentheses): New function.
397 * c-common.h (warn_about_parentheses): Declare.
398 * doc/invoke.texi (Warning Options): Update -Wparentheses
401 2006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
404 * config/i386/driver-i386.c (bit_SSSE3): New.
406 2006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260)
408 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2
411 2006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
413 * doc/invoke.texi (core2): Add item.
415 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
417 (TARGET_CPU_CPP_BUILTINS): Add code for core2.
418 (TARGET_CPU_DEFAULT_generic): Change value.
419 (TARGET_CPU_DEFAULT_NAMES): Add core2.
420 (processor_type): Add new constant PROCESSOR_CORE2.
422 * config/i386/i386.md (cpu): Add core2.
424 * config/i386/i386.c (core2_cost): New initialized variable.
425 (m_CORE2): New macro.
426 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
427 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
428 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
429 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
430 x86_partial_reg_dependency, x86_memory_mismatch_stall,
431 x86_accumulate_outgoing_args, x86_prologue_using_move,
432 x86_epilogue_using_move, x86_arch_always_fancy_math_387,
433 x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
434 x86_use_incdec, x86_four_jump_limit, x86_schedule,
435 x86_pad_returns): Add m_CORE2.
436 (override_options): Add entries for Core2.
437 (ix86_issue_rate): Add case for Core2.
439 2006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356)
441 * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on
442 inline static functions in c99 mode.
445 * doc/extend.texi (Inline): Update.
446 * c-tree.h (struct language_function): Remove field 'extern_inline'.
447 * c-decl.c (current_extern_inline): Delete.
448 (pop_scope): Adjust test for an undefined nested function.
449 Add warning about undeclared inline function.
450 (diagnose_mismatched_decls): Update comments. Disallow overriding
451 of inline functions in a translation unit in C99. Allow inline
452 declarations in C99 at any time.
453 (merge_decls): Boolize variables. Handle C99 'extern inline'
455 (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle
456 C99 inline semantics.
457 (start_function): Don't clear current_extern_inline. Don't set
459 (c_push_function_context): Don't push current_extern_inline.
460 (c_pop_function_context): Don't restore current_extern_inline.
463 * c-typeck.c (build_external_ref): Warn about static variables
464 used in extern inline functions.
465 * c-decl.c (start_decl): Warn about static variables declared
466 in extern inline functions.
468 2006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090)
470 * config/i386/i386.h (TARGET_GEODE):
471 (TARGET_CPU_CPP_BUILTINS): Add code for geode.
472 (TARGET_CPU_DEFAULT_geode): New macro.
473 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2,
474 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon,
475 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8,
476 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott,
477 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase
479 (TARGET_CPU_DEFAULT_NAMES): Add geode.
480 (processor_type): Add PROCESSOR_GEODE.
482 * config/i386/i386.md: Include geode.md.
485 * config/i386/i386.c (geode_cost): New initialized global
487 (m_GEODE, m_K6_GEODE): New macros.
488 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf,
489 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4,
490 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants,
491 x86_schedule): Use m_K6_GEODE instead of m_K6.
492 (x86_movx, x86_cmove): Set up m_GEODE.
493 (x86_integer_DFmode_moves): Clear m_GEODE.
494 (processor_target_table): Add entry for geode.
495 (processor_alias_table): Ditto.
497 * config/i386/geode.md: New file.
499 * doc/invoke.texi: Add entry about geode processor.
501 2006-10-24 Richard Guenther <rguenther@suse.de> (r118001)
504 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES
505 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS
506 for deciding optimizations in consistency with fold-const.c
507 (fold_builtin_unordered_cmp): Likewise.
509 2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958)
511 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
512 (x86_64-*-*): Likewise.
514 * config/i386/i386.c (pta_flags): Add PTA_SSSE3.
515 (override_options): Check SSSE3.
516 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
517 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
518 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
519 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
520 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
521 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
522 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
523 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
524 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
525 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
526 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
527 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
528 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
529 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
530 IX86_BUILTIN_PABSD128.
531 (bdesc_2arg): Add SSSE3.
532 (bdesc_1arg): Likewise.
533 (ix86_init_mmx_sse_builtins): Support SSSE3.
534 (ix86_expand_builtin): Likewise.
535 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
537 * config/i386/i386.md (UNSPEC_PSHUFB): New.
538 (UNSPEC_PSIGN): Likewise.
539 (UNSPEC_PALIGNR): Likewise.
540 Include mmx.md before sse.md.
542 * config/i386/i386.opt: Add -mssse3.
544 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
545 (ssse3_phaddwv4hi3): Likewise.
546 (ssse3_phadddv4si3): Likewise.
547 (ssse3_phadddv2si3): Likewise.
548 (ssse3_phaddswv8hi3): Likewise.
549 (ssse3_phaddswv4hi3): Likewise.
550 (ssse3_phsubwv8hi3): Likewise.
551 (ssse3_phsubwv4hi3): Likewise.
552 (ssse3_phsubdv4si3): Likewise.
553 (ssse3_phsubdv2si3): Likewise.
554 (ssse3_phsubswv8hi3): Likewise.
555 (ssse3_phsubswv4hi3): Likewise.
556 (ssse3_pmaddubswv8hi3): Likewise.
557 (ssse3_pmaddubswv4hi3): Likewise.
558 (ssse3_pmulhrswv8hi3): Likewise.
559 (ssse3_pmulhrswv4hi3): Likewise.
560 (ssse3_pshufbv16qi3): Likewise.
561 (ssse3_pshufbv8qi3): Likewise.
562 (ssse3_psign<mode>3): Likewise.
563 (ssse3_psign<mode>3): Likewise.
564 (ssse3_palignrti): Likewise.
565 (ssse3_palignrdi): Likewise.
566 (abs<mode>2): Likewise.
567 (abs<mode>2): Likewise.
569 * config/i386/tmmintrin.h: New file.
571 * doc/extend.texi: Document SSSE3 built-in functions.
573 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
575 2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959)
577 * config/i386/tmmintrin.h: Remove the duplicated content.
579 2006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
581 PR tree-optimization/3511
582 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
583 got new invariant arguments during PHI translation.
585 2006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
587 * builtins.c (fold_builtin_classify): Fix typo.