1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 (define_predicate "s_register_operand"
23 (match_code "reg,subreg")
25 if (GET_CODE (op) == SUBREG)
27 /* We don't consider registers whose class is NO_REGS
28 to be a register operand. */
29 /* XXX might have to check for lo regs only for thumb ??? */
30 return (GET_CODE (op) == REG
31 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
32 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
36 (define_predicate "arm_hard_register_operand"
39 return REGNO (op) < FIRST_PSEUDO_REGISTER;
42 ;; Any core register, or any pseudo. */
43 (define_predicate "arm_general_register_operand"
44 (match_code "reg,subreg")
46 if (GET_CODE (op) == SUBREG)
49 return (GET_CODE (op) == REG
50 && (REGNO (op) <= LAST_ARM_REGNUM
51 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
54 (define_predicate "f_register_operand"
55 (match_code "reg,subreg")
57 if (GET_CODE (op) == SUBREG)
60 /* We don't consider registers whose class is NO_REGS
61 to be a register operand. */
62 return (GET_CODE (op) == REG
63 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
64 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
67 ;; Reg, subreg(reg) or const_int.
68 (define_predicate "reg_or_int_operand"
69 (ior (match_code "const_int")
70 (match_operand 0 "s_register_operand")))
72 (define_predicate "arm_immediate_operand"
73 (and (match_code "const_int")
74 (match_test "const_ok_for_arm (INTVAL (op))")))
76 (define_predicate "arm_neg_immediate_operand"
77 (and (match_code "const_int")
78 (match_test "const_ok_for_arm (-INTVAL (op))")))
80 (define_predicate "arm_not_immediate_operand"
81 (and (match_code "const_int")
82 (match_test "const_ok_for_arm (~INTVAL (op))")))
84 ;; Something valid on the RHS of an ARM data-processing instruction
85 (define_predicate "arm_rhs_operand"
86 (ior (match_operand 0 "s_register_operand")
87 (match_operand 0 "arm_immediate_operand")))
89 (define_predicate "arm_rhsm_operand"
90 (ior (match_operand 0 "arm_rhs_operand")
91 (match_operand 0 "memory_operand")))
93 (define_predicate "arm_add_operand"
94 (ior (match_operand 0 "arm_rhs_operand")
95 (match_operand 0 "arm_neg_immediate_operand")))
97 (define_predicate "arm_addimm_operand"
98 (ior (match_operand 0 "arm_immediate_operand")
99 (match_operand 0 "arm_neg_immediate_operand")))
101 (define_predicate "arm_not_operand"
102 (ior (match_operand 0 "arm_rhs_operand")
103 (match_operand 0 "arm_not_immediate_operand")))
105 ;; True if the operand is a memory reference which contains an
106 ;; offsettable address.
107 (define_predicate "offsettable_memory_operand"
108 (and (match_code "mem")
110 "offsettable_address_p (reload_completed | reload_in_progress,
111 mode, XEXP (op, 0))")))
113 ;; True if the operand is a memory operand that does not have an
114 ;; automodified base register (and thus will not generate output reloads).
115 (define_predicate "call_memory_operand"
116 (and (match_code "mem")
117 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
119 (match_operand 0 "memory_operand"))))
121 (define_predicate "arm_reload_memory_operand"
122 (and (match_code "mem,reg,subreg")
123 (match_test "(!CONSTANT_P (op)
124 && (true_regnum(op) == -1
125 || (GET_CODE (op) == REG
126 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
128 ;; True for valid operands for the rhs of an floating point insns.
129 ;; Allows regs or certain consts on FPA, just regs for everything else.
130 (define_predicate "arm_float_rhs_operand"
131 (ior (match_operand 0 "s_register_operand")
132 (and (match_code "const_double")
133 (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
135 (define_predicate "arm_float_add_operand"
136 (ior (match_operand 0 "arm_float_rhs_operand")
137 (and (match_code "const_double")
138 (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
140 (define_predicate "vfp_compare_operand"
141 (ior (match_operand 0 "s_register_operand")
142 (and (match_code "const_double")
143 (match_test "arm_const_double_rtx (op)"))))
145 (define_predicate "arm_float_compare_operand"
146 (if_then_else (match_test "TARGET_VFP")
147 (match_operand 0 "vfp_compare_operand")
148 (match_operand 0 "arm_float_rhs_operand")))
150 ;; True for valid index operands.
151 (define_predicate "index_operand"
152 (ior (match_operand 0 "s_register_operand")
153 (and (match_operand 0 "immediate_operand")
154 (match_test "(GET_CODE (op) != CONST_INT
155 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
157 ;; True for operators that can be combined with a shift in ARM state.
158 (define_special_predicate "shiftable_operator"
159 (and (match_code "plus,minus,ior,xor,and")
160 (match_test "mode == GET_MODE (op)")))
162 ;; True for logical binary operators.
163 (define_special_predicate "logical_binary_operator"
164 (and (match_code "ior,xor,and")
165 (match_test "mode == GET_MODE (op)")))
167 ;; True for shift operators.
168 (define_special_predicate "shift_operator"
169 (and (ior (ior (and (match_code "mult")
170 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
171 (and (match_code "rotate")
172 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
173 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
174 (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
175 (match_test "mode == GET_MODE (op)")))
178 (define_special_predicate "equality_operator"
179 (match_code "eq,ne"))
181 ;; True for comparisons other than LTGT or UNEQ.
182 (define_special_predicate "arm_comparison_operator"
183 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
185 (define_special_predicate "minmax_operator"
186 (and (match_code "smin,smax,umin,umax")
187 (match_test "mode == GET_MODE (op)")))
189 (define_special_predicate "cc_register"
190 (and (match_code "reg")
191 (and (match_test "REGNO (op) == CC_REGNUM")
192 (ior (match_test "mode == GET_MODE (op)")
193 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
195 (define_special_predicate "dominant_cc_register"
198 if (mode == VOIDmode)
200 mode = GET_MODE (op);
202 if (GET_MODE_CLASS (mode) != MODE_CC)
206 return (cc_register (op, mode)
207 && (mode == CC_DNEmode
208 || mode == CC_DEQmode
209 || mode == CC_DLEmode
210 || mode == CC_DLTmode
211 || mode == CC_DGEmode
212 || mode == CC_DGTmode
213 || mode == CC_DLEUmode
214 || mode == CC_DLTUmode
215 || mode == CC_DGEUmode
216 || mode == CC_DGTUmode));
219 (define_special_predicate "arm_extendqisi_mem_op"
220 (and (match_operand 0 "memory_operand")
221 (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
224 (define_predicate "power_of_two_operand"
225 (match_code "const_int")
227 HOST_WIDE_INT value = INTVAL (op);
229 return value != 0 && (value & (value - 1)) == 0;
232 (define_predicate "nonimmediate_di_operand"
233 (match_code "reg,subreg,mem")
235 if (s_register_operand (op, mode))
238 if (GET_CODE (op) == SUBREG)
239 op = SUBREG_REG (op);
241 return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
244 (define_predicate "di_operand"
245 (ior (match_code "const_int,const_double")
246 (and (match_code "reg,subreg,mem")
247 (match_operand 0 "nonimmediate_di_operand"))))
249 (define_predicate "nonimmediate_soft_df_operand"
250 (match_code "reg,subreg,mem")
252 if (s_register_operand (op, mode))
255 if (GET_CODE (op) == SUBREG)
256 op = SUBREG_REG (op);
258 return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
261 (define_predicate "soft_df_operand"
262 (ior (match_code "const_double")
263 (and (match_code "reg,subreg,mem")
264 (match_operand 0 "nonimmediate_soft_df_operand"))))
266 (define_predicate "const_shift_operand"
267 (and (match_code "const_int")
268 (ior (match_operand 0 "power_of_two_operand")
269 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
272 (define_special_predicate "load_multiple_operation"
273 (match_code "parallel")
275 HOST_WIDE_INT count = XVECLEN (op, 0);
278 HOST_WIDE_INT i = 1, base = 0;
282 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
285 /* Check to see if this might be a write-back. */
286 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
291 /* Now check it more carefully. */
292 if (GET_CODE (SET_DEST (elt)) != REG
293 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
294 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
295 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
299 /* Perform a quick check so we don't blow up below. */
301 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
302 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
303 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
306 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
307 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
309 for (; i < count; i++)
311 elt = XVECEXP (op, 0, i);
313 if (GET_CODE (elt) != SET
314 || GET_CODE (SET_DEST (elt)) != REG
315 || GET_MODE (SET_DEST (elt)) != SImode
316 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
317 || GET_CODE (SET_SRC (elt)) != MEM
318 || GET_MODE (SET_SRC (elt)) != SImode
319 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
320 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
321 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
322 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
329 (define_special_predicate "store_multiple_operation"
330 (match_code "parallel")
332 HOST_WIDE_INT count = XVECLEN (op, 0);
335 HOST_WIDE_INT i = 1, base = 0;
339 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
342 /* Check to see if this might be a write-back. */
343 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
348 /* Now check it more carefully. */
349 if (GET_CODE (SET_DEST (elt)) != REG
350 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
351 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
352 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
356 /* Perform a quick check so we don't blow up below. */
358 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
359 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
360 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
363 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
364 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
366 for (; i < count; i++)
368 elt = XVECEXP (op, 0, i);
370 if (GET_CODE (elt) != SET
371 || GET_CODE (SET_SRC (elt)) != REG
372 || GET_MODE (SET_SRC (elt)) != SImode
373 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
374 || GET_CODE (SET_DEST (elt)) != MEM
375 || GET_MODE (SET_DEST (elt)) != SImode
376 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
377 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
378 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
379 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
386 (define_special_predicate "multi_register_push"
387 (match_code "parallel")
389 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
390 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
391 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
397 ;;-------------------------------------------------------------------------
402 (define_predicate "thumb_cmp_operand"
403 (ior (and (match_code "reg,subreg")
404 (match_operand 0 "s_register_operand"))
405 (and (match_code "const_int")
406 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
408 (define_predicate "thumb_cmpneg_operand"
409 (and (match_code "const_int")
410 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
412 ;; Return TRUE if a result can be stored in OP without clobbering the
413 ;; condition code register. Prior to reload we only accept a
414 ;; register. After reload we have to be able to handle memory as
415 ;; well, since a pseudo may not get a hard reg and reload cannot
416 ;; handle output-reloads on jump insns.
418 ;; We could possibly handle mem before reload as well, but that might
419 ;; complicate things with the need to handle increment
421 (define_predicate "thumb_cbrch_target_operand"
422 (and (match_code "reg,subreg,mem")
423 (ior (match_operand 0 "s_register_operand")
424 (and (match_test "reload_in_progress || reload_completed")
425 (match_operand 0 "memory_operand")))))
427 ;;-------------------------------------------------------------------------
429 ;; MAVERICK predicates
432 (define_predicate "cirrus_register_operand"
433 (match_code "reg,subreg")
435 if (GET_CODE (op) == SUBREG)
436 op = SUBREG_REG (op);
438 return (GET_CODE (op) == REG
439 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
440 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
443 (define_predicate "cirrus_fp_register"
444 (match_code "reg,subreg")
446 if (GET_CODE (op) == SUBREG)
447 op = SUBREG_REG (op);
449 return (GET_CODE (op) == REG
450 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
451 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
454 (define_predicate "cirrus_shift_const"
455 (and (match_code "const_int")
456 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))