1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
74 (UNSPEC_DLMZB_STRLEN 47)
78 ;; UNSPEC_VOLATILE usage
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
88 ;; Define an insn type attribute. This is used in function unit delay
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
91 (const_string "integer"))
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
100 (lt (minus (match_dup 0) (pc))
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
110 (const (symbol_ref "rs6000_cpu_attr")))
112 (automata_option "ndfa")
125 (include "power4.md")
126 (include "power5.md")
128 (include "predicates.md")
129 (include "constraints.md")
131 (include "darwin.md")
136 ; This mode macro allows :GPR to be used to indicate the allowable size
137 ; of whole values in GPRs.
138 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
140 ; Any supported integer mode.
141 (define_mode_macro INT [QI HI SI DI TI])
143 ; Any supported integer mode that fits in one register.
144 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
146 ; extend modes for DImode
147 (define_mode_macro QHSI [QI HI SI])
149 ; SImode or DImode, even if DImode doesn't fit in GPRs.
150 (define_mode_macro SDI [SI DI])
152 ; The size of a pointer. Also, the size of the value that a record-condition
153 ; (one with a '.') will compare.
154 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
156 ; Any hardware-supported floating-point mode
157 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
158 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
159 (TF "!TARGET_IEEEQUAD
160 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
162 ; Various instructions that come in SI and DI forms.
163 ; A generic w/d attribute, for things like cmpw/cmpd.
164 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
167 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
170 ;; Start with fixed-point load and store insns. Here we put only the more
171 ;; complex forms. Basic data transfer is done later.
173 (define_expand "zero_extend<mode>di2"
174 [(set (match_operand:DI 0 "gpc_reg_operand" "")
175 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
179 (define_insn "*zero_extend<mode>di2_internal1"
180 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
181 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
185 rldicl %0,%1,0,<dbits>"
186 [(set_attr "type" "load,*")])
188 (define_insn "*zero_extend<mode>di2_internal2"
189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
190 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
192 (clobber (match_scratch:DI 2 "=r,r"))]
195 rldicl. %2,%1,0,<dbits>
197 [(set_attr "type" "compare")
198 (set_attr "length" "4,8")])
201 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
202 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
204 (clobber (match_scratch:DI 2 ""))]
205 "TARGET_POWERPC64 && reload_completed"
207 (zero_extend:DI (match_dup 1)))
209 (compare:CC (match_dup 2)
213 (define_insn "*zero_extend<mode>di2_internal3"
214 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
215 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
217 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
218 (zero_extend:DI (match_dup 1)))]
221 rldicl. %0,%1,0,<dbits>
223 [(set_attr "type" "compare")
224 (set_attr "length" "4,8")])
227 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
228 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
230 (set (match_operand:DI 0 "gpc_reg_operand" "")
231 (zero_extend:DI (match_dup 1)))]
232 "TARGET_POWERPC64 && reload_completed"
234 (zero_extend:DI (match_dup 1)))
236 (compare:CC (match_dup 0)
240 (define_insn "extendqidi2"
241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
242 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
248 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
250 (clobber (match_scratch:DI 2 "=r,r"))]
255 [(set_attr "type" "compare")
256 (set_attr "length" "4,8")])
259 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
260 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
262 (clobber (match_scratch:DI 2 ""))]
263 "TARGET_POWERPC64 && reload_completed"
265 (sign_extend:DI (match_dup 1)))
267 (compare:CC (match_dup 2)
272 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
273 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
275 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
276 (sign_extend:DI (match_dup 1)))]
281 [(set_attr "type" "compare")
282 (set_attr "length" "4,8")])
285 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
286 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
288 (set (match_operand:DI 0 "gpc_reg_operand" "")
289 (sign_extend:DI (match_dup 1)))]
290 "TARGET_POWERPC64 && reload_completed"
292 (sign_extend:DI (match_dup 1)))
294 (compare:CC (match_dup 0)
298 (define_expand "extendhidi2"
299 [(set (match_operand:DI 0 "gpc_reg_operand" "")
300 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
306 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
311 [(set_attr "type" "load_ext,*")])
314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
315 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
317 (clobber (match_scratch:DI 2 "=r,r"))]
322 [(set_attr "type" "compare")
323 (set_attr "length" "4,8")])
326 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
327 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (clobber (match_scratch:DI 2 ""))]
330 "TARGET_POWERPC64 && reload_completed"
332 (sign_extend:DI (match_dup 1)))
334 (compare:CC (match_dup 2)
339 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
340 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
342 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
343 (sign_extend:DI (match_dup 1)))]
348 [(set_attr "type" "compare")
349 (set_attr "length" "4,8")])
352 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
353 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
355 (set (match_operand:DI 0 "gpc_reg_operand" "")
356 (sign_extend:DI (match_dup 1)))]
357 "TARGET_POWERPC64 && reload_completed"
359 (sign_extend:DI (match_dup 1)))
361 (compare:CC (match_dup 0)
365 (define_expand "extendsidi2"
366 [(set (match_operand:DI 0 "gpc_reg_operand" "")
367 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
373 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
378 [(set_attr "type" "load_ext,*")])
381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
382 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
384 (clobber (match_scratch:DI 2 "=r,r"))]
389 [(set_attr "type" "compare")
390 (set_attr "length" "4,8")])
393 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
394 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
396 (clobber (match_scratch:DI 2 ""))]
397 "TARGET_POWERPC64 && reload_completed"
399 (sign_extend:DI (match_dup 1)))
401 (compare:CC (match_dup 2)
406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
407 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
409 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
410 (sign_extend:DI (match_dup 1)))]
415 [(set_attr "type" "compare")
416 (set_attr "length" "4,8")])
419 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
420 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
422 (set (match_operand:DI 0 "gpc_reg_operand" "")
423 (sign_extend:DI (match_dup 1)))]
424 "TARGET_POWERPC64 && reload_completed"
426 (sign_extend:DI (match_dup 1)))
428 (compare:CC (match_dup 0)
432 (define_expand "zero_extendqisi2"
433 [(set (match_operand:SI 0 "gpc_reg_operand" "")
434 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
440 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
444 {rlinm|rlwinm} %0,%1,0,0xff"
445 [(set_attr "type" "load,*")])
448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
449 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
451 (clobber (match_scratch:SI 2 "=r,r"))]
454 {andil.|andi.} %2,%1,0xff
456 [(set_attr "type" "compare")
457 (set_attr "length" "4,8")])
460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
461 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
463 (clobber (match_scratch:SI 2 ""))]
466 (zero_extend:SI (match_dup 1)))
468 (compare:CC (match_dup 2)
473 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
474 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
476 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
477 (zero_extend:SI (match_dup 1)))]
480 {andil.|andi.} %0,%1,0xff
482 [(set_attr "type" "compare")
483 (set_attr "length" "4,8")])
486 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
487 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
489 (set (match_operand:SI 0 "gpc_reg_operand" "")
490 (zero_extend:SI (match_dup 1)))]
493 (zero_extend:SI (match_dup 1)))
495 (compare:CC (match_dup 0)
499 (define_expand "extendqisi2"
500 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
501 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
506 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
507 else if (TARGET_POWER)
508 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
510 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
514 (define_insn "extendqisi2_ppc"
515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
516 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
522 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
524 (clobber (match_scratch:SI 2 "=r,r"))]
529 [(set_attr "type" "compare")
530 (set_attr "length" "4,8")])
533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
534 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
536 (clobber (match_scratch:SI 2 ""))]
537 "TARGET_POWERPC && reload_completed"
539 (sign_extend:SI (match_dup 1)))
541 (compare:CC (match_dup 2)
546 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
547 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
549 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
550 (sign_extend:SI (match_dup 1)))]
555 [(set_attr "type" "compare")
556 (set_attr "length" "4,8")])
559 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
560 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
562 (set (match_operand:SI 0 "gpc_reg_operand" "")
563 (sign_extend:SI (match_dup 1)))]
564 "TARGET_POWERPC && reload_completed"
566 (sign_extend:SI (match_dup 1)))
568 (compare:CC (match_dup 0)
572 (define_expand "extendqisi2_power"
573 [(parallel [(set (match_dup 2)
574 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
576 (clobber (scratch:SI))])
577 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
578 (ashiftrt:SI (match_dup 2)
580 (clobber (scratch:SI))])]
583 { operands[1] = gen_lowpart (SImode, operands[1]);
584 operands[2] = gen_reg_rtx (SImode); }")
586 (define_expand "extendqisi2_no_power"
588 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
590 (set (match_operand:SI 0 "gpc_reg_operand" "")
591 (ashiftrt:SI (match_dup 2)
593 "! TARGET_POWER && ! TARGET_POWERPC"
595 { operands[1] = gen_lowpart (SImode, operands[1]);
596 operands[2] = gen_reg_rtx (SImode); }")
598 (define_expand "zero_extendqihi2"
599 [(set (match_operand:HI 0 "gpc_reg_operand" "")
600 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
605 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
606 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
610 {rlinm|rlwinm} %0,%1,0,0xff"
611 [(set_attr "type" "load,*")])
614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
615 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
617 (clobber (match_scratch:HI 2 "=r,r"))]
620 {andil.|andi.} %2,%1,0xff
622 [(set_attr "type" "compare")
623 (set_attr "length" "4,8")])
626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
627 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
629 (clobber (match_scratch:HI 2 ""))]
632 (zero_extend:HI (match_dup 1)))
634 (compare:CC (match_dup 2)
639 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
640 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
642 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
643 (zero_extend:HI (match_dup 1)))]
646 {andil.|andi.} %0,%1,0xff
648 [(set_attr "type" "compare")
649 (set_attr "length" "4,8")])
652 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
653 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
655 (set (match_operand:HI 0 "gpc_reg_operand" "")
656 (zero_extend:HI (match_dup 1)))]
659 (zero_extend:HI (match_dup 1)))
661 (compare:CC (match_dup 0)
665 (define_expand "extendqihi2"
666 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
667 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
672 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
673 else if (TARGET_POWER)
674 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
676 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
680 (define_insn "extendqihi2_ppc"
681 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
682 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
687 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
688 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
690 (clobber (match_scratch:HI 2 "=r,r"))]
695 [(set_attr "type" "compare")
696 (set_attr "length" "4,8")])
699 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
700 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
702 (clobber (match_scratch:HI 2 ""))]
703 "TARGET_POWERPC && reload_completed"
705 (sign_extend:HI (match_dup 1)))
707 (compare:CC (match_dup 2)
712 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
713 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
715 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
716 (sign_extend:HI (match_dup 1)))]
721 [(set_attr "type" "compare")
722 (set_attr "length" "4,8")])
725 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
726 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
728 (set (match_operand:HI 0 "gpc_reg_operand" "")
729 (sign_extend:HI (match_dup 1)))]
730 "TARGET_POWERPC && reload_completed"
732 (sign_extend:HI (match_dup 1)))
734 (compare:CC (match_dup 0)
738 (define_expand "extendqihi2_power"
739 [(parallel [(set (match_dup 2)
740 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
742 (clobber (scratch:SI))])
743 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
744 (ashiftrt:SI (match_dup 2)
746 (clobber (scratch:SI))])]
749 { operands[0] = gen_lowpart (SImode, operands[0]);
750 operands[1] = gen_lowpart (SImode, operands[1]);
751 operands[2] = gen_reg_rtx (SImode); }")
753 (define_expand "extendqihi2_no_power"
755 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
757 (set (match_operand:HI 0 "gpc_reg_operand" "")
758 (ashiftrt:SI (match_dup 2)
760 "! TARGET_POWER && ! TARGET_POWERPC"
762 { operands[0] = gen_lowpart (SImode, operands[0]);
763 operands[1] = gen_lowpart (SImode, operands[1]);
764 operands[2] = gen_reg_rtx (SImode); }")
766 (define_expand "zero_extendhisi2"
767 [(set (match_operand:SI 0 "gpc_reg_operand" "")
768 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
774 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
778 {rlinm|rlwinm} %0,%1,0,0xffff"
779 [(set_attr "type" "load,*")])
782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
783 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
785 (clobber (match_scratch:SI 2 "=r,r"))]
788 {andil.|andi.} %2,%1,0xffff
790 [(set_attr "type" "compare")
791 (set_attr "length" "4,8")])
794 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
795 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
797 (clobber (match_scratch:SI 2 ""))]
800 (zero_extend:SI (match_dup 1)))
802 (compare:CC (match_dup 2)
807 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
808 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
811 (zero_extend:SI (match_dup 1)))]
814 {andil.|andi.} %0,%1,0xffff
816 [(set_attr "type" "compare")
817 (set_attr "length" "4,8")])
820 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
821 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
823 (set (match_operand:SI 0 "gpc_reg_operand" "")
824 (zero_extend:SI (match_dup 1)))]
827 (zero_extend:SI (match_dup 1)))
829 (compare:CC (match_dup 0)
833 (define_expand "extendhisi2"
834 [(set (match_operand:SI 0 "gpc_reg_operand" "")
835 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
841 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
846 [(set_attr "type" "load_ext,*")])
849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
850 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
852 (clobber (match_scratch:SI 2 "=r,r"))]
857 [(set_attr "type" "compare")
858 (set_attr "length" "4,8")])
861 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
862 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
864 (clobber (match_scratch:SI 2 ""))]
867 (sign_extend:SI (match_dup 1)))
869 (compare:CC (match_dup 2)
874 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
875 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
878 (sign_extend:SI (match_dup 1)))]
883 [(set_attr "type" "compare")
884 (set_attr "length" "4,8")])
886 ;; IBM 405 and 440 half-word multiplication operations.
888 (define_insn "*macchwc"
889 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
890 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
891 (match_operand:SI 2 "gpc_reg_operand" "r")
894 (match_operand:HI 1 "gpc_reg_operand" "r")))
895 (match_operand:SI 4 "gpc_reg_operand" "0"))
897 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
898 (plus:SI (mult:SI (ashiftrt:SI
906 [(set_attr "type" "imul3")])
908 (define_insn "*macchw"
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
910 (plus:SI (mult:SI (ashiftrt:SI
911 (match_operand:SI 2 "gpc_reg_operand" "r")
914 (match_operand:HI 1 "gpc_reg_operand" "r")))
915 (match_operand:SI 3 "gpc_reg_operand" "0")))]
918 [(set_attr "type" "imul3")])
920 (define_insn "*macchwuc"
921 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
922 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
923 (match_operand:SI 2 "gpc_reg_operand" "r")
926 (match_operand:HI 1 "gpc_reg_operand" "r")))
927 (match_operand:SI 4 "gpc_reg_operand" "0"))
929 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
930 (plus:SI (mult:SI (lshiftrt:SI
937 "macchwu. %0, %1, %2"
938 [(set_attr "type" "imul3")])
940 (define_insn "*macchwu"
941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
942 (plus:SI (mult:SI (lshiftrt:SI
943 (match_operand:SI 2 "gpc_reg_operand" "r")
946 (match_operand:HI 1 "gpc_reg_operand" "r")))
947 (match_operand:SI 3 "gpc_reg_operand" "0")))]
950 [(set_attr "type" "imul3")])
952 (define_insn "*machhwc"
953 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
954 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
955 (match_operand:SI 1 "gpc_reg_operand" "%r")
958 (match_operand:SI 2 "gpc_reg_operand" "r")
960 (match_operand:SI 4 "gpc_reg_operand" "0"))
962 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
963 (plus:SI (mult:SI (ashiftrt:SI
972 [(set_attr "type" "imul3")])
974 (define_insn "*machhw"
975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
976 (plus:SI (mult:SI (ashiftrt:SI
977 (match_operand:SI 1 "gpc_reg_operand" "%r")
980 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (match_operand:SI 3 "gpc_reg_operand" "0")))]
985 [(set_attr "type" "imul3")])
987 (define_insn "*machhwuc"
988 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
989 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
990 (match_operand:SI 1 "gpc_reg_operand" "%r")
993 (match_operand:SI 2 "gpc_reg_operand" "r")
995 (match_operand:SI 4 "gpc_reg_operand" "0"))
997 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
998 (plus:SI (mult:SI (lshiftrt:SI
1006 "machhwu. %0, %1, %2"
1007 [(set_attr "type" "imul3")])
1009 (define_insn "*machhwu"
1010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1011 (plus:SI (mult:SI (lshiftrt:SI
1012 (match_operand:SI 1 "gpc_reg_operand" "%r")
1015 (match_operand:SI 2 "gpc_reg_operand" "r")
1017 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1019 "machhwu %0, %1, %2"
1020 [(set_attr "type" "imul3")])
1022 (define_insn "*maclhwc"
1023 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1024 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1025 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1027 (match_operand:HI 2 "gpc_reg_operand" "r")))
1028 (match_operand:SI 4 "gpc_reg_operand" "0"))
1030 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (sign_extend:SI
1037 "maclhw. %0, %1, %2"
1038 [(set_attr "type" "imul3")])
1040 (define_insn "*maclhw"
1041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1042 (plus:SI (mult:SI (sign_extend:SI
1043 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1045 (match_operand:HI 2 "gpc_reg_operand" "r")))
1046 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1049 [(set_attr "type" "imul3")])
1051 (define_insn "*maclhwuc"
1052 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1053 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1054 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1056 (match_operand:HI 2 "gpc_reg_operand" "r")))
1057 (match_operand:SI 4 "gpc_reg_operand" "0"))
1059 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1060 (plus:SI (mult:SI (zero_extend:SI
1066 "maclhwu. %0, %1, %2"
1067 [(set_attr "type" "imul3")])
1069 (define_insn "*maclhwu"
1070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (zero_extend:SI
1072 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1074 (match_operand:HI 2 "gpc_reg_operand" "r")))
1075 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1077 "maclhwu %0, %1, %2"
1078 [(set_attr "type" "imul3")])
1080 (define_insn "*nmacchwc"
1081 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1082 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1083 (mult:SI (ashiftrt:SI
1084 (match_operand:SI 2 "gpc_reg_operand" "r")
1087 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1089 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1090 (minus:SI (match_dup 4)
1091 (mult:SI (ashiftrt:SI
1097 "nmacchw. %0, %1, %2"
1098 [(set_attr "type" "imul3")])
1100 (define_insn "*nmacchw"
1101 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1102 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1103 (mult:SI (ashiftrt:SI
1104 (match_operand:SI 2 "gpc_reg_operand" "r")
1107 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1109 "nmacchw %0, %1, %2"
1110 [(set_attr "type" "imul3")])
1112 (define_insn "*nmachhwc"
1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1114 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1115 (mult:SI (ashiftrt:SI
1116 (match_operand:SI 1 "gpc_reg_operand" "%r")
1119 (match_operand:SI 2 "gpc_reg_operand" "r")
1122 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1123 (minus:SI (match_dup 4)
1124 (mult:SI (ashiftrt:SI
1131 "nmachhw. %0, %1, %2"
1132 [(set_attr "type" "imul3")])
1134 (define_insn "*nmachhw"
1135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1136 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1137 (mult:SI (ashiftrt:SI
1138 (match_operand:SI 1 "gpc_reg_operand" "%r")
1141 (match_operand:SI 2 "gpc_reg_operand" "r")
1144 "nmachhw %0, %1, %2"
1145 [(set_attr "type" "imul3")])
1147 (define_insn "*nmaclhwc"
1148 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1149 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1150 (mult:SI (sign_extend:SI
1151 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1153 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1155 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1156 (minus:SI (match_dup 4)
1157 (mult:SI (sign_extend:SI
1162 "nmaclhw. %0, %1, %2"
1163 [(set_attr "type" "imul3")])
1165 (define_insn "*nmaclhw"
1166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1167 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1168 (mult:SI (sign_extend:SI
1169 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1171 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1173 "nmaclhw %0, %1, %2"
1174 [(set_attr "type" "imul3")])
1176 (define_insn "*mulchwc"
1177 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1178 (compare:CC (mult:SI (ashiftrt:SI
1179 (match_operand:SI 2 "gpc_reg_operand" "r")
1182 (match_operand:HI 1 "gpc_reg_operand" "r")))
1184 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1185 (mult:SI (ashiftrt:SI
1191 "mulchw. %0, %1, %2"
1192 [(set_attr "type" "imul3")])
1194 (define_insn "*mulchw"
1195 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (mult:SI (ashiftrt:SI
1197 (match_operand:SI 2 "gpc_reg_operand" "r")
1200 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1203 [(set_attr "type" "imul3")])
1205 (define_insn "*mulchwuc"
1206 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1207 (compare:CC (mult:SI (lshiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1211 (match_operand:HI 1 "gpc_reg_operand" "r")))
1213 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1214 (mult:SI (lshiftrt:SI
1220 "mulchwu. %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1223 (define_insn "*mulchwu"
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (mult:SI (lshiftrt:SI
1226 (match_operand:SI 2 "gpc_reg_operand" "r")
1229 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1231 "mulchwu %0, %1, %2"
1232 [(set_attr "type" "imul3")])
1234 (define_insn "*mulhhwc"
1235 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1236 (compare:CC (mult:SI (ashiftrt:SI
1237 (match_operand:SI 1 "gpc_reg_operand" "%r")
1240 (match_operand:SI 2 "gpc_reg_operand" "r")
1243 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1244 (mult:SI (ashiftrt:SI
1251 "mulhhw. %0, %1, %2"
1252 [(set_attr "type" "imul3")])
1254 (define_insn "*mulhhw"
1255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (mult:SI (ashiftrt:SI
1257 (match_operand:SI 1 "gpc_reg_operand" "%r")
1260 (match_operand:SI 2 "gpc_reg_operand" "r")
1264 [(set_attr "type" "imul3")])
1266 (define_insn "*mulhhwuc"
1267 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1268 (compare:CC (mult:SI (lshiftrt:SI
1269 (match_operand:SI 1 "gpc_reg_operand" "%r")
1272 (match_operand:SI 2 "gpc_reg_operand" "r")
1275 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1276 (mult:SI (lshiftrt:SI
1283 "mulhhwu. %0, %1, %2"
1284 [(set_attr "type" "imul3")])
1286 (define_insn "*mulhhwu"
1287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1288 (mult:SI (lshiftrt:SI
1289 (match_operand:SI 1 "gpc_reg_operand" "%r")
1292 (match_operand:SI 2 "gpc_reg_operand" "r")
1295 "mulhhwu %0, %1, %2"
1296 [(set_attr "type" "imul3")])
1298 (define_insn "*mullhwc"
1299 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1300 (compare:CC (mult:SI (sign_extend:SI
1301 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1303 (match_operand:HI 2 "gpc_reg_operand" "r")))
1305 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1306 (mult:SI (sign_extend:SI
1311 "mullhw. %0, %1, %2"
1312 [(set_attr "type" "imul3")])
1314 (define_insn "*mullhw"
1315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1316 (mult:SI (sign_extend:SI
1317 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1319 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1322 [(set_attr "type" "imul3")])
1324 (define_insn "*mullhwuc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (zero_extend:SI
1327 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1329 (match_operand:HI 2 "gpc_reg_operand" "r")))
1331 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1332 (mult:SI (zero_extend:SI
1337 "mullhwu. %0, %1, %2"
1338 [(set_attr "type" "imul3")])
1340 (define_insn "*mullhwu"
1341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1342 (mult:SI (zero_extend:SI
1343 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1345 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1347 "mullhwu %0, %1, %2"
1348 [(set_attr "type" "imul3")])
1350 ;; IBM 405 and 440 string-search dlmzb instruction support.
1351 (define_insn "dlmzb"
1352 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1353 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1354 (match_operand:SI 2 "gpc_reg_operand" "r")]
1356 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (unspec:SI [(match_dup 1)
1361 "dlmzb. %0, %1, %2")
1363 (define_expand "strlensi"
1364 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1365 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1366 (match_operand:QI 2 "const_int_operand" "")
1367 (match_operand 3 "const_int_operand" "")]
1368 UNSPEC_DLMZB_STRLEN))
1369 (clobber (match_scratch:CC 4 "=x"))]
1370 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1372 rtx result = operands[0];
1373 rtx src = operands[1];
1374 rtx search_char = operands[2];
1375 rtx align = operands[3];
1376 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1377 rtx loop_label, end_label, mem, cr0, cond;
1378 if (search_char != const0_rtx
1379 || GET_CODE (align) != CONST_INT
1380 || INTVAL (align) < 8)
1382 word1 = gen_reg_rtx (SImode);
1383 word2 = gen_reg_rtx (SImode);
1384 scratch_dlmzb = gen_reg_rtx (SImode);
1385 scratch_string = gen_reg_rtx (Pmode);
1386 loop_label = gen_label_rtx ();
1387 end_label = gen_label_rtx ();
1388 addr = force_reg (Pmode, XEXP (src, 0));
1389 emit_move_insn (scratch_string, addr);
1390 emit_label (loop_label);
1391 mem = change_address (src, SImode, scratch_string);
1392 emit_move_insn (word1, mem);
1393 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1394 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1395 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1396 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1397 emit_jump_insn (gen_rtx_SET (VOIDmode,
1399 gen_rtx_IF_THEN_ELSE (VOIDmode,
1405 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1406 emit_jump_insn (gen_rtx_SET (VOIDmode,
1408 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1410 emit_label (end_label);
1411 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1412 emit_insn (gen_subsi3 (result, scratch_string, addr));
1413 emit_insn (gen_subsi3 (result, result, const1_rtx));
1418 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1419 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1421 (set (match_operand:SI 0 "gpc_reg_operand" "")
1422 (sign_extend:SI (match_dup 1)))]
1425 (sign_extend:SI (match_dup 1)))
1427 (compare:CC (match_dup 0)
1431 ;; Fixed-point arithmetic insns.
1433 (define_expand "add<mode>3"
1434 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1435 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1436 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1439 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1441 if (non_short_cint_operand (operands[2], DImode))
1444 else if (GET_CODE (operands[2]) == CONST_INT
1445 && ! add_operand (operands[2], <MODE>mode))
1447 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1448 ? operands[0] : gen_reg_rtx (<MODE>mode));
1450 HOST_WIDE_INT val = INTVAL (operands[2]);
1451 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1452 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1454 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1457 /* The ordering here is important for the prolog expander.
1458 When space is allocated from the stack, adding 'low' first may
1459 produce a temporary deallocation (which would be bad). */
1460 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1461 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1466 ;; Discourage ai/addic because of carry but provide it in an alternative
1467 ;; allowing register zero as source.
1468 (define_insn "*add<mode>3_internal1"
1469 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1470 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1471 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1475 {cal %0,%2(%1)|addi %0,%1,%2}
1477 {cau|addis} %0,%1,%v2"
1478 [(set_attr "length" "4,4,4,4")])
1480 (define_insn "addsi3_high"
1481 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1482 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1483 (high:SI (match_operand 2 "" ""))))]
1484 "TARGET_MACHO && !TARGET_64BIT"
1485 "{cau|addis} %0,%1,ha16(%2)"
1486 [(set_attr "length" "4")])
1488 (define_insn "*add<mode>3_internal2"
1489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1490 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1491 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1493 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1496 {cax.|add.} %3,%1,%2
1497 {ai.|addic.} %3,%1,%2
1500 [(set_attr "type" "fast_compare,compare,compare,compare")
1501 (set_attr "length" "4,4,8,8")])
1504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1505 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1506 (match_operand:GPR 2 "reg_or_short_operand" ""))
1508 (clobber (match_scratch:GPR 3 ""))]
1511 (plus:GPR (match_dup 1)
1514 (compare:CC (match_dup 3)
1518 (define_insn "*add<mode>3_internal3"
1519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1520 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1521 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1523 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1524 (plus:P (match_dup 1)
1528 {cax.|add.} %0,%1,%2
1529 {ai.|addic.} %0,%1,%2
1532 [(set_attr "type" "fast_compare,compare,compare,compare")
1533 (set_attr "length" "4,4,8,8")])
1536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1537 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1538 (match_operand:P 2 "reg_or_short_operand" ""))
1540 (set (match_operand:P 0 "gpc_reg_operand" "")
1541 (plus:P (match_dup 1) (match_dup 2)))]
1544 (plus:P (match_dup 1)
1547 (compare:CC (match_dup 0)
1551 ;; Split an add that we can't do in one insn into two insns, each of which
1552 ;; does one 16-bit part. This is used by combine. Note that the low-order
1553 ;; add should be last in case the result gets used in an address.
1556 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1557 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1558 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1560 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1561 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1563 HOST_WIDE_INT val = INTVAL (operands[2]);
1564 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1565 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1567 operands[4] = GEN_INT (low);
1568 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1569 operands[3] = GEN_INT (rest);
1570 else if (! no_new_pseudos)
1572 operands[3] = gen_reg_rtx (DImode);
1573 emit_move_insn (operands[3], operands[2]);
1574 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1581 (define_insn "one_cmpl<mode>2"
1582 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1583 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1589 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1591 (clobber (match_scratch:P 2 "=r,r"))]
1596 [(set_attr "type" "compare")
1597 (set_attr "length" "4,8")])
1600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1601 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1603 (clobber (match_scratch:P 2 ""))]
1606 (not:P (match_dup 1)))
1608 (compare:CC (match_dup 2)
1613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1614 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1616 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1617 (not:P (match_dup 1)))]
1622 [(set_attr "type" "compare")
1623 (set_attr "length" "4,8")])
1626 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1627 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1629 (set (match_operand:P 0 "gpc_reg_operand" "")
1630 (not:P (match_dup 1)))]
1633 (not:P (match_dup 1)))
1635 (compare:CC (match_dup 0)
1640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1641 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1642 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1644 "{sf%I1|subf%I1c} %0,%2,%1")
1647 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1648 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1649 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1657 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1658 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1660 (clobber (match_scratch:SI 3 "=r,r"))]
1663 {sf.|subfc.} %3,%2,%1
1665 [(set_attr "type" "compare")
1666 (set_attr "length" "4,8")])
1669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1670 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1671 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1673 (clobber (match_scratch:P 3 "=r,r"))]
1678 [(set_attr "type" "fast_compare")
1679 (set_attr "length" "4,8")])
1682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1683 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1684 (match_operand:P 2 "gpc_reg_operand" ""))
1686 (clobber (match_scratch:P 3 ""))]
1689 (minus:P (match_dup 1)
1692 (compare:CC (match_dup 3)
1697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1698 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1699 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1702 (minus:SI (match_dup 1) (match_dup 2)))]
1705 {sf.|subfc.} %0,%2,%1
1707 [(set_attr "type" "compare")
1708 (set_attr "length" "4,8")])
1711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1712 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1713 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1715 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1716 (minus:P (match_dup 1)
1722 [(set_attr "type" "fast_compare")
1723 (set_attr "length" "4,8")])
1726 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1728 (match_operand:P 2 "gpc_reg_operand" ""))
1730 (set (match_operand:P 0 "gpc_reg_operand" "")
1731 (minus:P (match_dup 1)
1735 (minus:P (match_dup 1)
1738 (compare:CC (match_dup 0)
1742 (define_expand "sub<mode>3"
1743 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1744 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1745 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1749 if (GET_CODE (operands[2]) == CONST_INT)
1751 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1752 negate_rtx (<MODE>mode, operands[2])));
1757 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1758 ;; instruction and some auxiliary computations. Then we just have a single
1759 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1762 (define_expand "sminsi3"
1764 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1765 (match_operand:SI 2 "reg_or_short_operand" ""))
1767 (minus:SI (match_dup 2) (match_dup 1))))
1768 (set (match_operand:SI 0 "gpc_reg_operand" "")
1769 (minus:SI (match_dup 2) (match_dup 3)))]
1770 "TARGET_POWER || TARGET_ISEL"
1775 operands[2] = force_reg (SImode, operands[2]);
1776 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1780 operands[3] = gen_reg_rtx (SImode);
1784 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1785 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1786 (match_operand:SI 2 "reg_or_short_operand" "")))
1787 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1790 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1792 (minus:SI (match_dup 2) (match_dup 1))))
1793 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1796 (define_expand "smaxsi3"
1798 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1799 (match_operand:SI 2 "reg_or_short_operand" ""))
1801 (minus:SI (match_dup 2) (match_dup 1))))
1802 (set (match_operand:SI 0 "gpc_reg_operand" "")
1803 (plus:SI (match_dup 3) (match_dup 1)))]
1804 "TARGET_POWER || TARGET_ISEL"
1809 operands[2] = force_reg (SImode, operands[2]);
1810 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1813 operands[3] = gen_reg_rtx (SImode);
1817 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1818 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1819 (match_operand:SI 2 "reg_or_short_operand" "")))
1820 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1823 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1825 (minus:SI (match_dup 2) (match_dup 1))))
1826 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1829 (define_expand "uminsi3"
1830 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1832 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1834 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1836 (minus:SI (match_dup 4) (match_dup 3))))
1837 (set (match_operand:SI 0 "gpc_reg_operand" "")
1838 (minus:SI (match_dup 2) (match_dup 3)))]
1839 "TARGET_POWER || TARGET_ISEL"
1844 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1847 operands[3] = gen_reg_rtx (SImode);
1848 operands[4] = gen_reg_rtx (SImode);
1849 operands[5] = GEN_INT (-2147483647 - 1);
1852 (define_expand "umaxsi3"
1853 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1857 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1859 (minus:SI (match_dup 4) (match_dup 3))))
1860 (set (match_operand:SI 0 "gpc_reg_operand" "")
1861 (plus:SI (match_dup 3) (match_dup 1)))]
1862 "TARGET_POWER || TARGET_ISEL"
1867 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1870 operands[3] = gen_reg_rtx (SImode);
1871 operands[4] = gen_reg_rtx (SImode);
1872 operands[5] = GEN_INT (-2147483647 - 1);
1876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1877 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1878 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1880 (minus:SI (match_dup 2) (match_dup 1))))]
1885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1887 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1888 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1890 (minus:SI (match_dup 2) (match_dup 1)))
1892 (clobber (match_scratch:SI 3 "=r,r"))]
1897 [(set_attr "type" "delayed_compare")
1898 (set_attr "length" "4,8")])
1901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1903 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1904 (match_operand:SI 2 "reg_or_short_operand" ""))
1906 (minus:SI (match_dup 2) (match_dup 1)))
1908 (clobber (match_scratch:SI 3 ""))]
1909 "TARGET_POWER && reload_completed"
1911 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1913 (minus:SI (match_dup 2) (match_dup 1))))
1915 (compare:CC (match_dup 3)
1920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1922 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1923 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1925 (minus:SI (match_dup 2) (match_dup 1)))
1927 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1928 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1930 (minus:SI (match_dup 2) (match_dup 1))))]
1935 [(set_attr "type" "delayed_compare")
1936 (set_attr "length" "4,8")])
1939 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1941 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1942 (match_operand:SI 2 "reg_or_short_operand" ""))
1944 (minus:SI (match_dup 2) (match_dup 1)))
1946 (set (match_operand:SI 0 "gpc_reg_operand" "")
1947 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1949 (minus:SI (match_dup 2) (match_dup 1))))]
1950 "TARGET_POWER && reload_completed"
1952 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1954 (minus:SI (match_dup 2) (match_dup 1))))
1956 (compare:CC (match_dup 0)
1960 ;; We don't need abs with condition code because such comparisons should
1962 (define_expand "abssi2"
1963 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1964 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1970 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1973 else if (! TARGET_POWER)
1975 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1980 (define_insn "*abssi2_power"
1981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1982 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1986 (define_insn_and_split "abssi2_isel"
1987 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1988 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1989 (clobber (match_scratch:SI 2 "=&b"))
1990 (clobber (match_scratch:CC 3 "=y"))]
1993 "&& reload_completed"
1994 [(set (match_dup 2) (neg:SI (match_dup 1)))
1996 (compare:CC (match_dup 1)
1999 (if_then_else:SI (ge (match_dup 3)
2005 (define_insn_and_split "abssi2_nopower"
2006 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2007 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2008 (clobber (match_scratch:SI 2 "=&r,&r"))]
2009 "! TARGET_POWER && ! TARGET_ISEL"
2011 "&& reload_completed"
2012 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2013 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2014 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2017 (define_insn "*nabs_power"
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2019 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2023 (define_insn_and_split "*nabs_nopower"
2024 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2025 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2026 (clobber (match_scratch:SI 2 "=&r,&r"))]
2029 "&& reload_completed"
2030 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2031 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2032 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2035 (define_expand "neg<mode>2"
2036 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2037 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2041 (define_insn "*neg<mode>2_internal"
2042 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2043 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2049 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2051 (clobber (match_scratch:P 2 "=r,r"))]
2056 [(set_attr "type" "fast_compare")
2057 (set_attr "length" "4,8")])
2060 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2061 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2063 (clobber (match_scratch:P 2 ""))]
2066 (neg:P (match_dup 1)))
2068 (compare:CC (match_dup 2)
2073 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2074 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2076 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2077 (neg:P (match_dup 1)))]
2082 [(set_attr "type" "fast_compare")
2083 (set_attr "length" "4,8")])
2086 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2087 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2089 (set (match_operand:P 0 "gpc_reg_operand" "")
2090 (neg:P (match_dup 1)))]
2093 (neg:P (match_dup 1)))
2095 (compare:CC (match_dup 0)
2099 (define_insn "clz<mode>2"
2100 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2101 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2103 "{cntlz|cntlz<wd>} %0,%1")
2105 (define_expand "ctz<mode>2"
2107 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2108 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2110 (clobber (scratch:CC))])
2111 (set (match_dup 4) (clz:GPR (match_dup 3)))
2112 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2113 (minus:GPR (match_dup 5) (match_dup 4)))]
2116 operands[2] = gen_reg_rtx (<MODE>mode);
2117 operands[3] = gen_reg_rtx (<MODE>mode);
2118 operands[4] = gen_reg_rtx (<MODE>mode);
2119 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2122 (define_expand "ffs<mode>2"
2124 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2125 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2127 (clobber (scratch:CC))])
2128 (set (match_dup 4) (clz:GPR (match_dup 3)))
2129 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2130 (minus:GPR (match_dup 5) (match_dup 4)))]
2133 operands[2] = gen_reg_rtx (<MODE>mode);
2134 operands[3] = gen_reg_rtx (<MODE>mode);
2135 operands[4] = gen_reg_rtx (<MODE>mode);
2136 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2139 (define_expand "popcount<mode>2"
2141 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2144 (mult:GPR (match_dup 2) (match_dup 4)))
2145 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2146 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2149 operands[2] = gen_reg_rtx (<MODE>mode);
2150 operands[3] = gen_reg_rtx (<MODE>mode);
2151 operands[4] = force_reg (<MODE>mode,
2152 <MODE>mode == SImode
2153 ? GEN_INT (0x01010101)
2154 : GEN_INT ((HOST_WIDE_INT)
2155 0x01010101 << 32 | 0x01010101));
2156 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
2159 (define_insn "popcntb<mode>2"
2160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2161 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2166 (define_expand "mulsi3"
2167 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2168 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2169 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2174 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2176 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2180 (define_insn "mulsi3_mq"
2181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2182 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2183 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2184 (clobber (match_scratch:SI 3 "=q,q"))]
2187 {muls|mullw} %0,%1,%2
2188 {muli|mulli} %0,%1,%2"
2190 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2191 (const_string "imul3")
2192 (match_operand:SI 2 "short_cint_operand" "")
2193 (const_string "imul2")]
2194 (const_string "imul")))])
2196 (define_insn "mulsi3_no_mq"
2197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2198 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2199 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2202 {muls|mullw} %0,%1,%2
2203 {muli|mulli} %0,%1,%2"
2205 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2206 (const_string "imul3")
2207 (match_operand:SI 2 "short_cint_operand" "")
2208 (const_string "imul2")]
2209 (const_string "imul")))])
2211 (define_insn "*mulsi3_mq_internal1"
2212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2213 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2214 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2216 (clobber (match_scratch:SI 3 "=r,r"))
2217 (clobber (match_scratch:SI 4 "=q,q"))]
2220 {muls.|mullw.} %3,%1,%2
2222 [(set_attr "type" "imul_compare")
2223 (set_attr "length" "4,8")])
2226 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2227 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2228 (match_operand:SI 2 "gpc_reg_operand" ""))
2230 (clobber (match_scratch:SI 3 ""))
2231 (clobber (match_scratch:SI 4 ""))]
2232 "TARGET_POWER && reload_completed"
2233 [(parallel [(set (match_dup 3)
2234 (mult:SI (match_dup 1) (match_dup 2)))
2235 (clobber (match_dup 4))])
2237 (compare:CC (match_dup 3)
2241 (define_insn "*mulsi3_no_mq_internal1"
2242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2243 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2244 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2246 (clobber (match_scratch:SI 3 "=r,r"))]
2249 {muls.|mullw.} %3,%1,%2
2251 [(set_attr "type" "imul_compare")
2252 (set_attr "length" "4,8")])
2255 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2256 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2257 (match_operand:SI 2 "gpc_reg_operand" ""))
2259 (clobber (match_scratch:SI 3 ""))]
2260 "! TARGET_POWER && reload_completed"
2262 (mult:SI (match_dup 1) (match_dup 2)))
2264 (compare:CC (match_dup 3)
2268 (define_insn "*mulsi3_mq_internal2"
2269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2270 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2271 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2273 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2274 (mult:SI (match_dup 1) (match_dup 2)))
2275 (clobber (match_scratch:SI 4 "=q,q"))]
2278 {muls.|mullw.} %0,%1,%2
2280 [(set_attr "type" "imul_compare")
2281 (set_attr "length" "4,8")])
2284 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2285 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2286 (match_operand:SI 2 "gpc_reg_operand" ""))
2288 (set (match_operand:SI 0 "gpc_reg_operand" "")
2289 (mult:SI (match_dup 1) (match_dup 2)))
2290 (clobber (match_scratch:SI 4 ""))]
2291 "TARGET_POWER && reload_completed"
2292 [(parallel [(set (match_dup 0)
2293 (mult:SI (match_dup 1) (match_dup 2)))
2294 (clobber (match_dup 4))])
2296 (compare:CC (match_dup 0)
2300 (define_insn "*mulsi3_no_mq_internal2"
2301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2302 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2303 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2306 (mult:SI (match_dup 1) (match_dup 2)))]
2309 {muls.|mullw.} %0,%1,%2
2311 [(set_attr "type" "imul_compare")
2312 (set_attr "length" "4,8")])
2315 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2317 (match_operand:SI 2 "gpc_reg_operand" ""))
2319 (set (match_operand:SI 0 "gpc_reg_operand" "")
2320 (mult:SI (match_dup 1) (match_dup 2)))]
2321 "! TARGET_POWER && reload_completed"
2323 (mult:SI (match_dup 1) (match_dup 2)))
2325 (compare:CC (match_dup 0)
2329 ;; Operand 1 is divided by operand 2; quotient goes to operand
2330 ;; 0 and remainder to operand 3.
2331 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2333 (define_expand "divmodsi4"
2334 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2335 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2336 (match_operand:SI 2 "gpc_reg_operand" "")))
2337 (set (match_operand:SI 3 "register_operand" "")
2338 (mod:SI (match_dup 1) (match_dup 2)))])]
2339 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2342 if (! TARGET_POWER && ! TARGET_POWERPC)
2344 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2345 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2346 emit_insn (gen_divss_call ());
2347 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2348 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2353 (define_insn "*divmodsi4_internal"
2354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2355 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2356 (match_operand:SI 2 "gpc_reg_operand" "r")))
2357 (set (match_operand:SI 3 "register_operand" "=q")
2358 (mod:SI (match_dup 1) (match_dup 2)))]
2361 [(set_attr "type" "idiv")])
2363 (define_expand "udiv<mode>3"
2364 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2365 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2366 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2367 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2370 if (! TARGET_POWER && ! TARGET_POWERPC)
2372 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2373 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2374 emit_insn (gen_quous_call ());
2375 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2378 else if (TARGET_POWER)
2380 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2385 (define_insn "udivsi3_mq"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2387 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2388 (match_operand:SI 2 "gpc_reg_operand" "r")))
2389 (clobber (match_scratch:SI 3 "=q"))]
2390 "TARGET_POWERPC && TARGET_POWER"
2392 [(set_attr "type" "idiv")])
2394 (define_insn "*udivsi3_no_mq"
2395 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2396 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2397 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2398 "TARGET_POWERPC && ! TARGET_POWER"
2400 [(set_attr "type" "idiv")])
2402 ;; For powers of two we can do srai/aze for divide and then adjust for
2403 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2404 ;; used; for PowerPC, force operands into register and do a normal divide;
2405 ;; for AIX common-mode, use quoss call on register operands.
2406 (define_expand "div<mode>3"
2407 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2408 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2409 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2413 if (GET_CODE (operands[2]) == CONST_INT
2414 && INTVAL (operands[2]) > 0
2415 && exact_log2 (INTVAL (operands[2])) >= 0)
2417 else if (TARGET_POWERPC)
2419 operands[2] = force_reg (<MODE>mode, operands[2]);
2422 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2426 else if (TARGET_POWER)
2430 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2431 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2432 emit_insn (gen_quoss_call ());
2433 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2438 (define_insn "divsi3_mq"
2439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2440 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2441 (match_operand:SI 2 "gpc_reg_operand" "r")))
2442 (clobber (match_scratch:SI 3 "=q"))]
2443 "TARGET_POWERPC && TARGET_POWER"
2445 [(set_attr "type" "idiv")])
2447 (define_insn "*div<mode>3_no_mq"
2448 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2449 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2450 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2451 "TARGET_POWERPC && ! TARGET_POWER"
2453 [(set_attr "type" "idiv")])
2455 (define_expand "mod<mode>3"
2456 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2457 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2458 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2466 if (GET_CODE (operands[2]) != CONST_INT
2467 || INTVAL (operands[2]) <= 0
2468 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2471 temp1 = gen_reg_rtx (<MODE>mode);
2472 temp2 = gen_reg_rtx (<MODE>mode);
2474 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2475 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2476 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2481 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2482 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2483 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2485 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2486 [(set_attr "type" "two")
2487 (set_attr "length" "8")])
2490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2491 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2492 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2494 (clobber (match_scratch:P 3 "=r,r"))]
2497 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2499 [(set_attr "type" "compare")
2500 (set_attr "length" "8,12")])
2503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2504 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2505 (match_operand:GPR 2 "exact_log2_cint_operand"
2508 (clobber (match_scratch:GPR 3 ""))]
2511 (div:<MODE> (match_dup 1) (match_dup 2)))
2513 (compare:CC (match_dup 3)
2518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2519 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2520 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2522 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2523 (div:P (match_dup 1) (match_dup 2)))]
2526 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2528 [(set_attr "type" "compare")
2529 (set_attr "length" "8,12")])
2532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2533 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2534 (match_operand:GPR 2 "exact_log2_cint_operand"
2537 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2538 (div:GPR (match_dup 1) (match_dup 2)))]
2541 (div:<MODE> (match_dup 1) (match_dup 2)))
2543 (compare:CC (match_dup 0)
2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2551 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2553 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2554 (match_operand:SI 3 "gpc_reg_operand" "r")))
2555 (set (match_operand:SI 2 "register_operand" "=*q")
2558 (zero_extend:DI (match_dup 1)) (const_int 32))
2559 (zero_extend:DI (match_dup 4)))
2563 [(set_attr "type" "idiv")])
2565 ;; To do unsigned divide we handle the cases of the divisor looking like a
2566 ;; negative number. If it is a constant that is less than 2**31, we don't
2567 ;; have to worry about the branches. So make a few subroutines here.
2569 ;; First comes the normal case.
2570 (define_expand "udivmodsi4_normal"
2571 [(set (match_dup 4) (const_int 0))
2572 (parallel [(set (match_operand:SI 0 "" "")
2573 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2575 (zero_extend:DI (match_operand:SI 1 "" "")))
2576 (match_operand:SI 2 "" "")))
2577 (set (match_operand:SI 3 "" "")
2578 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2580 (zero_extend:DI (match_dup 1)))
2584 { operands[4] = gen_reg_rtx (SImode); }")
2586 ;; This handles the branches.
2587 (define_expand "udivmodsi4_tests"
2588 [(set (match_operand:SI 0 "" "") (const_int 0))
2589 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2590 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2591 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2592 (label_ref (match_operand:SI 4 "" "")) (pc)))
2593 (set (match_dup 0) (const_int 1))
2594 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2595 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2596 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2597 (label_ref (match_dup 4)) (pc)))]
2600 { operands[5] = gen_reg_rtx (CCUNSmode);
2601 operands[6] = gen_reg_rtx (CCmode);
2604 (define_expand "udivmodsi4"
2605 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2606 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2607 (match_operand:SI 2 "reg_or_cint_operand" "")))
2608 (set (match_operand:SI 3 "gpc_reg_operand" "")
2609 (umod:SI (match_dup 1) (match_dup 2)))])]
2617 if (! TARGET_POWERPC)
2619 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2620 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2621 emit_insn (gen_divus_call ());
2622 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2623 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2630 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2632 operands[2] = force_reg (SImode, operands[2]);
2633 label = gen_label_rtx ();
2634 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2635 operands[3], label));
2638 operands[2] = force_reg (SImode, operands[2]);
2640 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2648 ;; AIX architecture-independent common-mode multiply (DImode),
2649 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2650 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2651 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2652 ;; assumed unused if generating common-mode, so ignore.
2653 (define_insn "mulh_call"
2656 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2657 (sign_extend:DI (reg:SI 4)))
2659 (clobber (match_scratch:SI 0 "=l"))]
2660 "! TARGET_POWER && ! TARGET_POWERPC"
2662 [(set_attr "type" "imul")])
2664 (define_insn "mull_call"
2666 (mult:DI (sign_extend:DI (reg:SI 3))
2667 (sign_extend:DI (reg:SI 4))))
2668 (clobber (match_scratch:SI 0 "=l"))
2669 (clobber (reg:SI 0))]
2670 "! TARGET_POWER && ! TARGET_POWERPC"
2672 [(set_attr "type" "imul")])
2674 (define_insn "divss_call"
2676 (div:SI (reg:SI 3) (reg:SI 4)))
2678 (mod:SI (reg:SI 3) (reg:SI 4)))
2679 (clobber (match_scratch:SI 0 "=l"))
2680 (clobber (reg:SI 0))]
2681 "! TARGET_POWER && ! TARGET_POWERPC"
2683 [(set_attr "type" "idiv")])
2685 (define_insn "divus_call"
2687 (udiv:SI (reg:SI 3) (reg:SI 4)))
2689 (umod:SI (reg:SI 3) (reg:SI 4)))
2690 (clobber (match_scratch:SI 0 "=l"))
2691 (clobber (reg:SI 0))
2692 (clobber (match_scratch:CC 1 "=x"))
2693 (clobber (reg:CC 69))]
2694 "! TARGET_POWER && ! TARGET_POWERPC"
2696 [(set_attr "type" "idiv")])
2698 (define_insn "quoss_call"
2700 (div:SI (reg:SI 3) (reg:SI 4)))
2701 (clobber (match_scratch:SI 0 "=l"))]
2702 "! TARGET_POWER && ! TARGET_POWERPC"
2704 [(set_attr "type" "idiv")])
2706 (define_insn "quous_call"
2708 (udiv:SI (reg:SI 3) (reg:SI 4)))
2709 (clobber (match_scratch:SI 0 "=l"))
2710 (clobber (reg:SI 0))
2711 (clobber (match_scratch:CC 1 "=x"))
2712 (clobber (reg:CC 69))]
2713 "! TARGET_POWER && ! TARGET_POWERPC"
2715 [(set_attr "type" "idiv")])
2717 ;; Logical instructions
2718 ;; The logical instructions are mostly combined by using match_operator,
2719 ;; but the plain AND insns are somewhat different because there is no
2720 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2721 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2723 (define_insn "andsi3"
2724 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2725 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2726 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2727 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2731 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2732 {andil.|andi.} %0,%1,%b2
2733 {andiu.|andis.} %0,%1,%u2"
2734 [(set_attr "type" "*,*,compare,compare")])
2736 ;; Note to set cr's other than cr0 we do the and immediate and then
2737 ;; the test again -- this avoids a mfcr which on the higher end
2738 ;; machines causes an execution serialization
2740 (define_insn "*andsi3_internal2"
2741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2742 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2743 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2745 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2746 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2750 {andil.|andi.} %3,%1,%b2
2751 {andiu.|andis.} %3,%1,%u2
2752 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2757 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2758 (set_attr "length" "4,4,4,4,8,8,8,8")])
2760 (define_insn "*andsi3_internal3"
2761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2762 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2763 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2765 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2766 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2770 {andil.|andi.} %3,%1,%b2
2771 {andiu.|andis.} %3,%1,%u2
2772 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2777 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2778 (set_attr "length" "8,4,4,4,8,8,8,8")])
2781 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2782 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2783 (match_operand:GPR 2 "and_operand" ""))
2785 (clobber (match_scratch:GPR 3 ""))
2786 (clobber (match_scratch:CC 4 ""))]
2788 [(parallel [(set (match_dup 3)
2789 (and:<MODE> (match_dup 1)
2791 (clobber (match_dup 4))])
2793 (compare:CC (match_dup 3)
2797 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2798 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2801 [(set (match_operand:CC 0 "cc_reg_operand" "")
2802 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2803 (match_operand:SI 2 "gpc_reg_operand" ""))
2805 (clobber (match_scratch:SI 3 ""))
2806 (clobber (match_scratch:CC 4 ""))]
2807 "TARGET_POWERPC64 && reload_completed"
2808 [(parallel [(set (match_dup 3)
2809 (and:SI (match_dup 1)
2811 (clobber (match_dup 4))])
2813 (compare:CC (match_dup 3)
2817 (define_insn "*andsi3_internal4"
2818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2819 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2820 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2822 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2823 (and:SI (match_dup 1)
2825 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2829 {andil.|andi.} %0,%1,%b2
2830 {andiu.|andis.} %0,%1,%u2
2831 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2836 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2837 (set_attr "length" "4,4,4,4,8,8,8,8")])
2839 (define_insn "*andsi3_internal5"
2840 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2841 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2842 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2845 (and:SI (match_dup 1)
2847 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2851 {andil.|andi.} %0,%1,%b2
2852 {andiu.|andis.} %0,%1,%u2
2853 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2858 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2859 (set_attr "length" "8,4,4,4,8,8,8,8")])
2862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2863 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2864 (match_operand:SI 2 "and_operand" ""))
2866 (set (match_operand:SI 0 "gpc_reg_operand" "")
2867 (and:SI (match_dup 1)
2869 (clobber (match_scratch:CC 4 ""))]
2871 [(parallel [(set (match_dup 0)
2872 (and:SI (match_dup 1)
2874 (clobber (match_dup 4))])
2876 (compare:CC (match_dup 0)
2881 [(set (match_operand:CC 3 "cc_reg_operand" "")
2882 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2883 (match_operand:SI 2 "gpc_reg_operand" ""))
2885 (set (match_operand:SI 0 "gpc_reg_operand" "")
2886 (and:SI (match_dup 1)
2888 (clobber (match_scratch:CC 4 ""))]
2889 "TARGET_POWERPC64 && reload_completed"
2890 [(parallel [(set (match_dup 0)
2891 (and:SI (match_dup 1)
2893 (clobber (match_dup 4))])
2895 (compare:CC (match_dup 0)
2899 ;; Handle the PowerPC64 rlwinm corner case
2901 (define_insn_and_split "*andsi3_internal6"
2902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2903 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2904 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2909 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2912 (rotate:SI (match_dup 0) (match_dup 5)))]
2915 int mb = extract_MB (operands[2]);
2916 int me = extract_ME (operands[2]);
2917 operands[3] = GEN_INT (me + 1);
2918 operands[5] = GEN_INT (32 - (me + 1));
2919 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2921 [(set_attr "length" "8")])
2923 (define_expand "iorsi3"
2924 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2925 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2926 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2930 if (GET_CODE (operands[2]) == CONST_INT
2931 && ! logical_operand (operands[2], SImode))
2933 HOST_WIDE_INT value = INTVAL (operands[2]);
2934 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2935 ? operands[0] : gen_reg_rtx (SImode));
2937 emit_insn (gen_iorsi3 (tmp, operands[1],
2938 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2939 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2944 (define_expand "xorsi3"
2945 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2946 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2947 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2951 if (GET_CODE (operands[2]) == CONST_INT
2952 && ! logical_operand (operands[2], SImode))
2954 HOST_WIDE_INT value = INTVAL (operands[2]);
2955 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2956 ? operands[0] : gen_reg_rtx (SImode));
2958 emit_insn (gen_xorsi3 (tmp, operands[1],
2959 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2960 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2965 (define_insn "*boolsi3_internal1"
2966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2967 (match_operator:SI 3 "boolean_or_operator"
2968 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2969 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2973 {%q3il|%q3i} %0,%1,%b2
2974 {%q3iu|%q3is} %0,%1,%u2")
2976 (define_insn "*boolsi3_internal2"
2977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2978 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2979 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2980 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2982 (clobber (match_scratch:SI 3 "=r,r"))]
2987 [(set_attr "type" "compare")
2988 (set_attr "length" "4,8")])
2991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2992 (compare:CC (match_operator:SI 4 "boolean_operator"
2993 [(match_operand:SI 1 "gpc_reg_operand" "")
2994 (match_operand:SI 2 "gpc_reg_operand" "")])
2996 (clobber (match_scratch:SI 3 ""))]
2997 "TARGET_32BIT && reload_completed"
2998 [(set (match_dup 3) (match_dup 4))
3000 (compare:CC (match_dup 3)
3004 (define_insn "*boolsi3_internal3"
3005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3006 (compare:CC (match_operator:SI 4 "boolean_operator"
3007 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3008 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3016 [(set_attr "type" "compare")
3017 (set_attr "length" "4,8")])
3020 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3021 (compare:CC (match_operator:SI 4 "boolean_operator"
3022 [(match_operand:SI 1 "gpc_reg_operand" "")
3023 (match_operand:SI 2 "gpc_reg_operand" "")])
3025 (set (match_operand:SI 0 "gpc_reg_operand" "")
3027 "TARGET_32BIT && reload_completed"
3028 [(set (match_dup 0) (match_dup 4))
3030 (compare:CC (match_dup 0)
3034 ;; Split a logical operation that we can't do in one insn into two insns,
3035 ;; each of which does one 16-bit part. This is used by combine.
3038 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3039 (match_operator:SI 3 "boolean_or_operator"
3040 [(match_operand:SI 1 "gpc_reg_operand" "")
3041 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3043 [(set (match_dup 0) (match_dup 4))
3044 (set (match_dup 0) (match_dup 5))]
3048 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3049 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3051 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3052 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3056 (define_insn "*boolcsi3_internal1"
3057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3058 (match_operator:SI 3 "boolean_operator"
3059 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3060 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3064 (define_insn "*boolcsi3_internal2"
3065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3066 (compare:CC (match_operator:SI 4 "boolean_operator"
3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3068 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3070 (clobber (match_scratch:SI 3 "=r,r"))]
3075 [(set_attr "type" "compare")
3076 (set_attr "length" "4,8")])
3079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3082 (match_operand:SI 2 "gpc_reg_operand" "")])
3084 (clobber (match_scratch:SI 3 ""))]
3085 "TARGET_32BIT && reload_completed"
3086 [(set (match_dup 3) (match_dup 4))
3088 (compare:CC (match_dup 3)
3092 (define_insn "*boolcsi3_internal3"
3093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3094 (compare:CC (match_operator:SI 4 "boolean_operator"
3095 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3096 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3098 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3104 [(set_attr "type" "compare")
3105 (set_attr "length" "4,8")])
3108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3109 (compare:CC (match_operator:SI 4 "boolean_operator"
3110 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3111 (match_operand:SI 2 "gpc_reg_operand" "")])
3113 (set (match_operand:SI 0 "gpc_reg_operand" "")
3115 "TARGET_32BIT && reload_completed"
3116 [(set (match_dup 0) (match_dup 4))
3118 (compare:CC (match_dup 0)
3122 (define_insn "*boolccsi3_internal1"
3123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3124 (match_operator:SI 3 "boolean_operator"
3125 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3126 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3130 (define_insn "*boolccsi3_internal2"
3131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3132 (compare:CC (match_operator:SI 4 "boolean_operator"
3133 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3134 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3136 (clobber (match_scratch:SI 3 "=r,r"))]
3141 [(set_attr "type" "compare")
3142 (set_attr "length" "4,8")])
3145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3146 (compare:CC (match_operator:SI 4 "boolean_operator"
3147 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3148 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3150 (clobber (match_scratch:SI 3 ""))]
3151 "TARGET_32BIT && reload_completed"
3152 [(set (match_dup 3) (match_dup 4))
3154 (compare:CC (match_dup 3)
3158 (define_insn "*boolccsi3_internal3"
3159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3160 (compare:CC (match_operator:SI 4 "boolean_operator"
3161 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3162 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3164 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3170 [(set_attr "type" "compare")
3171 (set_attr "length" "4,8")])
3174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3175 (compare:CC (match_operator:SI 4 "boolean_operator"
3176 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3177 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3179 (set (match_operand:SI 0 "gpc_reg_operand" "")
3181 "TARGET_32BIT && reload_completed"
3182 [(set (match_dup 0) (match_dup 4))
3184 (compare:CC (match_dup 0)
3188 ;; maskir insn. We need four forms because things might be in arbitrary
3189 ;; orders. Don't define forms that only set CR fields because these
3190 ;; would modify an input register.
3192 (define_insn "*maskir_internal1"
3193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3194 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3195 (match_operand:SI 1 "gpc_reg_operand" "0"))
3196 (and:SI (match_dup 2)
3197 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3201 (define_insn "*maskir_internal2"
3202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3203 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3204 (match_operand:SI 1 "gpc_reg_operand" "0"))
3205 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3210 (define_insn "*maskir_internal3"
3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3212 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3213 (match_operand:SI 3 "gpc_reg_operand" "r"))
3214 (and:SI (not:SI (match_dup 2))
3215 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3219 (define_insn "*maskir_internal4"
3220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3221 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3222 (match_operand:SI 2 "gpc_reg_operand" "r"))
3223 (and:SI (not:SI (match_dup 2))
3224 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3228 (define_insn "*maskir_internal5"
3229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3231 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3232 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3233 (and:SI (match_dup 2)
3234 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3237 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3238 (and:SI (match_dup 2) (match_dup 3))))]
3243 [(set_attr "type" "compare")
3244 (set_attr "length" "4,8")])
3247 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3249 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3250 (match_operand:SI 1 "gpc_reg_operand" ""))
3251 (and:SI (match_dup 2)
3252 (match_operand:SI 3 "gpc_reg_operand" "")))
3254 (set (match_operand:SI 0 "gpc_reg_operand" "")
3255 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3256 (and:SI (match_dup 2) (match_dup 3))))]
3257 "TARGET_POWER && reload_completed"
3259 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3260 (and:SI (match_dup 2) (match_dup 3))))
3262 (compare:CC (match_dup 0)
3266 (define_insn "*maskir_internal6"
3267 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3269 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3270 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3271 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3274 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3275 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3276 (and:SI (match_dup 3) (match_dup 2))))]
3281 [(set_attr "type" "compare")
3282 (set_attr "length" "4,8")])
3285 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3287 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3288 (match_operand:SI 1 "gpc_reg_operand" ""))
3289 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3292 (set (match_operand:SI 0 "gpc_reg_operand" "")
3293 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3294 (and:SI (match_dup 3) (match_dup 2))))]
3295 "TARGET_POWER && reload_completed"
3297 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3298 (and:SI (match_dup 3) (match_dup 2))))
3300 (compare:CC (match_dup 0)
3304 (define_insn "*maskir_internal7"
3305 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3307 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3309 (and:SI (not:SI (match_dup 2))
3310 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3312 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3313 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3314 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3319 [(set_attr "type" "compare")
3320 (set_attr "length" "4,8")])
3323 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3325 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3326 (match_operand:SI 3 "gpc_reg_operand" ""))
3327 (and:SI (not:SI (match_dup 2))
3328 (match_operand:SI 1 "gpc_reg_operand" "")))
3330 (set (match_operand:SI 0 "gpc_reg_operand" "")
3331 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3332 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3333 "TARGET_POWER && reload_completed"
3335 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3336 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3338 (compare:CC (match_dup 0)
3342 (define_insn "*maskir_internal8"
3343 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3345 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3346 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3347 (and:SI (not:SI (match_dup 2))
3348 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3351 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3352 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3357 [(set_attr "type" "compare")
3358 (set_attr "length" "4,8")])
3361 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3363 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3364 (match_operand:SI 2 "gpc_reg_operand" ""))
3365 (and:SI (not:SI (match_dup 2))
3366 (match_operand:SI 1 "gpc_reg_operand" "")))
3368 (set (match_operand:SI 0 "gpc_reg_operand" "")
3369 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3370 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3371 "TARGET_POWER && reload_completed"
3373 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3374 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3376 (compare:CC (match_dup 0)
3380 ;; Rotate and shift insns, in all their variants. These support shifts,
3381 ;; field inserts and extracts, and various combinations thereof.
3382 (define_expand "insv"
3383 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3384 (match_operand:SI 1 "const_int_operand" "")
3385 (match_operand:SI 2 "const_int_operand" ""))
3386 (match_operand 3 "gpc_reg_operand" ""))]
3390 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3391 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3392 compiler if the address of the structure is taken later. Likewise, do
3393 not handle invalid E500 subregs. */
3394 if (GET_CODE (operands[0]) == SUBREG
3395 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3396 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3397 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3400 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3401 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3403 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3407 (define_insn "insvsi"
3408 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3409 (match_operand:SI 1 "const_int_operand" "i")
3410 (match_operand:SI 2 "const_int_operand" "i"))
3411 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3415 int start = INTVAL (operands[2]) & 31;
3416 int size = INTVAL (operands[1]) & 31;
3418 operands[4] = GEN_INT (32 - start - size);
3419 operands[1] = GEN_INT (start + size - 1);
3420 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3422 [(set_attr "type" "insert_word")])
3424 (define_insn "*insvsi_internal1"
3425 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3426 (match_operand:SI 1 "const_int_operand" "i")
3427 (match_operand:SI 2 "const_int_operand" "i"))
3428 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3429 (match_operand:SI 4 "const_int_operand" "i")))]
3430 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3433 int shift = INTVAL (operands[4]) & 31;
3434 int start = INTVAL (operands[2]) & 31;
3435 int size = INTVAL (operands[1]) & 31;
3437 operands[4] = GEN_INT (shift - start - size);
3438 operands[1] = GEN_INT (start + size - 1);
3439 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3441 [(set_attr "type" "insert_word")])
3443 (define_insn "*insvsi_internal2"
3444 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3445 (match_operand:SI 1 "const_int_operand" "i")
3446 (match_operand:SI 2 "const_int_operand" "i"))
3447 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3448 (match_operand:SI 4 "const_int_operand" "i")))]
3449 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3452 int shift = INTVAL (operands[4]) & 31;
3453 int start = INTVAL (operands[2]) & 31;
3454 int size = INTVAL (operands[1]) & 31;
3456 operands[4] = GEN_INT (32 - shift - start - size);
3457 operands[1] = GEN_INT (start + size - 1);
3458 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3460 [(set_attr "type" "insert_word")])
3462 (define_insn "*insvsi_internal3"
3463 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3464 (match_operand:SI 1 "const_int_operand" "i")
3465 (match_operand:SI 2 "const_int_operand" "i"))
3466 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3467 (match_operand:SI 4 "const_int_operand" "i")))]
3468 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3471 int shift = INTVAL (operands[4]) & 31;
3472 int start = INTVAL (operands[2]) & 31;
3473 int size = INTVAL (operands[1]) & 31;
3475 operands[4] = GEN_INT (32 - shift - start - size);
3476 operands[1] = GEN_INT (start + size - 1);
3477 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3479 [(set_attr "type" "insert_word")])
3481 (define_insn "*insvsi_internal4"
3482 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3483 (match_operand:SI 1 "const_int_operand" "i")
3484 (match_operand:SI 2 "const_int_operand" "i"))
3485 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3486 (match_operand:SI 4 "const_int_operand" "i")
3487 (match_operand:SI 5 "const_int_operand" "i")))]
3488 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3491 int extract_start = INTVAL (operands[5]) & 31;
3492 int extract_size = INTVAL (operands[4]) & 31;
3493 int insert_start = INTVAL (operands[2]) & 31;
3494 int insert_size = INTVAL (operands[1]) & 31;
3496 /* Align extract field with insert field */
3497 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3498 operands[1] = GEN_INT (insert_start + insert_size - 1);
3499 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3501 [(set_attr "type" "insert_word")])
3503 ;; combine patterns for rlwimi
3504 (define_insn "*insvsi_internal5"
3505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3506 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3507 (match_operand:SI 1 "mask_operand" "i"))
3508 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3509 (match_operand:SI 2 "const_int_operand" "i"))
3510 (match_operand:SI 5 "mask_operand" "i"))))]
3511 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3514 int me = extract_ME(operands[5]);
3515 int mb = extract_MB(operands[5]);
3516 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3517 operands[2] = GEN_INT(mb);
3518 operands[1] = GEN_INT(me);
3519 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3521 [(set_attr "type" "insert_word")])
3523 (define_insn "*insvsi_internal6"
3524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3525 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3526 (match_operand:SI 2 "const_int_operand" "i"))
3527 (match_operand:SI 5 "mask_operand" "i"))
3528 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3529 (match_operand:SI 1 "mask_operand" "i"))))]
3530 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3533 int me = extract_ME(operands[5]);
3534 int mb = extract_MB(operands[5]);
3535 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3536 operands[2] = GEN_INT(mb);
3537 operands[1] = GEN_INT(me);
3538 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3540 [(set_attr "type" "insert_word")])
3542 (define_insn "insvdi"
3543 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3544 (match_operand:SI 1 "const_int_operand" "i")
3545 (match_operand:SI 2 "const_int_operand" "i"))
3546 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3550 int start = INTVAL (operands[2]) & 63;
3551 int size = INTVAL (operands[1]) & 63;
3553 operands[1] = GEN_INT (64 - start - size);
3554 return \"rldimi %0,%3,%H1,%H2\";
3557 (define_insn "*insvdi_internal2"
3558 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3559 (match_operand:SI 1 "const_int_operand" "i")
3560 (match_operand:SI 2 "const_int_operand" "i"))
3561 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3562 (match_operand:SI 4 "const_int_operand" "i")))]
3564 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3567 int shift = INTVAL (operands[4]) & 63;
3568 int start = (INTVAL (operands[2]) & 63) - 32;
3569 int size = INTVAL (operands[1]) & 63;
3571 operands[4] = GEN_INT (64 - shift - start - size);
3572 operands[2] = GEN_INT (start);
3573 operands[1] = GEN_INT (start + size - 1);
3574 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3577 (define_insn "*insvdi_internal3"
3578 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3579 (match_operand:SI 1 "const_int_operand" "i")
3580 (match_operand:SI 2 "const_int_operand" "i"))
3581 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3582 (match_operand:SI 4 "const_int_operand" "i")))]
3584 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3587 int shift = INTVAL (operands[4]) & 63;
3588 int start = (INTVAL (operands[2]) & 63) - 32;
3589 int size = INTVAL (operands[1]) & 63;
3591 operands[4] = GEN_INT (64 - shift - start - size);
3592 operands[2] = GEN_INT (start);
3593 operands[1] = GEN_INT (start + size - 1);
3594 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3597 (define_expand "extzv"
3598 [(set (match_operand 0 "gpc_reg_operand" "")
3599 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3600 (match_operand:SI 2 "const_int_operand" "")
3601 (match_operand:SI 3 "const_int_operand" "")))]
3605 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3606 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3607 compiler if the address of the structure is taken later. */
3608 if (GET_CODE (operands[0]) == SUBREG
3609 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3612 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3613 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3615 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3619 (define_insn "extzvsi"
3620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3621 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3622 (match_operand:SI 2 "const_int_operand" "i")
3623 (match_operand:SI 3 "const_int_operand" "i")))]
3627 int start = INTVAL (operands[3]) & 31;
3628 int size = INTVAL (operands[2]) & 31;
3630 if (start + size >= 32)
3631 operands[3] = const0_rtx;
3633 operands[3] = GEN_INT (start + size);
3634 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3637 (define_insn "*extzvsi_internal1"
3638 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3639 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3640 (match_operand:SI 2 "const_int_operand" "i,i")
3641 (match_operand:SI 3 "const_int_operand" "i,i"))
3643 (clobber (match_scratch:SI 4 "=r,r"))]
3647 int start = INTVAL (operands[3]) & 31;
3648 int size = INTVAL (operands[2]) & 31;
3650 /* Force split for non-cc0 compare. */
3651 if (which_alternative == 1)
3654 /* If the bit-field being tested fits in the upper or lower half of a
3655 word, it is possible to use andiu. or andil. to test it. This is
3656 useful because the condition register set-use delay is smaller for
3657 andi[ul]. than for rlinm. This doesn't work when the starting bit
3658 position is 0 because the LT and GT bits may be set wrong. */
3660 if ((start > 0 && start + size <= 16) || start >= 16)
3662 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3663 - (1 << (16 - (start & 15) - size))));
3665 return \"{andiu.|andis.} %4,%1,%3\";
3667 return \"{andil.|andi.} %4,%1,%3\";
3670 if (start + size >= 32)
3671 operands[3] = const0_rtx;
3673 operands[3] = GEN_INT (start + size);
3674 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3676 [(set_attr "type" "compare")
3677 (set_attr "length" "4,8")])
3680 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3681 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3682 (match_operand:SI 2 "const_int_operand" "")
3683 (match_operand:SI 3 "const_int_operand" ""))
3685 (clobber (match_scratch:SI 4 ""))]
3688 (zero_extract:SI (match_dup 1) (match_dup 2)
3691 (compare:CC (match_dup 4)
3695 (define_insn "*extzvsi_internal2"
3696 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3697 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3698 (match_operand:SI 2 "const_int_operand" "i,i")
3699 (match_operand:SI 3 "const_int_operand" "i,i"))
3701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3702 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3706 int start = INTVAL (operands[3]) & 31;
3707 int size = INTVAL (operands[2]) & 31;
3709 /* Force split for non-cc0 compare. */
3710 if (which_alternative == 1)
3713 /* Since we are using the output value, we can't ignore any need for
3714 a shift. The bit-field must end at the LSB. */
3715 if (start >= 16 && start + size == 32)
3717 operands[3] = GEN_INT ((1 << size) - 1);
3718 return \"{andil.|andi.} %0,%1,%3\";
3721 if (start + size >= 32)
3722 operands[3] = const0_rtx;
3724 operands[3] = GEN_INT (start + size);
3725 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3727 [(set_attr "type" "compare")
3728 (set_attr "length" "4,8")])
3731 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3732 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3733 (match_operand:SI 2 "const_int_operand" "")
3734 (match_operand:SI 3 "const_int_operand" ""))
3736 (set (match_operand:SI 0 "gpc_reg_operand" "")
3737 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3740 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3742 (compare:CC (match_dup 0)
3746 (define_insn "extzvdi"
3747 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3748 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3749 (match_operand:SI 2 "const_int_operand" "i")
3750 (match_operand:SI 3 "const_int_operand" "i")))]
3754 int start = INTVAL (operands[3]) & 63;
3755 int size = INTVAL (operands[2]) & 63;
3757 if (start + size >= 64)
3758 operands[3] = const0_rtx;
3760 operands[3] = GEN_INT (start + size);
3761 operands[2] = GEN_INT (64 - size);
3762 return \"rldicl %0,%1,%3,%2\";
3765 (define_insn "*extzvdi_internal1"
3766 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3767 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3768 (match_operand:SI 2 "const_int_operand" "i")
3769 (match_operand:SI 3 "const_int_operand" "i"))
3771 (clobber (match_scratch:DI 4 "=r"))]
3775 int start = INTVAL (operands[3]) & 63;
3776 int size = INTVAL (operands[2]) & 63;
3778 if (start + size >= 64)
3779 operands[3] = const0_rtx;
3781 operands[3] = GEN_INT (start + size);
3782 operands[2] = GEN_INT (64 - size);
3783 return \"rldicl. %4,%1,%3,%2\";
3785 [(set_attr "type" "compare")])
3787 (define_insn "*extzvdi_internal2"
3788 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3789 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3790 (match_operand:SI 2 "const_int_operand" "i")
3791 (match_operand:SI 3 "const_int_operand" "i"))
3793 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3794 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3798 int start = INTVAL (operands[3]) & 63;
3799 int size = INTVAL (operands[2]) & 63;
3801 if (start + size >= 64)
3802 operands[3] = const0_rtx;
3804 operands[3] = GEN_INT (start + size);
3805 operands[2] = GEN_INT (64 - size);
3806 return \"rldicl. %0,%1,%3,%2\";
3808 [(set_attr "type" "compare")])
3810 (define_insn "rotlsi3"
3811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3812 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3813 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3815 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3817 (define_insn "*rotlsi3_internal2"
3818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3819 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3820 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3822 (clobber (match_scratch:SI 3 "=r,r"))]
3825 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3827 [(set_attr "type" "delayed_compare")
3828 (set_attr "length" "4,8")])
3831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3832 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3833 (match_operand:SI 2 "reg_or_cint_operand" ""))
3835 (clobber (match_scratch:SI 3 ""))]
3838 (rotate:SI (match_dup 1) (match_dup 2)))
3840 (compare:CC (match_dup 3)
3844 (define_insn "*rotlsi3_internal3"
3845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3846 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3847 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3849 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3850 (rotate:SI (match_dup 1) (match_dup 2)))]
3853 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3855 [(set_attr "type" "delayed_compare")
3856 (set_attr "length" "4,8")])
3859 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3860 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3861 (match_operand:SI 2 "reg_or_cint_operand" ""))
3863 (set (match_operand:SI 0 "gpc_reg_operand" "")
3864 (rotate:SI (match_dup 1) (match_dup 2)))]
3867 (rotate:SI (match_dup 1) (match_dup 2)))
3869 (compare:CC (match_dup 0)
3873 (define_insn "*rotlsi3_internal4"
3874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3875 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3876 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3877 (match_operand:SI 3 "mask_operand" "n")))]
3879 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3881 (define_insn "*rotlsi3_internal5"
3882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3884 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3885 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3886 (match_operand:SI 3 "mask_operand" "n,n"))
3888 (clobber (match_scratch:SI 4 "=r,r"))]
3891 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3893 [(set_attr "type" "delayed_compare")
3894 (set_attr "length" "4,8")])
3897 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3899 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3900 (match_operand:SI 2 "reg_or_cint_operand" ""))
3901 (match_operand:SI 3 "mask_operand" ""))
3903 (clobber (match_scratch:SI 4 ""))]
3906 (and:SI (rotate:SI (match_dup 1)
3910 (compare:CC (match_dup 4)
3914 (define_insn "*rotlsi3_internal6"
3915 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3917 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3918 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3919 (match_operand:SI 3 "mask_operand" "n,n"))
3921 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3922 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3925 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3927 [(set_attr "type" "delayed_compare")
3928 (set_attr "length" "4,8")])
3931 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3933 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3934 (match_operand:SI 2 "reg_or_cint_operand" ""))
3935 (match_operand:SI 3 "mask_operand" ""))
3937 (set (match_operand:SI 0 "gpc_reg_operand" "")
3938 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3941 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3943 (compare:CC (match_dup 0)
3947 (define_insn "*rotlsi3_internal7"
3948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3951 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3952 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3954 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3956 (define_insn "*rotlsi3_internal8"
3957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3958 (compare:CC (zero_extend:SI
3960 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3961 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3963 (clobber (match_scratch:SI 3 "=r,r"))]
3966 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3968 [(set_attr "type" "delayed_compare")
3969 (set_attr "length" "4,8")])
3972 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3973 (compare:CC (zero_extend:SI
3975 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3976 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3978 (clobber (match_scratch:SI 3 ""))]
3981 (zero_extend:SI (subreg:QI
3982 (rotate:SI (match_dup 1)
3985 (compare:CC (match_dup 3)
3989 (define_insn "*rotlsi3_internal9"
3990 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3991 (compare:CC (zero_extend:SI
3993 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3994 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3996 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3997 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4000 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
4002 [(set_attr "type" "delayed_compare")
4003 (set_attr "length" "4,8")])
4006 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4007 (compare:CC (zero_extend:SI
4009 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4010 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4012 (set (match_operand:SI 0 "gpc_reg_operand" "")
4013 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4016 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4018 (compare:CC (match_dup 0)
4022 (define_insn "*rotlsi3_internal10"
4023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4026 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4027 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4029 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
4031 (define_insn "*rotlsi3_internal11"
4032 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4033 (compare:CC (zero_extend:SI
4035 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4036 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4038 (clobber (match_scratch:SI 3 "=r,r"))]
4041 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
4043 [(set_attr "type" "delayed_compare")
4044 (set_attr "length" "4,8")])
4047 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4048 (compare:CC (zero_extend:SI
4050 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4051 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4053 (clobber (match_scratch:SI 3 ""))]
4056 (zero_extend:SI (subreg:HI
4057 (rotate:SI (match_dup 1)
4060 (compare:CC (match_dup 3)
4064 (define_insn "*rotlsi3_internal12"
4065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4066 (compare:CC (zero_extend:SI
4068 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4069 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4071 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4072 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4075 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4077 [(set_attr "type" "delayed_compare")
4078 (set_attr "length" "4,8")])
4081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4082 (compare:CC (zero_extend:SI
4084 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4085 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4087 (set (match_operand:SI 0 "gpc_reg_operand" "")
4088 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4091 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4093 (compare:CC (match_dup 0)
4097 ;; Note that we use "sle." instead of "sl." so that we can set
4098 ;; SHIFT_COUNT_TRUNCATED.
4100 (define_expand "ashlsi3"
4101 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4102 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4103 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4108 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4110 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4114 (define_insn "ashlsi3_power"
4115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4116 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4117 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4118 (clobber (match_scratch:SI 3 "=q,X"))]
4122 {sli|slwi} %0,%1,%h2")
4124 (define_insn "ashlsi3_no_power"
4125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4126 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4127 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4129 "{sl|slw}%I2 %0,%1,%h2")
4132 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4133 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4134 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4136 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4137 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4141 {sli.|slwi.} %3,%1,%h2
4144 [(set_attr "type" "delayed_compare")
4145 (set_attr "length" "4,4,8,8")])
4148 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4149 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4150 (match_operand:SI 2 "reg_or_cint_operand" ""))
4152 (clobber (match_scratch:SI 3 ""))
4153 (clobber (match_scratch:SI 4 ""))]
4154 "TARGET_POWER && reload_completed"
4155 [(parallel [(set (match_dup 3)
4156 (ashift:SI (match_dup 1) (match_dup 2)))
4157 (clobber (match_dup 4))])
4159 (compare:CC (match_dup 3)
4164 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4165 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4166 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4168 (clobber (match_scratch:SI 3 "=r,r"))]
4169 "! TARGET_POWER && TARGET_32BIT"
4171 {sl|slw}%I2. %3,%1,%h2
4173 [(set_attr "type" "delayed_compare")
4174 (set_attr "length" "4,8")])
4177 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4178 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4179 (match_operand:SI 2 "reg_or_cint_operand" ""))
4181 (clobber (match_scratch:SI 3 ""))]
4182 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4184 (ashift:SI (match_dup 1) (match_dup 2)))
4186 (compare:CC (match_dup 3)
4191 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4192 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4193 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4195 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4196 (ashift:SI (match_dup 1) (match_dup 2)))
4197 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4201 {sli.|slwi.} %0,%1,%h2
4204 [(set_attr "type" "delayed_compare")
4205 (set_attr "length" "4,4,8,8")])
4208 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4209 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4210 (match_operand:SI 2 "reg_or_cint_operand" ""))
4212 (set (match_operand:SI 0 "gpc_reg_operand" "")
4213 (ashift:SI (match_dup 1) (match_dup 2)))
4214 (clobber (match_scratch:SI 4 ""))]
4215 "TARGET_POWER && reload_completed"
4216 [(parallel [(set (match_dup 0)
4217 (ashift:SI (match_dup 1) (match_dup 2)))
4218 (clobber (match_dup 4))])
4220 (compare:CC (match_dup 0)
4225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4226 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4227 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4229 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4230 (ashift:SI (match_dup 1) (match_dup 2)))]
4231 "! TARGET_POWER && TARGET_32BIT"
4233 {sl|slw}%I2. %0,%1,%h2
4235 [(set_attr "type" "delayed_compare")
4236 (set_attr "length" "4,8")])
4239 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4240 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4241 (match_operand:SI 2 "reg_or_cint_operand" ""))
4243 (set (match_operand:SI 0 "gpc_reg_operand" "")
4244 (ashift:SI (match_dup 1) (match_dup 2)))]
4245 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4247 (ashift:SI (match_dup 1) (match_dup 2)))
4249 (compare:CC (match_dup 0)
4253 (define_insn "rlwinm"
4254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4255 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4256 (match_operand:SI 2 "const_int_operand" "i"))
4257 (match_operand:SI 3 "mask_operand" "n")))]
4258 "includes_lshift_p (operands[2], operands[3])"
4259 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4262 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4264 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4265 (match_operand:SI 2 "const_int_operand" "i,i"))
4266 (match_operand:SI 3 "mask_operand" "n,n"))
4268 (clobber (match_scratch:SI 4 "=r,r"))]
4269 "includes_lshift_p (operands[2], operands[3])"
4271 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4273 [(set_attr "type" "delayed_compare")
4274 (set_attr "length" "4,8")])
4277 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4279 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4280 (match_operand:SI 2 "const_int_operand" ""))
4281 (match_operand:SI 3 "mask_operand" ""))
4283 (clobber (match_scratch:SI 4 ""))]
4284 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4286 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4289 (compare:CC (match_dup 4)
4294 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4296 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4297 (match_operand:SI 2 "const_int_operand" "i,i"))
4298 (match_operand:SI 3 "mask_operand" "n,n"))
4300 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4301 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4302 "includes_lshift_p (operands[2], operands[3])"
4304 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4306 [(set_attr "type" "delayed_compare")
4307 (set_attr "length" "4,8")])
4310 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4312 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4313 (match_operand:SI 2 "const_int_operand" ""))
4314 (match_operand:SI 3 "mask_operand" ""))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "")
4317 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4318 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4320 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4322 (compare:CC (match_dup 0)
4326 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4328 (define_expand "lshrsi3"
4329 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4330 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4331 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4336 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4338 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4342 (define_insn "lshrsi3_power"
4343 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4344 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4345 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4346 (clobber (match_scratch:SI 3 "=q,X,X"))]
4351 {s%A2i|s%A2wi} %0,%1,%h2")
4353 (define_insn "lshrsi3_no_power"
4354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4355 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4360 {sr|srw}%I2 %0,%1,%h2")
4363 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4364 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4365 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4367 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4368 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4373 {s%A2i.|s%A2wi.} %3,%1,%h2
4377 [(set_attr "type" "delayed_compare")
4378 (set_attr "length" "4,4,4,8,8,8")])
4381 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4382 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4383 (match_operand:SI 2 "reg_or_cint_operand" ""))
4385 (clobber (match_scratch:SI 3 ""))
4386 (clobber (match_scratch:SI 4 ""))]
4387 "TARGET_POWER && reload_completed"
4388 [(parallel [(set (match_dup 3)
4389 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4390 (clobber (match_dup 4))])
4392 (compare:CC (match_dup 3)
4397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4398 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4399 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4401 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4402 "! TARGET_POWER && TARGET_32BIT"
4405 {sr|srw}%I2. %3,%1,%h2
4408 [(set_attr "type" "delayed_compare")
4409 (set_attr "length" "4,4,8,8")])
4412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4413 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4414 (match_operand:SI 2 "reg_or_cint_operand" ""))
4416 (clobber (match_scratch:SI 3 ""))]
4417 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4419 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4421 (compare:CC (match_dup 3)
4426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4427 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4428 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4430 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4431 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4432 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4437 {s%A2i.|s%A2wi.} %0,%1,%h2
4441 [(set_attr "type" "delayed_compare")
4442 (set_attr "length" "4,4,4,8,8,8")])
4445 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4446 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4447 (match_operand:SI 2 "reg_or_cint_operand" ""))
4449 (set (match_operand:SI 0 "gpc_reg_operand" "")
4450 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4451 (clobber (match_scratch:SI 4 ""))]
4452 "TARGET_POWER && reload_completed"
4453 [(parallel [(set (match_dup 0)
4454 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4455 (clobber (match_dup 4))])
4457 (compare:CC (match_dup 0)
4462 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4463 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4464 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4466 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4467 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4468 "! TARGET_POWER && TARGET_32BIT"
4471 {sr|srw}%I2. %0,%1,%h2
4474 [(set_attr "type" "delayed_compare")
4475 (set_attr "length" "4,4,8,8")])
4478 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4479 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4480 (match_operand:SI 2 "reg_or_cint_operand" ""))
4482 (set (match_operand:SI 0 "gpc_reg_operand" "")
4483 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4484 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4486 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4488 (compare:CC (match_dup 0)
4493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4494 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4495 (match_operand:SI 2 "const_int_operand" "i"))
4496 (match_operand:SI 3 "mask_operand" "n")))]
4497 "includes_rshift_p (operands[2], operands[3])"
4498 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4503 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4504 (match_operand:SI 2 "const_int_operand" "i,i"))
4505 (match_operand:SI 3 "mask_operand" "n,n"))
4507 (clobber (match_scratch:SI 4 "=r,r"))]
4508 "includes_rshift_p (operands[2], operands[3])"
4510 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4512 [(set_attr "type" "delayed_compare")
4513 (set_attr "length" "4,8")])
4516 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4518 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4519 (match_operand:SI 2 "const_int_operand" ""))
4520 (match_operand:SI 3 "mask_operand" ""))
4522 (clobber (match_scratch:SI 4 ""))]
4523 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4525 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4528 (compare:CC (match_dup 4)
4533 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4535 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4536 (match_operand:SI 2 "const_int_operand" "i,i"))
4537 (match_operand:SI 3 "mask_operand" "n,n"))
4539 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4540 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4541 "includes_rshift_p (operands[2], operands[3])"
4543 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4545 [(set_attr "type" "delayed_compare")
4546 (set_attr "length" "4,8")])
4549 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4551 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4552 (match_operand:SI 2 "const_int_operand" ""))
4553 (match_operand:SI 3 "mask_operand" ""))
4555 (set (match_operand:SI 0 "gpc_reg_operand" "")
4556 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4557 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4559 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4561 (compare:CC (match_dup 0)
4566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4569 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4570 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4571 "includes_rshift_p (operands[2], GEN_INT (255))"
4572 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4579 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4580 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4582 (clobber (match_scratch:SI 3 "=r,r"))]
4583 "includes_rshift_p (operands[2], GEN_INT (255))"
4585 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4587 [(set_attr "type" "delayed_compare")
4588 (set_attr "length" "4,8")])
4591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4595 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4596 (match_operand:SI 2 "const_int_operand" "")) 0))
4598 (clobber (match_scratch:SI 3 ""))]
4599 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4601 (zero_extend:SI (subreg:QI
4602 (lshiftrt:SI (match_dup 1)
4605 (compare:CC (match_dup 3)
4610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4614 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4615 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4618 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4619 "includes_rshift_p (operands[2], GEN_INT (255))"
4621 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4623 [(set_attr "type" "delayed_compare")
4624 (set_attr "length" "4,8")])
4627 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4631 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4632 (match_operand:SI 2 "const_int_operand" "")) 0))
4634 (set (match_operand:SI 0 "gpc_reg_operand" "")
4635 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4636 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4638 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4640 (compare:CC (match_dup 0)
4645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4648 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4649 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4650 "includes_rshift_p (operands[2], GEN_INT (65535))"
4651 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4654 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4658 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4659 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4661 (clobber (match_scratch:SI 3 "=r,r"))]
4662 "includes_rshift_p (operands[2], GEN_INT (65535))"
4664 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4666 [(set_attr "type" "delayed_compare")
4667 (set_attr "length" "4,8")])
4670 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4674 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4675 (match_operand:SI 2 "const_int_operand" "")) 0))
4677 (clobber (match_scratch:SI 3 ""))]
4678 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4680 (zero_extend:SI (subreg:HI
4681 (lshiftrt:SI (match_dup 1)
4684 (compare:CC (match_dup 3)
4689 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4693 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4694 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4696 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4697 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4698 "includes_rshift_p (operands[2], GEN_INT (65535))"
4700 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4702 [(set_attr "type" "delayed_compare")
4703 (set_attr "length" "4,8")])
4706 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4710 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4711 (match_operand:SI 2 "const_int_operand" "")) 0))
4713 (set (match_operand:SI 0 "gpc_reg_operand" "")
4714 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4715 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4717 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4719 (compare:CC (match_dup 0)
4724 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4726 (match_operand:SI 1 "gpc_reg_operand" "r"))
4727 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4733 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4735 (match_operand:SI 1 "gpc_reg_operand" "r"))
4736 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4742 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4744 (match_operand:SI 1 "gpc_reg_operand" "r"))
4745 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4751 (define_expand "ashrsi3"
4752 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4753 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4754 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4759 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4761 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4765 (define_insn "ashrsi3_power"
4766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4767 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4768 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4769 (clobber (match_scratch:SI 3 "=q,X"))]
4773 {srai|srawi} %0,%1,%h2")
4775 (define_insn "ashrsi3_no_power"
4776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4777 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4778 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4780 "{sra|sraw}%I2 %0,%1,%h2")
4783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4784 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4785 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4787 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4788 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4792 {srai.|srawi.} %3,%1,%h2
4795 [(set_attr "type" "delayed_compare")
4796 (set_attr "length" "4,4,8,8")])
4799 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4800 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4801 (match_operand:SI 2 "reg_or_cint_operand" ""))
4803 (clobber (match_scratch:SI 3 ""))
4804 (clobber (match_scratch:SI 4 ""))]
4805 "TARGET_POWER && reload_completed"
4806 [(parallel [(set (match_dup 3)
4807 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4808 (clobber (match_dup 4))])
4810 (compare:CC (match_dup 3)
4815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4816 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4817 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4819 (clobber (match_scratch:SI 3 "=r,r"))]
4822 {sra|sraw}%I2. %3,%1,%h2
4824 [(set_attr "type" "delayed_compare")
4825 (set_attr "length" "4,8")])
4828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4829 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4830 (match_operand:SI 2 "reg_or_cint_operand" ""))
4832 (clobber (match_scratch:SI 3 ""))]
4833 "! TARGET_POWER && reload_completed"
4835 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4837 (compare:CC (match_dup 3)
4842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4843 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4844 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4846 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4847 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4848 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4852 {srai.|srawi.} %0,%1,%h2
4855 [(set_attr "type" "delayed_compare")
4856 (set_attr "length" "4,4,8,8")])
4859 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4860 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4861 (match_operand:SI 2 "reg_or_cint_operand" ""))
4863 (set (match_operand:SI 0 "gpc_reg_operand" "")
4864 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4865 (clobber (match_scratch:SI 4 ""))]
4866 "TARGET_POWER && reload_completed"
4867 [(parallel [(set (match_dup 0)
4868 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4869 (clobber (match_dup 4))])
4871 (compare:CC (match_dup 0)
4876 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4877 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4878 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4881 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4884 {sra|sraw}%I2. %0,%1,%h2
4886 [(set_attr "type" "delayed_compare")
4887 (set_attr "length" "4,8")])
4890 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4891 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4892 (match_operand:SI 2 "reg_or_cint_operand" ""))
4894 (set (match_operand:SI 0 "gpc_reg_operand" "")
4895 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4896 "! TARGET_POWER && reload_completed"
4898 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4900 (compare:CC (match_dup 0)
4904 ;; Floating-point insns, excluding normal data motion.
4906 ;; PowerPC has a full set of single-precision floating point instructions.
4908 ;; For the POWER architecture, we pretend that we have both SFmode and
4909 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4910 ;; The only conversions we will do will be when storing to memory. In that
4911 ;; case, we will use the "frsp" instruction before storing.
4913 ;; Note that when we store into a single-precision memory location, we need to
4914 ;; use the frsp insn first. If the register being stored isn't dead, we
4915 ;; need a scratch register for the frsp. But this is difficult when the store
4916 ;; is done by reload. It is not incorrect to do the frsp on the register in
4917 ;; this case, we just lose precision that we would have otherwise gotten but
4918 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4920 (define_expand "extendsfdf2"
4921 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4922 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4923 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4926 (define_insn_and_split "*extendsfdf2_fpr"
4927 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4928 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4929 "TARGET_HARD_FLOAT && TARGET_FPRS"
4934 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4937 emit_note (NOTE_INSN_DELETED);
4940 [(set_attr "type" "fp,fp,fpload")])
4942 (define_expand "truncdfsf2"
4943 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4944 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4945 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4948 (define_insn "*truncdfsf2_fpr"
4949 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4950 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4951 "TARGET_HARD_FLOAT && TARGET_FPRS"
4953 [(set_attr "type" "fp")])
4955 (define_insn "aux_truncdfsf2"
4956 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4957 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4958 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4960 [(set_attr "type" "fp")])
4962 (define_expand "negsf2"
4963 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4964 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4968 (define_insn "*negsf2"
4969 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4970 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4971 "TARGET_HARD_FLOAT && TARGET_FPRS"
4973 [(set_attr "type" "fp")])
4975 (define_expand "abssf2"
4976 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4977 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4981 (define_insn "*abssf2"
4982 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4983 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4984 "TARGET_HARD_FLOAT && TARGET_FPRS"
4986 [(set_attr "type" "fp")])
4989 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4990 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4991 "TARGET_HARD_FLOAT && TARGET_FPRS"
4993 [(set_attr "type" "fp")])
4995 (define_expand "addsf3"
4996 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4997 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4998 (match_operand:SF 2 "gpc_reg_operand" "")))]
5003 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5004 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5005 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5006 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5008 [(set_attr "type" "fp")])
5011 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5012 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5013 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5014 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5015 "{fa|fadd} %0,%1,%2"
5016 [(set_attr "type" "fp")])
5018 (define_expand "subsf3"
5019 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5020 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5021 (match_operand:SF 2 "gpc_reg_operand" "")))]
5026 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5027 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5028 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5029 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5031 [(set_attr "type" "fp")])
5034 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5035 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5036 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5037 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5038 "{fs|fsub} %0,%1,%2"
5039 [(set_attr "type" "fp")])
5041 (define_expand "mulsf3"
5042 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5043 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5044 (match_operand:SF 2 "gpc_reg_operand" "")))]
5049 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5050 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5051 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5052 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5054 [(set_attr "type" "fp")])
5057 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5058 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5059 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5060 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5061 "{fm|fmul} %0,%1,%2"
5062 [(set_attr "type" "dmul")])
5065 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5066 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5067 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5069 [(set_attr "type" "fp")])
5071 (define_expand "divsf3"
5072 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5073 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5074 (match_operand:SF 2 "gpc_reg_operand" "")))]
5077 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5078 && flag_finite_math_only && !flag_trapping_math)
5080 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5086 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5087 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5088 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5089 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5091 [(set_attr "type" "sdiv")])
5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5095 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5096 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5097 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5098 "{fd|fdiv} %0,%1,%2"
5099 [(set_attr "type" "ddiv")])
5102 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5103 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5104 (match_operand:SF 2 "gpc_reg_operand" "f"))
5105 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5106 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5107 "fmadds %0,%1,%2,%3"
5108 [(set_attr "type" "fp")])
5111 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5112 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5113 (match_operand:SF 2 "gpc_reg_operand" "f"))
5114 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5115 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5116 "{fma|fmadd} %0,%1,%2,%3"
5117 [(set_attr "type" "dmul")])
5120 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5121 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5122 (match_operand:SF 2 "gpc_reg_operand" "f"))
5123 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5124 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5125 "fmsubs %0,%1,%2,%3"
5126 [(set_attr "type" "fp")])
5129 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5130 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5131 (match_operand:SF 2 "gpc_reg_operand" "f"))
5132 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5133 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5134 "{fms|fmsub} %0,%1,%2,%3"
5135 [(set_attr "type" "dmul")])
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5139 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5140 (match_operand:SF 2 "gpc_reg_operand" "f"))
5141 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5142 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5143 && HONOR_SIGNED_ZEROS (SFmode)"
5144 "fnmadds %0,%1,%2,%3"
5145 [(set_attr "type" "fp")])
5148 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5149 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5150 (match_operand:SF 2 "gpc_reg_operand" "f"))
5151 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5152 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5153 && ! HONOR_SIGNED_ZEROS (SFmode)"
5154 "fnmadds %0,%1,%2,%3"
5155 [(set_attr "type" "fp")])
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5159 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5160 (match_operand:SF 2 "gpc_reg_operand" "f"))
5161 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5162 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5163 "{fnma|fnmadd} %0,%1,%2,%3"
5164 [(set_attr "type" "dmul")])
5167 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5168 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5169 (match_operand:SF 2 "gpc_reg_operand" "f"))
5170 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5171 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5172 && ! HONOR_SIGNED_ZEROS (SFmode)"
5173 "{fnma|fnmadd} %0,%1,%2,%3"
5174 [(set_attr "type" "dmul")])
5177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5178 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5179 (match_operand:SF 2 "gpc_reg_operand" "f"))
5180 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5181 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5182 && HONOR_SIGNED_ZEROS (SFmode)"
5183 "fnmsubs %0,%1,%2,%3"
5184 [(set_attr "type" "fp")])
5187 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5188 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5189 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5190 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5191 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5192 && ! HONOR_SIGNED_ZEROS (SFmode)"
5193 "fnmsubs %0,%1,%2,%3"
5194 [(set_attr "type" "fp")])
5197 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5198 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5199 (match_operand:SF 2 "gpc_reg_operand" "f"))
5200 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5201 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5202 "{fnms|fnmsub} %0,%1,%2,%3"
5203 [(set_attr "type" "dmul")])
5206 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5207 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5208 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5209 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5210 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5211 && ! HONOR_SIGNED_ZEROS (SFmode)"
5212 "{fnms|fnmsub} %0,%1,%2,%3"
5213 [(set_attr "type" "dmul")])
5215 (define_expand "sqrtsf2"
5216 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5217 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5218 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5222 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5223 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5224 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5226 [(set_attr "type" "ssqrt")])
5229 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5230 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5231 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5233 [(set_attr "type" "dsqrt")])
5235 (define_expand "copysignsf3"
5237 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5239 (neg:SF (abs:SF (match_dup 1))))
5240 (set (match_operand:SF 0 "gpc_reg_operand" "")
5241 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5245 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5246 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5248 operands[3] = gen_reg_rtx (SFmode);
5249 operands[4] = gen_reg_rtx (SFmode);
5250 operands[5] = CONST0_RTX (SFmode);
5253 (define_expand "copysigndf3"
5255 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5257 (neg:DF (abs:DF (match_dup 1))))
5258 (set (match_operand:DF 0 "gpc_reg_operand" "")
5259 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5263 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5264 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5266 operands[3] = gen_reg_rtx (DFmode);
5267 operands[4] = gen_reg_rtx (DFmode);
5268 operands[5] = CONST0_RTX (DFmode);
5271 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5272 ;; fsel instruction and some auxiliary computations. Then we just have a
5273 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5275 (define_expand "smaxsf3"
5276 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5277 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5278 (match_operand:SF 2 "gpc_reg_operand" ""))
5281 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5282 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5284 (define_expand "sminsf3"
5285 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5286 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5287 (match_operand:SF 2 "gpc_reg_operand" ""))
5290 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5291 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5295 (match_operator:SF 3 "min_max_operator"
5296 [(match_operand:SF 1 "gpc_reg_operand" "")
5297 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5298 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5301 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5302 operands[1], operands[2]);
5306 (define_expand "movsicc"
5307 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5308 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5309 (match_operand:SI 2 "gpc_reg_operand" "")
5310 (match_operand:SI 3 "gpc_reg_operand" "")))]
5314 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5320 ;; We use the BASE_REGS for the isel input operands because, if rA is
5321 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5322 ;; because we may switch the operands and rB may end up being rA.
5324 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5325 ;; leave out the mode in operand 4 and use one pattern, but reload can
5326 ;; change the mode underneath our feet and then gets confused trying
5327 ;; to reload the value.
5328 (define_insn "isel_signed"
5329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5331 (match_operator 1 "comparison_operator"
5332 [(match_operand:CC 4 "cc_reg_operand" "y")
5334 (match_operand:SI 2 "gpc_reg_operand" "b")
5335 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5338 { return output_isel (operands); }"
5339 [(set_attr "length" "4")])
5341 (define_insn "isel_unsigned"
5342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5344 (match_operator 1 "comparison_operator"
5345 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5347 (match_operand:SI 2 "gpc_reg_operand" "b")
5348 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5351 { return output_isel (operands); }"
5352 [(set_attr "length" "4")])
5354 (define_expand "movsfcc"
5355 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5356 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5357 (match_operand:SF 2 "gpc_reg_operand" "")
5358 (match_operand:SF 3 "gpc_reg_operand" "")))]
5359 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5362 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5368 (define_insn "*fselsfsf4"
5369 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5370 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5371 (match_operand:SF 4 "zero_fp_constant" "F"))
5372 (match_operand:SF 2 "gpc_reg_operand" "f")
5373 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5374 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5376 [(set_attr "type" "fp")])
5378 (define_insn "*fseldfsf4"
5379 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5380 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5381 (match_operand:DF 4 "zero_fp_constant" "F"))
5382 (match_operand:SF 2 "gpc_reg_operand" "f")
5383 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5384 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5386 [(set_attr "type" "fp")])
5388 (define_expand "negdf2"
5389 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5390 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5391 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5394 (define_insn "*negdf2_fpr"
5395 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5396 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5397 "TARGET_HARD_FLOAT && TARGET_FPRS"
5399 [(set_attr "type" "fp")])
5401 (define_expand "absdf2"
5402 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5403 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5404 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5407 (define_insn "*absdf2_fpr"
5408 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5409 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5410 "TARGET_HARD_FLOAT && TARGET_FPRS"
5412 [(set_attr "type" "fp")])
5414 (define_insn "*nabsdf2_fpr"
5415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5416 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5417 "TARGET_HARD_FLOAT && TARGET_FPRS"
5419 [(set_attr "type" "fp")])
5421 (define_expand "adddf3"
5422 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5423 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5424 (match_operand:DF 2 "gpc_reg_operand" "")))]
5425 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5428 (define_insn "*adddf3_fpr"
5429 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5430 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5431 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5432 "TARGET_HARD_FLOAT && TARGET_FPRS"
5433 "{fa|fadd} %0,%1,%2"
5434 [(set_attr "type" "fp")])
5436 (define_expand "subdf3"
5437 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5438 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5439 (match_operand:DF 2 "gpc_reg_operand" "")))]
5440 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5443 (define_insn "*subdf3_fpr"
5444 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5445 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5446 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5447 "TARGET_HARD_FLOAT && TARGET_FPRS"
5448 "{fs|fsub} %0,%1,%2"
5449 [(set_attr "type" "fp")])
5451 (define_expand "muldf3"
5452 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5453 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5454 (match_operand:DF 2 "gpc_reg_operand" "")))]
5455 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5458 (define_insn "*muldf3_fpr"
5459 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5460 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5461 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5462 "TARGET_HARD_FLOAT && TARGET_FPRS"
5463 "{fm|fmul} %0,%1,%2"
5464 [(set_attr "type" "dmul")])
5467 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5468 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5469 "TARGET_POPCNTB && flag_finite_math_only"
5471 [(set_attr "type" "fp")])
5473 (define_expand "divdf3"
5474 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5475 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5476 (match_operand:DF 2 "gpc_reg_operand" "")))]
5477 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5479 if (swdiv && !optimize_size && TARGET_POPCNTB
5480 && flag_finite_math_only && !flag_trapping_math)
5482 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5487 (define_insn "*divdf3_fpr"
5488 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5489 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5490 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5491 "TARGET_HARD_FLOAT && TARGET_FPRS"
5492 "{fd|fdiv} %0,%1,%2"
5493 [(set_attr "type" "ddiv")])
5496 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5497 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5498 (match_operand:DF 2 "gpc_reg_operand" "f"))
5499 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5500 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5501 "{fma|fmadd} %0,%1,%2,%3"
5502 [(set_attr "type" "dmul")])
5505 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5506 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5507 (match_operand:DF 2 "gpc_reg_operand" "f"))
5508 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5509 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5510 "{fms|fmsub} %0,%1,%2,%3"
5511 [(set_attr "type" "dmul")])
5514 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5515 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5516 (match_operand:DF 2 "gpc_reg_operand" "f"))
5517 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5518 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5519 && HONOR_SIGNED_ZEROS (DFmode)"
5520 "{fnma|fnmadd} %0,%1,%2,%3"
5521 [(set_attr "type" "dmul")])
5524 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5525 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5526 (match_operand:DF 2 "gpc_reg_operand" "f"))
5527 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5528 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5529 && ! HONOR_SIGNED_ZEROS (DFmode)"
5530 "{fnma|fnmadd} %0,%1,%2,%3"
5531 [(set_attr "type" "dmul")])
5534 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5535 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5536 (match_operand:DF 2 "gpc_reg_operand" "f"))
5537 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5538 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5539 && HONOR_SIGNED_ZEROS (DFmode)"
5540 "{fnms|fnmsub} %0,%1,%2,%3"
5541 [(set_attr "type" "dmul")])
5544 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5545 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5546 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5547 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5548 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5549 && ! HONOR_SIGNED_ZEROS (DFmode)"
5550 "{fnms|fnmsub} %0,%1,%2,%3"
5551 [(set_attr "type" "dmul")])
5553 (define_insn "sqrtdf2"
5554 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5555 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5556 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5558 [(set_attr "type" "dsqrt")])
5560 ;; The conditional move instructions allow us to perform max and min
5561 ;; operations even when
5563 (define_expand "smaxdf3"
5564 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5565 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5566 (match_operand:DF 2 "gpc_reg_operand" ""))
5569 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5570 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5572 (define_expand "smindf3"
5573 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5574 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5575 (match_operand:DF 2 "gpc_reg_operand" ""))
5578 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5579 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5582 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5583 (match_operator:DF 3 "min_max_operator"
5584 [(match_operand:DF 1 "gpc_reg_operand" "")
5585 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5586 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5589 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5590 operands[1], operands[2]);
5594 (define_expand "movdfcc"
5595 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5596 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5597 (match_operand:DF 2 "gpc_reg_operand" "")
5598 (match_operand:DF 3 "gpc_reg_operand" "")))]
5599 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5602 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5608 (define_insn "*fseldfdf4"
5609 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5610 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5611 (match_operand:DF 4 "zero_fp_constant" "F"))
5612 (match_operand:DF 2 "gpc_reg_operand" "f")
5613 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5614 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5616 [(set_attr "type" "fp")])
5618 (define_insn "*fselsfdf4"
5619 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5620 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5621 (match_operand:SF 4 "zero_fp_constant" "F"))
5622 (match_operand:DF 2 "gpc_reg_operand" "f")
5623 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5626 [(set_attr "type" "fp")])
5628 ;; Conversions to and from floating-point.
5630 (define_expand "fixuns_truncsfsi2"
5631 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5632 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5633 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5636 (define_expand "fix_truncsfsi2"
5637 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5638 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5639 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5642 ; For each of these conversions, there is a define_expand, a define_insn
5643 ; with a '#' template, and a define_split (with C code). The idea is
5644 ; to allow constant folding with the template of the define_insn,
5645 ; then to have the insns split later (between sched1 and final).
5647 (define_expand "floatsidf2"
5648 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5649 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5652 (clobber (match_dup 4))
5653 (clobber (match_dup 5))
5654 (clobber (match_dup 6))])]
5655 "TARGET_HARD_FLOAT && TARGET_FPRS"
5658 if (TARGET_E500_DOUBLE)
5660 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5663 if (TARGET_POWERPC64)
5665 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5666 rtx t1 = gen_reg_rtx (DImode);
5667 rtx t2 = gen_reg_rtx (DImode);
5668 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5672 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5673 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5674 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5675 operands[5] = gen_reg_rtx (DFmode);
5676 operands[6] = gen_reg_rtx (SImode);
5679 (define_insn_and_split "*floatsidf2_internal"
5680 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5681 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5682 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5683 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5684 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5685 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5686 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5687 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5689 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5693 rtx lowword, highword;
5694 gcc_assert (MEM_P (operands[4]));
5695 highword = adjust_address (operands[4], SImode, 0);
5696 lowword = adjust_address (operands[4], SImode, 4);
5697 if (! WORDS_BIG_ENDIAN)
5700 tmp = highword; highword = lowword; lowword = tmp;
5703 emit_insn (gen_xorsi3 (operands[6], operands[1],
5704 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5705 emit_move_insn (lowword, operands[6]);
5706 emit_move_insn (highword, operands[2]);
5707 emit_move_insn (operands[5], operands[4]);
5708 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5711 [(set_attr "length" "24")])
5713 (define_expand "floatunssisf2"
5714 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5715 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5716 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5719 (define_expand "floatunssidf2"
5720 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5721 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5724 (clobber (match_dup 4))
5725 (clobber (match_dup 5))])]
5726 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5729 if (TARGET_E500_DOUBLE)
5731 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5734 if (TARGET_POWERPC64)
5736 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5737 rtx t1 = gen_reg_rtx (DImode);
5738 rtx t2 = gen_reg_rtx (DImode);
5739 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5744 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5745 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5746 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5747 operands[5] = gen_reg_rtx (DFmode);
5750 (define_insn_and_split "*floatunssidf2_internal"
5751 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5752 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5753 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5754 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5755 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5756 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5757 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5759 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5763 rtx lowword, highword;
5764 gcc_assert (MEM_P (operands[4]));
5765 highword = adjust_address (operands[4], SImode, 0);
5766 lowword = adjust_address (operands[4], SImode, 4);
5767 if (! WORDS_BIG_ENDIAN)
5770 tmp = highword; highword = lowword; lowword = tmp;
5773 emit_move_insn (lowword, operands[1]);
5774 emit_move_insn (highword, operands[2]);
5775 emit_move_insn (operands[5], operands[4]);
5776 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5779 [(set_attr "length" "20")])
5781 (define_expand "fix_truncdfsi2"
5782 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5783 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5784 (clobber (match_dup 2))
5785 (clobber (match_dup 3))])]
5786 "(TARGET_POWER2 || TARGET_POWERPC)
5787 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5790 if (TARGET_E500_DOUBLE)
5792 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5795 operands[2] = gen_reg_rtx (DImode);
5796 if (TARGET_PPC_GFXOPT)
5798 rtx orig_dest = operands[0];
5799 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5800 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5801 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5803 if (operands[0] != orig_dest)
5804 emit_move_insn (orig_dest, operands[0]);
5807 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5810 (define_insn_and_split "*fix_truncdfsi2_internal"
5811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5812 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5813 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5814 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5815 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5817 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5822 gcc_assert (MEM_P (operands[3]));
5823 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5825 emit_insn (gen_fctiwz (operands[2], operands[1]));
5826 emit_move_insn (operands[3], operands[2]);
5827 emit_move_insn (operands[0], lowword);
5830 [(set_attr "length" "16")])
5832 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5833 [(set (match_operand:SI 0 "memory_operand" "=Z")
5834 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5835 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5836 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5837 && TARGET_PPC_GFXOPT"
5843 emit_insn (gen_fctiwz (operands[2], operands[1]));
5844 emit_insn (gen_stfiwx (operands[0], operands[2]));
5847 [(set_attr "length" "16")])
5849 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5850 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5851 ; because the first makes it clear that operand 0 is not live
5852 ; before the instruction.
5853 (define_insn "fctiwz"
5854 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5855 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5857 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5858 "{fcirz|fctiwz} %0,%1"
5859 [(set_attr "type" "fp")])
5861 (define_insn "btruncdf2"
5862 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5863 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5864 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5866 [(set_attr "type" "fp")])
5868 (define_insn "btruncsf2"
5869 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5870 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5871 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5873 [(set_attr "type" "fp")])
5875 (define_insn "ceildf2"
5876 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5877 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5878 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5880 [(set_attr "type" "fp")])
5882 (define_insn "ceilsf2"
5883 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5884 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5885 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5887 [(set_attr "type" "fp")])
5889 (define_insn "floordf2"
5890 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5891 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5892 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5894 [(set_attr "type" "fp")])
5896 (define_insn "floorsf2"
5897 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5898 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5899 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5901 [(set_attr "type" "fp")])
5903 (define_insn "rounddf2"
5904 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5905 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5906 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5908 [(set_attr "type" "fp")])
5910 (define_insn "roundsf2"
5911 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5912 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5913 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5915 [(set_attr "type" "fp")])
5917 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5918 (define_insn "stfiwx"
5919 [(set (match_operand:SI 0 "memory_operand" "=Z")
5920 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5924 [(set_attr "type" "fpstore")])
5926 (define_expand "floatsisf2"
5927 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5928 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5929 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5932 (define_insn "floatdidf2"
5933 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5934 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5935 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5937 [(set_attr "type" "fp")])
5939 (define_insn_and_split "floatsidf_ppc64"
5940 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5941 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5942 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5943 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5944 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5945 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5948 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5949 (set (match_dup 2) (match_dup 3))
5950 (set (match_dup 4) (match_dup 2))
5951 (set (match_dup 0) (float:DF (match_dup 4)))]
5954 (define_insn_and_split "floatunssidf_ppc64"
5955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5956 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5957 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5958 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5959 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5960 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5963 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5964 (set (match_dup 2) (match_dup 3))
5965 (set (match_dup 4) (match_dup 2))
5966 (set (match_dup 0) (float:DF (match_dup 4)))]
5969 (define_insn "fix_truncdfdi2"
5970 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5971 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5972 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5974 [(set_attr "type" "fp")])
5976 (define_expand "floatdisf2"
5977 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5978 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5979 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5982 rtx val = operands[1];
5983 if (!flag_unsafe_math_optimizations)
5985 rtx label = gen_label_rtx ();
5986 val = gen_reg_rtx (DImode);
5987 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5990 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5994 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5995 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5996 ;; from double rounding.
5997 (define_insn_and_split "floatdisf2_internal1"
5998 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5999 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
6000 (clobber (match_scratch:DF 2 "=f"))]
6001 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6003 "&& reload_completed"
6005 (float:DF (match_dup 1)))
6007 (float_truncate:SF (match_dup 2)))]
6010 ;; Twiddles bits to avoid double rounding.
6011 ;; Bits that might be truncated when converting to DFmode are replaced
6012 ;; by a bit that won't be lost at that stage, but is below the SFmode
6013 ;; rounding position.
6014 (define_expand "floatdisf2_internal2"
6015 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6017 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6019 (clobber (scratch:CC))])
6020 (set (match_dup 3) (plus:DI (match_dup 3)
6022 (set (match_dup 0) (plus:DI (match_dup 0)
6024 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6026 (set (match_dup 0) (ior:DI (match_dup 0)
6028 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6030 (clobber (scratch:CC))])
6031 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6032 (label_ref (match_operand:DI 2 "" ""))
6034 (set (match_dup 0) (match_dup 1))]
6035 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6038 operands[3] = gen_reg_rtx (DImode);
6039 operands[4] = gen_reg_rtx (CCUNSmode);
6042 ;; Define the DImode operations that can be done in a small number
6043 ;; of instructions. The & constraints are to prevent the register
6044 ;; allocator from allocating registers that overlap with the inputs
6045 ;; (for example, having an input in 7,8 and an output in 6,7). We
6046 ;; also allow for the output being the same as one of the inputs.
6048 (define_insn "*adddi3_noppc64"
6049 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6050 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6051 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6052 "! TARGET_POWERPC64"
6055 if (WORDS_BIG_ENDIAN)
6056 return (GET_CODE (operands[2])) != CONST_INT
6057 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6058 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6060 return (GET_CODE (operands[2])) != CONST_INT
6061 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6062 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6064 [(set_attr "type" "two")
6065 (set_attr "length" "8")])
6067 (define_insn "*subdi3_noppc64"
6068 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6069 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6070 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6071 "! TARGET_POWERPC64"
6074 if (WORDS_BIG_ENDIAN)
6075 return (GET_CODE (operands[1]) != CONST_INT)
6076 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6077 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6079 return (GET_CODE (operands[1]) != CONST_INT)
6080 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6081 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6083 [(set_attr "type" "two")
6084 (set_attr "length" "8")])
6086 (define_insn "*negdi2_noppc64"
6087 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6088 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6089 "! TARGET_POWERPC64"
6092 return (WORDS_BIG_ENDIAN)
6093 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6094 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6096 [(set_attr "type" "two")
6097 (set_attr "length" "8")])
6099 (define_expand "mulsidi3"
6100 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6101 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6102 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6103 "! TARGET_POWERPC64"
6106 if (! TARGET_POWER && ! TARGET_POWERPC)
6108 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6109 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6110 emit_insn (gen_mull_call ());
6111 if (WORDS_BIG_ENDIAN)
6112 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6115 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6116 gen_rtx_REG (SImode, 3));
6117 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6118 gen_rtx_REG (SImode, 4));
6122 else if (TARGET_POWER)
6124 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6129 (define_insn "mulsidi3_mq"
6130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6131 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6132 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6133 (clobber (match_scratch:SI 3 "=q"))]
6135 "mul %0,%1,%2\;mfmq %L0"
6136 [(set_attr "type" "imul")
6137 (set_attr "length" "8")])
6139 (define_insn "*mulsidi3_no_mq"
6140 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6141 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6142 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6143 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6146 return (WORDS_BIG_ENDIAN)
6147 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6148 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6150 [(set_attr "type" "imul")
6151 (set_attr "length" "8")])
6154 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6155 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6156 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6157 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6160 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6161 (sign_extend:DI (match_dup 2)))
6164 (mult:SI (match_dup 1)
6168 int endian = (WORDS_BIG_ENDIAN == 0);
6169 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6170 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6173 (define_expand "umulsidi3"
6174 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6175 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6176 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6177 "TARGET_POWERPC && ! TARGET_POWERPC64"
6182 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6187 (define_insn "umulsidi3_mq"
6188 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6189 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6190 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6191 (clobber (match_scratch:SI 3 "=q"))]
6192 "TARGET_POWERPC && TARGET_POWER"
6195 return (WORDS_BIG_ENDIAN)
6196 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6197 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6199 [(set_attr "type" "imul")
6200 (set_attr "length" "8")])
6202 (define_insn "*umulsidi3_no_mq"
6203 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6204 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6205 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6206 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6209 return (WORDS_BIG_ENDIAN)
6210 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6211 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6213 [(set_attr "type" "imul")
6214 (set_attr "length" "8")])
6217 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6218 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6219 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6220 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6223 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6224 (zero_extend:DI (match_dup 2)))
6227 (mult:SI (match_dup 1)
6231 int endian = (WORDS_BIG_ENDIAN == 0);
6232 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6233 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6236 (define_expand "smulsi3_highpart"
6237 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6239 (lshiftrt:DI (mult:DI (sign_extend:DI
6240 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6242 (match_operand:SI 2 "gpc_reg_operand" "r")))
6247 if (! TARGET_POWER && ! TARGET_POWERPC)
6249 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6250 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6251 emit_insn (gen_mulh_call ());
6252 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6255 else if (TARGET_POWER)
6257 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6262 (define_insn "smulsi3_highpart_mq"
6263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6265 (lshiftrt:DI (mult:DI (sign_extend:DI
6266 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6268 (match_operand:SI 2 "gpc_reg_operand" "r")))
6270 (clobber (match_scratch:SI 3 "=q"))]
6273 [(set_attr "type" "imul")])
6275 (define_insn "*smulsi3_highpart_no_mq"
6276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6278 (lshiftrt:DI (mult:DI (sign_extend:DI
6279 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6281 (match_operand:SI 2 "gpc_reg_operand" "r")))
6283 "TARGET_POWERPC && ! TARGET_POWER"
6285 [(set_attr "type" "imul")])
6287 (define_expand "umulsi3_highpart"
6288 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6290 (lshiftrt:DI (mult:DI (zero_extend:DI
6291 (match_operand:SI 1 "gpc_reg_operand" ""))
6293 (match_operand:SI 2 "gpc_reg_operand" "")))
6300 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6305 (define_insn "umulsi3_highpart_mq"
6306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6308 (lshiftrt:DI (mult:DI (zero_extend:DI
6309 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6311 (match_operand:SI 2 "gpc_reg_operand" "r")))
6313 (clobber (match_scratch:SI 3 "=q"))]
6314 "TARGET_POWERPC && TARGET_POWER"
6316 [(set_attr "type" "imul")])
6318 (define_insn "*umulsi3_highpart_no_mq"
6319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6321 (lshiftrt:DI (mult:DI (zero_extend:DI
6322 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6324 (match_operand:SI 2 "gpc_reg_operand" "r")))
6326 "TARGET_POWERPC && ! TARGET_POWER"
6328 [(set_attr "type" "imul")])
6330 ;; If operands 0 and 2 are in the same register, we have a problem. But
6331 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6332 ;; why we have the strange constraints below.
6333 (define_insn "ashldi3_power"
6334 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6335 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6336 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6337 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6340 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6341 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6342 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6343 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6344 [(set_attr "length" "8")])
6346 (define_insn "lshrdi3_power"
6347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6348 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6349 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6350 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6353 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6354 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6355 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6356 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6357 [(set_attr "length" "8")])
6359 ;; Shift by a variable amount is too complex to be worth open-coding. We
6360 ;; just handle shifts by constants.
6361 (define_insn "ashrdi3_power"
6362 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6363 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6364 (match_operand:SI 2 "const_int_operand" "M,i")))
6365 (clobber (match_scratch:SI 3 "=X,q"))]
6368 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6369 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6370 [(set_attr "length" "8")])
6372 (define_insn "ashrdi3_no_power"
6373 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6374 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6375 (match_operand:SI 2 "const_int_operand" "M,i")))]
6376 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6378 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6379 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6380 [(set_attr "type" "two,three")
6381 (set_attr "length" "8,12")])
6383 (define_insn "*ashrdisi3_noppc64"
6384 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6385 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6386 (const_int 32)) 4))]
6387 "TARGET_32BIT && !TARGET_POWERPC64"
6390 if (REGNO (operands[0]) == REGNO (operands[1]))
6393 return \"mr %0,%1\";
6395 [(set_attr "length" "4")])
6398 ;; PowerPC64 DImode operations.
6400 (define_insn_and_split "absdi2"
6401 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6402 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6403 (clobber (match_scratch:DI 2 "=&r,&r"))]
6406 "&& reload_completed"
6407 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6408 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6409 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6412 (define_insn_and_split "*nabsdi2"
6413 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6414 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6415 (clobber (match_scratch:DI 2 "=&r,&r"))]
6418 "&& reload_completed"
6419 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6420 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6421 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6424 (define_insn "muldi3"
6425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6426 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6427 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6433 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6434 (const_string "imul3")
6435 (match_operand:SI 2 "short_cint_operand" "")
6436 (const_string "imul2")]
6437 (const_string "lmul")))])
6439 (define_insn "*muldi3_internal1"
6440 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6441 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6442 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6444 (clobber (match_scratch:DI 3 "=r,r"))]
6449 [(set_attr "type" "lmul_compare")
6450 (set_attr "length" "4,8")])
6453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6454 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6455 (match_operand:DI 2 "gpc_reg_operand" ""))
6457 (clobber (match_scratch:DI 3 ""))]
6458 "TARGET_POWERPC64 && reload_completed"
6460 (mult:DI (match_dup 1) (match_dup 2)))
6462 (compare:CC (match_dup 3)
6466 (define_insn "*muldi3_internal2"
6467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6468 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6469 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6471 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6472 (mult:DI (match_dup 1) (match_dup 2)))]
6477 [(set_attr "type" "lmul_compare")
6478 (set_attr "length" "4,8")])
6481 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6482 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6483 (match_operand:DI 2 "gpc_reg_operand" ""))
6485 (set (match_operand:DI 0 "gpc_reg_operand" "")
6486 (mult:DI (match_dup 1) (match_dup 2)))]
6487 "TARGET_POWERPC64 && reload_completed"
6489 (mult:DI (match_dup 1) (match_dup 2)))
6491 (compare:CC (match_dup 0)
6495 (define_insn "smuldi3_highpart"
6496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6498 (lshiftrt:TI (mult:TI (sign_extend:TI
6499 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6501 (match_operand:DI 2 "gpc_reg_operand" "r")))
6505 [(set_attr "type" "lmul")])
6507 (define_insn "umuldi3_highpart"
6508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6510 (lshiftrt:TI (mult:TI (zero_extend:TI
6511 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6513 (match_operand:DI 2 "gpc_reg_operand" "r")))
6517 [(set_attr "type" "lmul")])
6519 (define_insn "rotldi3"
6520 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6521 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6522 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6524 "rld%I2cl %0,%1,%H2,0")
6526 (define_insn "*rotldi3_internal2"
6527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6528 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6529 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6531 (clobber (match_scratch:DI 3 "=r,r"))]
6534 rld%I2cl. %3,%1,%H2,0
6536 [(set_attr "type" "delayed_compare")
6537 (set_attr "length" "4,8")])
6540 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6541 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6542 (match_operand:DI 2 "reg_or_cint_operand" ""))
6544 (clobber (match_scratch:DI 3 ""))]
6545 "TARGET_POWERPC64 && reload_completed"
6547 (rotate:DI (match_dup 1) (match_dup 2)))
6549 (compare:CC (match_dup 3)
6553 (define_insn "*rotldi3_internal3"
6554 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6555 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6556 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6558 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6559 (rotate:DI (match_dup 1) (match_dup 2)))]
6562 rld%I2cl. %0,%1,%H2,0
6564 [(set_attr "type" "delayed_compare")
6565 (set_attr "length" "4,8")])
6568 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6569 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6570 (match_operand:DI 2 "reg_or_cint_operand" ""))
6572 (set (match_operand:DI 0 "gpc_reg_operand" "")
6573 (rotate:DI (match_dup 1) (match_dup 2)))]
6574 "TARGET_POWERPC64 && reload_completed"
6576 (rotate:DI (match_dup 1) (match_dup 2)))
6578 (compare:CC (match_dup 0)
6582 (define_insn "*rotldi3_internal4"
6583 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6584 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6585 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6586 (match_operand:DI 3 "mask64_operand" "n")))]
6588 "rld%I2c%B3 %0,%1,%H2,%S3")
6590 (define_insn "*rotldi3_internal5"
6591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6593 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6594 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6595 (match_operand:DI 3 "mask64_operand" "n,n"))
6597 (clobber (match_scratch:DI 4 "=r,r"))]
6600 rld%I2c%B3. %4,%1,%H2,%S3
6602 [(set_attr "type" "delayed_compare")
6603 (set_attr "length" "4,8")])
6606 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6608 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6609 (match_operand:DI 2 "reg_or_cint_operand" ""))
6610 (match_operand:DI 3 "mask64_operand" ""))
6612 (clobber (match_scratch:DI 4 ""))]
6613 "TARGET_POWERPC64 && reload_completed"
6615 (and:DI (rotate:DI (match_dup 1)
6619 (compare:CC (match_dup 4)
6623 (define_insn "*rotldi3_internal6"
6624 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6626 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6627 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6628 (match_operand:DI 3 "mask64_operand" "n,n"))
6630 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6631 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6634 rld%I2c%B3. %0,%1,%H2,%S3
6636 [(set_attr "type" "delayed_compare")
6637 (set_attr "length" "4,8")])
6640 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6642 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6643 (match_operand:DI 2 "reg_or_cint_operand" ""))
6644 (match_operand:DI 3 "mask64_operand" ""))
6646 (set (match_operand:DI 0 "gpc_reg_operand" "")
6647 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6648 "TARGET_POWERPC64 && reload_completed"
6650 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6652 (compare:CC (match_dup 0)
6656 (define_insn "*rotldi3_internal7"
6657 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6660 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6661 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6663 "rld%I2cl %0,%1,%H2,56")
6665 (define_insn "*rotldi3_internal8"
6666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6667 (compare:CC (zero_extend:DI
6669 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6670 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6672 (clobber (match_scratch:DI 3 "=r,r"))]
6675 rld%I2cl. %3,%1,%H2,56
6677 [(set_attr "type" "delayed_compare")
6678 (set_attr "length" "4,8")])
6681 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6682 (compare:CC (zero_extend:DI
6684 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6685 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6687 (clobber (match_scratch:DI 3 ""))]
6688 "TARGET_POWERPC64 && reload_completed"
6690 (zero_extend:DI (subreg:QI
6691 (rotate:DI (match_dup 1)
6694 (compare:CC (match_dup 3)
6698 (define_insn "*rotldi3_internal9"
6699 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6700 (compare:CC (zero_extend:DI
6702 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6703 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6705 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6706 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6709 rld%I2cl. %0,%1,%H2,56
6711 [(set_attr "type" "delayed_compare")
6712 (set_attr "length" "4,8")])
6715 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6716 (compare:CC (zero_extend:DI
6718 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6719 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6721 (set (match_operand:DI 0 "gpc_reg_operand" "")
6722 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6723 "TARGET_POWERPC64 && reload_completed"
6725 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6727 (compare:CC (match_dup 0)
6731 (define_insn "*rotldi3_internal10"
6732 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6735 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6736 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6738 "rld%I2cl %0,%1,%H2,48")
6740 (define_insn "*rotldi3_internal11"
6741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6742 (compare:CC (zero_extend:DI
6744 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6745 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6747 (clobber (match_scratch:DI 3 "=r,r"))]
6750 rld%I2cl. %3,%1,%H2,48
6752 [(set_attr "type" "delayed_compare")
6753 (set_attr "length" "4,8")])
6756 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6757 (compare:CC (zero_extend:DI
6759 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6760 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6762 (clobber (match_scratch:DI 3 ""))]
6763 "TARGET_POWERPC64 && reload_completed"
6765 (zero_extend:DI (subreg:HI
6766 (rotate:DI (match_dup 1)
6769 (compare:CC (match_dup 3)
6773 (define_insn "*rotldi3_internal12"
6774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6775 (compare:CC (zero_extend:DI
6777 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6778 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6780 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6781 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6784 rld%I2cl. %0,%1,%H2,48
6786 [(set_attr "type" "delayed_compare")
6787 (set_attr "length" "4,8")])
6790 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6791 (compare:CC (zero_extend:DI
6793 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6794 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6796 (set (match_operand:DI 0 "gpc_reg_operand" "")
6797 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6798 "TARGET_POWERPC64 && reload_completed"
6800 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6802 (compare:CC (match_dup 0)
6806 (define_insn "*rotldi3_internal13"
6807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6810 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6811 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6813 "rld%I2cl %0,%1,%H2,32")
6815 (define_insn "*rotldi3_internal14"
6816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6817 (compare:CC (zero_extend:DI
6819 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6820 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6822 (clobber (match_scratch:DI 3 "=r,r"))]
6825 rld%I2cl. %3,%1,%H2,32
6827 [(set_attr "type" "delayed_compare")
6828 (set_attr "length" "4,8")])
6831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6832 (compare:CC (zero_extend:DI
6834 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6835 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6837 (clobber (match_scratch:DI 3 ""))]
6838 "TARGET_POWERPC64 && reload_completed"
6840 (zero_extend:DI (subreg:SI
6841 (rotate:DI (match_dup 1)
6844 (compare:CC (match_dup 3)
6848 (define_insn "*rotldi3_internal15"
6849 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6850 (compare:CC (zero_extend:DI
6852 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6853 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6855 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6856 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6859 rld%I2cl. %0,%1,%H2,32
6861 [(set_attr "type" "delayed_compare")
6862 (set_attr "length" "4,8")])
6865 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6866 (compare:CC (zero_extend:DI
6868 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6869 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6871 (set (match_operand:DI 0 "gpc_reg_operand" "")
6872 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6873 "TARGET_POWERPC64 && reload_completed"
6875 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6877 (compare:CC (match_dup 0)
6881 (define_expand "ashldi3"
6882 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6883 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6884 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6885 "TARGET_POWERPC64 || TARGET_POWER"
6888 if (TARGET_POWERPC64)
6890 else if (TARGET_POWER)
6892 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6899 (define_insn "*ashldi3_internal1"
6900 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6901 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6902 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6906 (define_insn "*ashldi3_internal2"
6907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6908 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6909 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6911 (clobber (match_scratch:DI 3 "=r,r"))]
6916 [(set_attr "type" "delayed_compare")
6917 (set_attr "length" "4,8")])
6920 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6921 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6922 (match_operand:SI 2 "reg_or_cint_operand" ""))
6924 (clobber (match_scratch:DI 3 ""))]
6925 "TARGET_POWERPC64 && reload_completed"
6927 (ashift:DI (match_dup 1) (match_dup 2)))
6929 (compare:CC (match_dup 3)
6933 (define_insn "*ashldi3_internal3"
6934 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6935 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6936 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6938 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6939 (ashift:DI (match_dup 1) (match_dup 2)))]
6944 [(set_attr "type" "delayed_compare")
6945 (set_attr "length" "4,8")])
6948 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6949 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6950 (match_operand:SI 2 "reg_or_cint_operand" ""))
6952 (set (match_operand:DI 0 "gpc_reg_operand" "")
6953 (ashift:DI (match_dup 1) (match_dup 2)))]
6954 "TARGET_POWERPC64 && reload_completed"
6956 (ashift:DI (match_dup 1) (match_dup 2)))
6958 (compare:CC (match_dup 0)
6962 (define_insn "*ashldi3_internal4"
6963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6964 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6965 (match_operand:SI 2 "const_int_operand" "i"))
6966 (match_operand:DI 3 "const_int_operand" "n")))]
6967 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6968 "rldic %0,%1,%H2,%W3")
6970 (define_insn "ashldi3_internal5"
6971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6973 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6974 (match_operand:SI 2 "const_int_operand" "i,i"))
6975 (match_operand:DI 3 "const_int_operand" "n,n"))
6977 (clobber (match_scratch:DI 4 "=r,r"))]
6978 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6980 rldic. %4,%1,%H2,%W3
6982 [(set_attr "type" "compare")
6983 (set_attr "length" "4,8")])
6986 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6988 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6989 (match_operand:SI 2 "const_int_operand" ""))
6990 (match_operand:DI 3 "const_int_operand" ""))
6992 (clobber (match_scratch:DI 4 ""))]
6993 "TARGET_POWERPC64 && reload_completed
6994 && includes_rldic_lshift_p (operands[2], operands[3])"
6996 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6999 (compare:CC (match_dup 4)
7003 (define_insn "*ashldi3_internal6"
7004 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7006 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7007 (match_operand:SI 2 "const_int_operand" "i,i"))
7008 (match_operand:DI 3 "const_int_operand" "n,n"))
7010 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7011 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7012 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7014 rldic. %0,%1,%H2,%W3
7016 [(set_attr "type" "compare")
7017 (set_attr "length" "4,8")])
7020 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7022 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7023 (match_operand:SI 2 "const_int_operand" ""))
7024 (match_operand:DI 3 "const_int_operand" ""))
7026 (set (match_operand:DI 0 "gpc_reg_operand" "")
7027 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7028 "TARGET_POWERPC64 && reload_completed
7029 && includes_rldic_lshift_p (operands[2], operands[3])"
7031 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7034 (compare:CC (match_dup 0)
7038 (define_insn "*ashldi3_internal7"
7039 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7040 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7041 (match_operand:SI 2 "const_int_operand" "i"))
7042 (match_operand:DI 3 "mask64_operand" "n")))]
7043 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7044 "rldicr %0,%1,%H2,%S3")
7046 (define_insn "ashldi3_internal8"
7047 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7049 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7050 (match_operand:SI 2 "const_int_operand" "i,i"))
7051 (match_operand:DI 3 "mask64_operand" "n,n"))
7053 (clobber (match_scratch:DI 4 "=r,r"))]
7054 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7056 rldicr. %4,%1,%H2,%S3
7058 [(set_attr "type" "compare")
7059 (set_attr "length" "4,8")])
7062 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7064 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7065 (match_operand:SI 2 "const_int_operand" ""))
7066 (match_operand:DI 3 "mask64_operand" ""))
7068 (clobber (match_scratch:DI 4 ""))]
7069 "TARGET_POWERPC64 && reload_completed
7070 && includes_rldicr_lshift_p (operands[2], operands[3])"
7072 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7075 (compare:CC (match_dup 4)
7079 (define_insn "*ashldi3_internal9"
7080 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7082 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7083 (match_operand:SI 2 "const_int_operand" "i,i"))
7084 (match_operand:DI 3 "mask64_operand" "n,n"))
7086 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7087 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7088 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7090 rldicr. %0,%1,%H2,%S3
7092 [(set_attr "type" "compare")
7093 (set_attr "length" "4,8")])
7096 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7098 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7099 (match_operand:SI 2 "const_int_operand" ""))
7100 (match_operand:DI 3 "mask64_operand" ""))
7102 (set (match_operand:DI 0 "gpc_reg_operand" "")
7103 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7104 "TARGET_POWERPC64 && reload_completed
7105 && includes_rldicr_lshift_p (operands[2], operands[3])"
7107 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7110 (compare:CC (match_dup 0)
7114 (define_expand "lshrdi3"
7115 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7116 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7117 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7118 "TARGET_POWERPC64 || TARGET_POWER"
7121 if (TARGET_POWERPC64)
7123 else if (TARGET_POWER)
7125 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7132 (define_insn "*lshrdi3_internal1"
7133 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7134 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7135 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7139 (define_insn "*lshrdi3_internal2"
7140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7141 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7142 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7144 (clobber (match_scratch:DI 3 "=r,r"))]
7149 [(set_attr "type" "delayed_compare")
7150 (set_attr "length" "4,8")])
7153 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7154 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7155 (match_operand:SI 2 "reg_or_cint_operand" ""))
7157 (clobber (match_scratch:DI 3 ""))]
7158 "TARGET_POWERPC64 && reload_completed"
7160 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7162 (compare:CC (match_dup 3)
7166 (define_insn "*lshrdi3_internal3"
7167 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7168 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7169 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7171 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7172 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7177 [(set_attr "type" "delayed_compare")
7178 (set_attr "length" "4,8")])
7181 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7182 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7183 (match_operand:SI 2 "reg_or_cint_operand" ""))
7185 (set (match_operand:DI 0 "gpc_reg_operand" "")
7186 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7187 "TARGET_POWERPC64 && reload_completed"
7189 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7191 (compare:CC (match_dup 0)
7195 (define_expand "ashrdi3"
7196 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7197 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7198 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7202 if (TARGET_POWERPC64)
7204 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7206 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7209 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7210 && WORDS_BIG_ENDIAN)
7212 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7219 (define_insn "*ashrdi3_internal1"
7220 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7221 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7222 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7224 "srad%I2 %0,%1,%H2")
7226 (define_insn "*ashrdi3_internal2"
7227 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7228 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7229 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7231 (clobber (match_scratch:DI 3 "=r,r"))]
7236 [(set_attr "type" "delayed_compare")
7237 (set_attr "length" "4,8")])
7240 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7241 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7242 (match_operand:SI 2 "reg_or_cint_operand" ""))
7244 (clobber (match_scratch:DI 3 ""))]
7245 "TARGET_POWERPC64 && reload_completed"
7247 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7249 (compare:CC (match_dup 3)
7253 (define_insn "*ashrdi3_internal3"
7254 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7255 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7256 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7258 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7259 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7264 [(set_attr "type" "delayed_compare")
7265 (set_attr "length" "4,8")])
7268 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7269 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7270 (match_operand:SI 2 "reg_or_cint_operand" ""))
7272 (set (match_operand:DI 0 "gpc_reg_operand" "")
7273 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7274 "TARGET_POWERPC64 && reload_completed"
7276 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7278 (compare:CC (match_dup 0)
7282 (define_insn "anddi3"
7283 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7284 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7285 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7286 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7290 rldic%B2 %0,%1,0,%S2
7291 rlwinm %0,%1,0,%m2,%M2
7295 [(set_attr "type" "*,*,*,compare,compare,*")
7296 (set_attr "length" "4,4,4,4,4,8")])
7299 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7300 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7301 (match_operand:DI 2 "mask64_2_operand" "")))
7302 (clobber (match_scratch:CC 3 ""))]
7304 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7305 && !mask_operand (operands[2], DImode)
7306 && !mask64_operand (operands[2], DImode)"
7308 (and:DI (rotate:DI (match_dup 1)
7312 (and:DI (rotate:DI (match_dup 0)
7316 build_mask64_2_operands (operands[2], &operands[4]);
7319 (define_insn "*anddi3_internal2"
7320 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7321 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7322 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7324 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7325 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7329 rldic%B2. %3,%1,0,%S2
7330 rlwinm. %3,%1,0,%m2,%M2
7340 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7341 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7344 [(set (match_operand:CC 0 "cc_reg_operand" "")
7345 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7346 (match_operand:DI 2 "mask64_2_operand" ""))
7348 (clobber (match_scratch:DI 3 ""))
7349 (clobber (match_scratch:CC 4 ""))]
7350 "TARGET_64BIT && reload_completed
7351 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7352 && !mask_operand (operands[2], DImode)
7353 && !mask64_operand (operands[2], DImode)"
7355 (and:DI (rotate:DI (match_dup 1)
7358 (parallel [(set (match_dup 0)
7359 (compare:CC (and:DI (rotate:DI (match_dup 3)
7363 (clobber (match_dup 3))])]
7366 build_mask64_2_operands (operands[2], &operands[5]);
7369 (define_insn "*anddi3_internal3"
7370 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7371 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7372 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7374 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7375 (and:DI (match_dup 1) (match_dup 2)))
7376 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7380 rldic%B2. %0,%1,0,%S2
7381 rlwinm. %0,%1,0,%m2,%M2
7391 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7392 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7395 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7396 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7397 (match_operand:DI 2 "and64_2_operand" ""))
7399 (set (match_operand:DI 0 "gpc_reg_operand" "")
7400 (and:DI (match_dup 1) (match_dup 2)))
7401 (clobber (match_scratch:CC 4 ""))]
7402 "TARGET_64BIT && reload_completed"
7403 [(parallel [(set (match_dup 0)
7404 (and:DI (match_dup 1) (match_dup 2)))
7405 (clobber (match_dup 4))])
7407 (compare:CC (match_dup 0)
7412 [(set (match_operand:CC 3 "cc_reg_operand" "")
7413 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7414 (match_operand:DI 2 "mask64_2_operand" ""))
7416 (set (match_operand:DI 0 "gpc_reg_operand" "")
7417 (and:DI (match_dup 1) (match_dup 2)))
7418 (clobber (match_scratch:CC 4 ""))]
7419 "TARGET_64BIT && reload_completed
7420 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7421 && !mask_operand (operands[2], DImode)
7422 && !mask64_operand (operands[2], DImode)"
7424 (and:DI (rotate:DI (match_dup 1)
7427 (parallel [(set (match_dup 3)
7428 (compare:CC (and:DI (rotate:DI (match_dup 0)
7433 (and:DI (rotate:DI (match_dup 0)
7438 build_mask64_2_operands (operands[2], &operands[5]);
7441 (define_expand "iordi3"
7442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7443 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7444 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7448 if (non_logical_cint_operand (operands[2], DImode))
7450 HOST_WIDE_INT value;
7451 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7452 ? operands[0] : gen_reg_rtx (DImode));
7454 if (GET_CODE (operands[2]) == CONST_INT)
7456 value = INTVAL (operands[2]);
7457 emit_insn (gen_iordi3 (tmp, operands[1],
7458 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7462 value = CONST_DOUBLE_LOW (operands[2]);
7463 emit_insn (gen_iordi3 (tmp, operands[1],
7464 immed_double_const (value
7465 & (~ (HOST_WIDE_INT) 0xffff),
7469 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7474 (define_expand "xordi3"
7475 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7476 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7477 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7481 if (non_logical_cint_operand (operands[2], DImode))
7483 HOST_WIDE_INT value;
7484 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7485 ? operands[0] : gen_reg_rtx (DImode));
7487 if (GET_CODE (operands[2]) == CONST_INT)
7489 value = INTVAL (operands[2]);
7490 emit_insn (gen_xordi3 (tmp, operands[1],
7491 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7495 value = CONST_DOUBLE_LOW (operands[2]);
7496 emit_insn (gen_xordi3 (tmp, operands[1],
7497 immed_double_const (value
7498 & (~ (HOST_WIDE_INT) 0xffff),
7502 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7507 (define_insn "*booldi3_internal1"
7508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7509 (match_operator:DI 3 "boolean_or_operator"
7510 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7511 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7518 (define_insn "*booldi3_internal2"
7519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7520 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7521 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7522 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7524 (clobber (match_scratch:DI 3 "=r,r"))]
7529 [(set_attr "type" "compare")
7530 (set_attr "length" "4,8")])
7533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7534 (compare:CC (match_operator:DI 4 "boolean_operator"
7535 [(match_operand:DI 1 "gpc_reg_operand" "")
7536 (match_operand:DI 2 "gpc_reg_operand" "")])
7538 (clobber (match_scratch:DI 3 ""))]
7539 "TARGET_POWERPC64 && reload_completed"
7540 [(set (match_dup 3) (match_dup 4))
7542 (compare:CC (match_dup 3)
7546 (define_insn "*booldi3_internal3"
7547 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7548 (compare:CC (match_operator:DI 4 "boolean_operator"
7549 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7550 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7552 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7558 [(set_attr "type" "compare")
7559 (set_attr "length" "4,8")])
7562 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7563 (compare:CC (match_operator:DI 4 "boolean_operator"
7564 [(match_operand:DI 1 "gpc_reg_operand" "")
7565 (match_operand:DI 2 "gpc_reg_operand" "")])
7567 (set (match_operand:DI 0 "gpc_reg_operand" "")
7569 "TARGET_POWERPC64 && reload_completed"
7570 [(set (match_dup 0) (match_dup 4))
7572 (compare:CC (match_dup 0)
7576 ;; Split a logical operation that we can't do in one insn into two insns,
7577 ;; each of which does one 16-bit part. This is used by combine.
7580 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7581 (match_operator:DI 3 "boolean_or_operator"
7582 [(match_operand:DI 1 "gpc_reg_operand" "")
7583 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7585 [(set (match_dup 0) (match_dup 4))
7586 (set (match_dup 0) (match_dup 5))]
7591 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7593 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7594 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7596 i4 = GEN_INT (value & 0xffff);
7600 i3 = GEN_INT (INTVAL (operands[2])
7601 & (~ (HOST_WIDE_INT) 0xffff));
7602 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7604 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7606 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7610 (define_insn "*boolcdi3_internal1"
7611 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7612 (match_operator:DI 3 "boolean_operator"
7613 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7614 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7618 (define_insn "*boolcdi3_internal2"
7619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7620 (compare:CC (match_operator:DI 4 "boolean_operator"
7621 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7622 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7624 (clobber (match_scratch:DI 3 "=r,r"))]
7629 [(set_attr "type" "compare")
7630 (set_attr "length" "4,8")])
7633 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7634 (compare:CC (match_operator:DI 4 "boolean_operator"
7635 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7636 (match_operand:DI 2 "gpc_reg_operand" "")])
7638 (clobber (match_scratch:DI 3 ""))]
7639 "TARGET_POWERPC64 && reload_completed"
7640 [(set (match_dup 3) (match_dup 4))
7642 (compare:CC (match_dup 3)
7646 (define_insn "*boolcdi3_internal3"
7647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7648 (compare:CC (match_operator:DI 4 "boolean_operator"
7649 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7650 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7652 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7658 [(set_attr "type" "compare")
7659 (set_attr "length" "4,8")])
7662 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7663 (compare:CC (match_operator:DI 4 "boolean_operator"
7664 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7665 (match_operand:DI 2 "gpc_reg_operand" "")])
7667 (set (match_operand:DI 0 "gpc_reg_operand" "")
7669 "TARGET_POWERPC64 && reload_completed"
7670 [(set (match_dup 0) (match_dup 4))
7672 (compare:CC (match_dup 0)
7676 (define_insn "*boolccdi3_internal1"
7677 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7678 (match_operator:DI 3 "boolean_operator"
7679 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7680 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7684 (define_insn "*boolccdi3_internal2"
7685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7686 (compare:CC (match_operator:DI 4 "boolean_operator"
7687 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7688 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7690 (clobber (match_scratch:DI 3 "=r,r"))]
7695 [(set_attr "type" "compare")
7696 (set_attr "length" "4,8")])
7699 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7700 (compare:CC (match_operator:DI 4 "boolean_operator"
7701 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7702 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7704 (clobber (match_scratch:DI 3 ""))]
7705 "TARGET_POWERPC64 && reload_completed"
7706 [(set (match_dup 3) (match_dup 4))
7708 (compare:CC (match_dup 3)
7712 (define_insn "*boolccdi3_internal3"
7713 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7714 (compare:CC (match_operator:DI 4 "boolean_operator"
7715 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7716 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7718 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7724 [(set_attr "type" "compare")
7725 (set_attr "length" "4,8")])
7728 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7729 (compare:CC (match_operator:DI 4 "boolean_operator"
7730 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7731 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7733 (set (match_operand:DI 0 "gpc_reg_operand" "")
7735 "TARGET_POWERPC64 && reload_completed"
7736 [(set (match_dup 0) (match_dup 4))
7738 (compare:CC (match_dup 0)
7742 ;; Now define ways of moving data around.
7744 ;; Set up a register with a value from the GOT table
7746 (define_expand "movsi_got"
7747 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7748 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7749 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7750 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7753 if (GET_CODE (operands[1]) == CONST)
7755 rtx offset = const0_rtx;
7756 HOST_WIDE_INT value;
7758 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7759 value = INTVAL (offset);
7762 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7763 emit_insn (gen_movsi_got (tmp, operands[1]));
7764 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7769 operands[2] = rs6000_got_register (operands[1]);
7772 (define_insn "*movsi_got_internal"
7773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7774 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7775 (match_operand:SI 2 "gpc_reg_operand" "b")]
7777 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7778 "{l|lwz} %0,%a1@got(%2)"
7779 [(set_attr "type" "load")])
7781 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7782 ;; didn't get allocated to a hard register.
7784 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7785 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7786 (match_operand:SI 2 "memory_operand" "")]
7788 "DEFAULT_ABI == ABI_V4
7790 && (reload_in_progress || reload_completed)"
7791 [(set (match_dup 0) (match_dup 2))
7792 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7796 ;; For SI, we special-case integers that can't be loaded in one insn. We
7797 ;; do the load 16-bits at a time. We could do this by loading from memory,
7798 ;; and this is even supposed to be faster, but it is simpler not to get
7799 ;; integers in the TOC.
7800 (define_insn "movsi_low"
7801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7802 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7803 (match_operand 2 "" ""))))]
7804 "TARGET_MACHO && ! TARGET_64BIT"
7805 "{l|lwz} %0,lo16(%2)(%1)"
7806 [(set_attr "type" "load")
7807 (set_attr "length" "4")])
7809 (define_insn "*movsi_internal1"
7810 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7811 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7812 "gpc_reg_operand (operands[0], SImode)
7813 || gpc_reg_operand (operands[1], SImode)"
7817 {l%U1%X1|lwz%U1%X1} %0,%1
7818 {st%U0%X0|stw%U0%X0} %1,%0
7828 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7829 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7831 ;; Split a load of a large constant into the appropriate two-insn
7835 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7836 (match_operand:SI 1 "const_int_operand" ""))]
7837 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7838 && (INTVAL (operands[1]) & 0xffff) != 0"
7842 (ior:SI (match_dup 0)
7845 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7847 if (tem == operands[0])
7853 (define_insn "*mov<mode>_internal2"
7854 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7855 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7857 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7860 {cmpi|cmp<wd>i} %2,%0,0
7863 [(set_attr "type" "cmp,compare,cmp")
7864 (set_attr "length" "4,4,8")])
7867 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7868 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7870 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7872 [(set (match_dup 0) (match_dup 1))
7874 (compare:CC (match_dup 0)
7878 (define_insn "*movhi_internal"
7879 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7880 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7881 "gpc_reg_operand (operands[0], HImode)
7882 || gpc_reg_operand (operands[1], HImode)"
7892 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7894 (define_expand "mov<mode>"
7895 [(set (match_operand:INT 0 "general_operand" "")
7896 (match_operand:INT 1 "any_operand" ""))]
7898 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7900 (define_insn "*movqi_internal"
7901 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7902 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7903 "gpc_reg_operand (operands[0], QImode)
7904 || gpc_reg_operand (operands[1], QImode)"
7914 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7916 ;; Here is how to move condition codes around. When we store CC data in
7917 ;; an integer register or memory, we store just the high-order 4 bits.
7918 ;; This lets us not shift in the most common case of CR0.
7919 (define_expand "movcc"
7920 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7921 (match_operand:CC 1 "nonimmediate_operand" ""))]
7925 (define_insn "*movcc_internal1"
7926 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
7927 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
7928 "register_operand (operands[0], CCmode)
7929 || register_operand (operands[1], CCmode)"
7933 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7936 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7942 {l%U1%X1|lwz%U1%X1} %0,%1
7943 {st%U0%U1|stw%U0%U1} %1,%0"
7945 (cond [(eq_attr "alternative" "0,3")
7946 (const_string "cr_logical")
7947 (eq_attr "alternative" "1,2")
7948 (const_string "mtcr")
7949 (eq_attr "alternative" "6,7,9")
7950 (const_string "integer")
7951 (eq_attr "alternative" "8")
7952 (const_string "mfjmpr")
7953 (eq_attr "alternative" "10")
7954 (const_string "mtjmpr")
7955 (eq_attr "alternative" "11")
7956 (const_string "load")
7957 (eq_attr "alternative" "12")
7958 (const_string "store")
7959 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7960 (const_string "mfcrf")
7962 (const_string "mfcr")))
7963 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
7965 ;; For floating-point, we normally deal with the floating-point registers
7966 ;; unless -msoft-float is used. The sole exception is that parameter passing
7967 ;; can produce floating-point values in fixed-point registers. Unless the
7968 ;; value is a simple constant or already in memory, we deal with this by
7969 ;; allocating memory and copying the value explicitly via that memory location.
7970 (define_expand "movsf"
7971 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7972 (match_operand:SF 1 "any_operand" ""))]
7974 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7977 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7978 (match_operand:SF 1 "const_double_operand" ""))]
7980 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7981 || (GET_CODE (operands[0]) == SUBREG
7982 && GET_CODE (SUBREG_REG (operands[0])) == REG
7983 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7984 [(set (match_dup 2) (match_dup 3))]
7990 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7991 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7993 if (! TARGET_POWERPC64)
7994 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7996 operands[2] = gen_lowpart (SImode, operands[0]);
7998 operands[3] = gen_int_mode (l, SImode);
8001 (define_insn "*movsf_hardfloat"
8002 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8003 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8004 "(gpc_reg_operand (operands[0], SFmode)
8005 || gpc_reg_operand (operands[1], SFmode))
8006 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8009 {l%U1%X1|lwz%U1%X1} %0,%1
8010 {st%U0%X0|stw%U0%X0} %1,%0
8020 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8021 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8023 (define_insn "*movsf_softfloat"
8024 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8025 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8026 "(gpc_reg_operand (operands[0], SFmode)
8027 || gpc_reg_operand (operands[1], SFmode))
8028 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8034 {l%U1%X1|lwz%U1%X1} %0,%1
8035 {st%U0%X0|stw%U0%X0} %1,%0
8042 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8043 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8046 (define_expand "movdf"
8047 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8048 (match_operand:DF 1 "any_operand" ""))]
8050 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8053 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8054 (match_operand:DF 1 "const_int_operand" ""))]
8055 "! TARGET_POWERPC64 && reload_completed
8056 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8057 || (GET_CODE (operands[0]) == SUBREG
8058 && GET_CODE (SUBREG_REG (operands[0])) == REG
8059 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8060 [(set (match_dup 2) (match_dup 4))
8061 (set (match_dup 3) (match_dup 1))]
8064 int endian = (WORDS_BIG_ENDIAN == 0);
8065 HOST_WIDE_INT value = INTVAL (operands[1]);
8067 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8068 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8069 #if HOST_BITS_PER_WIDE_INT == 32
8070 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8072 operands[4] = GEN_INT (value >> 32);
8073 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8078 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8079 (match_operand:DF 1 "const_double_operand" ""))]
8080 "! TARGET_POWERPC64 && reload_completed
8081 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8082 || (GET_CODE (operands[0]) == SUBREG
8083 && GET_CODE (SUBREG_REG (operands[0])) == REG
8084 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8085 [(set (match_dup 2) (match_dup 4))
8086 (set (match_dup 3) (match_dup 5))]
8089 int endian = (WORDS_BIG_ENDIAN == 0);
8093 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8094 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8096 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8097 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8098 operands[4] = gen_int_mode (l[endian], SImode);
8099 operands[5] = gen_int_mode (l[1 - endian], SImode);
8103 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8104 (match_operand:DF 1 "const_double_operand" ""))]
8105 "TARGET_POWERPC64 && reload_completed
8106 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8107 || (GET_CODE (operands[0]) == SUBREG
8108 && GET_CODE (SUBREG_REG (operands[0])) == REG
8109 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8110 [(set (match_dup 2) (match_dup 3))]
8113 int endian = (WORDS_BIG_ENDIAN == 0);
8116 #if HOST_BITS_PER_WIDE_INT >= 64
8120 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8121 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8123 operands[2] = gen_lowpart (DImode, operands[0]);
8124 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8125 #if HOST_BITS_PER_WIDE_INT >= 64
8126 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8127 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8129 operands[3] = gen_int_mode (val, DImode);
8131 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8135 ;; Don't have reload use general registers to load a constant. First,
8136 ;; it might not work if the output operand is the equivalent of
8137 ;; a non-offsettable memref, but also it is less efficient than loading
8138 ;; the constant into an FP register, since it will probably be used there.
8139 ;; The "??" is a kludge until we can figure out a more reasonable way
8140 ;; of handling these non-offsettable values.
8141 (define_insn "*movdf_hardfloat32"
8142 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8143 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8144 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8145 && (gpc_reg_operand (operands[0], DFmode)
8146 || gpc_reg_operand (operands[1], DFmode))"
8149 switch (which_alternative)
8154 /* We normally copy the low-numbered register first. However, if
8155 the first register operand 0 is the same as the second register
8156 of operand 1, we must copy in the opposite order. */
8157 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8158 return \"mr %L0,%L1\;mr %0,%1\";
8160 return \"mr %0,%1\;mr %L0,%L1\";
8162 if (rs6000_offsettable_memref_p (operands[1])
8163 || (GET_CODE (operands[1]) == MEM
8164 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8165 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8166 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8168 /* If the low-address word is used in the address, we must load
8169 it last. Otherwise, load it first. Note that we cannot have
8170 auto-increment in that case since the address register is
8171 known to be dead. */
8172 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8174 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8176 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8182 addreg = find_addr_reg (XEXP (operands[1], 0));
8183 if (refers_to_regno_p (REGNO (operands[0]),
8184 REGNO (operands[0]) + 1,
8187 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8188 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8189 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8190 return \"{lx|lwzx} %0,%1\";
8194 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8195 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8196 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8197 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8202 if (rs6000_offsettable_memref_p (operands[0])
8203 || (GET_CODE (operands[0]) == MEM
8204 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8205 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8206 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8207 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8212 addreg = find_addr_reg (XEXP (operands[0], 0));
8213 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8214 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8215 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8216 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8220 return \"fmr %0,%1\";
8222 return \"lfd%U1%X1 %0,%1\";
8224 return \"stfd%U0%X0 %1,%0\";
8231 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8232 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8234 (define_insn "*movdf_softfloat32"
8235 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8236 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8237 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8238 && (gpc_reg_operand (operands[0], DFmode)
8239 || gpc_reg_operand (operands[1], DFmode))"
8242 switch (which_alternative)
8247 /* We normally copy the low-numbered register first. However, if
8248 the first register operand 0 is the same as the second register of
8249 operand 1, we must copy in the opposite order. */
8250 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8251 return \"mr %L0,%L1\;mr %0,%1\";
8253 return \"mr %0,%1\;mr %L0,%L1\";
8255 /* If the low-address word is used in the address, we must load
8256 it last. Otherwise, load it first. Note that we cannot have
8257 auto-increment in that case since the address register is
8258 known to be dead. */
8259 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8261 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8263 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8265 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8272 [(set_attr "type" "two,load,store,*,*,*")
8273 (set_attr "length" "8,8,8,8,12,16")])
8275 ; ld/std require word-aligned displacements -> 'Y' constraint.
8276 ; List Y->r and r->Y before r->r for reload.
8277 (define_insn "*movdf_hardfloat64"
8278 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8279 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8280 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8281 && (gpc_reg_operand (operands[0], DFmode)
8282 || gpc_reg_operand (operands[1], DFmode))"
8296 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8297 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8299 (define_insn "*movdf_softfloat64"
8300 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8301 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8302 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8303 && (gpc_reg_operand (operands[0], DFmode)
8304 || gpc_reg_operand (operands[1], DFmode))"
8315 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8316 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8318 (define_expand "movtf"
8319 [(set (match_operand:TF 0 "general_operand" "")
8320 (match_operand:TF 1 "any_operand" ""))]
8321 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8322 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8324 ; It's important to list the o->f and f->o moves before f->f because
8325 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8326 ; which doesn't make progress. Likewise r->Y must be before r->r.
8327 (define_insn_and_split "*movtf_internal"
8328 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8329 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8331 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8332 && (gpc_reg_operand (operands[0], TFmode)
8333 || gpc_reg_operand (operands[1], TFmode))"
8335 "&& reload_completed"
8337 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8338 [(set_attr "length" "8,8,8,20,20,16")])
8340 (define_insn_and_split "*movtf_softfloat"
8341 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,Y,r")
8342 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8344 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8345 && (gpc_reg_operand (operands[0], TFmode)
8346 || gpc_reg_operand (operands[1], TFmode))"
8348 "&& reload_completed"
8350 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8351 [(set_attr "length" "20,20,16")])
8353 (define_expand "extenddftf2"
8354 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8355 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8356 (use (match_dup 2))])]
8358 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8360 operands[2] = CONST0_RTX (DFmode);
8361 /* Generate GOT reference early for SVR4 PIC. */
8362 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8363 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8366 (define_insn_and_split "*extenddftf2_internal"
8367 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8368 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8369 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8371 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8373 "&& reload_completed"
8376 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8377 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8378 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8380 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8385 (define_expand "extendsftf2"
8386 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8387 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8389 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8391 rtx tmp = gen_reg_rtx (DFmode);
8392 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8393 emit_insn (gen_extenddftf2 (operands[0], tmp));
8397 (define_expand "trunctfdf2"
8398 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8399 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8401 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8404 (define_insn_and_split "trunctfdf2_internal1"
8405 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8406 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8407 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8408 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8412 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8415 emit_note (NOTE_INSN_DELETED);
8418 [(set_attr "type" "fp")])
8420 (define_insn "trunctfdf2_internal2"
8421 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8422 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8423 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8424 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8426 [(set_attr "type" "fp")])
8428 (define_insn_and_split "trunctfsf2"
8429 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8430 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8431 (clobber (match_scratch:DF 2 "=f"))]
8433 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8435 "&& reload_completed"
8437 (float_truncate:DF (match_dup 1)))
8439 (float_truncate:SF (match_dup 2)))]
8442 (define_expand "floatsitf2"
8443 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8444 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8446 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8448 rtx tmp = gen_reg_rtx (DFmode);
8449 expand_float (tmp, operands[1], false);
8450 emit_insn (gen_extenddftf2 (operands[0], tmp));
8454 ; fadd, but rounding towards zero.
8455 ; This is probably not the optimal code sequence.
8456 (define_insn "fix_trunc_helper"
8457 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8458 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8459 UNSPEC_FIX_TRUNC_TF))
8460 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8461 "TARGET_HARD_FLOAT && TARGET_FPRS"
8462 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8463 [(set_attr "type" "fp")
8464 (set_attr "length" "20")])
8466 (define_expand "fix_trunctfsi2"
8467 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8468 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8469 (clobber (match_dup 2))
8470 (clobber (match_dup 3))
8471 (clobber (match_dup 4))
8472 (clobber (match_dup 5))])]
8474 && (TARGET_POWER2 || TARGET_POWERPC)
8475 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8477 operands[2] = gen_reg_rtx (DFmode);
8478 operands[3] = gen_reg_rtx (DFmode);
8479 operands[4] = gen_reg_rtx (DImode);
8480 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8483 (define_insn_and_split "*fix_trunctfsi2_internal"
8484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8485 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8486 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8487 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8488 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8489 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8491 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8493 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8497 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8499 gcc_assert (MEM_P (operands[5]));
8500 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8502 emit_insn (gen_fctiwz (operands[4], operands[2]));
8503 emit_move_insn (operands[5], operands[4]);
8504 emit_move_insn (operands[0], lowword);
8508 (define_insn "negtf2"
8509 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8510 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8512 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8515 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8516 return \"fneg %L0,%L1\;fneg %0,%1\";
8518 return \"fneg %0,%1\;fneg %L0,%L1\";
8520 [(set_attr "type" "fp")
8521 (set_attr "length" "8")])
8523 (define_expand "abstf2"
8524 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8525 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8527 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8530 rtx label = gen_label_rtx ();
8531 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8536 (define_expand "abstf2_internal"
8537 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8538 (match_operand:TF 1 "gpc_reg_operand" "f"))
8539 (set (match_dup 3) (match_dup 5))
8540 (set (match_dup 5) (abs:DF (match_dup 5)))
8541 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8542 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8543 (label_ref (match_operand 2 "" ""))
8545 (set (match_dup 6) (neg:DF (match_dup 6)))]
8547 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8550 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8551 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8552 operands[3] = gen_reg_rtx (DFmode);
8553 operands[4] = gen_reg_rtx (CCFPmode);
8554 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8555 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8558 ;; Next come the multi-word integer load and store and the load and store
8561 ; List r->r after r->"o<>", otherwise reload will try to reload a
8562 ; non-offsettable address by using r->r which won't make progress.
8563 (define_insn "*movdi_internal32"
8564 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8565 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8567 && (gpc_reg_operand (operands[0], DImode)
8568 || gpc_reg_operand (operands[1], DImode))"
8577 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8580 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8581 (match_operand:DI 1 "const_int_operand" ""))]
8582 "! TARGET_POWERPC64 && reload_completed"
8583 [(set (match_dup 2) (match_dup 4))
8584 (set (match_dup 3) (match_dup 1))]
8587 HOST_WIDE_INT value = INTVAL (operands[1]);
8588 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8590 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8592 #if HOST_BITS_PER_WIDE_INT == 32
8593 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8595 operands[4] = GEN_INT (value >> 32);
8596 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8601 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8602 (match_operand:DI 1 "input_operand" ""))]
8603 "reload_completed && !TARGET_POWERPC64
8604 && gpr_or_gpr_p (operands[0], operands[1])"
8606 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8608 (define_insn "*movdi_internal64"
8609 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8610 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8612 && (gpc_reg_operand (operands[0], DImode)
8613 || gpc_reg_operand (operands[1], DImode))"
8628 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8629 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8631 ;; immediate value valid for a single instruction hiding in a const_double
8633 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8634 (match_operand:DI 1 "const_double_operand" "F"))]
8635 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8636 && GET_CODE (operands[1]) == CONST_DOUBLE
8637 && num_insns_constant (operands[1], DImode) == 1"
8640 return ((unsigned HOST_WIDE_INT)
8641 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8642 ? \"li %0,%1\" : \"lis %0,%v1\";
8645 ;; Generate all one-bits and clear left or right.
8646 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8648 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8649 (match_operand:DI 1 "mask64_operand" ""))]
8650 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8651 [(set (match_dup 0) (const_int -1))
8653 (and:DI (rotate:DI (match_dup 0)
8658 ;; Split a load of a large constant into the appropriate five-instruction
8659 ;; sequence. Handle anything in a constant number of insns.
8660 ;; When non-easy constants can go in the TOC, this should use
8661 ;; easy_fp_constant predicate.
8663 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8664 (match_operand:DI 1 "const_int_operand" ""))]
8665 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8666 [(set (match_dup 0) (match_dup 2))
8667 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8669 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8671 if (tem == operands[0])
8678 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8679 (match_operand:DI 1 "const_double_operand" ""))]
8680 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8681 [(set (match_dup 0) (match_dup 2))
8682 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8684 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8686 if (tem == operands[0])
8692 ;; TImode is similar, except that we usually want to compute the address into
8693 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8694 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8696 ;; We say that MQ is clobbered in the last alternative because the first
8697 ;; alternative would never get used otherwise since it would need a reload
8698 ;; while the 2nd alternative would not. We put memory cases first so they
8699 ;; are preferred. Otherwise, we'd try to reload the output instead of
8700 ;; giving the SCRATCH mq.
8702 (define_insn "*movti_power"
8703 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8704 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8705 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8706 "TARGET_POWER && ! TARGET_POWERPC64
8707 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8710 switch (which_alternative)
8717 return \"{stsi|stswi} %1,%P0,16\";
8722 /* If the address is not used in the output, we can use lsi. Otherwise,
8723 fall through to generating four loads. */
8725 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8726 return \"{lsi|lswi} %0,%P1,16\";
8727 /* ... fall through ... */
8733 [(set_attr "type" "store,store,*,load,load,*")])
8735 (define_insn "*movti_string"
8736 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8737 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8738 "! TARGET_POWER && ! TARGET_POWERPC64
8739 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8742 switch (which_alternative)
8748 return \"{stsi|stswi} %1,%P0,16\";
8753 /* If the address is not used in the output, we can use lsi. Otherwise,
8754 fall through to generating four loads. */
8756 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8757 return \"{lsi|lswi} %0,%P1,16\";
8758 /* ... fall through ... */
8764 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8766 (define_insn "*movti_ppc64"
8767 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8768 (match_operand:TI 1 "input_operand" "r,r,m"))]
8769 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8770 || gpc_reg_operand (operands[1], TImode))"
8772 [(set_attr "type" "*,load,store")])
8775 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8776 (match_operand:TI 1 "const_double_operand" ""))]
8778 [(set (match_dup 2) (match_dup 4))
8779 (set (match_dup 3) (match_dup 5))]
8782 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8784 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8786 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8788 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8789 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8791 else if (GET_CODE (operands[1]) == CONST_INT)
8793 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8794 operands[5] = operands[1];
8801 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8802 (match_operand:TI 1 "input_operand" ""))]
8804 && gpr_or_gpr_p (operands[0], operands[1])"
8806 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8808 (define_expand "load_multiple"
8809 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8810 (match_operand:SI 1 "" ""))
8811 (use (match_operand:SI 2 "" ""))])]
8812 "TARGET_STRING && !TARGET_POWERPC64"
8820 /* Support only loading a constant number of fixed-point registers from
8821 memory and only bother with this if more than two; the machine
8822 doesn't support more than eight. */
8823 if (GET_CODE (operands[2]) != CONST_INT
8824 || INTVAL (operands[2]) <= 2
8825 || INTVAL (operands[2]) > 8
8826 || GET_CODE (operands[1]) != MEM
8827 || GET_CODE (operands[0]) != REG
8828 || REGNO (operands[0]) >= 32)
8831 count = INTVAL (operands[2]);
8832 regno = REGNO (operands[0]);
8834 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8835 op1 = replace_equiv_address (operands[1],
8836 force_reg (SImode, XEXP (operands[1], 0)));
8838 for (i = 0; i < count; i++)
8839 XVECEXP (operands[3], 0, i)
8840 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8841 adjust_address_nv (op1, SImode, i * 4));
8844 (define_insn "*ldmsi8"
8845 [(match_parallel 0 "load_multiple_operation"
8846 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8847 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8848 (set (match_operand:SI 3 "gpc_reg_operand" "")
8849 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8850 (set (match_operand:SI 4 "gpc_reg_operand" "")
8851 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8852 (set (match_operand:SI 5 "gpc_reg_operand" "")
8853 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8854 (set (match_operand:SI 6 "gpc_reg_operand" "")
8855 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8856 (set (match_operand:SI 7 "gpc_reg_operand" "")
8857 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8858 (set (match_operand:SI 8 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8860 (set (match_operand:SI 9 "gpc_reg_operand" "")
8861 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8862 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8864 { return rs6000_output_load_multiple (operands); }"
8865 [(set_attr "type" "load_ux")
8866 (set_attr "length" "32")])
8868 (define_insn "*ldmsi7"
8869 [(match_parallel 0 "load_multiple_operation"
8870 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8871 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8872 (set (match_operand:SI 3 "gpc_reg_operand" "")
8873 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8874 (set (match_operand:SI 4 "gpc_reg_operand" "")
8875 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8876 (set (match_operand:SI 5 "gpc_reg_operand" "")
8877 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8878 (set (match_operand:SI 6 "gpc_reg_operand" "")
8879 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8880 (set (match_operand:SI 7 "gpc_reg_operand" "")
8881 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8882 (set (match_operand:SI 8 "gpc_reg_operand" "")
8883 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8884 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8886 { return rs6000_output_load_multiple (operands); }"
8887 [(set_attr "type" "load_ux")
8888 (set_attr "length" "32")])
8890 (define_insn "*ldmsi6"
8891 [(match_parallel 0 "load_multiple_operation"
8892 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8893 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8894 (set (match_operand:SI 3 "gpc_reg_operand" "")
8895 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8896 (set (match_operand:SI 4 "gpc_reg_operand" "")
8897 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8898 (set (match_operand:SI 5 "gpc_reg_operand" "")
8899 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8900 (set (match_operand:SI 6 "gpc_reg_operand" "")
8901 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8902 (set (match_operand:SI 7 "gpc_reg_operand" "")
8903 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8904 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8906 { return rs6000_output_load_multiple (operands); }"
8907 [(set_attr "type" "load_ux")
8908 (set_attr "length" "32")])
8910 (define_insn "*ldmsi5"
8911 [(match_parallel 0 "load_multiple_operation"
8912 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8913 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8914 (set (match_operand:SI 3 "gpc_reg_operand" "")
8915 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8916 (set (match_operand:SI 4 "gpc_reg_operand" "")
8917 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8918 (set (match_operand:SI 5 "gpc_reg_operand" "")
8919 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8920 (set (match_operand:SI 6 "gpc_reg_operand" "")
8921 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8922 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8924 { return rs6000_output_load_multiple (operands); }"
8925 [(set_attr "type" "load_ux")
8926 (set_attr "length" "32")])
8928 (define_insn "*ldmsi4"
8929 [(match_parallel 0 "load_multiple_operation"
8930 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8931 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8932 (set (match_operand:SI 3 "gpc_reg_operand" "")
8933 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8934 (set (match_operand:SI 4 "gpc_reg_operand" "")
8935 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8936 (set (match_operand:SI 5 "gpc_reg_operand" "")
8937 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8938 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8940 { return rs6000_output_load_multiple (operands); }"
8941 [(set_attr "type" "load_ux")
8942 (set_attr "length" "32")])
8944 (define_insn "*ldmsi3"
8945 [(match_parallel 0 "load_multiple_operation"
8946 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8947 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8948 (set (match_operand:SI 3 "gpc_reg_operand" "")
8949 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8950 (set (match_operand:SI 4 "gpc_reg_operand" "")
8951 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8952 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8954 { return rs6000_output_load_multiple (operands); }"
8955 [(set_attr "type" "load_ux")
8956 (set_attr "length" "32")])
8958 (define_expand "store_multiple"
8959 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8960 (match_operand:SI 1 "" ""))
8961 (clobber (scratch:SI))
8962 (use (match_operand:SI 2 "" ""))])]
8963 "TARGET_STRING && !TARGET_POWERPC64"
8972 /* Support only storing a constant number of fixed-point registers to
8973 memory and only bother with this if more than two; the machine
8974 doesn't support more than eight. */
8975 if (GET_CODE (operands[2]) != CONST_INT
8976 || INTVAL (operands[2]) <= 2
8977 || INTVAL (operands[2]) > 8
8978 || GET_CODE (operands[0]) != MEM
8979 || GET_CODE (operands[1]) != REG
8980 || REGNO (operands[1]) >= 32)
8983 count = INTVAL (operands[2]);
8984 regno = REGNO (operands[1]);
8986 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8987 to = force_reg (SImode, XEXP (operands[0], 0));
8988 op0 = replace_equiv_address (operands[0], to);
8990 XVECEXP (operands[3], 0, 0)
8991 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8992 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8993 gen_rtx_SCRATCH (SImode));
8995 for (i = 1; i < count; i++)
8996 XVECEXP (operands[3], 0, i + 1)
8997 = gen_rtx_SET (VOIDmode,
8998 adjust_address_nv (op0, SImode, i * 4),
8999 gen_rtx_REG (SImode, regno + i));
9002 (define_insn "*stmsi8"
9003 [(match_parallel 0 "store_multiple_operation"
9004 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9005 (match_operand:SI 2 "gpc_reg_operand" "r"))
9006 (clobber (match_scratch:SI 3 "=X"))
9007 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9008 (match_operand:SI 4 "gpc_reg_operand" "r"))
9009 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9010 (match_operand:SI 5 "gpc_reg_operand" "r"))
9011 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9012 (match_operand:SI 6 "gpc_reg_operand" "r"))
9013 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9014 (match_operand:SI 7 "gpc_reg_operand" "r"))
9015 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9016 (match_operand:SI 8 "gpc_reg_operand" "r"))
9017 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9018 (match_operand:SI 9 "gpc_reg_operand" "r"))
9019 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9020 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9021 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9022 "{stsi|stswi} %2,%1,%O0"
9023 [(set_attr "type" "store_ux")])
9025 (define_insn "*stmsi7"
9026 [(match_parallel 0 "store_multiple_operation"
9027 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9028 (match_operand:SI 2 "gpc_reg_operand" "r"))
9029 (clobber (match_scratch:SI 3 "=X"))
9030 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9031 (match_operand:SI 4 "gpc_reg_operand" "r"))
9032 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9033 (match_operand:SI 5 "gpc_reg_operand" "r"))
9034 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9035 (match_operand:SI 6 "gpc_reg_operand" "r"))
9036 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9037 (match_operand:SI 7 "gpc_reg_operand" "r"))
9038 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9039 (match_operand:SI 8 "gpc_reg_operand" "r"))
9040 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9041 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9042 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9043 "{stsi|stswi} %2,%1,%O0"
9044 [(set_attr "type" "store_ux")])
9046 (define_insn "*stmsi6"
9047 [(match_parallel 0 "store_multiple_operation"
9048 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9049 (match_operand:SI 2 "gpc_reg_operand" "r"))
9050 (clobber (match_scratch:SI 3 "=X"))
9051 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9052 (match_operand:SI 4 "gpc_reg_operand" "r"))
9053 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9054 (match_operand:SI 5 "gpc_reg_operand" "r"))
9055 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9056 (match_operand:SI 6 "gpc_reg_operand" "r"))
9057 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9058 (match_operand:SI 7 "gpc_reg_operand" "r"))
9059 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9060 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9061 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9062 "{stsi|stswi} %2,%1,%O0"
9063 [(set_attr "type" "store_ux")])
9065 (define_insn "*stmsi5"
9066 [(match_parallel 0 "store_multiple_operation"
9067 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9068 (match_operand:SI 2 "gpc_reg_operand" "r"))
9069 (clobber (match_scratch:SI 3 "=X"))
9070 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9071 (match_operand:SI 4 "gpc_reg_operand" "r"))
9072 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9073 (match_operand:SI 5 "gpc_reg_operand" "r"))
9074 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9075 (match_operand:SI 6 "gpc_reg_operand" "r"))
9076 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9077 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9078 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9079 "{stsi|stswi} %2,%1,%O0"
9080 [(set_attr "type" "store_ux")])
9082 (define_insn "*stmsi4"
9083 [(match_parallel 0 "store_multiple_operation"
9084 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9085 (match_operand:SI 2 "gpc_reg_operand" "r"))
9086 (clobber (match_scratch:SI 3 "=X"))
9087 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9088 (match_operand:SI 4 "gpc_reg_operand" "r"))
9089 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9090 (match_operand:SI 5 "gpc_reg_operand" "r"))
9091 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9092 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9093 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9094 "{stsi|stswi} %2,%1,%O0"
9095 [(set_attr "type" "store_ux")])
9097 (define_insn "*stmsi3"
9098 [(match_parallel 0 "store_multiple_operation"
9099 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9100 (match_operand:SI 2 "gpc_reg_operand" "r"))
9101 (clobber (match_scratch:SI 3 "=X"))
9102 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9103 (match_operand:SI 4 "gpc_reg_operand" "r"))
9104 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9105 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9106 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9107 "{stsi|stswi} %2,%1,%O0"
9108 [(set_attr "type" "store_ux")])
9110 (define_insn "*stmsi8_power"
9111 [(match_parallel 0 "store_multiple_operation"
9112 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9113 (match_operand:SI 2 "gpc_reg_operand" "r"))
9114 (clobber (match_scratch:SI 3 "=q"))
9115 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9116 (match_operand:SI 4 "gpc_reg_operand" "r"))
9117 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9118 (match_operand:SI 5 "gpc_reg_operand" "r"))
9119 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9120 (match_operand:SI 6 "gpc_reg_operand" "r"))
9121 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9122 (match_operand:SI 7 "gpc_reg_operand" "r"))
9123 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9124 (match_operand:SI 8 "gpc_reg_operand" "r"))
9125 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9126 (match_operand:SI 9 "gpc_reg_operand" "r"))
9127 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9128 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9129 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9130 "{stsi|stswi} %2,%1,%O0"
9131 [(set_attr "type" "store_ux")])
9133 (define_insn "*stmsi7_power"
9134 [(match_parallel 0 "store_multiple_operation"
9135 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9136 (match_operand:SI 2 "gpc_reg_operand" "r"))
9137 (clobber (match_scratch:SI 3 "=q"))
9138 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9139 (match_operand:SI 4 "gpc_reg_operand" "r"))
9140 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9141 (match_operand:SI 5 "gpc_reg_operand" "r"))
9142 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9143 (match_operand:SI 6 "gpc_reg_operand" "r"))
9144 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9145 (match_operand:SI 7 "gpc_reg_operand" "r"))
9146 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9147 (match_operand:SI 8 "gpc_reg_operand" "r"))
9148 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9149 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9150 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9151 "{stsi|stswi} %2,%1,%O0"
9152 [(set_attr "type" "store_ux")])
9154 (define_insn "*stmsi6_power"
9155 [(match_parallel 0 "store_multiple_operation"
9156 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9157 (match_operand:SI 2 "gpc_reg_operand" "r"))
9158 (clobber (match_scratch:SI 3 "=q"))
9159 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9160 (match_operand:SI 4 "gpc_reg_operand" "r"))
9161 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9162 (match_operand:SI 5 "gpc_reg_operand" "r"))
9163 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9164 (match_operand:SI 6 "gpc_reg_operand" "r"))
9165 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9166 (match_operand:SI 7 "gpc_reg_operand" "r"))
9167 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9168 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9169 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9170 "{stsi|stswi} %2,%1,%O0"
9171 [(set_attr "type" "store_ux")])
9173 (define_insn "*stmsi5_power"
9174 [(match_parallel 0 "store_multiple_operation"
9175 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9176 (match_operand:SI 2 "gpc_reg_operand" "r"))
9177 (clobber (match_scratch:SI 3 "=q"))
9178 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9179 (match_operand:SI 4 "gpc_reg_operand" "r"))
9180 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9181 (match_operand:SI 5 "gpc_reg_operand" "r"))
9182 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9183 (match_operand:SI 6 "gpc_reg_operand" "r"))
9184 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9185 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9186 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9187 "{stsi|stswi} %2,%1,%O0"
9188 [(set_attr "type" "store_ux")])
9190 (define_insn "*stmsi4_power"
9191 [(match_parallel 0 "store_multiple_operation"
9192 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9193 (match_operand:SI 2 "gpc_reg_operand" "r"))
9194 (clobber (match_scratch:SI 3 "=q"))
9195 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9196 (match_operand:SI 4 "gpc_reg_operand" "r"))
9197 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9198 (match_operand:SI 5 "gpc_reg_operand" "r"))
9199 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9200 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9201 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9202 "{stsi|stswi} %2,%1,%O0"
9203 [(set_attr "type" "store_ux")])
9205 (define_insn "*stmsi3_power"
9206 [(match_parallel 0 "store_multiple_operation"
9207 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9208 (match_operand:SI 2 "gpc_reg_operand" "r"))
9209 (clobber (match_scratch:SI 3 "=q"))
9210 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9211 (match_operand:SI 4 "gpc_reg_operand" "r"))
9212 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9213 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9214 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9215 "{stsi|stswi} %2,%1,%O0"
9216 [(set_attr "type" "store_ux")])
9218 (define_expand "setmemsi"
9219 [(parallel [(set (match_operand:BLK 0 "" "")
9220 (match_operand 2 "const_int_operand" ""))
9221 (use (match_operand:SI 1 "" ""))
9222 (use (match_operand:SI 3 "" ""))])]
9226 /* If value to set is not zero, use the library routine. */
9227 if (operands[2] != const0_rtx)
9230 if (expand_block_clear (operands))
9236 ;; String/block move insn.
9237 ;; Argument 0 is the destination
9238 ;; Argument 1 is the source
9239 ;; Argument 2 is the length
9240 ;; Argument 3 is the alignment
9242 (define_expand "movmemsi"
9243 [(parallel [(set (match_operand:BLK 0 "" "")
9244 (match_operand:BLK 1 "" ""))
9245 (use (match_operand:SI 2 "" ""))
9246 (use (match_operand:SI 3 "" ""))])]
9250 if (expand_block_move (operands))
9256 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9257 ;; register allocator doesn't have a clue about allocating 8 word registers.
9258 ;; rD/rS = r5 is preferred, efficient form.
9259 (define_expand "movmemsi_8reg"
9260 [(parallel [(set (match_operand 0 "" "")
9261 (match_operand 1 "" ""))
9262 (use (match_operand 2 "" ""))
9263 (use (match_operand 3 "" ""))
9264 (clobber (reg:SI 5))
9265 (clobber (reg:SI 6))
9266 (clobber (reg:SI 7))
9267 (clobber (reg:SI 8))
9268 (clobber (reg:SI 9))
9269 (clobber (reg:SI 10))
9270 (clobber (reg:SI 11))
9271 (clobber (reg:SI 12))
9272 (clobber (match_scratch:SI 4 ""))])]
9277 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9278 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9279 (use (match_operand:SI 2 "immediate_operand" "i"))
9280 (use (match_operand:SI 3 "immediate_operand" "i"))
9281 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9282 (clobber (reg:SI 6))
9283 (clobber (reg:SI 7))
9284 (clobber (reg:SI 8))
9285 (clobber (reg:SI 9))
9286 (clobber (reg:SI 10))
9287 (clobber (reg:SI 11))
9288 (clobber (reg:SI 12))
9289 (clobber (match_scratch:SI 5 "=q"))]
9290 "TARGET_STRING && TARGET_POWER
9291 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9292 || INTVAL (operands[2]) == 0)
9293 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9294 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9295 && REGNO (operands[4]) == 5"
9296 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9297 [(set_attr "type" "store_ux")
9298 (set_attr "length" "8")])
9301 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9302 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9303 (use (match_operand:SI 2 "immediate_operand" "i"))
9304 (use (match_operand:SI 3 "immediate_operand" "i"))
9305 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9306 (clobber (reg:SI 6))
9307 (clobber (reg:SI 7))
9308 (clobber (reg:SI 8))
9309 (clobber (reg:SI 9))
9310 (clobber (reg:SI 10))
9311 (clobber (reg:SI 11))
9312 (clobber (reg:SI 12))
9313 (clobber (match_scratch:SI 5 "=X"))]
9314 "TARGET_STRING && ! TARGET_POWER
9315 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9316 || INTVAL (operands[2]) == 0)
9317 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9318 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9319 && REGNO (operands[4]) == 5"
9320 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9321 [(set_attr "type" "store_ux")
9322 (set_attr "length" "8")])
9324 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9325 ;; register allocator doesn't have a clue about allocating 6 word registers.
9326 ;; rD/rS = r5 is preferred, efficient form.
9327 (define_expand "movmemsi_6reg"
9328 [(parallel [(set (match_operand 0 "" "")
9329 (match_operand 1 "" ""))
9330 (use (match_operand 2 "" ""))
9331 (use (match_operand 3 "" ""))
9332 (clobber (reg:SI 5))
9333 (clobber (reg:SI 6))
9334 (clobber (reg:SI 7))
9335 (clobber (reg:SI 8))
9336 (clobber (reg:SI 9))
9337 (clobber (reg:SI 10))
9338 (clobber (match_scratch:SI 4 ""))])]
9343 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9344 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9345 (use (match_operand:SI 2 "immediate_operand" "i"))
9346 (use (match_operand:SI 3 "immediate_operand" "i"))
9347 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9348 (clobber (reg:SI 6))
9349 (clobber (reg:SI 7))
9350 (clobber (reg:SI 8))
9351 (clobber (reg:SI 9))
9352 (clobber (reg:SI 10))
9353 (clobber (match_scratch:SI 5 "=q"))]
9354 "TARGET_STRING && TARGET_POWER
9355 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9356 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9357 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9358 && REGNO (operands[4]) == 5"
9359 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9360 [(set_attr "type" "store_ux")
9361 (set_attr "length" "8")])
9364 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9365 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9366 (use (match_operand:SI 2 "immediate_operand" "i"))
9367 (use (match_operand:SI 3 "immediate_operand" "i"))
9368 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9369 (clobber (reg:SI 6))
9370 (clobber (reg:SI 7))
9371 (clobber (reg:SI 8))
9372 (clobber (reg:SI 9))
9373 (clobber (reg:SI 10))
9374 (clobber (match_scratch:SI 5 "=X"))]
9375 "TARGET_STRING && ! TARGET_POWER
9376 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9377 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9378 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9379 && REGNO (operands[4]) == 5"
9380 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9381 [(set_attr "type" "store_ux")
9382 (set_attr "length" "8")])
9384 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9385 ;; problems with TImode.
9386 ;; rD/rS = r5 is preferred, efficient form.
9387 (define_expand "movmemsi_4reg"
9388 [(parallel [(set (match_operand 0 "" "")
9389 (match_operand 1 "" ""))
9390 (use (match_operand 2 "" ""))
9391 (use (match_operand 3 "" ""))
9392 (clobber (reg:SI 5))
9393 (clobber (reg:SI 6))
9394 (clobber (reg:SI 7))
9395 (clobber (reg:SI 8))
9396 (clobber (match_scratch:SI 4 ""))])]
9401 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9402 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9403 (use (match_operand:SI 2 "immediate_operand" "i"))
9404 (use (match_operand:SI 3 "immediate_operand" "i"))
9405 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9406 (clobber (reg:SI 6))
9407 (clobber (reg:SI 7))
9408 (clobber (reg:SI 8))
9409 (clobber (match_scratch:SI 5 "=q"))]
9410 "TARGET_STRING && TARGET_POWER
9411 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9412 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9413 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9414 && REGNO (operands[4]) == 5"
9415 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9416 [(set_attr "type" "store_ux")
9417 (set_attr "length" "8")])
9420 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9421 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9422 (use (match_operand:SI 2 "immediate_operand" "i"))
9423 (use (match_operand:SI 3 "immediate_operand" "i"))
9424 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9425 (clobber (reg:SI 6))
9426 (clobber (reg:SI 7))
9427 (clobber (reg:SI 8))
9428 (clobber (match_scratch:SI 5 "=X"))]
9429 "TARGET_STRING && ! TARGET_POWER
9430 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9431 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9432 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9433 && REGNO (operands[4]) == 5"
9434 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9435 [(set_attr "type" "store_ux")
9436 (set_attr "length" "8")])
9438 ;; Move up to 8 bytes at a time.
9439 (define_expand "movmemsi_2reg"
9440 [(parallel [(set (match_operand 0 "" "")
9441 (match_operand 1 "" ""))
9442 (use (match_operand 2 "" ""))
9443 (use (match_operand 3 "" ""))
9444 (clobber (match_scratch:DI 4 ""))
9445 (clobber (match_scratch:SI 5 ""))])]
9446 "TARGET_STRING && ! TARGET_POWERPC64"
9450 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9451 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9452 (use (match_operand:SI 2 "immediate_operand" "i"))
9453 (use (match_operand:SI 3 "immediate_operand" "i"))
9454 (clobber (match_scratch:DI 4 "=&r"))
9455 (clobber (match_scratch:SI 5 "=q"))]
9456 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9457 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9458 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9459 [(set_attr "type" "store_ux")
9460 (set_attr "length" "8")])
9463 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9464 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9465 (use (match_operand:SI 2 "immediate_operand" "i"))
9466 (use (match_operand:SI 3 "immediate_operand" "i"))
9467 (clobber (match_scratch:DI 4 "=&r"))
9468 (clobber (match_scratch:SI 5 "=X"))]
9469 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9470 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9471 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9472 [(set_attr "type" "store_ux")
9473 (set_attr "length" "8")])
9475 ;; Move up to 4 bytes at a time.
9476 (define_expand "movmemsi_1reg"
9477 [(parallel [(set (match_operand 0 "" "")
9478 (match_operand 1 "" ""))
9479 (use (match_operand 2 "" ""))
9480 (use (match_operand 3 "" ""))
9481 (clobber (match_scratch:SI 4 ""))
9482 (clobber (match_scratch:SI 5 ""))])]
9487 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9488 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9489 (use (match_operand:SI 2 "immediate_operand" "i"))
9490 (use (match_operand:SI 3 "immediate_operand" "i"))
9491 (clobber (match_scratch:SI 4 "=&r"))
9492 (clobber (match_scratch:SI 5 "=q"))]
9493 "TARGET_STRING && TARGET_POWER
9494 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9495 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9496 [(set_attr "type" "store_ux")
9497 (set_attr "length" "8")])
9500 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9501 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9502 (use (match_operand:SI 2 "immediate_operand" "i"))
9503 (use (match_operand:SI 3 "immediate_operand" "i"))
9504 (clobber (match_scratch:SI 4 "=&r"))
9505 (clobber (match_scratch:SI 5 "=X"))]
9506 "TARGET_STRING && ! TARGET_POWER
9507 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9508 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9509 [(set_attr "type" "store_ux")
9510 (set_attr "length" "8")])
9512 ;; Define insns that do load or store with update. Some of these we can
9513 ;; get by using pre-decrement or pre-increment, but the hardware can also
9514 ;; do cases where the increment is not the size of the object.
9516 ;; In all these cases, we use operands 0 and 1 for the register being
9517 ;; incremented because those are the operands that local-alloc will
9518 ;; tie and these are the pair most likely to be tieable (and the ones
9519 ;; that will benefit the most).
9521 (define_insn "*movdi_update1"
9522 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9523 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9524 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9525 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9526 (plus:DI (match_dup 1) (match_dup 2)))]
9527 "TARGET_POWERPC64 && TARGET_UPDATE"
9531 [(set_attr "type" "load_ux,load_u")])
9533 (define_insn "movdi_<mode>_update"
9534 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9535 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9536 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9537 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9538 (plus:P (match_dup 1) (match_dup 2)))]
9539 "TARGET_POWERPC64 && TARGET_UPDATE"
9543 [(set_attr "type" "store_ux,store_u")])
9545 (define_insn "*movsi_update1"
9546 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9547 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9548 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9549 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9550 (plus:SI (match_dup 1) (match_dup 2)))]
9553 {lux|lwzux} %3,%0,%2
9554 {lu|lwzu} %3,%2(%0)"
9555 [(set_attr "type" "load_ux,load_u")])
9557 (define_insn "*movsi_update2"
9558 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9560 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9561 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9562 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9563 (plus:DI (match_dup 1) (match_dup 2)))]
9566 [(set_attr "type" "load_ext_ux")])
9568 (define_insn "movsi_update"
9569 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9570 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9571 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9572 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9573 (plus:SI (match_dup 1) (match_dup 2)))]
9576 {stux|stwux} %3,%0,%2
9577 {stu|stwu} %3,%2(%0)"
9578 [(set_attr "type" "store_ux,store_u")])
9580 (define_insn "*movhi_update1"
9581 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9582 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9583 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9584 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9585 (plus:SI (match_dup 1) (match_dup 2)))]
9590 [(set_attr "type" "load_ux,load_u")])
9592 (define_insn "*movhi_update2"
9593 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9595 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9596 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9597 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9598 (plus:SI (match_dup 1) (match_dup 2)))]
9603 [(set_attr "type" "load_ux,load_u")])
9605 (define_insn "*movhi_update3"
9606 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9608 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9609 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9610 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9611 (plus:SI (match_dup 1) (match_dup 2)))]
9616 [(set_attr "type" "load_ext_ux,load_ext_u")])
9618 (define_insn "*movhi_update4"
9619 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9620 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9621 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9622 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9623 (plus:SI (match_dup 1) (match_dup 2)))]
9628 [(set_attr "type" "store_ux,store_u")])
9630 (define_insn "*movqi_update1"
9631 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9632 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9633 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9634 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9635 (plus:SI (match_dup 1) (match_dup 2)))]
9640 [(set_attr "type" "load_ux,load_u")])
9642 (define_insn "*movqi_update2"
9643 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9645 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9646 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9647 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9648 (plus:SI (match_dup 1) (match_dup 2)))]
9653 [(set_attr "type" "load_ux,load_u")])
9655 (define_insn "*movqi_update3"
9656 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9657 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9658 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9659 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9660 (plus:SI (match_dup 1) (match_dup 2)))]
9665 [(set_attr "type" "store_ux,store_u")])
9667 (define_insn "*movsf_update1"
9668 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9669 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9670 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9671 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9672 (plus:SI (match_dup 1) (match_dup 2)))]
9673 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9677 [(set_attr "type" "fpload_ux,fpload_u")])
9679 (define_insn "*movsf_update2"
9680 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9681 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9682 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9683 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9684 (plus:SI (match_dup 1) (match_dup 2)))]
9685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9689 [(set_attr "type" "fpstore_ux,fpstore_u")])
9691 (define_insn "*movsf_update3"
9692 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9693 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9694 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9695 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9696 (plus:SI (match_dup 1) (match_dup 2)))]
9697 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9699 {lux|lwzux} %3,%0,%2
9700 {lu|lwzu} %3,%2(%0)"
9701 [(set_attr "type" "load_ux,load_u")])
9703 (define_insn "*movsf_update4"
9704 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9705 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9706 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9707 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9708 (plus:SI (match_dup 1) (match_dup 2)))]
9709 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9711 {stux|stwux} %3,%0,%2
9712 {stu|stwu} %3,%2(%0)"
9713 [(set_attr "type" "store_ux,store_u")])
9715 (define_insn "*movdf_update1"
9716 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9717 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9718 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9719 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9720 (plus:SI (match_dup 1) (match_dup 2)))]
9721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9725 [(set_attr "type" "fpload_ux,fpload_u")])
9727 (define_insn "*movdf_update2"
9728 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9729 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9730 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9731 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9732 (plus:SI (match_dup 1) (match_dup 2)))]
9733 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9737 [(set_attr "type" "fpstore_ux,fpstore_u")])
9739 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9741 (define_insn "*lfq_power2"
9742 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9743 (match_operand:V2DF 1 "memory_operand" ""))]
9745 && TARGET_HARD_FLOAT && TARGET_FPRS"
9749 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9750 (match_operand:DF 1 "memory_operand" ""))
9751 (set (match_operand:DF 2 "gpc_reg_operand" "")
9752 (match_operand:DF 3 "memory_operand" ""))]
9754 && TARGET_HARD_FLOAT && TARGET_FPRS
9755 && registers_ok_for_quad_peep (operands[0], operands[2])
9756 && mems_ok_for_quad_peep (operands[1], operands[3])"
9759 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9760 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9762 (define_insn "*stfq_power2"
9763 [(set (match_operand:V2DF 0 "memory_operand" "")
9764 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9766 && TARGET_HARD_FLOAT && TARGET_FPRS"
9771 [(set (match_operand:DF 0 "memory_operand" "")
9772 (match_operand:DF 1 "gpc_reg_operand" ""))
9773 (set (match_operand:DF 2 "memory_operand" "")
9774 (match_operand:DF 3 "gpc_reg_operand" ""))]
9776 && TARGET_HARD_FLOAT && TARGET_FPRS
9777 && registers_ok_for_quad_peep (operands[1], operands[3])
9778 && mems_ok_for_quad_peep (operands[0], operands[2])"
9781 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9782 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9784 ;; After inserting conditional returns we can sometimes have
9785 ;; unnecessary register moves. Unfortunately we cannot have a
9786 ;; modeless peephole here, because some single SImode sets have early
9787 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9788 ;; sequences, using get_attr_length here will smash the operands
9789 ;; array. Neither is there an early_cobbler_p predicate.
9790 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9792 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9793 (match_operand:DF 1 "any_operand" ""))
9794 (set (match_operand:DF 2 "gpc_reg_operand" "")
9796 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9797 && peep2_reg_dead_p (2, operands[0])"
9798 [(set (match_dup 2) (match_dup 1))])
9801 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9802 (match_operand:SF 1 "any_operand" ""))
9803 (set (match_operand:SF 2 "gpc_reg_operand" "")
9805 "peep2_reg_dead_p (2, operands[0])"
9806 [(set (match_dup 2) (match_dup 1))])
9811 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9812 (define_insn "tls_gd_32"
9813 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9814 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9815 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9817 "HAVE_AS_TLS && !TARGET_64BIT"
9818 "addi %0,%1,%2@got@tlsgd")
9820 (define_insn "tls_gd_64"
9821 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9822 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9823 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9825 "HAVE_AS_TLS && TARGET_64BIT"
9826 "addi %0,%1,%2@got@tlsgd")
9828 (define_insn "tls_ld_32"
9829 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9830 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9832 "HAVE_AS_TLS && !TARGET_64BIT"
9833 "addi %0,%1,%&@got@tlsld")
9835 (define_insn "tls_ld_64"
9836 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9837 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9839 "HAVE_AS_TLS && TARGET_64BIT"
9840 "addi %0,%1,%&@got@tlsld")
9842 (define_insn "tls_dtprel_32"
9843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9844 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9845 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9847 "HAVE_AS_TLS && !TARGET_64BIT"
9848 "addi %0,%1,%2@dtprel")
9850 (define_insn "tls_dtprel_64"
9851 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9852 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9853 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9855 "HAVE_AS_TLS && TARGET_64BIT"
9856 "addi %0,%1,%2@dtprel")
9858 (define_insn "tls_dtprel_ha_32"
9859 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9860 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9861 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9862 UNSPEC_TLSDTPRELHA))]
9863 "HAVE_AS_TLS && !TARGET_64BIT"
9864 "addis %0,%1,%2@dtprel@ha")
9866 (define_insn "tls_dtprel_ha_64"
9867 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9868 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9869 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9870 UNSPEC_TLSDTPRELHA))]
9871 "HAVE_AS_TLS && TARGET_64BIT"
9872 "addis %0,%1,%2@dtprel@ha")
9874 (define_insn "tls_dtprel_lo_32"
9875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9876 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9877 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9878 UNSPEC_TLSDTPRELLO))]
9879 "HAVE_AS_TLS && !TARGET_64BIT"
9880 "addi %0,%1,%2@dtprel@l")
9882 (define_insn "tls_dtprel_lo_64"
9883 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9884 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9885 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9886 UNSPEC_TLSDTPRELLO))]
9887 "HAVE_AS_TLS && TARGET_64BIT"
9888 "addi %0,%1,%2@dtprel@l")
9890 (define_insn "tls_got_dtprel_32"
9891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9892 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9893 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9894 UNSPEC_TLSGOTDTPREL))]
9895 "HAVE_AS_TLS && !TARGET_64BIT"
9896 "lwz %0,%2@got@dtprel(%1)")
9898 (define_insn "tls_got_dtprel_64"
9899 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9900 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9901 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9902 UNSPEC_TLSGOTDTPREL))]
9903 "HAVE_AS_TLS && TARGET_64BIT"
9904 "ld %0,%2@got@dtprel(%1)")
9906 (define_insn "tls_tprel_32"
9907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9908 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9909 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9911 "HAVE_AS_TLS && !TARGET_64BIT"
9912 "addi %0,%1,%2@tprel")
9914 (define_insn "tls_tprel_64"
9915 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9916 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9917 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9919 "HAVE_AS_TLS && TARGET_64BIT"
9920 "addi %0,%1,%2@tprel")
9922 (define_insn "tls_tprel_ha_32"
9923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9924 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9925 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9926 UNSPEC_TLSTPRELHA))]
9927 "HAVE_AS_TLS && !TARGET_64BIT"
9928 "addis %0,%1,%2@tprel@ha")
9930 (define_insn "tls_tprel_ha_64"
9931 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9932 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9933 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9934 UNSPEC_TLSTPRELHA))]
9935 "HAVE_AS_TLS && TARGET_64BIT"
9936 "addis %0,%1,%2@tprel@ha")
9938 (define_insn "tls_tprel_lo_32"
9939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9940 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9941 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9942 UNSPEC_TLSTPRELLO))]
9943 "HAVE_AS_TLS && !TARGET_64BIT"
9944 "addi %0,%1,%2@tprel@l")
9946 (define_insn "tls_tprel_lo_64"
9947 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9948 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9949 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9950 UNSPEC_TLSTPRELLO))]
9951 "HAVE_AS_TLS && TARGET_64BIT"
9952 "addi %0,%1,%2@tprel@l")
9954 ;; "b" output constraint here and on tls_tls input to support linker tls
9955 ;; optimization. The linker may edit the instructions emitted by a
9956 ;; tls_got_tprel/tls_tls pair to addis,addi.
9957 (define_insn "tls_got_tprel_32"
9958 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9959 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9960 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9961 UNSPEC_TLSGOTTPREL))]
9962 "HAVE_AS_TLS && !TARGET_64BIT"
9963 "lwz %0,%2@got@tprel(%1)")
9965 (define_insn "tls_got_tprel_64"
9966 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9967 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9968 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9969 UNSPEC_TLSGOTTPREL))]
9970 "HAVE_AS_TLS && TARGET_64BIT"
9971 "ld %0,%2@got@tprel(%1)")
9973 (define_insn "tls_tls_32"
9974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9975 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9976 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9978 "HAVE_AS_TLS && !TARGET_64BIT"
9981 (define_insn "tls_tls_64"
9982 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9983 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9984 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9986 "HAVE_AS_TLS && TARGET_64BIT"
9989 ;; Next come insns related to the calling sequence.
9991 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9992 ;; We move the back-chain and decrement the stack pointer.
9994 (define_expand "allocate_stack"
9995 [(set (match_operand 0 "gpc_reg_operand" "=r")
9996 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9998 (minus (reg 1) (match_dup 1)))]
10001 { rtx chain = gen_reg_rtx (Pmode);
10002 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10005 emit_move_insn (chain, stack_bot);
10007 /* Check stack bounds if necessary. */
10008 if (current_function_limit_stack)
10011 available = expand_binop (Pmode, sub_optab,
10012 stack_pointer_rtx, stack_limit_rtx,
10013 NULL_RTX, 1, OPTAB_WIDEN);
10014 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10017 if (GET_CODE (operands[1]) != CONST_INT
10018 || INTVAL (operands[1]) < -32767
10019 || INTVAL (operands[1]) > 32768)
10021 neg_op0 = gen_reg_rtx (Pmode);
10023 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10025 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10028 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10031 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10032 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10036 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10037 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10038 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10041 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10045 ;; These patterns say how to save and restore the stack pointer. We need not
10046 ;; save the stack pointer at function level since we are careful to
10047 ;; preserve the backchain. At block level, we have to restore the backchain
10048 ;; when we restore the stack pointer.
10050 ;; For nonlocal gotos, we must save both the stack pointer and its
10051 ;; backchain and restore both. Note that in the nonlocal case, the
10052 ;; save area is a memory location.
10054 (define_expand "save_stack_function"
10055 [(match_operand 0 "any_operand" "")
10056 (match_operand 1 "any_operand" "")]
10060 (define_expand "restore_stack_function"
10061 [(match_operand 0 "any_operand" "")
10062 (match_operand 1 "any_operand" "")]
10066 ;; Adjust stack pointer (op0) to a new value (op1).
10067 ;; First copy old stack backchain to new location, and ensure that the
10068 ;; scheduler won't reorder the sp assignment before the backchain write.
10069 (define_expand "restore_stack_block"
10070 [(set (match_dup 2) (match_dup 3))
10071 (set (match_dup 4) (match_dup 2))
10072 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10073 (set (match_operand 0 "register_operand" "")
10074 (match_operand 1 "register_operand" ""))]
10078 operands[1] = force_reg (Pmode, operands[1]);
10079 operands[2] = gen_reg_rtx (Pmode);
10080 operands[3] = gen_frame_mem (Pmode, operands[0]);
10081 operands[4] = gen_frame_mem (Pmode, operands[1]);
10082 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10085 (define_expand "save_stack_nonlocal"
10086 [(set (match_dup 3) (match_dup 4))
10087 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10088 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10092 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10094 /* Copy the backchain to the first word, sp to the second. */
10095 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10096 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10097 operands[3] = gen_reg_rtx (Pmode);
10098 operands[4] = gen_frame_mem (Pmode, operands[1]);
10101 (define_expand "restore_stack_nonlocal"
10102 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10103 (set (match_dup 3) (match_dup 4))
10104 (set (match_dup 5) (match_dup 2))
10105 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10106 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10110 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10112 /* Restore the backchain from the first word, sp from the second. */
10113 operands[2] = gen_reg_rtx (Pmode);
10114 operands[3] = gen_reg_rtx (Pmode);
10115 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10116 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10117 operands[5] = gen_frame_mem (Pmode, operands[3]);
10118 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10121 ;; TOC register handling.
10123 ;; Code to initialize the TOC register...
10125 (define_insn "load_toc_aix_si"
10126 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10127 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10128 (use (reg:SI 2))])]
10129 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10133 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10134 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10135 operands[2] = gen_rtx_REG (Pmode, 2);
10136 return \"{l|lwz} %0,%1(%2)\";
10138 [(set_attr "type" "load")])
10140 (define_insn "load_toc_aix_di"
10141 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10142 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10143 (use (reg:DI 2))])]
10144 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10148 #ifdef TARGET_RELOCATABLE
10149 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10150 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10152 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10155 strcat (buf, \"@toc\");
10156 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10157 operands[2] = gen_rtx_REG (Pmode, 2);
10158 return \"ld %0,%1(%2)\";
10160 [(set_attr "type" "load")])
10162 (define_insn "load_toc_v4_pic_si"
10163 [(set (match_operand:SI 0 "register_operand" "=l")
10164 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10165 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10166 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10167 [(set_attr "type" "branch")
10168 (set_attr "length" "4")])
10170 (define_insn "load_toc_v4_PIC_1"
10171 [(set (match_operand:SI 0 "register_operand" "=l")
10172 (match_operand:SI 1 "immediate_operand" "s"))
10173 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10174 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10175 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10176 "bcl 20,31,%1\\n%1:"
10177 [(set_attr "type" "branch")
10178 (set_attr "length" "4")])
10180 (define_insn "load_toc_v4_PIC_1b"
10181 [(set (match_operand:SI 0 "register_operand" "=l")
10182 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10184 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10185 "bcl 20,31,$+8\\n\\t.long %1-$"
10186 [(set_attr "type" "branch")
10187 (set_attr "length" "8")])
10189 (define_insn "load_toc_v4_PIC_2"
10190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10191 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10192 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10193 (match_operand:SI 3 "immediate_operand" "s")))))]
10194 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10195 "{l|lwz} %0,%2-%3(%1)"
10196 [(set_attr "type" "load")])
10198 (define_insn "load_toc_v4_PIC_3b"
10199 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10200 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10202 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10203 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10204 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10205 "{cau|addis} %0,%1,%2-%3@ha")
10207 (define_insn "load_toc_v4_PIC_3c"
10208 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10209 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10210 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10211 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10212 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10213 "{cal|addi} %0,%1,%2-%3@l")
10215 ;; If the TOC is shared over a translation unit, as happens with all
10216 ;; the kinds of PIC that we support, we need to restore the TOC
10217 ;; pointer only when jumping over units of translation.
10218 ;; On Darwin, we need to reload the picbase.
10220 (define_expand "builtin_setjmp_receiver"
10221 [(use (label_ref (match_operand 0 "" "")))]
10222 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10223 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10224 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10228 if (DEFAULT_ABI == ABI_DARWIN)
10230 const char *picbase = machopic_function_base_name ();
10231 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10232 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10236 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10237 CODE_LABEL_NUMBER (operands[0]));
10238 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10240 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10241 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10245 rs6000_emit_load_toc_table (FALSE);
10249 ;; Elf specific ways of loading addresses for non-PIC code.
10250 ;; The output of this could be r0, but we make a very strong
10251 ;; preference for a base register because it will usually
10252 ;; be needed there.
10253 (define_insn "elf_high"
10254 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10255 (high:SI (match_operand 1 "" "")))]
10256 "TARGET_ELF && ! TARGET_64BIT"
10257 "{liu|lis} %0,%1@ha")
10259 (define_insn "elf_low"
10260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10261 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10262 (match_operand 2 "" "")))]
10263 "TARGET_ELF && ! TARGET_64BIT"
10265 {cal|la} %0,%2@l(%1)
10266 {ai|addic} %0,%1,%K2")
10268 ;; A function pointer under AIX is a pointer to a data area whose first word
10269 ;; contains the actual address of the function, whose second word contains a
10270 ;; pointer to its TOC, and whose third word contains a value to place in the
10271 ;; static chain register (r11). Note that if we load the static chain, our
10272 ;; "trampoline" need not have any executable code.
10274 (define_expand "call_indirect_aix32"
10275 [(set (match_dup 2)
10276 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10277 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10280 (mem:SI (plus:SI (match_dup 0)
10283 (mem:SI (plus:SI (match_dup 0)
10285 (parallel [(call (mem:SI (match_dup 2))
10286 (match_operand 1 "" ""))
10290 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10291 (clobber (scratch:SI))])]
10294 { operands[2] = gen_reg_rtx (SImode); }")
10296 (define_expand "call_indirect_aix64"
10297 [(set (match_dup 2)
10298 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10299 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10302 (mem:DI (plus:DI (match_dup 0)
10305 (mem:DI (plus:DI (match_dup 0)
10307 (parallel [(call (mem:SI (match_dup 2))
10308 (match_operand 1 "" ""))
10312 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10313 (clobber (scratch:SI))])]
10316 { operands[2] = gen_reg_rtx (DImode); }")
10318 (define_expand "call_value_indirect_aix32"
10319 [(set (match_dup 3)
10320 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10321 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10324 (mem:SI (plus:SI (match_dup 1)
10327 (mem:SI (plus:SI (match_dup 1)
10329 (parallel [(set (match_operand 0 "" "")
10330 (call (mem:SI (match_dup 3))
10331 (match_operand 2 "" "")))
10335 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10336 (clobber (scratch:SI))])]
10339 { operands[3] = gen_reg_rtx (SImode); }")
10341 (define_expand "call_value_indirect_aix64"
10342 [(set (match_dup 3)
10343 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10344 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10347 (mem:DI (plus:DI (match_dup 1)
10350 (mem:DI (plus:DI (match_dup 1)
10352 (parallel [(set (match_operand 0 "" "")
10353 (call (mem:SI (match_dup 3))
10354 (match_operand 2 "" "")))
10358 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10359 (clobber (scratch:SI))])]
10362 { operands[3] = gen_reg_rtx (DImode); }")
10364 ;; Now the definitions for the call and call_value insns
10365 (define_expand "call"
10366 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10367 (match_operand 1 "" ""))
10368 (use (match_operand 2 "" ""))
10369 (clobber (scratch:SI))])]
10374 if (MACHOPIC_INDIRECT)
10375 operands[0] = machopic_indirect_call_target (operands[0]);
10378 gcc_assert (GET_CODE (operands[0]) == MEM);
10379 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10381 operands[0] = XEXP (operands[0], 0);
10383 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10385 && GET_CODE (operands[0]) == SYMBOL_REF
10386 && !SYMBOL_REF_LOCAL_P (operands[0]))
10391 tmp = gen_rtvec (3,
10392 gen_rtx_CALL (VOIDmode,
10393 gen_rtx_MEM (SImode, operands[0]),
10395 gen_rtx_USE (VOIDmode, operands[2]),
10396 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10397 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10398 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10402 if (GET_CODE (operands[0]) != SYMBOL_REF
10403 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10404 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10406 if (INTVAL (operands[2]) & CALL_LONG)
10407 operands[0] = rs6000_longcall_ref (operands[0]);
10409 switch (DEFAULT_ABI)
10413 operands[0] = force_reg (Pmode, operands[0]);
10417 /* AIX function pointers are really pointers to a three word
10419 emit_call_insn (TARGET_32BIT
10420 ? gen_call_indirect_aix32 (force_reg (SImode,
10423 : gen_call_indirect_aix64 (force_reg (DImode,
10429 gcc_unreachable ();
10434 (define_expand "call_value"
10435 [(parallel [(set (match_operand 0 "" "")
10436 (call (mem:SI (match_operand 1 "address_operand" ""))
10437 (match_operand 2 "" "")))
10438 (use (match_operand 3 "" ""))
10439 (clobber (scratch:SI))])]
10444 if (MACHOPIC_INDIRECT)
10445 operands[1] = machopic_indirect_call_target (operands[1]);
10448 gcc_assert (GET_CODE (operands[1]) == MEM);
10449 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10451 operands[1] = XEXP (operands[1], 0);
10453 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10455 && GET_CODE (operands[1]) == SYMBOL_REF
10456 && !SYMBOL_REF_LOCAL_P (operands[1]))
10461 tmp = gen_rtvec (3,
10462 gen_rtx_SET (VOIDmode,
10464 gen_rtx_CALL (VOIDmode,
10465 gen_rtx_MEM (SImode,
10468 gen_rtx_USE (VOIDmode, operands[3]),
10469 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10470 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10471 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10475 if (GET_CODE (operands[1]) != SYMBOL_REF
10476 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10477 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10479 if (INTVAL (operands[3]) & CALL_LONG)
10480 operands[1] = rs6000_longcall_ref (operands[1]);
10482 switch (DEFAULT_ABI)
10486 operands[1] = force_reg (Pmode, operands[1]);
10490 /* AIX function pointers are really pointers to a three word
10492 emit_call_insn (TARGET_32BIT
10493 ? gen_call_value_indirect_aix32 (operands[0],
10497 : gen_call_value_indirect_aix64 (operands[0],
10504 gcc_unreachable ();
10509 ;; Call to function in current module. No TOC pointer reload needed.
10510 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10511 ;; either the function was not prototyped, or it was prototyped as a
10512 ;; variable argument function. It is > 0 if FP registers were passed
10513 ;; and < 0 if they were not.
10515 (define_insn "*call_local32"
10516 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10517 (match_operand 1 "" "g,g"))
10518 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10519 (clobber (match_scratch:SI 3 "=l,l"))]
10520 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10523 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10524 output_asm_insn (\"crxor 6,6,6\", operands);
10526 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10527 output_asm_insn (\"creqv 6,6,6\", operands);
10529 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10531 [(set_attr "type" "branch")
10532 (set_attr "length" "4,8")])
10534 (define_insn "*call_local64"
10535 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10536 (match_operand 1 "" "g,g"))
10537 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10538 (clobber (match_scratch:SI 3 "=l,l"))]
10539 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10542 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10543 output_asm_insn (\"crxor 6,6,6\", operands);
10545 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10546 output_asm_insn (\"creqv 6,6,6\", operands);
10548 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10550 [(set_attr "type" "branch")
10551 (set_attr "length" "4,8")])
10553 (define_insn "*call_value_local32"
10554 [(set (match_operand 0 "" "")
10555 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10556 (match_operand 2 "" "g,g")))
10557 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10558 (clobber (match_scratch:SI 4 "=l,l"))]
10559 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10562 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10563 output_asm_insn (\"crxor 6,6,6\", operands);
10565 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10566 output_asm_insn (\"creqv 6,6,6\", operands);
10568 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10570 [(set_attr "type" "branch")
10571 (set_attr "length" "4,8")])
10574 (define_insn "*call_value_local64"
10575 [(set (match_operand 0 "" "")
10576 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10577 (match_operand 2 "" "g,g")))
10578 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10579 (clobber (match_scratch:SI 4 "=l,l"))]
10580 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10583 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10584 output_asm_insn (\"crxor 6,6,6\", operands);
10586 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10587 output_asm_insn (\"creqv 6,6,6\", operands);
10589 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10591 [(set_attr "type" "branch")
10592 (set_attr "length" "4,8")])
10594 ;; Call to function which may be in another module. Restore the TOC
10595 ;; pointer (r2) after the call unless this is System V.
10596 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10597 ;; either the function was not prototyped, or it was prototyped as a
10598 ;; variable argument function. It is > 0 if FP registers were passed
10599 ;; and < 0 if they were not.
10601 (define_insn "*call_indirect_nonlocal_aix32"
10602 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10603 (match_operand 1 "" "g,g"))
10607 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10608 (clobber (match_scratch:SI 2 "=l,l"))]
10609 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10610 "b%T0l\;{l|lwz} 2,20(1)"
10611 [(set_attr "type" "jmpreg")
10612 (set_attr "length" "8")])
10614 (define_insn "*call_nonlocal_aix32"
10615 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10616 (match_operand 1 "" "g"))
10617 (use (match_operand:SI 2 "immediate_operand" "O"))
10618 (clobber (match_scratch:SI 3 "=l"))]
10620 && DEFAULT_ABI == ABI_AIX
10621 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10623 [(set_attr "type" "branch")
10624 (set_attr "length" "8")])
10626 (define_insn "*call_indirect_nonlocal_aix64"
10627 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10628 (match_operand 1 "" "g,g"))
10632 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10633 (clobber (match_scratch:SI 2 "=l,l"))]
10634 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10635 "b%T0l\;ld 2,40(1)"
10636 [(set_attr "type" "jmpreg")
10637 (set_attr "length" "8")])
10639 (define_insn "*call_nonlocal_aix64"
10640 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10641 (match_operand 1 "" "g"))
10642 (use (match_operand:SI 2 "immediate_operand" "O"))
10643 (clobber (match_scratch:SI 3 "=l"))]
10645 && DEFAULT_ABI == ABI_AIX
10646 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10648 [(set_attr "type" "branch")
10649 (set_attr "length" "8")])
10651 (define_insn "*call_value_indirect_nonlocal_aix32"
10652 [(set (match_operand 0 "" "")
10653 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10654 (match_operand 2 "" "g,g")))
10658 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10659 (clobber (match_scratch:SI 3 "=l,l"))]
10660 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10661 "b%T1l\;{l|lwz} 2,20(1)"
10662 [(set_attr "type" "jmpreg")
10663 (set_attr "length" "8")])
10665 (define_insn "*call_value_nonlocal_aix32"
10666 [(set (match_operand 0 "" "")
10667 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10668 (match_operand 2 "" "g")))
10669 (use (match_operand:SI 3 "immediate_operand" "O"))
10670 (clobber (match_scratch:SI 4 "=l"))]
10672 && DEFAULT_ABI == ABI_AIX
10673 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10675 [(set_attr "type" "branch")
10676 (set_attr "length" "8")])
10678 (define_insn "*call_value_indirect_nonlocal_aix64"
10679 [(set (match_operand 0 "" "")
10680 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10681 (match_operand 2 "" "g,g")))
10685 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10686 (clobber (match_scratch:SI 3 "=l,l"))]
10687 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10688 "b%T1l\;ld 2,40(1)"
10689 [(set_attr "type" "jmpreg")
10690 (set_attr "length" "8")])
10692 (define_insn "*call_value_nonlocal_aix64"
10693 [(set (match_operand 0 "" "")
10694 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10695 (match_operand 2 "" "g")))
10696 (use (match_operand:SI 3 "immediate_operand" "O"))
10697 (clobber (match_scratch:SI 4 "=l"))]
10699 && DEFAULT_ABI == ABI_AIX
10700 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10702 [(set_attr "type" "branch")
10703 (set_attr "length" "8")])
10705 ;; A function pointer under System V is just a normal pointer
10706 ;; operands[0] is the function pointer
10707 ;; operands[1] is the stack size to clean up
10708 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10709 ;; which indicates how to set cr1
10711 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10712 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10713 (match_operand 1 "" "g,g,g,g"))
10714 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10715 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10716 "DEFAULT_ABI == ABI_V4
10717 || DEFAULT_ABI == ABI_DARWIN"
10719 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10720 output_asm_insn ("crxor 6,6,6", operands);
10722 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10723 output_asm_insn ("creqv 6,6,6", operands);
10727 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10728 (set_attr "length" "4,4,8,8")])
10730 (define_insn "*call_nonlocal_sysv<mode>"
10731 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10732 (match_operand 1 "" "g,g"))
10733 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10734 (clobber (match_scratch:SI 3 "=l,l"))]
10735 "(DEFAULT_ABI == ABI_DARWIN
10736 || (DEFAULT_ABI == ABI_V4
10737 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10739 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10740 output_asm_insn ("crxor 6,6,6", operands);
10742 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10743 output_asm_insn ("creqv 6,6,6", operands);
10746 return output_call(insn, operands, 0, 2);
10748 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10750 if (TARGET_SECURE_PLT && flag_pic == 2)
10751 /* The magic 32768 offset here and in the other sysv call insns
10752 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10753 See sysv4.h:toc_section. */
10754 return "bl %z0+32768@plt";
10756 return "bl %z0@plt";
10762 [(set_attr "type" "branch,branch")
10763 (set_attr "length" "4,8")])
10765 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10766 [(set (match_operand 0 "" "")
10767 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10768 (match_operand 2 "" "g,g,g,g")))
10769 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10770 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10771 "DEFAULT_ABI == ABI_V4
10772 || DEFAULT_ABI == ABI_DARWIN"
10774 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10775 output_asm_insn ("crxor 6,6,6", operands);
10777 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10778 output_asm_insn ("creqv 6,6,6", operands);
10782 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10783 (set_attr "length" "4,4,8,8")])
10785 (define_insn "*call_value_nonlocal_sysv<mode>"
10786 [(set (match_operand 0 "" "")
10787 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10788 (match_operand 2 "" "g,g")))
10789 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10790 (clobber (match_scratch:SI 4 "=l,l"))]
10791 "(DEFAULT_ABI == ABI_DARWIN
10792 || (DEFAULT_ABI == ABI_V4
10793 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10795 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10796 output_asm_insn ("crxor 6,6,6", operands);
10798 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10799 output_asm_insn ("creqv 6,6,6", operands);
10802 return output_call(insn, operands, 1, 3);
10804 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10806 if (TARGET_SECURE_PLT && flag_pic == 2)
10807 return "bl %z1+32768@plt";
10809 return "bl %z1@plt";
10815 [(set_attr "type" "branch,branch")
10816 (set_attr "length" "4,8")])
10818 ;; Call subroutine returning any type.
10819 (define_expand "untyped_call"
10820 [(parallel [(call (match_operand 0 "" "")
10822 (match_operand 1 "" "")
10823 (match_operand 2 "" "")])]
10829 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10831 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10833 rtx set = XVECEXP (operands[2], 0, i);
10834 emit_move_insn (SET_DEST (set), SET_SRC (set));
10837 /* The optimizer does not know that the call sets the function value
10838 registers we stored in the result block. We avoid problems by
10839 claiming that all hard registers are used and clobbered at this
10841 emit_insn (gen_blockage ());
10846 ;; sibling call patterns
10847 (define_expand "sibcall"
10848 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10849 (match_operand 1 "" ""))
10850 (use (match_operand 2 "" ""))
10851 (use (match_operand 3 "" ""))
10857 if (MACHOPIC_INDIRECT)
10858 operands[0] = machopic_indirect_call_target (operands[0]);
10861 gcc_assert (GET_CODE (operands[0]) == MEM);
10862 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10864 operands[0] = XEXP (operands[0], 0);
10865 operands[3] = gen_reg_rtx (SImode);
10869 ;; this and similar patterns must be marked as using LR, otherwise
10870 ;; dataflow will try to delete the store into it. This is true
10871 ;; even when the actual reg to jump to is in CTR, when LR was
10872 ;; saved and restored around the PIC-setting BCL.
10873 (define_insn "*sibcall_local32"
10874 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10875 (match_operand 1 "" "g,g"))
10876 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10877 (use (match_operand:SI 3 "register_operand" "l,l"))
10879 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10882 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10883 output_asm_insn (\"crxor 6,6,6\", operands);
10885 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10886 output_asm_insn (\"creqv 6,6,6\", operands);
10888 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10890 [(set_attr "type" "branch")
10891 (set_attr "length" "4,8")])
10893 (define_insn "*sibcall_local64"
10894 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10895 (match_operand 1 "" "g,g"))
10896 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10897 (use (match_operand:SI 3 "register_operand" "l,l"))
10899 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10902 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10903 output_asm_insn (\"crxor 6,6,6\", operands);
10905 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10906 output_asm_insn (\"creqv 6,6,6\", operands);
10908 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10910 [(set_attr "type" "branch")
10911 (set_attr "length" "4,8")])
10913 (define_insn "*sibcall_value_local32"
10914 [(set (match_operand 0 "" "")
10915 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10916 (match_operand 2 "" "g,g")))
10917 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10918 (use (match_operand:SI 4 "register_operand" "l,l"))
10920 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10923 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10924 output_asm_insn (\"crxor 6,6,6\", operands);
10926 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10927 output_asm_insn (\"creqv 6,6,6\", operands);
10929 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10931 [(set_attr "type" "branch")
10932 (set_attr "length" "4,8")])
10935 (define_insn "*sibcall_value_local64"
10936 [(set (match_operand 0 "" "")
10937 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10938 (match_operand 2 "" "g,g")))
10939 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10940 (use (match_operand:SI 4 "register_operand" "l,l"))
10942 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10945 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10946 output_asm_insn (\"crxor 6,6,6\", operands);
10948 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10949 output_asm_insn (\"creqv 6,6,6\", operands);
10951 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10953 [(set_attr "type" "branch")
10954 (set_attr "length" "4,8")])
10956 (define_insn "*sibcall_nonlocal_aix32"
10957 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10958 (match_operand 1 "" "g"))
10959 (use (match_operand:SI 2 "immediate_operand" "O"))
10960 (use (match_operand:SI 3 "register_operand" "l"))
10963 && DEFAULT_ABI == ABI_AIX
10964 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10966 [(set_attr "type" "branch")
10967 (set_attr "length" "4")])
10969 (define_insn "*sibcall_nonlocal_aix64"
10970 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10971 (match_operand 1 "" "g"))
10972 (use (match_operand:SI 2 "immediate_operand" "O"))
10973 (use (match_operand:SI 3 "register_operand" "l"))
10976 && DEFAULT_ABI == ABI_AIX
10977 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10979 [(set_attr "type" "branch")
10980 (set_attr "length" "4")])
10982 (define_insn "*sibcall_value_nonlocal_aix32"
10983 [(set (match_operand 0 "" "")
10984 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10985 (match_operand 2 "" "g")))
10986 (use (match_operand:SI 3 "immediate_operand" "O"))
10987 (use (match_operand:SI 4 "register_operand" "l"))
10990 && DEFAULT_ABI == ABI_AIX
10991 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10993 [(set_attr "type" "branch")
10994 (set_attr "length" "4")])
10996 (define_insn "*sibcall_value_nonlocal_aix64"
10997 [(set (match_operand 0 "" "")
10998 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10999 (match_operand 2 "" "g")))
11000 (use (match_operand:SI 3 "immediate_operand" "O"))
11001 (use (match_operand:SI 4 "register_operand" "l"))
11004 && DEFAULT_ABI == ABI_AIX
11005 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11007 [(set_attr "type" "branch")
11008 (set_attr "length" "4")])
11010 (define_insn "*sibcall_nonlocal_sysv<mode>"
11011 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11012 (match_operand 1 "" ""))
11013 (use (match_operand 2 "immediate_operand" "O,n"))
11014 (use (match_operand:SI 3 "register_operand" "l,l"))
11016 "(DEFAULT_ABI == ABI_DARWIN
11017 || DEFAULT_ABI == ABI_V4)
11018 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11021 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11022 output_asm_insn (\"crxor 6,6,6\", operands);
11024 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11025 output_asm_insn (\"creqv 6,6,6\", operands);
11027 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11029 if (TARGET_SECURE_PLT && flag_pic == 2)
11030 return \"b %z0+32768@plt\";
11032 return \"b %z0@plt\";
11037 [(set_attr "type" "branch,branch")
11038 (set_attr "length" "4,8")])
11040 (define_expand "sibcall_value"
11041 [(parallel [(set (match_operand 0 "register_operand" "")
11042 (call (mem:SI (match_operand 1 "address_operand" ""))
11043 (match_operand 2 "" "")))
11044 (use (match_operand 3 "" ""))
11045 (use (match_operand 4 "" ""))
11051 if (MACHOPIC_INDIRECT)
11052 operands[1] = machopic_indirect_call_target (operands[1]);
11055 gcc_assert (GET_CODE (operands[1]) == MEM);
11056 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11058 operands[1] = XEXP (operands[1], 0);
11059 operands[4] = gen_reg_rtx (SImode);
11063 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11064 [(set (match_operand 0 "" "")
11065 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11066 (match_operand 2 "" "")))
11067 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11068 (use (match_operand:SI 4 "register_operand" "l,l"))
11070 "(DEFAULT_ABI == ABI_DARWIN
11071 || DEFAULT_ABI == ABI_V4)
11072 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11075 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11076 output_asm_insn (\"crxor 6,6,6\", operands);
11078 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11079 output_asm_insn (\"creqv 6,6,6\", operands);
11081 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11083 if (TARGET_SECURE_PLT && flag_pic == 2)
11084 return \"b %z1+32768@plt\";
11086 return \"b %z1@plt\";
11091 [(set_attr "type" "branch,branch")
11092 (set_attr "length" "4,8")])
11094 (define_expand "sibcall_epilogue"
11095 [(use (const_int 0))]
11096 "TARGET_SCHED_PROLOG"
11099 rs6000_emit_epilogue (TRUE);
11103 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11104 ;; all of memory. This blocks insns from being moved across this point.
11106 (define_insn "blockage"
11107 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11111 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11112 ;; signed & unsigned, and one type of branch.
11114 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11115 ;; insns, and branches. We store the operands of compares until we see
11117 (define_expand "cmp<mode>"
11119 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11120 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11124 /* Take care of the possibility that operands[1] might be negative but
11125 this might be a logical operation. That insn doesn't exist. */
11126 if (GET_CODE (operands[1]) == CONST_INT
11127 && INTVAL (operands[1]) < 0)
11128 operands[1] = force_reg (<MODE>mode, operands[1]);
11130 rs6000_compare_op0 = operands[0];
11131 rs6000_compare_op1 = operands[1];
11132 rs6000_compare_fp_p = 0;
11136 (define_expand "cmp<mode>"
11137 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11138 (match_operand:FP 1 "gpc_reg_operand" "")))]
11142 rs6000_compare_op0 = operands[0];
11143 rs6000_compare_op1 = operands[1];
11144 rs6000_compare_fp_p = 1;
11148 (define_expand "beq"
11149 [(use (match_operand 0 "" ""))]
11151 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11153 (define_expand "bne"
11154 [(use (match_operand 0 "" ""))]
11156 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11158 (define_expand "bge"
11159 [(use (match_operand 0 "" ""))]
11161 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11163 (define_expand "bgt"
11164 [(use (match_operand 0 "" ""))]
11166 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11168 (define_expand "ble"
11169 [(use (match_operand 0 "" ""))]
11171 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11173 (define_expand "blt"
11174 [(use (match_operand 0 "" ""))]
11176 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11178 (define_expand "bgeu"
11179 [(use (match_operand 0 "" ""))]
11181 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11183 (define_expand "bgtu"
11184 [(use (match_operand 0 "" ""))]
11186 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11188 (define_expand "bleu"
11189 [(use (match_operand 0 "" ""))]
11191 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11193 (define_expand "bltu"
11194 [(use (match_operand 0 "" ""))]
11196 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11198 (define_expand "bunordered"
11199 [(use (match_operand 0 "" ""))]
11200 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11201 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11203 (define_expand "bordered"
11204 [(use (match_operand 0 "" ""))]
11205 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11206 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11208 (define_expand "buneq"
11209 [(use (match_operand 0 "" ""))]
11211 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11213 (define_expand "bunge"
11214 [(use (match_operand 0 "" ""))]
11216 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11218 (define_expand "bungt"
11219 [(use (match_operand 0 "" ""))]
11221 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11223 (define_expand "bunle"
11224 [(use (match_operand 0 "" ""))]
11226 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11228 (define_expand "bunlt"
11229 [(use (match_operand 0 "" ""))]
11231 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11233 (define_expand "bltgt"
11234 [(use (match_operand 0 "" ""))]
11236 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11238 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11239 ;; For SEQ, likewise, except that comparisons with zero should be done
11240 ;; with an scc insns. However, due to the order that combine see the
11241 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11242 ;; the cases we don't want to handle.
11243 (define_expand "seq"
11244 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11246 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11248 (define_expand "sne"
11249 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11253 if (! rs6000_compare_fp_p)
11256 rs6000_emit_sCOND (NE, operands[0]);
11260 ;; A >= 0 is best done the portable way for A an integer.
11261 (define_expand "sge"
11262 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11266 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11269 rs6000_emit_sCOND (GE, operands[0]);
11273 ;; A > 0 is best done using the portable sequence, so fail in that case.
11274 (define_expand "sgt"
11275 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11279 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11282 rs6000_emit_sCOND (GT, operands[0]);
11286 ;; A <= 0 is best done the portable way for A an integer.
11287 (define_expand "sle"
11288 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11292 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11295 rs6000_emit_sCOND (LE, operands[0]);
11299 ;; A < 0 is best done in the portable way for A an integer.
11300 (define_expand "slt"
11301 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11305 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11308 rs6000_emit_sCOND (LT, operands[0]);
11312 (define_expand "sgeu"
11313 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11315 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11317 (define_expand "sgtu"
11318 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11320 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11322 (define_expand "sleu"
11323 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11325 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11327 (define_expand "sltu"
11328 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11330 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11332 (define_expand "sunordered"
11333 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11334 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11335 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11337 (define_expand "sordered"
11338 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11339 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11340 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11342 (define_expand "suneq"
11343 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11345 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11347 (define_expand "sunge"
11348 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11350 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11352 (define_expand "sungt"
11353 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11355 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11357 (define_expand "sunle"
11358 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11360 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11362 (define_expand "sunlt"
11363 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11365 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11367 (define_expand "sltgt"
11368 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11370 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11372 (define_expand "stack_protect_set"
11373 [(match_operand 0 "memory_operand" "")
11374 (match_operand 1 "memory_operand" "")]
11377 #ifdef TARGET_THREAD_SSP_OFFSET
11378 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11379 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11380 operands[1] = gen_rtx_MEM (Pmode, addr);
11383 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11385 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11389 (define_insn "stack_protect_setsi"
11390 [(set (match_operand:SI 0 "memory_operand" "=m")
11391 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11392 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11394 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11395 [(set_attr "type" "three")
11396 (set_attr "length" "12")])
11398 (define_insn "stack_protect_setdi"
11399 [(set (match_operand:DI 0 "memory_operand" "=m")
11400 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11401 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11403 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11404 [(set_attr "type" "three")
11405 (set_attr "length" "12")])
11407 (define_expand "stack_protect_test"
11408 [(match_operand 0 "memory_operand" "")
11409 (match_operand 1 "memory_operand" "")
11410 (match_operand 2 "" "")]
11413 #ifdef TARGET_THREAD_SSP_OFFSET
11414 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11415 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11416 operands[1] = gen_rtx_MEM (Pmode, addr);
11418 rs6000_compare_op0 = operands[0];
11419 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11421 rs6000_compare_fp_p = 0;
11422 emit_jump_insn (gen_beq (operands[2]));
11426 (define_insn "stack_protect_testsi"
11427 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11428 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11429 (match_operand:SI 2 "memory_operand" "m,m")]
11431 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11432 (clobber (match_scratch:SI 3 "=&r,&r"))]
11435 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11436 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11437 [(set_attr "length" "16,20")])
11439 (define_insn "stack_protect_testdi"
11440 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11441 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11442 (match_operand:DI 2 "memory_operand" "m,m")]
11444 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11445 (clobber (match_scratch:DI 3 "=&r,&r"))]
11448 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11449 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11450 [(set_attr "length" "16,20")])
11453 ;; Here are the actual compare insns.
11454 (define_insn "*cmp<mode>_internal1"
11455 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11456 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11457 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11459 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11460 [(set_attr "type" "cmp")])
11462 ;; If we are comparing a register for equality with a large constant,
11463 ;; we can do this with an XOR followed by a compare. But this is profitable
11464 ;; only if the large constant is only used for the comparison (and in this
11465 ;; case we already have a register to reuse as scratch).
11467 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11468 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11471 [(set (match_operand:SI 0 "register_operand")
11472 (match_operand:SI 1 "logical_const_operand" ""))
11473 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11475 (match_operand:SI 2 "logical_const_operand" "")]))
11476 (set (match_operand:CC 4 "cc_reg_operand" "")
11477 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11480 (if_then_else (match_operator 6 "equality_operator"
11481 [(match_dup 4) (const_int 0)])
11482 (match_operand 7 "" "")
11483 (match_operand 8 "" "")))]
11484 "peep2_reg_dead_p (3, operands[0])
11485 && peep2_reg_dead_p (4, operands[4])"
11486 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11487 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11488 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11491 /* Get the constant we are comparing against, and see what it looks like
11492 when sign-extended from 16 to 32 bits. Then see what constant we could
11493 XOR with SEXTC to get the sign-extended value. */
11494 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11496 operands[1], operands[2]);
11497 HOST_WIDE_INT c = INTVAL (cnst);
11498 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11499 HOST_WIDE_INT xorv = c ^ sextc;
11501 operands[9] = GEN_INT (xorv);
11502 operands[10] = GEN_INT (sextc);
11505 (define_insn "*cmpsi_internal2"
11506 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11507 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11508 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11510 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11511 [(set_attr "type" "cmp")])
11513 (define_insn "*cmpdi_internal2"
11514 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11515 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11516 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11518 "cmpld%I2 %0,%1,%b2"
11519 [(set_attr "type" "cmp")])
11521 ;; The following two insns don't exist as single insns, but if we provide
11522 ;; them, we can swap an add and compare, which will enable us to overlap more
11523 ;; of the required delay between a compare and branch. We generate code for
11524 ;; them by splitting.
11527 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11528 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11529 (match_operand:SI 2 "short_cint_operand" "i")))
11530 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11531 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11534 [(set_attr "length" "8")])
11537 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11538 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11539 (match_operand:SI 2 "u_short_cint_operand" "i")))
11540 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11541 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11544 [(set_attr "length" "8")])
11547 [(set (match_operand:CC 3 "cc_reg_operand" "")
11548 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11549 (match_operand:SI 2 "short_cint_operand" "")))
11550 (set (match_operand:SI 0 "gpc_reg_operand" "")
11551 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11553 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11554 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11557 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11558 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11559 (match_operand:SI 2 "u_short_cint_operand" "")))
11560 (set (match_operand:SI 0 "gpc_reg_operand" "")
11561 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11563 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11564 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11566 (define_insn "*cmpsf_internal1"
11567 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11568 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11569 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11570 "TARGET_HARD_FLOAT && TARGET_FPRS"
11572 [(set_attr "type" "fpcompare")])
11574 (define_insn "*cmpdf_internal1"
11575 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11576 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11577 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11578 "TARGET_HARD_FLOAT && TARGET_FPRS"
11580 [(set_attr "type" "fpcompare")])
11582 ;; Only need to compare second words if first words equal
11583 (define_insn "*cmptf_internal1"
11584 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11585 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11586 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11587 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11588 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11589 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11590 [(set_attr "type" "fpcompare")
11591 (set_attr "length" "12")])
11593 (define_insn_and_split "*cmptf_internal2"
11594 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11595 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11596 (match_operand:TF 2 "gpc_reg_operand" "f")))
11597 (clobber (match_scratch:DF 3 "=f"))
11598 (clobber (match_scratch:DF 4 "=f"))
11599 (clobber (match_scratch:DF 5 "=f"))
11600 (clobber (match_scratch:DF 6 "=f"))
11601 (clobber (match_scratch:DF 7 "=f"))
11602 (clobber (match_scratch:DF 8 "=f"))
11603 (clobber (match_scratch:DF 9 "=f"))
11604 (clobber (match_scratch:DF 10 "=f"))]
11605 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11606 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11608 "&& reload_completed"
11609 [(set (match_dup 3) (match_dup 13))
11610 (set (match_dup 4) (match_dup 14))
11611 (set (match_dup 9) (abs:DF (match_dup 5)))
11612 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11613 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11614 (label_ref (match_dup 11))
11616 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11617 (set (pc) (label_ref (match_dup 12)))
11619 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11620 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11621 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11622 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11625 REAL_VALUE_TYPE rv;
11626 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11627 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11629 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11630 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11631 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11632 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11633 operands[11] = gen_label_rtx ();
11634 operands[12] = gen_label_rtx ();
11636 operands[13] = force_const_mem (DFmode,
11637 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11638 operands[14] = force_const_mem (DFmode,
11639 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11643 operands[13] = gen_const_mem (DFmode,
11644 create_TOC_reference (XEXP (operands[13], 0)));
11645 operands[14] = gen_const_mem (DFmode,
11646 create_TOC_reference (XEXP (operands[14], 0)));
11647 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11648 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11652 ;; Now we have the scc insns. We can do some combinations because of the
11653 ;; way the machine works.
11655 ;; Note that this is probably faster if we can put an insn between the
11656 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11657 ;; cases the insns below which don't use an intermediate CR field will
11658 ;; be used instead.
11660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11661 (match_operator:SI 1 "scc_comparison_operator"
11662 [(match_operand 2 "cc_reg_operand" "y")
11665 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11666 [(set (attr "type")
11667 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11668 (const_string "mfcrf")
11670 (const_string "mfcr")))
11671 (set_attr "length" "8")])
11673 ;; Same as above, but get the GT bit.
11674 (define_insn "move_from_CR_gt_bit"
11675 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11676 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11678 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11679 [(set_attr "type" "mfcr")
11680 (set_attr "length" "8")])
11682 ;; Same as above, but get the OV/ORDERED bit.
11683 (define_insn "move_from_CR_ov_bit"
11684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11685 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11687 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11688 [(set_attr "type" "mfcr")
11689 (set_attr "length" "8")])
11692 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11693 (match_operator:DI 1 "scc_comparison_operator"
11694 [(match_operand 2 "cc_reg_operand" "y")
11697 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11698 [(set (attr "type")
11699 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11700 (const_string "mfcrf")
11702 (const_string "mfcr")))
11703 (set_attr "length" "8")])
11706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11707 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11708 [(match_operand 2 "cc_reg_operand" "y,y")
11711 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11712 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11715 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11717 [(set_attr "type" "delayed_compare")
11718 (set_attr "length" "8,16")])
11721 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11722 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11723 [(match_operand 2 "cc_reg_operand" "")
11726 (set (match_operand:SI 3 "gpc_reg_operand" "")
11727 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11728 "TARGET_32BIT && reload_completed"
11729 [(set (match_dup 3)
11730 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11732 (compare:CC (match_dup 3)
11737 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11738 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11739 [(match_operand 2 "cc_reg_operand" "y")
11741 (match_operand:SI 3 "const_int_operand" "n")))]
11745 int is_bit = ccr_bit (operands[1], 1);
11746 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11749 if (is_bit >= put_bit)
11750 count = is_bit - put_bit;
11752 count = 32 - (put_bit - is_bit);
11754 operands[4] = GEN_INT (count);
11755 operands[5] = GEN_INT (put_bit);
11757 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11759 [(set (attr "type")
11760 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11761 (const_string "mfcrf")
11763 (const_string "mfcr")))
11764 (set_attr "length" "8")])
11767 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11769 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11770 [(match_operand 2 "cc_reg_operand" "y,y")
11772 (match_operand:SI 3 "const_int_operand" "n,n"))
11774 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11775 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11780 int is_bit = ccr_bit (operands[1], 1);
11781 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11784 /* Force split for non-cc0 compare. */
11785 if (which_alternative == 1)
11788 if (is_bit >= put_bit)
11789 count = is_bit - put_bit;
11791 count = 32 - (put_bit - is_bit);
11793 operands[5] = GEN_INT (count);
11794 operands[6] = GEN_INT (put_bit);
11796 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11798 [(set_attr "type" "delayed_compare")
11799 (set_attr "length" "8,16")])
11802 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11804 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11805 [(match_operand 2 "cc_reg_operand" "")
11807 (match_operand:SI 3 "const_int_operand" ""))
11809 (set (match_operand:SI 4 "gpc_reg_operand" "")
11810 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11813 [(set (match_dup 4)
11814 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11817 (compare:CC (match_dup 4)
11821 ;; There is a 3 cycle delay between consecutive mfcr instructions
11822 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11825 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11826 (match_operator:SI 1 "scc_comparison_operator"
11827 [(match_operand 2 "cc_reg_operand" "y")
11829 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11830 (match_operator:SI 4 "scc_comparison_operator"
11831 [(match_operand 5 "cc_reg_operand" "y")
11833 "REGNO (operands[2]) != REGNO (operands[5])"
11834 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11835 [(set_attr "type" "mfcr")
11836 (set_attr "length" "12")])
11839 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11840 (match_operator:DI 1 "scc_comparison_operator"
11841 [(match_operand 2 "cc_reg_operand" "y")
11843 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11844 (match_operator:DI 4 "scc_comparison_operator"
11845 [(match_operand 5 "cc_reg_operand" "y")
11847 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11848 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11849 [(set_attr "type" "mfcr")
11850 (set_attr "length" "12")])
11852 ;; There are some scc insns that can be done directly, without a compare.
11853 ;; These are faster because they don't involve the communications between
11854 ;; the FXU and branch units. In fact, we will be replacing all of the
11855 ;; integer scc insns here or in the portable methods in emit_store_flag.
11857 ;; Also support (neg (scc ..)) since that construct is used to replace
11858 ;; branches, (plus (scc ..) ..) since that construct is common and
11859 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11860 ;; cases where it is no more expensive than (neg (scc ..)).
11862 ;; Have reload force a constant into a register for the simple insns that
11863 ;; otherwise won't accept constants. We do this because it is faster than
11864 ;; the cmp/mfcr sequence we would otherwise generate.
11866 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11869 (define_insn_and_split "*eq<mode>"
11870 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11871 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11872 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11876 [(set (match_dup 0)
11877 (clz:GPR (match_dup 3)))
11879 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11881 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11883 /* Use output operand as intermediate. */
11884 operands[3] = operands[0];
11886 if (logical_operand (operands[2], <MODE>mode))
11887 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11888 gen_rtx_XOR (<MODE>mode,
11889 operands[1], operands[2])));
11891 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11892 gen_rtx_PLUS (<MODE>mode, operands[1],
11893 negate_rtx (<MODE>mode,
11897 operands[3] = operands[1];
11899 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11902 (define_insn_and_split "*eq<mode>_compare"
11903 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11905 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11906 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11908 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11909 (eq:P (match_dup 1) (match_dup 2)))]
11910 "!TARGET_POWER && optimize_size"
11912 "!TARGET_POWER && optimize_size"
11913 [(set (match_dup 0)
11914 (clz:P (match_dup 4)))
11915 (parallel [(set (match_dup 3)
11916 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11919 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11921 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11923 /* Use output operand as intermediate. */
11924 operands[4] = operands[0];
11926 if (logical_operand (operands[2], <MODE>mode))
11927 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11928 gen_rtx_XOR (<MODE>mode,
11929 operands[1], operands[2])));
11931 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11932 gen_rtx_PLUS (<MODE>mode, operands[1],
11933 negate_rtx (<MODE>mode,
11937 operands[4] = operands[1];
11939 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11942 (define_insn "*eqsi_power"
11943 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11944 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11945 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11946 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11949 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11950 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11951 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11952 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11953 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11954 [(set_attr "type" "three,two,three,three,three")
11955 (set_attr "length" "12,8,12,12,12")])
11957 ;; We have insns of the form shown by the first define_insn below. If
11958 ;; there is something inside the comparison operation, we must split it.
11960 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11961 (plus:SI (match_operator 1 "comparison_operator"
11962 [(match_operand:SI 2 "" "")
11963 (match_operand:SI 3
11964 "reg_or_cint_operand" "")])
11965 (match_operand:SI 4 "gpc_reg_operand" "")))
11966 (clobber (match_operand:SI 5 "register_operand" ""))]
11967 "! gpc_reg_operand (operands[2], SImode)"
11968 [(set (match_dup 5) (match_dup 2))
11969 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11972 (define_insn "*plus_eqsi"
11973 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11974 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11975 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11976 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11979 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11980 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11981 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11982 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11983 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11984 [(set_attr "type" "three,two,three,three,three")
11985 (set_attr "length" "12,8,12,12,12")])
11987 (define_insn "*compare_plus_eqsi"
11988 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11991 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11992 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11993 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11995 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11996 "TARGET_32BIT && optimize_size"
11998 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11999 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12000 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12001 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12002 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12008 [(set_attr "type" "compare")
12009 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12012 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12015 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12016 (match_operand:SI 2 "scc_eq_operand" ""))
12017 (match_operand:SI 3 "gpc_reg_operand" ""))
12019 (clobber (match_scratch:SI 4 ""))]
12020 "TARGET_32BIT && optimize_size && reload_completed"
12021 [(set (match_dup 4)
12022 (plus:SI (eq:SI (match_dup 1)
12026 (compare:CC (match_dup 4)
12030 (define_insn "*plus_eqsi_compare"
12031 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12034 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12035 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12036 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12038 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12039 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12040 "TARGET_32BIT && optimize_size"
12042 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12043 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12044 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12045 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12046 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12052 [(set_attr "type" "compare")
12053 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12056 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12059 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12060 (match_operand:SI 2 "scc_eq_operand" ""))
12061 (match_operand:SI 3 "gpc_reg_operand" ""))
12063 (set (match_operand:SI 0 "gpc_reg_operand" "")
12064 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12065 "TARGET_32BIT && optimize_size && reload_completed"
12066 [(set (match_dup 0)
12067 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12069 (compare:CC (match_dup 0)
12073 (define_insn "*neg_eq0<mode>"
12074 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12075 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12078 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12079 [(set_attr "type" "two")
12080 (set_attr "length" "8")])
12082 (define_insn_and_split "*neg_eq<mode>"
12083 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12084 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12085 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12089 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12091 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12093 /* Use output operand as intermediate. */
12094 operands[3] = operands[0];
12096 if (logical_operand (operands[2], <MODE>mode))
12097 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12098 gen_rtx_XOR (<MODE>mode,
12099 operands[1], operands[2])));
12101 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12102 gen_rtx_PLUS (<MODE>mode, operands[1],
12103 negate_rtx (<MODE>mode,
12107 operands[3] = operands[1];
12110 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12111 ;; since it nabs/sr is just as fast.
12112 (define_insn "*ne0si"
12113 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12114 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12116 (clobber (match_scratch:SI 2 "=&r"))]
12117 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12118 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12119 [(set_attr "type" "two")
12120 (set_attr "length" "8")])
12122 (define_insn "*ne0di"
12123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12124 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12126 (clobber (match_scratch:DI 2 "=&r"))]
12128 "addic %2,%1,-1\;subfe %0,%2,%1"
12129 [(set_attr "type" "two")
12130 (set_attr "length" "8")])
12132 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12133 (define_insn "*plus_ne0si"
12134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12135 (plus:SI (lshiftrt:SI
12136 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12138 (match_operand:SI 2 "gpc_reg_operand" "r")))
12139 (clobber (match_scratch:SI 3 "=&r"))]
12141 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12142 [(set_attr "type" "two")
12143 (set_attr "length" "8")])
12145 (define_insn "*plus_ne0di"
12146 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12147 (plus:DI (lshiftrt:DI
12148 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12150 (match_operand:DI 2 "gpc_reg_operand" "r")))
12151 (clobber (match_scratch:DI 3 "=&r"))]
12153 "addic %3,%1,-1\;addze %0,%2"
12154 [(set_attr "type" "two")
12155 (set_attr "length" "8")])
12157 (define_insn "*compare_plus_ne0si"
12158 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12160 (plus:SI (lshiftrt:SI
12161 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12163 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12165 (clobber (match_scratch:SI 3 "=&r,&r"))
12166 (clobber (match_scratch:SI 4 "=X,&r"))]
12169 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12171 [(set_attr "type" "compare")
12172 (set_attr "length" "8,12")])
12175 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12177 (plus:SI (lshiftrt:SI
12178 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12180 (match_operand:SI 2 "gpc_reg_operand" ""))
12182 (clobber (match_scratch:SI 3 ""))
12183 (clobber (match_scratch:SI 4 ""))]
12184 "TARGET_32BIT && reload_completed"
12185 [(parallel [(set (match_dup 3)
12186 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12189 (clobber (match_dup 4))])
12191 (compare:CC (match_dup 3)
12195 (define_insn "*compare_plus_ne0di"
12196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12198 (plus:DI (lshiftrt:DI
12199 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12201 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12203 (clobber (match_scratch:DI 3 "=&r,&r"))]
12206 addic %3,%1,-1\;addze. %3,%2
12208 [(set_attr "type" "compare")
12209 (set_attr "length" "8,12")])
12212 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12214 (plus:DI (lshiftrt:DI
12215 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12217 (match_operand:DI 2 "gpc_reg_operand" ""))
12219 (clobber (match_scratch:DI 3 ""))]
12220 "TARGET_64BIT && reload_completed"
12221 [(set (match_dup 3)
12222 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12226 (compare:CC (match_dup 3)
12230 (define_insn "*plus_ne0si_compare"
12231 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12233 (plus:SI (lshiftrt:SI
12234 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12236 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12238 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12239 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12241 (clobber (match_scratch:SI 3 "=&r,&r"))]
12244 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12246 [(set_attr "type" "compare")
12247 (set_attr "length" "8,12")])
12250 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12252 (plus:SI (lshiftrt:SI
12253 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12255 (match_operand:SI 2 "gpc_reg_operand" ""))
12257 (set (match_operand:SI 0 "gpc_reg_operand" "")
12258 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12260 (clobber (match_scratch:SI 3 ""))]
12261 "TARGET_32BIT && reload_completed"
12262 [(parallel [(set (match_dup 0)
12263 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12265 (clobber (match_dup 3))])
12267 (compare:CC (match_dup 0)
12271 (define_insn "*plus_ne0di_compare"
12272 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12274 (plus:DI (lshiftrt:DI
12275 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12277 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12279 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12280 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12282 (clobber (match_scratch:DI 3 "=&r,&r"))]
12285 addic %3,%1,-1\;addze. %0,%2
12287 [(set_attr "type" "compare")
12288 (set_attr "length" "8,12")])
12291 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12293 (plus:DI (lshiftrt:DI
12294 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12296 (match_operand:DI 2 "gpc_reg_operand" ""))
12298 (set (match_operand:DI 0 "gpc_reg_operand" "")
12299 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12301 (clobber (match_scratch:DI 3 ""))]
12302 "TARGET_64BIT && reload_completed"
12303 [(parallel [(set (match_dup 0)
12304 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12306 (clobber (match_dup 3))])
12308 (compare:CC (match_dup 0)
12313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12314 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12315 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12316 (clobber (match_scratch:SI 3 "=r,X"))]
12319 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12320 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12321 [(set_attr "length" "12")])
12324 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12326 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12327 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12329 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12330 (le:SI (match_dup 1) (match_dup 2)))
12331 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12334 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12335 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12338 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12339 (set_attr "length" "12,12,16,16")])
12342 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12344 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12345 (match_operand:SI 2 "reg_or_short_operand" ""))
12347 (set (match_operand:SI 0 "gpc_reg_operand" "")
12348 (le:SI (match_dup 1) (match_dup 2)))
12349 (clobber (match_scratch:SI 3 ""))]
12350 "TARGET_POWER && reload_completed"
12351 [(parallel [(set (match_dup 0)
12352 (le:SI (match_dup 1) (match_dup 2)))
12353 (clobber (match_dup 3))])
12355 (compare:CC (match_dup 0)
12360 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12361 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12362 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12363 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12366 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12367 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12368 [(set_attr "length" "12")])
12371 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12373 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12374 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12375 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12377 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12380 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12381 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12384 [(set_attr "type" "compare")
12385 (set_attr "length" "12,12,16,16")])
12388 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12390 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12391 (match_operand:SI 2 "reg_or_short_operand" ""))
12392 (match_operand:SI 3 "gpc_reg_operand" ""))
12394 (clobber (match_scratch:SI 4 ""))]
12395 "TARGET_POWER && reload_completed"
12396 [(set (match_dup 4)
12397 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12400 (compare:CC (match_dup 4)
12405 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12407 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12408 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12409 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12411 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12412 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12415 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12416 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12419 [(set_attr "type" "compare")
12420 (set_attr "length" "12,12,16,16")])
12423 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12425 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12426 (match_operand:SI 2 "reg_or_short_operand" ""))
12427 (match_operand:SI 3 "gpc_reg_operand" ""))
12429 (set (match_operand:SI 0 "gpc_reg_operand" "")
12430 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12431 "TARGET_POWER && reload_completed"
12432 [(set (match_dup 0)
12433 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12435 (compare:CC (match_dup 0)
12440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12441 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12442 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12445 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12446 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12447 [(set_attr "length" "12")])
12449 (define_insn "*leu<mode>"
12450 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12451 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12452 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12454 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12455 [(set_attr "type" "three")
12456 (set_attr "length" "12")])
12458 (define_insn "*leu<mode>_compare"
12459 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12461 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12462 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12464 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12465 (leu:P (match_dup 1) (match_dup 2)))]
12468 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12470 [(set_attr "type" "compare")
12471 (set_attr "length" "12,16")])
12474 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12476 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12477 (match_operand:P 2 "reg_or_short_operand" ""))
12479 (set (match_operand:P 0 "gpc_reg_operand" "")
12480 (leu:P (match_dup 1) (match_dup 2)))]
12482 [(set (match_dup 0)
12483 (leu:P (match_dup 1) (match_dup 2)))
12485 (compare:CC (match_dup 0)
12489 (define_insn "*plus_leu<mode>"
12490 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12491 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12492 (match_operand:P 2 "reg_or_short_operand" "rI"))
12493 (match_operand:P 3 "gpc_reg_operand" "r")))]
12495 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12496 [(set_attr "type" "two")
12497 (set_attr "length" "8")])
12500 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12502 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12503 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12504 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12506 (clobber (match_scratch:SI 4 "=&r,&r"))]
12509 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12511 [(set_attr "type" "compare")
12512 (set_attr "length" "8,12")])
12515 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12517 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12518 (match_operand:SI 2 "reg_or_short_operand" ""))
12519 (match_operand:SI 3 "gpc_reg_operand" ""))
12521 (clobber (match_scratch:SI 4 ""))]
12522 "TARGET_32BIT && reload_completed"
12523 [(set (match_dup 4)
12524 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12527 (compare:CC (match_dup 4)
12532 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12534 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12535 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12536 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12538 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12539 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12542 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12544 [(set_attr "type" "compare")
12545 (set_attr "length" "8,12")])
12548 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12550 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12551 (match_operand:SI 2 "reg_or_short_operand" ""))
12552 (match_operand:SI 3 "gpc_reg_operand" ""))
12554 (set (match_operand:SI 0 "gpc_reg_operand" "")
12555 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12556 "TARGET_32BIT && reload_completed"
12557 [(set (match_dup 0)
12558 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12560 (compare:CC (match_dup 0)
12564 (define_insn "*neg_leu<mode>"
12565 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12566 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12567 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12569 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12570 [(set_attr "type" "three")
12571 (set_attr "length" "12")])
12573 (define_insn "*and_neg_leu<mode>"
12574 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12576 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12577 (match_operand:P 2 "reg_or_short_operand" "rI")))
12578 (match_operand:P 3 "gpc_reg_operand" "r")))]
12580 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12581 [(set_attr "type" "three")
12582 (set_attr "length" "12")])
12585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12588 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12589 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12590 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12592 (clobber (match_scratch:SI 4 "=&r,&r"))]
12595 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12597 [(set_attr "type" "compare")
12598 (set_attr "length" "12,16")])
12601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12604 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12605 (match_operand:SI 2 "reg_or_short_operand" "")))
12606 (match_operand:SI 3 "gpc_reg_operand" ""))
12608 (clobber (match_scratch:SI 4 ""))]
12609 "TARGET_32BIT && reload_completed"
12610 [(set (match_dup 4)
12611 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12614 (compare:CC (match_dup 4)
12619 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12622 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12623 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12624 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12626 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12627 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12630 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12632 [(set_attr "type" "compare")
12633 (set_attr "length" "12,16")])
12636 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12639 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12640 (match_operand:SI 2 "reg_or_short_operand" "")))
12641 (match_operand:SI 3 "gpc_reg_operand" ""))
12643 (set (match_operand:SI 0 "gpc_reg_operand" "")
12644 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12645 "TARGET_32BIT && reload_completed"
12646 [(set (match_dup 0)
12647 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12650 (compare:CC (match_dup 0)
12655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12656 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12657 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12659 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12660 [(set_attr "length" "12")])
12663 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12665 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12666 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12668 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12669 (lt:SI (match_dup 1) (match_dup 2)))]
12672 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12674 [(set_attr "type" "delayed_compare")
12675 (set_attr "length" "12,16")])
12678 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12680 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12681 (match_operand:SI 2 "reg_or_short_operand" ""))
12683 (set (match_operand:SI 0 "gpc_reg_operand" "")
12684 (lt:SI (match_dup 1) (match_dup 2)))]
12685 "TARGET_POWER && reload_completed"
12686 [(set (match_dup 0)
12687 (lt:SI (match_dup 1) (match_dup 2)))
12689 (compare:CC (match_dup 0)
12694 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12695 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12696 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12697 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12699 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12700 [(set_attr "length" "12")])
12703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12705 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12706 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12707 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12709 (clobber (match_scratch:SI 4 "=&r,&r"))]
12712 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12714 [(set_attr "type" "compare")
12715 (set_attr "length" "12,16")])
12718 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12720 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12721 (match_operand:SI 2 "reg_or_short_operand" ""))
12722 (match_operand:SI 3 "gpc_reg_operand" ""))
12724 (clobber (match_scratch:SI 4 ""))]
12725 "TARGET_POWER && reload_completed"
12726 [(set (match_dup 4)
12727 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12730 (compare:CC (match_dup 4)
12735 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12737 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12738 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12739 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12741 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12742 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12745 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12747 [(set_attr "type" "compare")
12748 (set_attr "length" "12,16")])
12751 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12753 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12754 (match_operand:SI 2 "reg_or_short_operand" ""))
12755 (match_operand:SI 3 "gpc_reg_operand" ""))
12757 (set (match_operand:SI 0 "gpc_reg_operand" "")
12758 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12759 "TARGET_POWER && reload_completed"
12760 [(set (match_dup 0)
12761 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12763 (compare:CC (match_dup 0)
12768 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12769 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12770 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12772 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12773 [(set_attr "length" "12")])
12775 (define_insn_and_split "*ltu<mode>"
12776 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12777 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12778 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12782 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12783 (set (match_dup 0) (neg:P (match_dup 0)))]
12786 (define_insn_and_split "*ltu<mode>_compare"
12787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12789 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12790 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12792 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12793 (ltu:P (match_dup 1) (match_dup 2)))]
12797 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12798 (parallel [(set (match_dup 3)
12799 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12800 (set (match_dup 0) (neg:P (match_dup 0)))])]
12803 (define_insn_and_split "*plus_ltu<mode>"
12804 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12805 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12806 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12807 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12810 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12811 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12812 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12815 (define_insn_and_split "*plus_ltu<mode>_compare"
12816 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12818 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12819 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12820 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12822 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12823 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12826 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12827 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12828 (parallel [(set (match_dup 4)
12829 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12831 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12834 (define_insn "*neg_ltu<mode>"
12835 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12836 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12837 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12840 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12841 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12842 [(set_attr "type" "two")
12843 (set_attr "length" "8")])
12846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12847 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12848 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12849 (clobber (match_scratch:SI 3 "=r"))]
12851 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12852 [(set_attr "length" "12")])
12855 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12857 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12858 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12860 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12861 (ge:SI (match_dup 1) (match_dup 2)))
12862 (clobber (match_scratch:SI 3 "=r,r"))]
12865 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12867 [(set_attr "type" "compare")
12868 (set_attr "length" "12,16")])
12871 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12873 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12874 (match_operand:SI 2 "reg_or_short_operand" ""))
12876 (set (match_operand:SI 0 "gpc_reg_operand" "")
12877 (ge:SI (match_dup 1) (match_dup 2)))
12878 (clobber (match_scratch:SI 3 ""))]
12879 "TARGET_POWER && reload_completed"
12880 [(parallel [(set (match_dup 0)
12881 (ge:SI (match_dup 1) (match_dup 2)))
12882 (clobber (match_dup 3))])
12884 (compare:CC (match_dup 0)
12889 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12890 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12891 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12892 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12894 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12895 [(set_attr "length" "12")])
12898 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12900 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12901 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12902 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12904 (clobber (match_scratch:SI 4 "=&r,&r"))]
12907 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12909 [(set_attr "type" "compare")
12910 (set_attr "length" "12,16")])
12913 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12915 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12916 (match_operand:SI 2 "reg_or_short_operand" ""))
12917 (match_operand:SI 3 "gpc_reg_operand" ""))
12919 (clobber (match_scratch:SI 4 ""))]
12920 "TARGET_POWER && reload_completed"
12921 [(set (match_dup 4)
12922 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12925 (compare:CC (match_dup 4)
12930 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12932 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12933 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12934 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12936 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12937 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12940 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12942 [(set_attr "type" "compare")
12943 (set_attr "length" "12,16")])
12946 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12948 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12949 (match_operand:SI 2 "reg_or_short_operand" ""))
12950 (match_operand:SI 3 "gpc_reg_operand" ""))
12952 (set (match_operand:SI 0 "gpc_reg_operand" "")
12953 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12954 "TARGET_POWER && reload_completed"
12955 [(set (match_dup 0)
12956 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12958 (compare:CC (match_dup 0)
12963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12964 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12965 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12967 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12968 [(set_attr "length" "12")])
12970 (define_insn "*geu<mode>"
12971 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12972 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12973 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12976 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12977 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12978 [(set_attr "type" "three")
12979 (set_attr "length" "12")])
12981 (define_insn "*geu<mode>_compare"
12982 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12984 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12985 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12987 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12988 (geu:P (match_dup 1) (match_dup 2)))]
12991 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12992 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12995 [(set_attr "type" "compare")
12996 (set_attr "length" "12,12,16,16")])
12999 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13001 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13002 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13004 (set (match_operand:P 0 "gpc_reg_operand" "")
13005 (geu:P (match_dup 1) (match_dup 2)))]
13007 [(set (match_dup 0)
13008 (geu:P (match_dup 1) (match_dup 2)))
13010 (compare:CC (match_dup 0)
13014 (define_insn "*plus_geu<mode>"
13015 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13016 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13017 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13018 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13021 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13022 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13023 [(set_attr "type" "two")
13024 (set_attr "length" "8")])
13027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13029 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13030 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13031 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13033 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13036 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13037 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13040 [(set_attr "type" "compare")
13041 (set_attr "length" "8,8,12,12")])
13044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13046 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13047 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13048 (match_operand:SI 3 "gpc_reg_operand" ""))
13050 (clobber (match_scratch:SI 4 ""))]
13051 "TARGET_32BIT && reload_completed"
13052 [(set (match_dup 4)
13053 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13056 (compare:CC (match_dup 4)
13061 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13063 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13064 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13065 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13067 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13068 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13071 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13072 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13075 [(set_attr "type" "compare")
13076 (set_attr "length" "8,8,12,12")])
13079 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13081 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13082 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13083 (match_operand:SI 3 "gpc_reg_operand" ""))
13085 (set (match_operand:SI 0 "gpc_reg_operand" "")
13086 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13087 "TARGET_32BIT && reload_completed"
13088 [(set (match_dup 0)
13089 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13091 (compare:CC (match_dup 0)
13095 (define_insn "*neg_geu<mode>"
13096 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13097 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13098 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13101 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13102 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13103 [(set_attr "type" "three")
13104 (set_attr "length" "12")])
13106 (define_insn "*and_neg_geu<mode>"
13107 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13109 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13110 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13111 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13114 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13115 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13116 [(set_attr "type" "three")
13117 (set_attr "length" "12")])
13120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13123 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13124 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13125 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13127 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13130 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13131 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13134 [(set_attr "type" "compare")
13135 (set_attr "length" "12,12,16,16")])
13138 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13141 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13142 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13143 (match_operand:SI 3 "gpc_reg_operand" ""))
13145 (clobber (match_scratch:SI 4 ""))]
13146 "TARGET_32BIT && reload_completed"
13147 [(set (match_dup 4)
13148 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13151 (compare:CC (match_dup 4)
13156 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13159 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13160 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13161 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13163 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13164 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13167 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13168 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13171 [(set_attr "type" "compare")
13172 (set_attr "length" "12,12,16,16")])
13175 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13178 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13179 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13180 (match_operand:SI 3 "gpc_reg_operand" ""))
13182 (set (match_operand:SI 0 "gpc_reg_operand" "")
13183 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13184 "TARGET_32BIT && reload_completed"
13185 [(set (match_dup 0)
13186 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13188 (compare:CC (match_dup 0)
13193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13194 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13195 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13197 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13198 [(set_attr "length" "12")])
13201 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13203 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13204 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13206 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13207 (gt:SI (match_dup 1) (match_dup 2)))]
13210 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13212 [(set_attr "type" "delayed_compare")
13213 (set_attr "length" "12,16")])
13216 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13218 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13219 (match_operand:SI 2 "reg_or_short_operand" ""))
13221 (set (match_operand:SI 0 "gpc_reg_operand" "")
13222 (gt:SI (match_dup 1) (match_dup 2)))]
13223 "TARGET_POWER && reload_completed"
13224 [(set (match_dup 0)
13225 (gt:SI (match_dup 1) (match_dup 2)))
13227 (compare:CC (match_dup 0)
13231 (define_insn "*plus_gt0<mode>"
13232 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13233 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13235 (match_operand:P 2 "gpc_reg_operand" "r")))]
13237 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13238 [(set_attr "type" "three")
13239 (set_attr "length" "12")])
13242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13244 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13246 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13248 (clobber (match_scratch:SI 3 "=&r,&r"))]
13251 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13253 [(set_attr "type" "compare")
13254 (set_attr "length" "12,16")])
13257 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13259 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13261 (match_operand:SI 2 "gpc_reg_operand" ""))
13263 (clobber (match_scratch:SI 3 ""))]
13264 "TARGET_32BIT && reload_completed"
13265 [(set (match_dup 3)
13266 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13269 (compare:CC (match_dup 3)
13274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13276 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13278 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13280 (clobber (match_scratch:DI 3 "=&r,&r"))]
13283 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13285 [(set_attr "type" "compare")
13286 (set_attr "length" "12,16")])
13289 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13291 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13293 (match_operand:DI 2 "gpc_reg_operand" ""))
13295 (clobber (match_scratch:DI 3 ""))]
13296 "TARGET_64BIT && reload_completed"
13297 [(set (match_dup 3)
13298 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13301 (compare:CC (match_dup 3)
13306 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13308 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13310 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13312 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13313 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13316 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13318 [(set_attr "type" "compare")
13319 (set_attr "length" "12,16")])
13322 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13324 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13326 (match_operand:SI 2 "gpc_reg_operand" ""))
13328 (set (match_operand:SI 0 "gpc_reg_operand" "")
13329 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13330 "TARGET_32BIT && reload_completed"
13331 [(set (match_dup 0)
13332 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13334 (compare:CC (match_dup 0)
13339 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13341 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13343 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13345 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13346 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13349 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13351 [(set_attr "type" "compare")
13352 (set_attr "length" "12,16")])
13355 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13357 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13359 (match_operand:DI 2 "gpc_reg_operand" ""))
13361 (set (match_operand:DI 0 "gpc_reg_operand" "")
13362 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13363 "TARGET_64BIT && reload_completed"
13364 [(set (match_dup 0)
13365 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13367 (compare:CC (match_dup 0)
13372 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13373 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13374 (match_operand:SI 2 "reg_or_short_operand" "r"))
13375 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13377 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13378 [(set_attr "length" "12")])
13381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13383 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13384 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13385 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13387 (clobber (match_scratch:SI 4 "=&r,&r"))]
13390 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13392 [(set_attr "type" "compare")
13393 (set_attr "length" "12,16")])
13396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13398 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13399 (match_operand:SI 2 "reg_or_short_operand" ""))
13400 (match_operand:SI 3 "gpc_reg_operand" ""))
13402 (clobber (match_scratch:SI 4 ""))]
13403 "TARGET_POWER && reload_completed"
13404 [(set (match_dup 4)
13405 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13407 (compare:CC (match_dup 4)
13412 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13414 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13415 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13416 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13418 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13419 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13422 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13424 [(set_attr "type" "compare")
13425 (set_attr "length" "12,16")])
13428 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13430 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13431 (match_operand:SI 2 "reg_or_short_operand" ""))
13432 (match_operand:SI 3 "gpc_reg_operand" ""))
13434 (set (match_operand:SI 0 "gpc_reg_operand" "")
13435 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13436 "TARGET_POWER && reload_completed"
13437 [(set (match_dup 0)
13438 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13440 (compare:CC (match_dup 0)
13445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13446 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13447 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13449 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13450 [(set_attr "length" "12")])
13452 (define_insn_and_split "*gtu<mode>"
13453 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13454 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13455 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13459 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13460 (set (match_dup 0) (neg:P (match_dup 0)))]
13463 (define_insn_and_split "*gtu<mode>_compare"
13464 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13466 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13467 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13469 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13470 (gtu:P (match_dup 1) (match_dup 2)))]
13474 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13475 (parallel [(set (match_dup 3)
13476 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13477 (set (match_dup 0) (neg:P (match_dup 0)))])]
13480 (define_insn_and_split "*plus_gtu<mode>"
13481 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13482 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13483 (match_operand:P 2 "reg_or_short_operand" "rI"))
13484 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13487 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13488 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13489 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13492 (define_insn_and_split "*plus_gtu<mode>_compare"
13493 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13495 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13496 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13497 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13499 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13500 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13503 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13504 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13505 (parallel [(set (match_dup 4)
13506 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13508 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13511 (define_insn "*neg_gtu<mode>"
13512 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13513 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13514 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13516 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13517 [(set_attr "type" "two")
13518 (set_attr "length" "8")])
13521 ;; Define both directions of branch and return. If we need a reload
13522 ;; register, we'd rather use CR0 since it is much easier to copy a
13523 ;; register CC value to there.
13527 (if_then_else (match_operator 1 "branch_comparison_operator"
13529 "cc_reg_operand" "y")
13531 (label_ref (match_operand 0 "" ""))
13536 return output_cbranch (operands[1], \"%l0\", 0, insn);
13538 [(set_attr "type" "branch")])
13542 (if_then_else (match_operator 0 "branch_comparison_operator"
13544 "cc_reg_operand" "y")
13551 return output_cbranch (operands[0], NULL, 0, insn);
13553 [(set_attr "type" "jmpreg")
13554 (set_attr "length" "4")])
13558 (if_then_else (match_operator 1 "branch_comparison_operator"
13560 "cc_reg_operand" "y")
13563 (label_ref (match_operand 0 "" ""))))]
13567 return output_cbranch (operands[1], \"%l0\", 1, insn);
13569 [(set_attr "type" "branch")])
13573 (if_then_else (match_operator 0 "branch_comparison_operator"
13575 "cc_reg_operand" "y")
13582 return output_cbranch (operands[0], NULL, 1, insn);
13584 [(set_attr "type" "jmpreg")
13585 (set_attr "length" "4")])
13587 ;; Logic on condition register values.
13589 ; This pattern matches things like
13590 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13591 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13593 ; which are generated by the branch logic.
13594 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13596 (define_insn "*cceq_ior_compare"
13597 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13598 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13599 [(match_operator:SI 2
13600 "branch_positive_comparison_operator"
13602 "cc_reg_operand" "y,y")
13604 (match_operator:SI 4
13605 "branch_positive_comparison_operator"
13607 "cc_reg_operand" "0,y")
13611 "cr%q1 %E0,%j2,%j4"
13612 [(set_attr "type" "cr_logical,delayed_cr")])
13614 ; Why is the constant -1 here, but 1 in the previous pattern?
13615 ; Because ~1 has all but the low bit set.
13617 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13618 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13619 [(not:SI (match_operator:SI 2
13620 "branch_positive_comparison_operator"
13622 "cc_reg_operand" "y,y")
13624 (match_operator:SI 4
13625 "branch_positive_comparison_operator"
13627 "cc_reg_operand" "0,y")
13631 "cr%q1 %E0,%j2,%j4"
13632 [(set_attr "type" "cr_logical,delayed_cr")])
13634 (define_insn "*cceq_rev_compare"
13635 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13636 (compare:CCEQ (match_operator:SI 1
13637 "branch_positive_comparison_operator"
13639 "cc_reg_operand" "0,y")
13643 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13644 [(set_attr "type" "cr_logical,delayed_cr")])
13646 ;; If we are comparing the result of two comparisons, this can be done
13647 ;; using creqv or crxor.
13649 (define_insn_and_split ""
13650 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13651 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13652 [(match_operand 2 "cc_reg_operand" "y")
13654 (match_operator 3 "branch_comparison_operator"
13655 [(match_operand 4 "cc_reg_operand" "y")
13660 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13664 int positive_1, positive_2;
13666 positive_1 = branch_positive_comparison_operator (operands[1],
13667 GET_MODE (operands[1]));
13668 positive_2 = branch_positive_comparison_operator (operands[3],
13669 GET_MODE (operands[3]));
13672 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13673 GET_CODE (operands[1])),
13675 operands[2], const0_rtx);
13676 else if (GET_MODE (operands[1]) != SImode)
13677 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13678 operands[2], const0_rtx);
13681 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13682 GET_CODE (operands[3])),
13684 operands[4], const0_rtx);
13685 else if (GET_MODE (operands[3]) != SImode)
13686 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13687 operands[4], const0_rtx);
13689 if (positive_1 == positive_2)
13691 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13692 operands[5] = constm1_rtx;
13696 operands[5] = const1_rtx;
13700 ;; Unconditional branch and return.
13702 (define_insn "jump"
13704 (label_ref (match_operand 0 "" "")))]
13707 [(set_attr "type" "branch")])
13709 (define_insn "return"
13713 [(set_attr "type" "jmpreg")])
13715 (define_expand "indirect_jump"
13716 [(set (pc) (match_operand 0 "register_operand" ""))])
13718 (define_insn "*indirect_jump<mode>"
13719 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13724 [(set_attr "type" "jmpreg")])
13726 ;; Table jump for switch statements:
13727 (define_expand "tablejump"
13728 [(use (match_operand 0 "" ""))
13729 (use (label_ref (match_operand 1 "" "")))]
13734 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13736 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13740 (define_expand "tablejumpsi"
13741 [(set (match_dup 3)
13742 (plus:SI (match_operand:SI 0 "" "")
13744 (parallel [(set (pc) (match_dup 3))
13745 (use (label_ref (match_operand 1 "" "")))])]
13748 { operands[0] = force_reg (SImode, operands[0]);
13749 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13750 operands[3] = gen_reg_rtx (SImode);
13753 (define_expand "tablejumpdi"
13754 [(set (match_dup 4)
13755 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13757 (plus:DI (match_dup 4)
13759 (parallel [(set (pc) (match_dup 3))
13760 (use (label_ref (match_operand 1 "" "")))])]
13763 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13764 operands[3] = gen_reg_rtx (DImode);
13765 operands[4] = gen_reg_rtx (DImode);
13768 (define_insn "*tablejump<mode>_internal1"
13770 (match_operand:P 0 "register_operand" "c,*l"))
13771 (use (label_ref (match_operand 1 "" "")))]
13776 [(set_attr "type" "jmpreg")])
13781 "{cror 0,0,0|nop}")
13783 ;; Define the subtract-one-and-jump insns, starting with the template
13784 ;; so loop.c knows what to generate.
13786 (define_expand "doloop_end"
13787 [(use (match_operand 0 "" "")) ; loop pseudo
13788 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13789 (use (match_operand 2 "" "")) ; max iterations
13790 (use (match_operand 3 "" "")) ; loop level
13791 (use (match_operand 4 "" ""))] ; label
13795 /* Only use this on innermost loops. */
13796 if (INTVAL (operands[3]) > 1)
13800 if (GET_MODE (operands[0]) != DImode)
13802 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13806 if (GET_MODE (operands[0]) != SImode)
13808 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13813 (define_expand "ctr<mode>"
13814 [(parallel [(set (pc)
13815 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13817 (label_ref (match_operand 1 "" ""))
13820 (plus:P (match_dup 0)
13822 (clobber (match_scratch:CC 2 ""))
13823 (clobber (match_scratch:P 3 ""))])]
13827 ;; We need to be able to do this for any operand, including MEM, or we
13828 ;; will cause reload to blow up since we don't allow output reloads on
13830 ;; For the length attribute to be calculated correctly, the
13831 ;; label MUST be operand 0.
13833 (define_insn "*ctr<mode>_internal1"
13835 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13837 (label_ref (match_operand 0 "" ""))
13839 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13840 (plus:P (match_dup 1)
13842 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13843 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13847 if (which_alternative != 0)
13849 else if (get_attr_length (insn) == 4)
13850 return \"{bdn|bdnz} %l0\";
13852 return \"bdz $+8\;b %l0\";
13854 [(set_attr "type" "branch")
13855 (set_attr "length" "*,12,16,16")])
13857 (define_insn "*ctr<mode>_internal2"
13859 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13862 (label_ref (match_operand 0 "" ""))))
13863 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13864 (plus:P (match_dup 1)
13866 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13867 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13871 if (which_alternative != 0)
13873 else if (get_attr_length (insn) == 4)
13874 return \"bdz %l0\";
13876 return \"{bdn|bdnz} $+8\;b %l0\";
13878 [(set_attr "type" "branch")
13879 (set_attr "length" "*,12,16,16")])
13881 ;; Similar but use EQ
13883 (define_insn "*ctr<mode>_internal5"
13885 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13887 (label_ref (match_operand 0 "" ""))
13889 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13890 (plus:P (match_dup 1)
13892 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13893 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13897 if (which_alternative != 0)
13899 else if (get_attr_length (insn) == 4)
13900 return \"bdz %l0\";
13902 return \"{bdn|bdnz} $+8\;b %l0\";
13904 [(set_attr "type" "branch")
13905 (set_attr "length" "*,12,16,16")])
13907 (define_insn "*ctr<mode>_internal6"
13909 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13912 (label_ref (match_operand 0 "" ""))))
13913 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13914 (plus:P (match_dup 1)
13916 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13917 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13921 if (which_alternative != 0)
13923 else if (get_attr_length (insn) == 4)
13924 return \"{bdn|bdnz} %l0\";
13926 return \"bdz $+8\;b %l0\";
13928 [(set_attr "type" "branch")
13929 (set_attr "length" "*,12,16,16")])
13931 ;; Now the splitters if we could not allocate the CTR register
13935 (if_then_else (match_operator 2 "comparison_operator"
13936 [(match_operand:P 1 "gpc_reg_operand" "")
13938 (match_operand 5 "" "")
13939 (match_operand 6 "" "")))
13940 (set (match_operand:P 0 "gpc_reg_operand" "")
13941 (plus:P (match_dup 1) (const_int -1)))
13942 (clobber (match_scratch:CC 3 ""))
13943 (clobber (match_scratch:P 4 ""))]
13945 [(parallel [(set (match_dup 3)
13946 (compare:CC (plus:P (match_dup 1)
13950 (plus:P (match_dup 1)
13952 (set (pc) (if_then_else (match_dup 7)
13956 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13957 operands[3], const0_rtx); }")
13961 (if_then_else (match_operator 2 "comparison_operator"
13962 [(match_operand:P 1 "gpc_reg_operand" "")
13964 (match_operand 5 "" "")
13965 (match_operand 6 "" "")))
13966 (set (match_operand:P 0 "nonimmediate_operand" "")
13967 (plus:P (match_dup 1) (const_int -1)))
13968 (clobber (match_scratch:CC 3 ""))
13969 (clobber (match_scratch:P 4 ""))]
13970 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13971 [(parallel [(set (match_dup 3)
13972 (compare:CC (plus:P (match_dup 1)
13976 (plus:P (match_dup 1)
13980 (set (pc) (if_then_else (match_dup 7)
13984 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13985 operands[3], const0_rtx); }")
13987 (define_insn "trap"
13988 [(trap_if (const_int 1) (const_int 0))]
13992 (define_expand "conditional_trap"
13993 [(trap_if (match_operator 0 "trap_comparison_operator"
13994 [(match_dup 2) (match_dup 3)])
13995 (match_operand 1 "const_int_operand" ""))]
13997 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13998 operands[2] = rs6000_compare_op0;
13999 operands[3] = rs6000_compare_op1;")
14002 [(trap_if (match_operator 0 "trap_comparison_operator"
14003 [(match_operand:GPR 1 "register_operand" "r")
14004 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14007 "{t|t<wd>}%V0%I2 %1,%2")
14009 ;; Insns related to generating the function prologue and epilogue.
14011 (define_expand "prologue"
14012 [(use (const_int 0))]
14013 "TARGET_SCHED_PROLOG"
14016 rs6000_emit_prologue ();
14020 (define_insn "*movesi_from_cr_one"
14021 [(match_parallel 0 "mfcr_operation"
14022 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14023 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14024 (match_operand 3 "immediate_operand" "n")]
14025 UNSPEC_MOVESI_FROM_CR))])]
14031 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14033 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14034 operands[4] = GEN_INT (mask);
14035 output_asm_insn (\"mfcr %1,%4\", operands);
14039 [(set_attr "type" "mfcrf")])
14041 (define_insn "movesi_from_cr"
14042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14043 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14044 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14045 UNSPEC_MOVESI_FROM_CR))]
14048 [(set_attr "type" "mfcr")])
14050 (define_insn "*stmw"
14051 [(match_parallel 0 "stmw_operation"
14052 [(set (match_operand:SI 1 "memory_operand" "=m")
14053 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14056 [(set_attr "type" "store_ux")])
14058 (define_insn "*save_fpregs_<mode>"
14059 [(match_parallel 0 "any_parallel_operand"
14060 [(clobber (match_operand:P 1 "register_operand" "=l"))
14061 (use (match_operand:P 2 "call_operand" "s"))
14062 (set (match_operand:DF 3 "memory_operand" "=m")
14063 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14066 [(set_attr "type" "branch")
14067 (set_attr "length" "4")])
14069 ; These are to explain that changes to the stack pointer should
14070 ; not be moved over stores to stack memory.
14071 (define_insn "stack_tie"
14072 [(set (match_operand:BLK 0 "memory_operand" "+m")
14073 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14076 [(set_attr "length" "0")])
14079 (define_expand "epilogue"
14080 [(use (const_int 0))]
14081 "TARGET_SCHED_PROLOG"
14084 rs6000_emit_epilogue (FALSE);
14088 ; On some processors, doing the mtcrf one CC register at a time is
14089 ; faster (like on the 604e). On others, doing them all at once is
14090 ; faster; for instance, on the 601 and 750.
14092 (define_expand "movsi_to_cr_one"
14093 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14094 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14095 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14097 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14099 (define_insn "*movsi_to_cr"
14100 [(match_parallel 0 "mtcrf_operation"
14101 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14102 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14103 (match_operand 3 "immediate_operand" "n")]
14104 UNSPEC_MOVESI_TO_CR))])]
14110 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14111 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14112 operands[4] = GEN_INT (mask);
14113 return \"mtcrf %4,%2\";
14115 [(set_attr "type" "mtcr")])
14117 (define_insn "*mtcrfsi"
14118 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14119 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14120 (match_operand 2 "immediate_operand" "n")]
14121 UNSPEC_MOVESI_TO_CR))]
14122 "GET_CODE (operands[0]) == REG
14123 && CR_REGNO_P (REGNO (operands[0]))
14124 && GET_CODE (operands[2]) == CONST_INT
14125 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14127 [(set_attr "type" "mtcr")])
14129 ; The load-multiple instructions have similar properties.
14130 ; Note that "load_multiple" is a name known to the machine-independent
14131 ; code that actually corresponds to the PowerPC load-string.
14133 (define_insn "*lmw"
14134 [(match_parallel 0 "lmw_operation"
14135 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14136 (match_operand:SI 2 "memory_operand" "m"))])]
14139 [(set_attr "type" "load_ux")])
14141 (define_insn "*return_internal_<mode>"
14143 (use (match_operand:P 0 "register_operand" "lc"))]
14146 [(set_attr "type" "jmpreg")])
14148 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14149 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14151 (define_insn "*return_and_restore_fpregs_<mode>"
14152 [(match_parallel 0 "any_parallel_operand"
14154 (use (match_operand:P 1 "register_operand" "l"))
14155 (use (match_operand:P 2 "call_operand" "s"))
14156 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14157 (match_operand:DF 4 "memory_operand" "m"))])]
14161 ; This is used in compiling the unwind routines.
14162 (define_expand "eh_return"
14163 [(use (match_operand 0 "general_operand" ""))]
14168 emit_insn (gen_eh_set_lr_si (operands[0]));
14170 emit_insn (gen_eh_set_lr_di (operands[0]));
14174 ; We can't expand this before we know where the link register is stored.
14175 (define_insn "eh_set_lr_<mode>"
14176 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14178 (clobber (match_scratch:P 1 "=&b"))]
14183 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14184 (clobber (match_scratch 1 ""))]
14189 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14193 (define_insn "prefetch"
14194 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14195 (match_operand:SI 1 "const_int_operand" "n")
14196 (match_operand:SI 2 "const_int_operand" "n"))]
14200 if (GET_CODE (operands[0]) == REG)
14201 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14202 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14204 [(set_attr "type" "load")])
14207 (include "sync.md")
14208 (include "altivec.md")