1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/ADT/StringRef.h"
23 class InstrItineraryData;
29 class PassManagerBase;
32 class TargetELFWriterInfo;
33 class TargetFrameLowering;
34 class TargetInstrInfo;
35 class TargetIntrinsicInfo;
38 class TargetRegisterInfo;
39 class TargetSelectionDAGInfo;
40 class TargetSubtargetInfo;
41 class formatted_raw_ostream;
44 // Relocation model types.
49 PIC_, // Cannot be named PIC due to collision with -DPIC
65 // Code generation optimization level.
66 namespace CodeGenOpt {
77 None, // No preference
78 Latency, // Scheduling for shortest total latency.
79 RegPressure, // Scheduling for lowest register pressure.
80 Hybrid, // Scheduling for both latency and register pressure.
81 ILP // Scheduling for ILP in low register pressure mode.
85 //===----------------------------------------------------------------------===//
87 /// TargetMachine - Primary interface to the complete machine description for
88 /// the target machine. All target-specific information should be accessible
89 /// through this interface.
92 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
93 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
94 protected: // Can only create subclasses.
95 TargetMachine(const Target &T, StringRef TargetTriple,
96 StringRef CPU, StringRef FS);
98 /// getSubtargetImpl - virtual method implemented by subclasses that returns
99 /// a reference to that target's TargetSubtargetInfo-derived member variable.
100 virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
102 /// TheTarget - The Target that this machine was created for.
103 const Target &TheTarget;
105 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
106 /// feature strings the TargetMachine instance is created with.
107 std::string TargetTriple;
108 std::string TargetCPU;
109 std::string TargetFS;
111 /// AsmInfo - Contains target specific asm information.
113 const MCAsmInfo *AsmInfo;
115 unsigned MCRelaxAll : 1;
116 unsigned MCNoExecStack : 1;
117 unsigned MCSaveTempLabels : 1;
118 unsigned MCUseLoc : 1;
119 unsigned MCUseCFI : 1;
122 virtual ~TargetMachine();
124 const Target &getTarget() const { return TheTarget; }
126 const StringRef getTargetTriple() const { return TargetTriple; }
127 const StringRef getTargetCPU() const { return TargetCPU; }
128 const StringRef getTargetFeatureString() const { return TargetFS; }
130 // Interfaces to the major aspects of target machine information:
131 // -- Instruction opcode and operand information
132 // -- Pipelines and scheduling information
133 // -- Stack frame information
134 // -- Selection DAG lowering information
136 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
137 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
138 virtual const TargetLowering *getTargetLowering() const { return 0; }
139 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
140 virtual const TargetData *getTargetData() const { return 0; }
142 /// getMCAsmInfo - Return target specific asm information.
144 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
146 /// getSubtarget - This method returns a pointer to the specified type of
147 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
148 /// returned is of the correct type.
149 template<typename STC> const STC &getSubtarget() const {
150 return *static_cast<const STC*>(getSubtargetImpl());
153 /// getRegisterInfo - If register information is available, return it. If
154 /// not, return null. This is kept separate from RegInfo until RegInfo has
155 /// details of graph coloring register allocation removed from it.
157 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
159 /// getIntrinsicInfo - If intrinsic information is available, return it. If
160 /// not, return null.
162 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
164 /// getJITInfo - If this target supports a JIT, return information for it,
165 /// otherwise return null.
167 virtual TargetJITInfo *getJITInfo() { return 0; }
169 /// getInstrItineraryData - Returns instruction itinerary data for the target
170 /// or specific subtarget.
172 virtual const InstrItineraryData *getInstrItineraryData() const {
176 /// getELFWriterInfo - If this target supports an ELF writer, return
177 /// information for it, otherwise return null.
179 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
181 /// hasMCRelaxAll - Check whether all machine code instructions should be
183 bool hasMCRelaxAll() const { return MCRelaxAll; }
185 /// setMCRelaxAll - Set whether all machine code instructions should be
187 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
189 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
190 /// (i.e., not treated as temporary).
191 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
193 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
194 /// (i.e., not treated as temporary).
195 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
197 /// hasMCNoExecStack - Check whether an executable stack is not needed.
198 bool hasMCNoExecStack() const { return MCNoExecStack; }
200 /// setMCNoExecStack - Set whether an executabel stack is not needed.
201 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
203 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
204 bool hasMCUseLoc() const { return MCUseLoc; }
206 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
207 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
209 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
210 bool hasMCUseCFI() const { return MCUseCFI; }
212 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
213 void setMCUseCFI(bool Value) { MCUseCFI = Value; }
215 /// getRelocationModel - Returns the code generation relocation model. The
216 /// choices are static, PIC, and dynamic-no-pic, and target default.
217 static Reloc::Model getRelocationModel();
219 /// setRelocationModel - Sets the code generation relocation model.
221 static void setRelocationModel(Reloc::Model Model);
223 /// getCodeModel - Returns the code model. The choices are small, kernel,
224 /// medium, large, and target default.
225 static CodeModel::Model getCodeModel();
227 /// setCodeModel - Sets the code model.
229 static void setCodeModel(CodeModel::Model Model);
231 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
233 static bool getAsmVerbosityDefault();
235 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
237 static void setAsmVerbosityDefault(bool);
239 /// getDataSections - Return true if data objects should be emitted into their
240 /// own section, corresponds to -fdata-sections.
241 static bool getDataSections();
243 /// getFunctionSections - Return true if functions should be emitted into
244 /// their own section, corresponding to -ffunction-sections.
245 static bool getFunctionSections();
247 /// setDataSections - Set if the data are emit into separate sections.
248 static void setDataSections(bool);
250 /// setFunctionSections - Set if the functions are emit into separate
252 static void setFunctionSections(bool);
254 /// CodeGenFileType - These enums are meant to be passed into
255 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
256 /// it to indicate what type of file could actually be made.
257 enum CodeGenFileType {
260 CGFT_Null // Do not emit any output.
263 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
264 /// on this target. User flag overrides.
265 virtual bool getEnableTailMergeDefault() const { return true; }
267 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
268 /// specified file emitted. Typically this will involve several steps of code
269 /// generation. This method should return true if emission of this file type
270 /// is not supported, or false on success.
271 virtual bool addPassesToEmitFile(PassManagerBase &,
272 formatted_raw_ostream &,
279 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
280 /// get machine code emitted. This uses a JITCodeEmitter object to handle
281 /// actually outputting the machine code and resolving things like the address
282 /// of functions. This method returns true if machine code emission is
285 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
292 /// addPassesToEmitMC - Add passes to the specified pass manager to get
293 /// machine code emitted with the MCJIT. This method returns true if machine
294 /// code is not supported. It fills the MCContext Ctx pointer which can be
295 /// used to build custom MCStreamer.
297 virtual bool addPassesToEmitMC(PassManagerBase &,
306 /// LLVMTargetMachine - This class describes a target machine that is
307 /// implemented with the LLVM target-independent code generator.
309 class LLVMTargetMachine : public TargetMachine {
310 protected: // Can only create subclasses.
311 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
312 StringRef CPU, StringRef FS);
315 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
316 /// both emitting to assembly files or machine code output.
318 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
319 bool DisableVerify, MCContext *&OutCtx);
321 virtual void setCodeModelForJIT();
322 virtual void setCodeModelForStatic();
325 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
326 /// specified file emitted. Typically this will involve several steps of code
327 /// generation. If OptLevel is None, the code generator should emit code as
328 /// fast as possible, though the generated code may be less efficient.
329 virtual bool addPassesToEmitFile(PassManagerBase &PM,
330 formatted_raw_ostream &Out,
331 CodeGenFileType FileType,
333 bool DisableVerify = true);
335 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
336 /// get machine code emitted. This uses a JITCodeEmitter object to handle
337 /// actually outputting the machine code and resolving things like the address
338 /// of functions. This method returns true if machine code emission is
341 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
344 bool DisableVerify = true);
346 /// addPassesToEmitMC - Add passes to the specified pass manager to get
347 /// machine code emitted with the MCJIT. This method returns true if machine
348 /// code is not supported. It fills the MCContext Ctx pointer which can be
349 /// used to build custom MCStreamer.
351 virtual bool addPassesToEmitMC(PassManagerBase &PM,
354 CodeGenOpt::Level OptLevel,
355 bool DisableVerify = true);
357 /// Target-Independent Code Generator Pass Configuration Options.
359 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
360 /// passes (which are run just before instruction selector).
361 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
365 /// addInstSelector - This method should install an instruction selector pass,
366 /// which converts from LLVM code to machine instructions.
367 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
371 /// addPreRegAlloc - This method may be implemented by targets that want to
372 /// run passes immediately before register allocation. This should return
373 /// true if -print-machineinstrs should print after these passes.
374 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
378 /// addPostRegAlloc - This method may be implemented by targets that want
379 /// to run passes after register allocation but before prolog-epilog
380 /// insertion. This should return true if -print-machineinstrs should print
381 /// after these passes.
382 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
386 /// addPreSched2 - This method may be implemented by targets that want to
387 /// run passes after prolog-epilog insertion and before the second instruction
388 /// scheduling pass. This should return true if -print-machineinstrs should
389 /// print after these passes.
390 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
394 /// addPreEmitPass - This pass may be implemented by targets that want to run
395 /// passes immediately before machine code is emitted. This should return
396 /// true if -print-machineinstrs should print out the code after the passes.
397 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
402 /// addCodeEmitter - This pass should be overridden by the target to add a
403 /// code emitter, if supported. If this is not supported, 'true' should be
405 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
410 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
411 /// on this target. User flag overrides.
412 virtual bool getEnableTailMergeDefault() const { return true; }
415 } // End llvm namespace