1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
142 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
143 ISD::NodeType ExtType);
145 /// combine - call the node-specific routine that knows how to fold each
146 /// particular type of node. If that doesn't do anything, try the
147 /// target-specific DAG combines.
148 SDValue combine(SDNode *N);
150 // Visitation implementation - Implement dag node combining for different
151 // node types. The semantics are as follows:
153 // SDValue.getNode() == 0 - No change was made
154 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
155 // otherwise - N should be replaced by the returned Operand.
157 SDValue visitTokenFactor(SDNode *N);
158 SDValue visitMERGE_VALUES(SDNode *N);
159 SDValue visitADD(SDNode *N);
160 SDValue visitSUB(SDNode *N);
161 SDValue visitADDC(SDNode *N);
162 SDValue visitADDE(SDNode *N);
163 SDValue visitMUL(SDNode *N);
164 SDValue visitSDIV(SDNode *N);
165 SDValue visitUDIV(SDNode *N);
166 SDValue visitSREM(SDNode *N);
167 SDValue visitUREM(SDNode *N);
168 SDValue visitMULHU(SDNode *N);
169 SDValue visitMULHS(SDNode *N);
170 SDValue visitSMUL_LOHI(SDNode *N);
171 SDValue visitUMUL_LOHI(SDNode *N);
172 SDValue visitSMULO(SDNode *N);
173 SDValue visitUMULO(SDNode *N);
174 SDValue visitSDIVREM(SDNode *N);
175 SDValue visitUDIVREM(SDNode *N);
176 SDValue visitAND(SDNode *N);
177 SDValue visitOR(SDNode *N);
178 SDValue visitXOR(SDNode *N);
179 SDValue SimplifyVBinOp(SDNode *N);
180 SDValue visitSHL(SDNode *N);
181 SDValue visitSRA(SDNode *N);
182 SDValue visitSRL(SDNode *N);
183 SDValue visitCTLZ(SDNode *N);
184 SDValue visitCTTZ(SDNode *N);
185 SDValue visitCTPOP(SDNode *N);
186 SDValue visitSELECT(SDNode *N);
187 SDValue visitSELECT_CC(SDNode *N);
188 SDValue visitSETCC(SDNode *N);
189 SDValue visitSIGN_EXTEND(SDNode *N);
190 SDValue visitZERO_EXTEND(SDNode *N);
191 SDValue visitANY_EXTEND(SDNode *N);
192 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
193 SDValue visitTRUNCATE(SDNode *N);
194 SDValue visitBITCAST(SDNode *N);
195 SDValue visitBUILD_PAIR(SDNode *N);
196 SDValue visitFADD(SDNode *N);
197 SDValue visitFSUB(SDNode *N);
198 SDValue visitFMUL(SDNode *N);
199 SDValue visitFDIV(SDNode *N);
200 SDValue visitFREM(SDNode *N);
201 SDValue visitFCOPYSIGN(SDNode *N);
202 SDValue visitSINT_TO_FP(SDNode *N);
203 SDValue visitUINT_TO_FP(SDNode *N);
204 SDValue visitFP_TO_SINT(SDNode *N);
205 SDValue visitFP_TO_UINT(SDNode *N);
206 SDValue visitFP_ROUND(SDNode *N);
207 SDValue visitFP_ROUND_INREG(SDNode *N);
208 SDValue visitFP_EXTEND(SDNode *N);
209 SDValue visitFNEG(SDNode *N);
210 SDValue visitFABS(SDNode *N);
211 SDValue visitBRCOND(SDNode *N);
212 SDValue visitBR_CC(SDNode *N);
213 SDValue visitLOAD(SDNode *N);
214 SDValue visitSTORE(SDNode *N);
215 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
216 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
217 SDValue visitBUILD_VECTOR(SDNode *N);
218 SDValue visitCONCAT_VECTORS(SDNode *N);
219 SDValue visitVECTOR_SHUFFLE(SDNode *N);
220 SDValue visitMEMBARRIER(SDNode *N);
222 SDValue XformToShuffleWithZero(SDNode *N);
223 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
225 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
227 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
228 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
229 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
230 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
231 SDValue N3, ISD::CondCode CC,
232 bool NotExtCompare = false);
233 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
234 DebugLoc DL, bool foldBooleans = true);
235 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
237 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
238 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
239 SDValue BuildSDIV(SDNode *N);
240 SDValue BuildUDIV(SDNode *N);
241 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
242 bool DemandHighBits = true);
243 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
244 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
245 SDValue ReduceLoadWidth(SDNode *N);
246 SDValue ReduceLoadOpStoreWidth(SDNode *N);
247 SDValue TransformFPLoadStorePair(SDNode *N);
249 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
251 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
252 /// looking for aliasing nodes and adding them to the Aliases vector.
253 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
254 SmallVector<SDValue, 8> &Aliases);
256 /// isAlias - Return true if there is any possibility that the two addresses
258 bool isAlias(SDValue Ptr1, int64_t Size1,
259 const Value *SrcValue1, int SrcValueOffset1,
260 unsigned SrcValueAlign1,
261 const MDNode *TBAAInfo1,
262 SDValue Ptr2, int64_t Size2,
263 const Value *SrcValue2, int SrcValueOffset2,
264 unsigned SrcValueAlign2,
265 const MDNode *TBAAInfo2) const;
267 /// FindAliasInfo - Extracts the relevant alias information from the memory
268 /// node. Returns true if the operand was a load.
269 bool FindAliasInfo(SDNode *N,
270 SDValue &Ptr, int64_t &Size,
271 const Value *&SrcValue, int &SrcValueOffset,
272 unsigned &SrcValueAlignment,
273 const MDNode *&TBAAInfo) const;
275 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
276 /// looking for a better chain (aliasing node.)
277 SDValue FindBetterChain(SDNode *N, SDValue Chain);
280 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
281 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
282 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
284 /// Run - runs the dag combiner on all nodes in the work list
285 void Run(CombineLevel AtLevel);
287 SelectionDAG &getDAG() const { return DAG; }
289 /// getShiftAmountTy - Returns a type large enough to hold any valid
290 /// shift amount - before type legalization these can be huge.
291 EVT getShiftAmountTy(EVT LHSTy) {
292 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
295 /// isTypeLegal - This method returns true if we are running before type
296 /// legalization or if the specified VT is legal.
297 bool isTypeLegal(const EVT &VT) {
298 if (!LegalTypes) return true;
299 return TLI.isTypeLegal(VT);
306 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
307 /// nodes from the worklist.
308 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
311 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
313 virtual void NodeDeleted(SDNode *N, SDNode *E) {
314 DC.removeFromWorkList(N);
317 virtual void NodeUpdated(SDNode *N) {
323 //===----------------------------------------------------------------------===//
324 // TargetLowering::DAGCombinerInfo implementation
325 //===----------------------------------------------------------------------===//
327 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
328 ((DAGCombiner*)DC)->AddToWorkList(N);
331 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
332 ((DAGCombiner*)DC)->removeFromWorkList(N);
335 SDValue TargetLowering::DAGCombinerInfo::
336 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
337 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
340 SDValue TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
342 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
346 SDValue TargetLowering::DAGCombinerInfo::
347 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
348 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
351 void TargetLowering::DAGCombinerInfo::
352 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
353 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
361 /// specified expression for the same cost as the expression itself, or 2 if we
362 /// can compute the negated form more cheaply than the expression itself.
363 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
364 unsigned Depth = 0) {
365 // No compile time optimizations on this type.
366 if (Op.getValueType() == MVT::ppcf128)
369 // fneg is removable even if it has multiple uses.
370 if (Op.getOpcode() == ISD::FNEG) return 2;
372 // Don't allow anything with multiple uses.
373 if (!Op.hasOneUse()) return 0;
375 // Don't recurse exponentially.
376 if (Depth > 6) return 0;
378 switch (Op.getOpcode()) {
379 default: return false;
380 case ISD::ConstantFP:
381 // Don't invert constant FP values after legalize. The negated constant
382 // isn't necessarily legal.
383 return LegalOperations ? 0 : 1;
385 // FIXME: determine better conditions for this xform.
386 if (!UnsafeFPMath) return 0;
388 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
389 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
391 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
392 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
394 // We can't turn -(A-B) into B-A when we honor signed zeros.
395 if (!UnsafeFPMath) return 0;
397 // fold (fneg (fsub A, B)) -> (fsub B, A)
402 if (HonorSignDependentRoundingFPMath()) return 0;
404 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
405 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
408 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
413 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
417 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
418 /// returns the newly negated expression.
419 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
420 bool LegalOperations, unsigned Depth = 0) {
421 // fneg is removable even if it has multiple uses.
422 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
424 // Don't allow anything with multiple uses.
425 assert(Op.hasOneUse() && "Unknown reuse!");
427 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
428 switch (Op.getOpcode()) {
429 default: llvm_unreachable("Unknown code");
430 case ISD::ConstantFP: {
431 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
433 return DAG.getConstantFP(V, Op.getValueType());
436 // FIXME: determine better conditions for this xform.
437 assert(UnsafeFPMath);
439 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
440 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
441 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
442 GetNegatedExpression(Op.getOperand(0), DAG,
443 LegalOperations, Depth+1),
445 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
446 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
447 GetNegatedExpression(Op.getOperand(1), DAG,
448 LegalOperations, Depth+1),
451 // We can't turn -(A-B) into B-A when we honor signed zeros.
452 assert(UnsafeFPMath);
454 // fold (fneg (fsub 0, B)) -> B
455 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
456 if (N0CFP->getValueAPF().isZero())
457 return Op.getOperand(1);
459 // fold (fneg (fsub A, B)) -> (fsub B, A)
460 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
461 Op.getOperand(1), Op.getOperand(0));
465 assert(!HonorSignDependentRoundingFPMath());
467 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
468 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
469 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
470 GetNegatedExpression(Op.getOperand(0), DAG,
471 LegalOperations, Depth+1),
474 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
475 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
477 GetNegatedExpression(Op.getOperand(1), DAG,
478 LegalOperations, Depth+1));
482 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
483 GetNegatedExpression(Op.getOperand(0), DAG,
484 LegalOperations, Depth+1));
486 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
487 GetNegatedExpression(Op.getOperand(0), DAG,
488 LegalOperations, Depth+1),
494 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
495 // that selects between the values 1 and 0, making it equivalent to a setcc.
496 // Also, set the incoming LHS, RHS, and CC references to the appropriate
497 // nodes based on the type of node we are checking. This simplifies life a
498 // bit for the callers.
499 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
501 if (N.getOpcode() == ISD::SETCC) {
502 LHS = N.getOperand(0);
503 RHS = N.getOperand(1);
504 CC = N.getOperand(2);
507 if (N.getOpcode() == ISD::SELECT_CC &&
508 N.getOperand(2).getOpcode() == ISD::Constant &&
509 N.getOperand(3).getOpcode() == ISD::Constant &&
510 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
511 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
512 LHS = N.getOperand(0);
513 RHS = N.getOperand(1);
514 CC = N.getOperand(4);
520 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
521 // one use. If this is true, it allows the users to invert the operation for
522 // free when it is profitable to do so.
523 static bool isOneUseSetCC(SDValue N) {
525 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
530 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
531 SDValue N0, SDValue N1) {
532 EVT VT = N0.getValueType();
533 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
534 if (isa<ConstantSDNode>(N1)) {
535 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
537 DAG.FoldConstantArithmetic(Opc, VT,
538 cast<ConstantSDNode>(N0.getOperand(1)),
539 cast<ConstantSDNode>(N1));
540 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
542 if (N0.hasOneUse()) {
543 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
544 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
545 N0.getOperand(0), N1);
546 AddToWorkList(OpNode.getNode());
547 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
551 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
552 if (isa<ConstantSDNode>(N0)) {
553 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
555 DAG.FoldConstantArithmetic(Opc, VT,
556 cast<ConstantSDNode>(N1.getOperand(1)),
557 cast<ConstantSDNode>(N0));
558 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
560 if (N1.hasOneUse()) {
561 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
562 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
563 N1.getOperand(0), N0);
564 AddToWorkList(OpNode.getNode());
565 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
572 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
574 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
576 DEBUG(dbgs() << "\nReplacing.1 ";
578 dbgs() << "\nWith: ";
579 To[0].getNode()->dump(&DAG);
580 dbgs() << " and " << NumTo-1 << " other values\n";
581 for (unsigned i = 0, e = NumTo; i != e; ++i)
582 assert((!To[i].getNode() ||
583 N->getValueType(i) == To[i].getValueType()) &&
584 "Cannot combine value to value of different type!"));
585 WorkListRemover DeadNodes(*this);
586 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
589 // Push the new nodes and any users onto the worklist
590 for (unsigned i = 0, e = NumTo; i != e; ++i) {
591 if (To[i].getNode()) {
592 AddToWorkList(To[i].getNode());
593 AddUsersToWorkList(To[i].getNode());
598 // Finally, if the node is now dead, remove it from the graph. The node
599 // may not be dead if the replacement process recursively simplified to
600 // something else needing this node.
601 if (N->use_empty()) {
602 // Nodes can be reintroduced into the worklist. Make sure we do not
603 // process a node that has been replaced.
604 removeFromWorkList(N);
606 // Finally, since the node is now dead, remove it from the graph.
609 return SDValue(N, 0);
613 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
614 // Replace all uses. If any nodes become isomorphic to other nodes and
615 // are deleted, make sure to remove them from our worklist.
616 WorkListRemover DeadNodes(*this);
617 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
619 // Push the new node and any (possibly new) users onto the worklist.
620 AddToWorkList(TLO.New.getNode());
621 AddUsersToWorkList(TLO.New.getNode());
623 // Finally, if the node is now dead, remove it from the graph. The node
624 // may not be dead if the replacement process recursively simplified to
625 // something else needing this node.
626 if (TLO.Old.getNode()->use_empty()) {
627 removeFromWorkList(TLO.Old.getNode());
629 // If the operands of this node are only used by the node, they will now
630 // be dead. Make sure to visit them first to delete dead nodes early.
631 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
632 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
633 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
635 DAG.DeleteNode(TLO.Old.getNode());
639 /// SimplifyDemandedBits - Check the specified integer node value to see if
640 /// it can be simplified or if things it uses can be simplified by bit
641 /// propagation. If so, return true.
642 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
643 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
644 APInt KnownZero, KnownOne;
645 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
649 AddToWorkList(Op.getNode());
651 // Replace the old value with the new one.
653 DEBUG(dbgs() << "\nReplacing.2 ";
654 TLO.Old.getNode()->dump(&DAG);
655 dbgs() << "\nWith: ";
656 TLO.New.getNode()->dump(&DAG);
659 CommitTargetLoweringOpt(TLO);
663 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
664 DebugLoc dl = Load->getDebugLoc();
665 EVT VT = Load->getValueType(0);
666 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
668 DEBUG(dbgs() << "\nReplacing.9 ";
670 dbgs() << "\nWith: ";
671 Trunc.getNode()->dump(&DAG);
673 WorkListRemover DeadNodes(*this);
674 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
675 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
677 removeFromWorkList(Load);
678 DAG.DeleteNode(Load);
679 AddToWorkList(Trunc.getNode());
682 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
684 DebugLoc dl = Op.getDebugLoc();
685 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
686 EVT MemVT = LD->getMemoryVT();
687 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
688 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
690 : LD->getExtensionType();
692 return DAG.getExtLoad(ExtType, dl, PVT,
693 LD->getChain(), LD->getBasePtr(),
694 LD->getPointerInfo(),
695 MemVT, LD->isVolatile(),
696 LD->isNonTemporal(), LD->getAlignment());
699 unsigned Opc = Op.getOpcode();
702 case ISD::AssertSext:
703 return DAG.getNode(ISD::AssertSext, dl, PVT,
704 SExtPromoteOperand(Op.getOperand(0), PVT),
706 case ISD::AssertZext:
707 return DAG.getNode(ISD::AssertZext, dl, PVT,
708 ZExtPromoteOperand(Op.getOperand(0), PVT),
710 case ISD::Constant: {
712 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
713 return DAG.getNode(ExtOpc, dl, PVT, Op);
717 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
719 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
722 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
723 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
725 EVT OldVT = Op.getValueType();
726 DebugLoc dl = Op.getDebugLoc();
727 bool Replace = false;
728 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
729 if (NewOp.getNode() == 0)
731 AddToWorkList(NewOp.getNode());
734 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
735 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
736 DAG.getValueType(OldVT));
739 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
740 EVT OldVT = Op.getValueType();
741 DebugLoc dl = Op.getDebugLoc();
742 bool Replace = false;
743 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
744 if (NewOp.getNode() == 0)
746 AddToWorkList(NewOp.getNode());
749 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
750 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
753 /// PromoteIntBinOp - Promote the specified integer binary operation if the
754 /// target indicates it is beneficial. e.g. On x86, it's usually better to
755 /// promote i16 operations to i32 since i16 instructions are longer.
756 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
757 if (!LegalOperations)
760 EVT VT = Op.getValueType();
761 if (VT.isVector() || !VT.isInteger())
764 // If operation type is 'undesirable', e.g. i16 on x86, consider
766 unsigned Opc = Op.getOpcode();
767 if (TLI.isTypeDesirableForOp(Opc, VT))
771 // Consult target whether it is a good idea to promote this operation and
772 // what's the right type to promote it to.
773 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
774 assert(PVT != VT && "Don't know what type to promote to!");
776 bool Replace0 = false;
777 SDValue N0 = Op.getOperand(0);
778 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
779 if (NN0.getNode() == 0)
782 bool Replace1 = false;
783 SDValue N1 = Op.getOperand(1);
788 NN1 = PromoteOperand(N1, PVT, Replace1);
789 if (NN1.getNode() == 0)
793 AddToWorkList(NN0.getNode());
795 AddToWorkList(NN1.getNode());
798 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
800 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
802 DEBUG(dbgs() << "\nPromoting ";
803 Op.getNode()->dump(&DAG));
804 DebugLoc dl = Op.getDebugLoc();
805 return DAG.getNode(ISD::TRUNCATE, dl, VT,
806 DAG.getNode(Opc, dl, PVT, NN0, NN1));
811 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
812 /// target indicates it is beneficial. e.g. On x86, it's usually better to
813 /// promote i16 operations to i32 since i16 instructions are longer.
814 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
815 if (!LegalOperations)
818 EVT VT = Op.getValueType();
819 if (VT.isVector() || !VT.isInteger())
822 // If operation type is 'undesirable', e.g. i16 on x86, consider
824 unsigned Opc = Op.getOpcode();
825 if (TLI.isTypeDesirableForOp(Opc, VT))
829 // Consult target whether it is a good idea to promote this operation and
830 // what's the right type to promote it to.
831 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
832 assert(PVT != VT && "Don't know what type to promote to!");
834 bool Replace = false;
835 SDValue N0 = Op.getOperand(0);
837 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
838 else if (Opc == ISD::SRL)
839 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
841 N0 = PromoteOperand(N0, PVT, Replace);
842 if (N0.getNode() == 0)
845 AddToWorkList(N0.getNode());
847 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
849 DEBUG(dbgs() << "\nPromoting ";
850 Op.getNode()->dump(&DAG));
851 DebugLoc dl = Op.getDebugLoc();
852 return DAG.getNode(ISD::TRUNCATE, dl, VT,
853 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
858 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
859 if (!LegalOperations)
862 EVT VT = Op.getValueType();
863 if (VT.isVector() || !VT.isInteger())
866 // If operation type is 'undesirable', e.g. i16 on x86, consider
868 unsigned Opc = Op.getOpcode();
869 if (TLI.isTypeDesirableForOp(Opc, VT))
873 // Consult target whether it is a good idea to promote this operation and
874 // what's the right type to promote it to.
875 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
876 assert(PVT != VT && "Don't know what type to promote to!");
877 // fold (aext (aext x)) -> (aext x)
878 // fold (aext (zext x)) -> (zext x)
879 // fold (aext (sext x)) -> (sext x)
880 DEBUG(dbgs() << "\nPromoting ";
881 Op.getNode()->dump(&DAG));
882 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
887 bool DAGCombiner::PromoteLoad(SDValue Op) {
888 if (!LegalOperations)
891 EVT VT = Op.getValueType();
892 if (VT.isVector() || !VT.isInteger())
895 // If operation type is 'undesirable', e.g. i16 on x86, consider
897 unsigned Opc = Op.getOpcode();
898 if (TLI.isTypeDesirableForOp(Opc, VT))
902 // Consult target whether it is a good idea to promote this operation and
903 // what's the right type to promote it to.
904 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
905 assert(PVT != VT && "Don't know what type to promote to!");
907 DebugLoc dl = Op.getDebugLoc();
908 SDNode *N = Op.getNode();
909 LoadSDNode *LD = cast<LoadSDNode>(N);
910 EVT MemVT = LD->getMemoryVT();
911 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
912 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
914 : LD->getExtensionType();
915 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
916 LD->getChain(), LD->getBasePtr(),
917 LD->getPointerInfo(),
918 MemVT, LD->isVolatile(),
919 LD->isNonTemporal(), LD->getAlignment());
920 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
922 DEBUG(dbgs() << "\nPromoting ";
925 Result.getNode()->dump(&DAG);
927 WorkListRemover DeadNodes(*this);
928 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
929 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
930 removeFromWorkList(N);
932 AddToWorkList(Result.getNode());
939 //===----------------------------------------------------------------------===//
940 // Main DAG Combiner implementation
941 //===----------------------------------------------------------------------===//
943 void DAGCombiner::Run(CombineLevel AtLevel) {
944 // set the instance variables, so that the various visit routines may use it.
946 LegalOperations = Level >= NoIllegalOperations;
947 LegalTypes = Level >= NoIllegalTypes;
949 // Add all the dag nodes to the worklist.
950 WorkList.reserve(DAG.allnodes_size());
951 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
952 E = DAG.allnodes_end(); I != E; ++I)
953 WorkList.push_back(I);
955 // Create a dummy node (which is not added to allnodes), that adds a reference
956 // to the root node, preventing it from being deleted, and tracking any
957 // changes of the root.
958 HandleSDNode Dummy(DAG.getRoot());
960 // The root of the dag may dangle to deleted nodes until the dag combiner is
961 // done. Set it to null to avoid confusion.
962 DAG.setRoot(SDValue());
964 // while the worklist isn't empty, inspect the node on the end of it and
965 // try and combine it.
966 while (!WorkList.empty()) {
967 SDNode *N = WorkList.back();
970 // If N has no uses, it is dead. Make sure to revisit all N's operands once
971 // N is deleted from the DAG, since they too may now be dead or may have a
972 // reduced number of uses, allowing other xforms.
973 if (N->use_empty() && N != &Dummy) {
974 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
975 AddToWorkList(N->getOperand(i).getNode());
981 SDValue RV = combine(N);
983 if (RV.getNode() == 0)
988 // If we get back the same node we passed in, rather than a new node or
989 // zero, we know that the node must have defined multiple values and
990 // CombineTo was used. Since CombineTo takes care of the worklist
991 // mechanics for us, we have no work to do in this case.
992 if (RV.getNode() == N)
995 assert(N->getOpcode() != ISD::DELETED_NODE &&
996 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
997 "Node was deleted but visit returned new node!");
999 DEBUG(dbgs() << "\nReplacing.3 ";
1001 dbgs() << "\nWith: ";
1002 RV.getNode()->dump(&DAG);
1005 // Transfer debug value.
1006 DAG.TransferDbgValues(SDValue(N, 0), RV);
1007 WorkListRemover DeadNodes(*this);
1008 if (N->getNumValues() == RV.getNode()->getNumValues())
1009 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1011 assert(N->getValueType(0) == RV.getValueType() &&
1012 N->getNumValues() == 1 && "Type mismatch");
1014 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1017 // Push the new node and any users onto the worklist
1018 AddToWorkList(RV.getNode());
1019 AddUsersToWorkList(RV.getNode());
1021 // Add any uses of the old node to the worklist in case this node is the
1022 // last one that uses them. They may become dead after this node is
1024 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1025 AddToWorkList(N->getOperand(i).getNode());
1027 // Finally, if the node is now dead, remove it from the graph. The node
1028 // may not be dead if the replacement process recursively simplified to
1029 // something else needing this node.
1030 if (N->use_empty()) {
1031 // Nodes can be reintroduced into the worklist. Make sure we do not
1032 // process a node that has been replaced.
1033 removeFromWorkList(N);
1035 // Finally, since the node is now dead, remove it from the graph.
1040 // If the root changed (e.g. it was a dead load, update the root).
1041 DAG.setRoot(Dummy.getValue());
1044 SDValue DAGCombiner::visit(SDNode *N) {
1045 switch (N->getOpcode()) {
1047 case ISD::TokenFactor: return visitTokenFactor(N);
1048 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1049 case ISD::ADD: return visitADD(N);
1050 case ISD::SUB: return visitSUB(N);
1051 case ISD::ADDC: return visitADDC(N);
1052 case ISD::ADDE: return visitADDE(N);
1053 case ISD::MUL: return visitMUL(N);
1054 case ISD::SDIV: return visitSDIV(N);
1055 case ISD::UDIV: return visitUDIV(N);
1056 case ISD::SREM: return visitSREM(N);
1057 case ISD::UREM: return visitUREM(N);
1058 case ISD::MULHU: return visitMULHU(N);
1059 case ISD::MULHS: return visitMULHS(N);
1060 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1061 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1062 case ISD::SMULO: return visitSMULO(N);
1063 case ISD::UMULO: return visitUMULO(N);
1064 case ISD::SDIVREM: return visitSDIVREM(N);
1065 case ISD::UDIVREM: return visitUDIVREM(N);
1066 case ISD::AND: return visitAND(N);
1067 case ISD::OR: return visitOR(N);
1068 case ISD::XOR: return visitXOR(N);
1069 case ISD::SHL: return visitSHL(N);
1070 case ISD::SRA: return visitSRA(N);
1071 case ISD::SRL: return visitSRL(N);
1072 case ISD::CTLZ: return visitCTLZ(N);
1073 case ISD::CTTZ: return visitCTTZ(N);
1074 case ISD::CTPOP: return visitCTPOP(N);
1075 case ISD::SELECT: return visitSELECT(N);
1076 case ISD::SELECT_CC: return visitSELECT_CC(N);
1077 case ISD::SETCC: return visitSETCC(N);
1078 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1079 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1080 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1081 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1082 case ISD::TRUNCATE: return visitTRUNCATE(N);
1083 case ISD::BITCAST: return visitBITCAST(N);
1084 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1085 case ISD::FADD: return visitFADD(N);
1086 case ISD::FSUB: return visitFSUB(N);
1087 case ISD::FMUL: return visitFMUL(N);
1088 case ISD::FDIV: return visitFDIV(N);
1089 case ISD::FREM: return visitFREM(N);
1090 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1091 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1092 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1093 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1094 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1095 case ISD::FP_ROUND: return visitFP_ROUND(N);
1096 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1097 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1098 case ISD::FNEG: return visitFNEG(N);
1099 case ISD::FABS: return visitFABS(N);
1100 case ISD::BRCOND: return visitBRCOND(N);
1101 case ISD::BR_CC: return visitBR_CC(N);
1102 case ISD::LOAD: return visitLOAD(N);
1103 case ISD::STORE: return visitSTORE(N);
1104 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1105 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1106 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1107 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1108 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1109 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1114 SDValue DAGCombiner::combine(SDNode *N) {
1115 SDValue RV = visit(N);
1117 // If nothing happened, try a target-specific DAG combine.
1118 if (RV.getNode() == 0) {
1119 assert(N->getOpcode() != ISD::DELETED_NODE &&
1120 "Node was deleted but visit returned NULL!");
1122 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1123 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1125 // Expose the DAG combiner to the target combiner impls.
1126 TargetLowering::DAGCombinerInfo
1127 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1129 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1133 // If nothing happened still, try promoting the operation.
1134 if (RV.getNode() == 0) {
1135 switch (N->getOpcode()) {
1143 RV = PromoteIntBinOp(SDValue(N, 0));
1148 RV = PromoteIntShiftOp(SDValue(N, 0));
1150 case ISD::SIGN_EXTEND:
1151 case ISD::ZERO_EXTEND:
1152 case ISD::ANY_EXTEND:
1153 RV = PromoteExtend(SDValue(N, 0));
1156 if (PromoteLoad(SDValue(N, 0)))
1162 // If N is a commutative binary node, try commuting it to enable more
1164 if (RV.getNode() == 0 &&
1165 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1166 N->getNumValues() == 1) {
1167 SDValue N0 = N->getOperand(0);
1168 SDValue N1 = N->getOperand(1);
1170 // Constant operands are canonicalized to RHS.
1171 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1172 SDValue Ops[] = { N1, N0 };
1173 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1176 return SDValue(CSENode, 0);
1183 /// getInputChainForNode - Given a node, return its input chain if it has one,
1184 /// otherwise return a null sd operand.
1185 static SDValue getInputChainForNode(SDNode *N) {
1186 if (unsigned NumOps = N->getNumOperands()) {
1187 if (N->getOperand(0).getValueType() == MVT::Other)
1188 return N->getOperand(0);
1189 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1190 return N->getOperand(NumOps-1);
1191 for (unsigned i = 1; i < NumOps-1; ++i)
1192 if (N->getOperand(i).getValueType() == MVT::Other)
1193 return N->getOperand(i);
1198 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1199 // If N has two operands, where one has an input chain equal to the other,
1200 // the 'other' chain is redundant.
1201 if (N->getNumOperands() == 2) {
1202 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1203 return N->getOperand(0);
1204 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1205 return N->getOperand(1);
1208 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1209 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1210 SmallPtrSet<SDNode*, 16> SeenOps;
1211 bool Changed = false; // If we should replace this token factor.
1213 // Start out with this token factor.
1216 // Iterate through token factors. The TFs grows when new token factors are
1218 for (unsigned i = 0; i < TFs.size(); ++i) {
1219 SDNode *TF = TFs[i];
1221 // Check each of the operands.
1222 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1223 SDValue Op = TF->getOperand(i);
1225 switch (Op.getOpcode()) {
1226 case ISD::EntryToken:
1227 // Entry tokens don't need to be added to the list. They are
1232 case ISD::TokenFactor:
1233 if (Op.hasOneUse() &&
1234 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1235 // Queue up for processing.
1236 TFs.push_back(Op.getNode());
1237 // Clean up in case the token factor is removed.
1238 AddToWorkList(Op.getNode());
1245 // Only add if it isn't already in the list.
1246 if (SeenOps.insert(Op.getNode()))
1257 // If we've change things around then replace token factor.
1260 // The entry token is the only possible outcome.
1261 Result = DAG.getEntryNode();
1263 // New and improved token factor.
1264 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1265 MVT::Other, &Ops[0], Ops.size());
1268 // Don't add users to work list.
1269 return CombineTo(N, Result, false);
1275 /// MERGE_VALUES can always be eliminated.
1276 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1277 WorkListRemover DeadNodes(*this);
1278 // Replacing results may cause a different MERGE_VALUES to suddenly
1279 // be CSE'd with N, and carry its uses with it. Iterate until no
1280 // uses remain, to ensure that the node can be safely deleted.
1282 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1283 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1285 } while (!N->use_empty());
1286 removeFromWorkList(N);
1288 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1292 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1293 SelectionDAG &DAG) {
1294 EVT VT = N0.getValueType();
1295 SDValue N00 = N0.getOperand(0);
1296 SDValue N01 = N0.getOperand(1);
1297 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1299 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1300 isa<ConstantSDNode>(N00.getOperand(1))) {
1301 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1302 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1303 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1304 N00.getOperand(0), N01),
1305 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1306 N00.getOperand(1), N01));
1307 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1313 SDValue DAGCombiner::visitADD(SDNode *N) {
1314 SDValue N0 = N->getOperand(0);
1315 SDValue N1 = N->getOperand(1);
1316 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1317 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1318 EVT VT = N0.getValueType();
1321 if (VT.isVector()) {
1322 SDValue FoldedVOp = SimplifyVBinOp(N);
1323 if (FoldedVOp.getNode()) return FoldedVOp;
1326 // fold (add x, undef) -> undef
1327 if (N0.getOpcode() == ISD::UNDEF)
1329 if (N1.getOpcode() == ISD::UNDEF)
1331 // fold (add c1, c2) -> c1+c2
1333 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1334 // canonicalize constant to RHS
1336 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1337 // fold (add x, 0) -> x
1338 if (N1C && N1C->isNullValue())
1340 // fold (add Sym, c) -> Sym+c
1341 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1342 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1343 GA->getOpcode() == ISD::GlobalAddress)
1344 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1346 (uint64_t)N1C->getSExtValue());
1347 // fold ((c1-A)+c2) -> (c1+c2)-A
1348 if (N1C && N0.getOpcode() == ISD::SUB)
1349 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1350 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1351 DAG.getConstant(N1C->getAPIntValue()+
1352 N0C->getAPIntValue(), VT),
1355 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1356 if (RADD.getNode() != 0)
1358 // fold ((0-A) + B) -> B-A
1359 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1360 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1361 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1362 // fold (A + (0-B)) -> A-B
1363 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1364 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1365 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1366 // fold (A+(B-A)) -> B
1367 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1368 return N1.getOperand(0);
1369 // fold ((B-A)+A) -> B
1370 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1371 return N0.getOperand(0);
1372 // fold (A+(B-(A+C))) to (B-C)
1373 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1374 N0 == N1.getOperand(1).getOperand(0))
1375 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1376 N1.getOperand(1).getOperand(1));
1377 // fold (A+(B-(C+A))) to (B-C)
1378 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1379 N0 == N1.getOperand(1).getOperand(1))
1380 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1381 N1.getOperand(1).getOperand(0));
1382 // fold (A+((B-A)+or-C)) to (B+or-C)
1383 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1384 N1.getOperand(0).getOpcode() == ISD::SUB &&
1385 N0 == N1.getOperand(0).getOperand(1))
1386 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1387 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1389 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1390 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1391 SDValue N00 = N0.getOperand(0);
1392 SDValue N01 = N0.getOperand(1);
1393 SDValue N10 = N1.getOperand(0);
1394 SDValue N11 = N1.getOperand(1);
1396 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1397 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1398 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1399 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1402 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1403 return SDValue(N, 0);
1405 // fold (a+b) -> (a|b) iff a and b share no bits.
1406 if (VT.isInteger() && !VT.isVector()) {
1407 APInt LHSZero, LHSOne;
1408 APInt RHSZero, RHSOne;
1409 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1410 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1412 if (LHSZero.getBoolValue()) {
1413 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1415 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1416 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1417 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1418 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1419 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1423 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1424 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1425 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1426 if (Result.getNode()) return Result;
1428 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1429 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1430 if (Result.getNode()) return Result;
1433 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1434 if (N1.getOpcode() == ISD::SHL &&
1435 N1.getOperand(0).getOpcode() == ISD::SUB)
1436 if (ConstantSDNode *C =
1437 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1438 if (C->getAPIntValue() == 0)
1439 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1440 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1441 N1.getOperand(0).getOperand(1),
1443 if (N0.getOpcode() == ISD::SHL &&
1444 N0.getOperand(0).getOpcode() == ISD::SUB)
1445 if (ConstantSDNode *C =
1446 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1447 if (C->getAPIntValue() == 0)
1448 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1449 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1450 N0.getOperand(0).getOperand(1),
1453 if (N1.getOpcode() == ISD::AND) {
1454 SDValue AndOp0 = N1.getOperand(0);
1455 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1456 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1457 unsigned DestBits = VT.getScalarType().getSizeInBits();
1459 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1460 // and similar xforms where the inner op is either ~0 or 0.
1461 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1462 DebugLoc DL = N->getDebugLoc();
1463 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1467 // add (sext i1), X -> sub X, (zext i1)
1468 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1469 N0.getOperand(0).getValueType() == MVT::i1 &&
1470 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1471 DebugLoc DL = N->getDebugLoc();
1472 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1473 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1479 SDValue DAGCombiner::visitADDC(SDNode *N) {
1480 SDValue N0 = N->getOperand(0);
1481 SDValue N1 = N->getOperand(1);
1482 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1483 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1484 EVT VT = N0.getValueType();
1486 // If the flag result is dead, turn this into an ADD.
1487 if (N->hasNUsesOfValue(0, 1))
1488 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1489 DAG.getNode(ISD::CARRY_FALSE,
1490 N->getDebugLoc(), MVT::Glue));
1492 // canonicalize constant to RHS.
1494 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1496 // fold (addc x, 0) -> x + no carry out
1497 if (N1C && N1C->isNullValue())
1498 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1499 N->getDebugLoc(), MVT::Glue));
1501 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1502 APInt LHSZero, LHSOne;
1503 APInt RHSZero, RHSOne;
1504 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1505 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1507 if (LHSZero.getBoolValue()) {
1508 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1510 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1511 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1512 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1513 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1514 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1515 DAG.getNode(ISD::CARRY_FALSE,
1516 N->getDebugLoc(), MVT::Glue));
1522 SDValue DAGCombiner::visitADDE(SDNode *N) {
1523 SDValue N0 = N->getOperand(0);
1524 SDValue N1 = N->getOperand(1);
1525 SDValue CarryIn = N->getOperand(2);
1526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1527 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1529 // If both operands are null we know that carry out will always be false.
1530 if (N0C && N0C->isNullValue() && N0 == N1)
1531 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE,
1535 // canonicalize constant to RHS
1537 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1540 // fold (adde x, y, false) -> (addc x, y)
1541 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1542 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1547 // Since it may not be valid to emit a fold to zero for vector initializers
1548 // check if we can before folding.
1549 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1550 SelectionDAG &DAG, bool LegalOperations) {
1551 if (!VT.isVector()) {
1552 return DAG.getConstant(0, VT);
1554 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1555 // Produce a vector of zeros.
1556 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1557 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1558 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1559 &Ops[0], Ops.size());
1564 SDValue DAGCombiner::visitSUB(SDNode *N) {
1565 SDValue N0 = N->getOperand(0);
1566 SDValue N1 = N->getOperand(1);
1567 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1568 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1569 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1570 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1571 EVT VT = N0.getValueType();
1574 if (VT.isVector()) {
1575 SDValue FoldedVOp = SimplifyVBinOp(N);
1576 if (FoldedVOp.getNode()) return FoldedVOp;
1579 // fold (sub x, x) -> 0
1580 // FIXME: Refactor this and xor and other similar operations together.
1582 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1583 // fold (sub c1, c2) -> c1-c2
1585 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1586 // fold (sub x, c) -> (add x, -c)
1588 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1589 DAG.getConstant(-N1C->getAPIntValue(), VT));
1590 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1591 if (N0C && N0C->isAllOnesValue())
1592 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1593 // fold A-(A-B) -> B
1594 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1595 return N1.getOperand(1);
1596 // fold (A+B)-A -> B
1597 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1598 return N0.getOperand(1);
1599 // fold (A+B)-B -> A
1600 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1601 return N0.getOperand(0);
1602 // fold C2-(A+C1) -> (C2-C1)-A
1603 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1604 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1605 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1608 // fold ((A+(B+or-C))-B) -> A+or-C
1609 if (N0.getOpcode() == ISD::ADD &&
1610 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1611 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1612 N0.getOperand(1).getOperand(0) == N1)
1613 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1614 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1615 // fold ((A+(C+B))-B) -> A+C
1616 if (N0.getOpcode() == ISD::ADD &&
1617 N0.getOperand(1).getOpcode() == ISD::ADD &&
1618 N0.getOperand(1).getOperand(1) == N1)
1619 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1620 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1621 // fold ((A-(B-C))-C) -> A-B
1622 if (N0.getOpcode() == ISD::SUB &&
1623 N0.getOperand(1).getOpcode() == ISD::SUB &&
1624 N0.getOperand(1).getOperand(1) == N1)
1625 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1626 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1628 // If either operand of a sub is undef, the result is undef
1629 if (N0.getOpcode() == ISD::UNDEF)
1631 if (N1.getOpcode() == ISD::UNDEF)
1634 // If the relocation model supports it, consider symbol offsets.
1635 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1636 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1637 // fold (sub Sym, c) -> Sym-c
1638 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1639 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1641 (uint64_t)N1C->getSExtValue());
1642 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1643 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1644 if (GA->getGlobal() == GB->getGlobal())
1645 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1652 SDValue DAGCombiner::visitMUL(SDNode *N) {
1653 SDValue N0 = N->getOperand(0);
1654 SDValue N1 = N->getOperand(1);
1655 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1656 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1657 EVT VT = N0.getValueType();
1660 if (VT.isVector()) {
1661 SDValue FoldedVOp = SimplifyVBinOp(N);
1662 if (FoldedVOp.getNode()) return FoldedVOp;
1665 // fold (mul x, undef) -> 0
1666 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1667 return DAG.getConstant(0, VT);
1668 // fold (mul c1, c2) -> c1*c2
1670 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1671 // canonicalize constant to RHS
1673 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1674 // fold (mul x, 0) -> 0
1675 if (N1C && N1C->isNullValue())
1677 // fold (mul x, -1) -> 0-x
1678 if (N1C && N1C->isAllOnesValue())
1679 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1680 DAG.getConstant(0, VT), N0);
1681 // fold (mul x, (1 << c)) -> x << c
1682 if (N1C && N1C->getAPIntValue().isPowerOf2())
1683 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1684 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1685 getShiftAmountTy(N0.getValueType())));
1686 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1687 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1688 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1689 // FIXME: If the input is something that is easily negated (e.g. a
1690 // single-use add), we should put the negate there.
1691 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1692 DAG.getConstant(0, VT),
1693 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1694 DAG.getConstant(Log2Val,
1695 getShiftAmountTy(N0.getValueType()))));
1697 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1698 if (N1C && N0.getOpcode() == ISD::SHL &&
1699 isa<ConstantSDNode>(N0.getOperand(1))) {
1700 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1701 N1, N0.getOperand(1));
1702 AddToWorkList(C3.getNode());
1703 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1704 N0.getOperand(0), C3);
1707 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1710 SDValue Sh(0,0), Y(0,0);
1711 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1712 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1713 N0.getNode()->hasOneUse()) {
1715 } else if (N1.getOpcode() == ISD::SHL &&
1716 isa<ConstantSDNode>(N1.getOperand(1)) &&
1717 N1.getNode()->hasOneUse()) {
1722 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1723 Sh.getOperand(0), Y);
1724 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1725 Mul, Sh.getOperand(1));
1729 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1730 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1731 isa<ConstantSDNode>(N0.getOperand(1)))
1732 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1733 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1734 N0.getOperand(0), N1),
1735 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1736 N0.getOperand(1), N1));
1739 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1740 if (RMUL.getNode() != 0)
1746 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1747 SDValue N0 = N->getOperand(0);
1748 SDValue N1 = N->getOperand(1);
1749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1751 EVT VT = N->getValueType(0);
1754 if (VT.isVector()) {
1755 SDValue FoldedVOp = SimplifyVBinOp(N);
1756 if (FoldedVOp.getNode()) return FoldedVOp;
1759 // fold (sdiv c1, c2) -> c1/c2
1760 if (N0C && N1C && !N1C->isNullValue())
1761 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1762 // fold (sdiv X, 1) -> X
1763 if (N1C && N1C->getSExtValue() == 1LL)
1765 // fold (sdiv X, -1) -> 0-X
1766 if (N1C && N1C->isAllOnesValue())
1767 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1768 DAG.getConstant(0, VT), N0);
1769 // If we know the sign bits of both operands are zero, strength reduce to a
1770 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1771 if (!VT.isVector()) {
1772 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1773 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1776 // fold (sdiv X, pow2) -> simple ops after legalize
1777 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1778 (isPowerOf2_64(N1C->getSExtValue()) ||
1779 isPowerOf2_64(-N1C->getSExtValue()))) {
1780 // If dividing by powers of two is cheap, then don't perform the following
1782 if (TLI.isPow2DivCheap())
1785 int64_t pow2 = N1C->getSExtValue();
1786 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1787 unsigned lg2 = Log2_64(abs2);
1789 // Splat the sign bit into the register
1790 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1791 DAG.getConstant(VT.getSizeInBits()-1,
1792 getShiftAmountTy(N0.getValueType())));
1793 AddToWorkList(SGN.getNode());
1795 // Add (N0 < 0) ? abs2 - 1 : 0;
1796 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1797 DAG.getConstant(VT.getSizeInBits() - lg2,
1798 getShiftAmountTy(SGN.getValueType())));
1799 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1800 AddToWorkList(SRL.getNode());
1801 AddToWorkList(ADD.getNode()); // Divide by pow2
1802 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1803 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1805 // If we're dividing by a positive value, we're done. Otherwise, we must
1806 // negate the result.
1810 AddToWorkList(SRA.getNode());
1811 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1812 DAG.getConstant(0, VT), SRA);
1815 // if integer divide is expensive and we satisfy the requirements, emit an
1816 // alternate sequence.
1817 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1818 !TLI.isIntDivCheap()) {
1819 SDValue Op = BuildSDIV(N);
1820 if (Op.getNode()) return Op;
1824 if (N0.getOpcode() == ISD::UNDEF)
1825 return DAG.getConstant(0, VT);
1826 // X / undef -> undef
1827 if (N1.getOpcode() == ISD::UNDEF)
1833 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1834 SDValue N0 = N->getOperand(0);
1835 SDValue N1 = N->getOperand(1);
1836 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1837 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1838 EVT VT = N->getValueType(0);
1841 if (VT.isVector()) {
1842 SDValue FoldedVOp = SimplifyVBinOp(N);
1843 if (FoldedVOp.getNode()) return FoldedVOp;
1846 // fold (udiv c1, c2) -> c1/c2
1847 if (N0C && N1C && !N1C->isNullValue())
1848 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1849 // fold (udiv x, (1 << c)) -> x >>u c
1850 if (N1C && N1C->getAPIntValue().isPowerOf2())
1851 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1852 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1853 getShiftAmountTy(N0.getValueType())));
1854 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1855 if (N1.getOpcode() == ISD::SHL) {
1856 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1857 if (SHC->getAPIntValue().isPowerOf2()) {
1858 EVT ADDVT = N1.getOperand(1).getValueType();
1859 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1861 DAG.getConstant(SHC->getAPIntValue()
1864 AddToWorkList(Add.getNode());
1865 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1869 // fold (udiv x, c) -> alternate
1870 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1871 SDValue Op = BuildUDIV(N);
1872 if (Op.getNode()) return Op;
1876 if (N0.getOpcode() == ISD::UNDEF)
1877 return DAG.getConstant(0, VT);
1878 // X / undef -> undef
1879 if (N1.getOpcode() == ISD::UNDEF)
1885 SDValue DAGCombiner::visitSREM(SDNode *N) {
1886 SDValue N0 = N->getOperand(0);
1887 SDValue N1 = N->getOperand(1);
1888 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1889 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1890 EVT VT = N->getValueType(0);
1892 // fold (srem c1, c2) -> c1%c2
1893 if (N0C && N1C && !N1C->isNullValue())
1894 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1895 // If we know the sign bits of both operands are zero, strength reduce to a
1896 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1897 if (!VT.isVector()) {
1898 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1899 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1902 // If X/C can be simplified by the division-by-constant logic, lower
1903 // X%C to the equivalent of X-X/C*C.
1904 if (N1C && !N1C->isNullValue()) {
1905 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1906 AddToWorkList(Div.getNode());
1907 SDValue OptimizedDiv = combine(Div.getNode());
1908 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1909 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1911 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1912 AddToWorkList(Mul.getNode());
1918 if (N0.getOpcode() == ISD::UNDEF)
1919 return DAG.getConstant(0, VT);
1920 // X % undef -> undef
1921 if (N1.getOpcode() == ISD::UNDEF)
1927 SDValue DAGCombiner::visitUREM(SDNode *N) {
1928 SDValue N0 = N->getOperand(0);
1929 SDValue N1 = N->getOperand(1);
1930 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1931 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1932 EVT VT = N->getValueType(0);
1934 // fold (urem c1, c2) -> c1%c2
1935 if (N0C && N1C && !N1C->isNullValue())
1936 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1937 // fold (urem x, pow2) -> (and x, pow2-1)
1938 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1939 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1940 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1941 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1942 if (N1.getOpcode() == ISD::SHL) {
1943 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1944 if (SHC->getAPIntValue().isPowerOf2()) {
1946 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1947 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1949 AddToWorkList(Add.getNode());
1950 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1955 // If X/C can be simplified by the division-by-constant logic, lower
1956 // X%C to the equivalent of X-X/C*C.
1957 if (N1C && !N1C->isNullValue()) {
1958 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1959 AddToWorkList(Div.getNode());
1960 SDValue OptimizedDiv = combine(Div.getNode());
1961 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1962 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1964 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1965 AddToWorkList(Mul.getNode());
1971 if (N0.getOpcode() == ISD::UNDEF)
1972 return DAG.getConstant(0, VT);
1973 // X % undef -> undef
1974 if (N1.getOpcode() == ISD::UNDEF)
1980 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1981 SDValue N0 = N->getOperand(0);
1982 SDValue N1 = N->getOperand(1);
1983 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1984 EVT VT = N->getValueType(0);
1985 DebugLoc DL = N->getDebugLoc();
1987 // fold (mulhs x, 0) -> 0
1988 if (N1C && N1C->isNullValue())
1990 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1991 if (N1C && N1C->getAPIntValue() == 1)
1992 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1993 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1994 getShiftAmountTy(N0.getValueType())));
1995 // fold (mulhs x, undef) -> 0
1996 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1997 return DAG.getConstant(0, VT);
1999 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2001 if (VT.isSimple() && !VT.isVector()) {
2002 MVT Simple = VT.getSimpleVT();
2003 unsigned SimpleSize = Simple.getSizeInBits();
2004 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2005 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2006 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2007 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2008 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2009 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2010 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2011 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2018 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2019 SDValue N0 = N->getOperand(0);
2020 SDValue N1 = N->getOperand(1);
2021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2022 EVT VT = N->getValueType(0);
2023 DebugLoc DL = N->getDebugLoc();
2025 // fold (mulhu x, 0) -> 0
2026 if (N1C && N1C->isNullValue())
2028 // fold (mulhu x, 1) -> 0
2029 if (N1C && N1C->getAPIntValue() == 1)
2030 return DAG.getConstant(0, N0.getValueType());
2031 // fold (mulhu x, undef) -> 0
2032 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2033 return DAG.getConstant(0, VT);
2035 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2037 if (VT.isSimple() && !VT.isVector()) {
2038 MVT Simple = VT.getSimpleVT();
2039 unsigned SimpleSize = Simple.getSizeInBits();
2040 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2041 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2042 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2043 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2044 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2045 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2046 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2047 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2054 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2055 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2056 /// that are being performed. Return true if a simplification was made.
2058 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2060 // If the high half is not needed, just compute the low half.
2061 bool HiExists = N->hasAnyUseOfValue(1);
2063 (!LegalOperations ||
2064 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2065 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2066 N->op_begin(), N->getNumOperands());
2067 return CombineTo(N, Res, Res);
2070 // If the low half is not needed, just compute the high half.
2071 bool LoExists = N->hasAnyUseOfValue(0);
2073 (!LegalOperations ||
2074 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2075 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2076 N->op_begin(), N->getNumOperands());
2077 return CombineTo(N, Res, Res);
2080 // If both halves are used, return as it is.
2081 if (LoExists && HiExists)
2084 // If the two computed results can be simplified separately, separate them.
2086 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2087 N->op_begin(), N->getNumOperands());
2088 AddToWorkList(Lo.getNode());
2089 SDValue LoOpt = combine(Lo.getNode());
2090 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2091 (!LegalOperations ||
2092 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2093 return CombineTo(N, LoOpt, LoOpt);
2097 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2098 N->op_begin(), N->getNumOperands());
2099 AddToWorkList(Hi.getNode());
2100 SDValue HiOpt = combine(Hi.getNode());
2101 if (HiOpt.getNode() && HiOpt != Hi &&
2102 (!LegalOperations ||
2103 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2104 return CombineTo(N, HiOpt, HiOpt);
2110 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2111 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2112 if (Res.getNode()) return Res;
2114 EVT VT = N->getValueType(0);
2115 DebugLoc DL = N->getDebugLoc();
2117 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2119 if (VT.isSimple() && !VT.isVector()) {
2120 MVT Simple = VT.getSimpleVT();
2121 unsigned SimpleSize = Simple.getSizeInBits();
2122 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2123 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2124 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2125 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2126 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2127 // Compute the high part as N1.
2128 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2129 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2130 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2131 // Compute the low part as N0.
2132 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2133 return CombineTo(N, Lo, Hi);
2140 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2141 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2142 if (Res.getNode()) return Res;
2144 EVT VT = N->getValueType(0);
2145 DebugLoc DL = N->getDebugLoc();
2147 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2149 if (VT.isSimple() && !VT.isVector()) {
2150 MVT Simple = VT.getSimpleVT();
2151 unsigned SimpleSize = Simple.getSizeInBits();
2152 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2153 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2154 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2155 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2156 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2157 // Compute the high part as N1.
2158 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2159 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2160 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2161 // Compute the low part as N0.
2162 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2163 return CombineTo(N, Lo, Hi);
2170 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2171 // (smulo x, 2) -> (saddo x, x)
2172 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2173 if (C2->getAPIntValue() == 2)
2174 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2175 N->getOperand(0), N->getOperand(0));
2180 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2181 // (umulo x, 2) -> (uaddo x, x)
2182 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2183 if (C2->getAPIntValue() == 2)
2184 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2185 N->getOperand(0), N->getOperand(0));
2190 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2191 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2192 if (Res.getNode()) return Res;
2197 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2198 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2199 if (Res.getNode()) return Res;
2204 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2205 /// two operands of the same opcode, try to simplify it.
2206 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2207 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2208 EVT VT = N0.getValueType();
2209 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2211 // Bail early if none of these transforms apply.
2212 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2214 // For each of OP in AND/OR/XOR:
2215 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2216 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2217 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2218 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2220 // do not sink logical op inside of a vector extend, since it may combine
2222 EVT Op0VT = N0.getOperand(0).getValueType();
2223 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2224 N0.getOpcode() == ISD::SIGN_EXTEND ||
2225 // Avoid infinite looping with PromoteIntBinOp.
2226 (N0.getOpcode() == ISD::ANY_EXTEND &&
2227 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2228 (N0.getOpcode() == ISD::TRUNCATE &&
2229 (!TLI.isZExtFree(VT, Op0VT) ||
2230 !TLI.isTruncateFree(Op0VT, VT)) &&
2231 TLI.isTypeLegal(Op0VT))) &&
2233 Op0VT == N1.getOperand(0).getValueType() &&
2234 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2235 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2236 N0.getOperand(0).getValueType(),
2237 N0.getOperand(0), N1.getOperand(0));
2238 AddToWorkList(ORNode.getNode());
2239 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2242 // For each of OP in SHL/SRL/SRA/AND...
2243 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2244 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2245 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2246 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2247 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2248 N0.getOperand(1) == N1.getOperand(1)) {
2249 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2250 N0.getOperand(0).getValueType(),
2251 N0.getOperand(0), N1.getOperand(0));
2252 AddToWorkList(ORNode.getNode());
2253 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2254 ORNode, N0.getOperand(1));
2260 SDValue DAGCombiner::visitAND(SDNode *N) {
2261 SDValue N0 = N->getOperand(0);
2262 SDValue N1 = N->getOperand(1);
2263 SDValue LL, LR, RL, RR, CC0, CC1;
2264 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2265 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2266 EVT VT = N1.getValueType();
2267 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2270 if (VT.isVector()) {
2271 SDValue FoldedVOp = SimplifyVBinOp(N);
2272 if (FoldedVOp.getNode()) return FoldedVOp;
2275 // fold (and x, undef) -> 0
2276 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2277 return DAG.getConstant(0, VT);
2278 // fold (and c1, c2) -> c1&c2
2280 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2281 // canonicalize constant to RHS
2283 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2284 // fold (and x, -1) -> x
2285 if (N1C && N1C->isAllOnesValue())
2287 // if (and x, c) is known to be zero, return 0
2288 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2289 APInt::getAllOnesValue(BitWidth)))
2290 return DAG.getConstant(0, VT);
2292 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2293 if (RAND.getNode() != 0)
2295 // fold (and (or x, C), D) -> D if (C & D) == D
2296 if (N1C && N0.getOpcode() == ISD::OR)
2297 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2298 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2300 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2301 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2302 SDValue N0Op0 = N0.getOperand(0);
2303 APInt Mask = ~N1C->getAPIntValue();
2304 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2305 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2306 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2307 N0.getValueType(), N0Op0);
2309 // Replace uses of the AND with uses of the Zero extend node.
2312 // We actually want to replace all uses of the any_extend with the
2313 // zero_extend, to avoid duplicating things. This will later cause this
2314 // AND to be folded.
2315 CombineTo(N0.getNode(), Zext);
2316 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2319 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2320 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2321 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2322 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2324 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2325 LL.getValueType().isInteger()) {
2326 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2327 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2328 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2329 LR.getValueType(), LL, RL);
2330 AddToWorkList(ORNode.getNode());
2331 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2333 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2334 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2335 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2336 LR.getValueType(), LL, RL);
2337 AddToWorkList(ANDNode.getNode());
2338 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2340 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2341 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2342 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2343 LR.getValueType(), LL, RL);
2344 AddToWorkList(ORNode.getNode());
2345 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2348 // canonicalize equivalent to ll == rl
2349 if (LL == RR && LR == RL) {
2350 Op1 = ISD::getSetCCSwappedOperands(Op1);
2353 if (LL == RL && LR == RR) {
2354 bool isInteger = LL.getValueType().isInteger();
2355 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2356 if (Result != ISD::SETCC_INVALID &&
2357 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2358 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2363 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2364 if (N0.getOpcode() == N1.getOpcode()) {
2365 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2366 if (Tmp.getNode()) return Tmp;
2369 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2370 // fold (and (sra)) -> (and (srl)) when possible.
2371 if (!VT.isVector() &&
2372 SimplifyDemandedBits(SDValue(N, 0)))
2373 return SDValue(N, 0);
2375 // fold (zext_inreg (extload x)) -> (zextload x)
2376 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2377 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2378 EVT MemVT = LN0->getMemoryVT();
2379 // If we zero all the possible extended bits, then we can turn this into
2380 // a zextload if we are running before legalize or the operation is legal.
2381 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2382 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2383 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2384 ((!LegalOperations && !LN0->isVolatile()) ||
2385 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2386 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2387 LN0->getChain(), LN0->getBasePtr(),
2388 LN0->getPointerInfo(), MemVT,
2389 LN0->isVolatile(), LN0->isNonTemporal(),
2390 LN0->getAlignment());
2392 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2393 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2396 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2397 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2399 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2400 EVT MemVT = LN0->getMemoryVT();
2401 // If we zero all the possible extended bits, then we can turn this into
2402 // a zextload if we are running before legalize or the operation is legal.
2403 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2404 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2405 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2406 ((!LegalOperations && !LN0->isVolatile()) ||
2407 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2408 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2410 LN0->getBasePtr(), LN0->getPointerInfo(),
2412 LN0->isVolatile(), LN0->isNonTemporal(),
2413 LN0->getAlignment());
2415 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2416 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2420 // fold (and (load x), 255) -> (zextload x, i8)
2421 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2422 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2423 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2424 (N0.getOpcode() == ISD::ANY_EXTEND &&
2425 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2426 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2427 LoadSDNode *LN0 = HasAnyExt
2428 ? cast<LoadSDNode>(N0.getOperand(0))
2429 : cast<LoadSDNode>(N0);
2430 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2431 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2432 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2433 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2434 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2435 EVT LoadedVT = LN0->getMemoryVT();
2437 if (ExtVT == LoadedVT &&
2438 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2439 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2442 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2443 LN0->getChain(), LN0->getBasePtr(),
2444 LN0->getPointerInfo(),
2445 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2446 LN0->getAlignment());
2448 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2449 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2452 // Do not change the width of a volatile load.
2453 // Do not generate loads of non-round integer types since these can
2454 // be expensive (and would be wrong if the type is not byte sized).
2455 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2456 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2457 EVT PtrType = LN0->getOperand(1).getValueType();
2459 unsigned Alignment = LN0->getAlignment();
2460 SDValue NewPtr = LN0->getBasePtr();
2462 // For big endian targets, we need to add an offset to the pointer
2463 // to load the correct bytes. For little endian systems, we merely
2464 // need to read fewer bytes from the same pointer.
2465 if (TLI.isBigEndian()) {
2466 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2467 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2468 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2469 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2470 NewPtr, DAG.getConstant(PtrOff, PtrType));
2471 Alignment = MinAlign(Alignment, PtrOff);
2474 AddToWorkList(NewPtr.getNode());
2476 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2478 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2479 LN0->getChain(), NewPtr,
2480 LN0->getPointerInfo(),
2481 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2484 CombineTo(LN0, Load, Load.getValue(1));
2485 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2494 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2496 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2497 bool DemandHighBits) {
2498 if (!LegalOperations)
2501 EVT VT = N->getValueType(0);
2502 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2504 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2507 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2508 bool LookPassAnd0 = false;
2509 bool LookPassAnd1 = false;
2510 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2512 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2514 if (N0.getOpcode() == ISD::AND) {
2515 if (!N0.getNode()->hasOneUse())
2517 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2518 if (!N01C || N01C->getZExtValue() != 0xFF00)
2520 N0 = N0.getOperand(0);
2521 LookPassAnd0 = true;
2524 if (N1.getOpcode() == ISD::AND) {
2525 if (!N1.getNode()->hasOneUse())
2527 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2528 if (!N11C || N11C->getZExtValue() != 0xFF)
2530 N1 = N1.getOperand(0);
2531 LookPassAnd1 = true;
2534 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2536 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2538 if (!N0.getNode()->hasOneUse() ||
2539 !N1.getNode()->hasOneUse())
2542 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2543 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2546 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2549 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2550 SDValue N00 = N0->getOperand(0);
2551 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2552 if (!N00.getNode()->hasOneUse())
2554 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2555 if (!N001C || N001C->getZExtValue() != 0xFF)
2557 N00 = N00.getOperand(0);
2558 LookPassAnd0 = true;
2561 SDValue N10 = N1->getOperand(0);
2562 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2563 if (!N10.getNode()->hasOneUse())
2565 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2566 if (!N101C || N101C->getZExtValue() != 0xFF00)
2568 N10 = N10.getOperand(0);
2569 LookPassAnd1 = true;
2575 // Make sure everything beyond the low halfword is zero since the SRL 16
2576 // will clear the top bits.
2577 unsigned OpSizeInBits = VT.getSizeInBits();
2578 if (DemandHighBits && OpSizeInBits > 16 &&
2579 (!LookPassAnd0 || !LookPassAnd1) &&
2580 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2583 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2584 if (OpSizeInBits > 16)
2585 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2586 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2590 /// isBSwapHWordElement - Return true if the specified node is an element
2591 /// that makes up a 32-bit packed halfword byteswap. i.e.
2592 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2593 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2594 if (!N.getNode()->hasOneUse())
2597 unsigned Opc = N.getOpcode();
2598 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2601 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2606 switch (N1C->getZExtValue()) {
2609 case 0xFF: Num = 0; break;
2610 case 0xFF00: Num = 1; break;
2611 case 0xFF0000: Num = 2; break;
2612 case 0xFF000000: Num = 3; break;
2615 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2616 SDValue N0 = N.getOperand(0);
2617 if (Opc == ISD::AND) {
2618 if (Num == 0 || Num == 2) {
2620 // (x >> 8) & 0xff0000
2621 if (N0.getOpcode() != ISD::SRL)
2623 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2624 if (!C || C->getZExtValue() != 8)
2627 // (x << 8) & 0xff00
2628 // (x << 8) & 0xff000000
2629 if (N0.getOpcode() != ISD::SHL)
2631 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2632 if (!C || C->getZExtValue() != 8)
2635 } else if (Opc == ISD::SHL) {
2637 // (x & 0xff0000) << 8
2638 if (Num != 0 && Num != 2)
2640 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2641 if (!C || C->getZExtValue() != 8)
2643 } else { // Opc == ISD::SRL
2644 // (x & 0xff00) >> 8
2645 // (x & 0xff000000) >> 8
2646 if (Num != 1 && Num != 3)
2648 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2649 if (!C || C->getZExtValue() != 8)
2656 Parts[Num] = N0.getOperand(0).getNode();
2660 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2661 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2662 /// => (rotl (bswap x), 16)
2663 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2664 if (!LegalOperations)
2667 EVT VT = N->getValueType(0);
2670 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2673 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2675 // (or (or (and), (and)), (or (and), (and)))
2676 // (or (or (or (and), (and)), (and)), (and))
2677 if (N0.getOpcode() != ISD::OR)
2679 SDValue N00 = N0.getOperand(0);
2680 SDValue N01 = N0.getOperand(1);
2682 if (N1.getOpcode() == ISD::OR) {
2683 // (or (or (and), (and)), (or (and), (and)))
2684 SDValue N000 = N00.getOperand(0);
2685 if (!isBSwapHWordElement(N000, Parts))
2688 SDValue N001 = N00.getOperand(1);
2689 if (!isBSwapHWordElement(N001, Parts))
2691 SDValue N010 = N01.getOperand(0);
2692 if (!isBSwapHWordElement(N010, Parts))
2694 SDValue N011 = N01.getOperand(1);
2695 if (!isBSwapHWordElement(N011, Parts))
2698 // (or (or (or (and), (and)), (and)), (and))
2699 if (!isBSwapHWordElement(N1, Parts))
2701 if (!isBSwapHWordElement(N01, Parts))
2703 if (N00.getOpcode() != ISD::OR)
2705 SDValue N000 = N00.getOperand(0);
2706 if (!isBSwapHWordElement(N000, Parts))
2708 SDValue N001 = N00.getOperand(1);
2709 if (!isBSwapHWordElement(N001, Parts))
2713 // Make sure the parts are all coming from the same node.
2714 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2717 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2718 SDValue(Parts[0],0));
2720 // Result of the bswap should be rotated by 16. If it's not legal, than
2721 // do (x << 16) | (x >> 16).
2722 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2723 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2724 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2725 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2726 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2727 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2728 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2729 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2732 SDValue DAGCombiner::visitOR(SDNode *N) {
2733 SDValue N0 = N->getOperand(0);
2734 SDValue N1 = N->getOperand(1);
2735 SDValue LL, LR, RL, RR, CC0, CC1;
2736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2738 EVT VT = N1.getValueType();
2741 if (VT.isVector()) {
2742 SDValue FoldedVOp = SimplifyVBinOp(N);
2743 if (FoldedVOp.getNode()) return FoldedVOp;
2746 // fold (or x, undef) -> -1
2747 if (!LegalOperations &&
2748 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2749 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2750 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2752 // fold (or c1, c2) -> c1|c2
2754 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2755 // canonicalize constant to RHS
2757 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2758 // fold (or x, 0) -> x
2759 if (N1C && N1C->isNullValue())
2761 // fold (or x, -1) -> -1
2762 if (N1C && N1C->isAllOnesValue())
2764 // fold (or x, c) -> c iff (x & ~c) == 0
2765 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2768 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2769 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2770 if (BSwap.getNode() != 0)
2772 BSwap = MatchBSwapHWordLow(N, N0, N1);
2773 if (BSwap.getNode() != 0)
2777 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2778 if (ROR.getNode() != 0)
2780 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2781 // iff (c1 & c2) == 0.
2782 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2783 isa<ConstantSDNode>(N0.getOperand(1))) {
2784 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2785 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2786 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2787 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2788 N0.getOperand(0), N1),
2789 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2791 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2792 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2793 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2794 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2796 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2797 LL.getValueType().isInteger()) {
2798 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2799 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2800 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2801 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2802 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2803 LR.getValueType(), LL, RL);
2804 AddToWorkList(ORNode.getNode());
2805 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2807 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2808 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2809 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2810 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2811 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2812 LR.getValueType(), LL, RL);
2813 AddToWorkList(ANDNode.getNode());
2814 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2817 // canonicalize equivalent to ll == rl
2818 if (LL == RR && LR == RL) {
2819 Op1 = ISD::getSetCCSwappedOperands(Op1);
2822 if (LL == RL && LR == RR) {
2823 bool isInteger = LL.getValueType().isInteger();
2824 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2825 if (Result != ISD::SETCC_INVALID &&
2826 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2827 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2832 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2833 if (N0.getOpcode() == N1.getOpcode()) {
2834 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2835 if (Tmp.getNode()) return Tmp;
2838 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2839 if (N0.getOpcode() == ISD::AND &&
2840 N1.getOpcode() == ISD::AND &&
2841 N0.getOperand(1).getOpcode() == ISD::Constant &&
2842 N1.getOperand(1).getOpcode() == ISD::Constant &&
2843 // Don't increase # computations.
2844 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2845 // We can only do this xform if we know that bits from X that are set in C2
2846 // but not in C1 are already zero. Likewise for Y.
2847 const APInt &LHSMask =
2848 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2849 const APInt &RHSMask =
2850 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2852 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2853 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2854 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2855 N0.getOperand(0), N1.getOperand(0));
2856 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2857 DAG.getConstant(LHSMask | RHSMask, VT));
2861 // See if this is some rotate idiom.
2862 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2863 return SDValue(Rot, 0);
2865 // Simplify the operands using demanded-bits information.
2866 if (!VT.isVector() &&
2867 SimplifyDemandedBits(SDValue(N, 0)))
2868 return SDValue(N, 0);
2873 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2874 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2875 if (Op.getOpcode() == ISD::AND) {
2876 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2877 Mask = Op.getOperand(1);
2878 Op = Op.getOperand(0);
2884 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2892 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2893 // idioms for rotate, and if the target supports rotation instructions, generate
2895 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2896 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2897 EVT VT = LHS.getValueType();
2898 if (!TLI.isTypeLegal(VT)) return 0;
2900 // The target must have at least one rotate flavor.
2901 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2902 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2903 if (!HasROTL && !HasROTR) return 0;
2905 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2906 SDValue LHSShift; // The shift.
2907 SDValue LHSMask; // AND value if any.
2908 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2909 return 0; // Not part of a rotate.
2911 SDValue RHSShift; // The shift.
2912 SDValue RHSMask; // AND value if any.
2913 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2914 return 0; // Not part of a rotate.
2916 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2917 return 0; // Not shifting the same value.
2919 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2920 return 0; // Shifts must disagree.
2922 // Canonicalize shl to left side in a shl/srl pair.
2923 if (RHSShift.getOpcode() == ISD::SHL) {
2924 std::swap(LHS, RHS);
2925 std::swap(LHSShift, RHSShift);
2926 std::swap(LHSMask , RHSMask );
2929 unsigned OpSizeInBits = VT.getSizeInBits();
2930 SDValue LHSShiftArg = LHSShift.getOperand(0);
2931 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2932 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2934 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2935 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2936 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2937 RHSShiftAmt.getOpcode() == ISD::Constant) {
2938 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2939 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2940 if ((LShVal + RShVal) != OpSizeInBits)
2945 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2947 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2949 // If there is an AND of either shifted operand, apply it to the result.
2950 if (LHSMask.getNode() || RHSMask.getNode()) {
2951 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2953 if (LHSMask.getNode()) {
2954 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2955 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2957 if (RHSMask.getNode()) {
2958 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2959 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2962 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2965 return Rot.getNode();
2968 // If there is a mask here, and we have a variable shift, we can't be sure
2969 // that we're masking out the right stuff.
2970 if (LHSMask.getNode() || RHSMask.getNode())
2973 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2974 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2975 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2976 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2977 if (ConstantSDNode *SUBC =
2978 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2979 if (SUBC->getAPIntValue() == OpSizeInBits) {
2981 return DAG.getNode(ISD::ROTL, DL, VT,
2982 LHSShiftArg, LHSShiftAmt).getNode();
2984 return DAG.getNode(ISD::ROTR, DL, VT,
2985 LHSShiftArg, RHSShiftAmt).getNode();
2990 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2991 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2992 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2993 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2994 if (ConstantSDNode *SUBC =
2995 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2996 if (SUBC->getAPIntValue() == OpSizeInBits) {
2998 return DAG.getNode(ISD::ROTR, DL, VT,
2999 LHSShiftArg, RHSShiftAmt).getNode();
3001 return DAG.getNode(ISD::ROTL, DL, VT,
3002 LHSShiftArg, LHSShiftAmt).getNode();
3007 // Look for sign/zext/any-extended or truncate cases:
3008 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3009 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3010 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3011 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3012 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3013 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3014 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3015 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3016 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3017 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3018 if (RExtOp0.getOpcode() == ISD::SUB &&
3019 RExtOp0.getOperand(1) == LExtOp0) {
3020 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3022 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3023 // (rotr x, (sub 32, y))
3024 if (ConstantSDNode *SUBC =
3025 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3026 if (SUBC->getAPIntValue() == OpSizeInBits) {
3027 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3029 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3032 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3033 RExtOp0 == LExtOp0.getOperand(1)) {
3034 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3036 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3037 // (rotl x, (sub 32, y))
3038 if (ConstantSDNode *SUBC =
3039 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3040 if (SUBC->getAPIntValue() == OpSizeInBits) {
3041 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3043 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3052 SDValue DAGCombiner::visitXOR(SDNode *N) {
3053 SDValue N0 = N->getOperand(0);
3054 SDValue N1 = N->getOperand(1);
3055 SDValue LHS, RHS, CC;
3056 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3057 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3058 EVT VT = N0.getValueType();
3061 if (VT.isVector()) {
3062 SDValue FoldedVOp = SimplifyVBinOp(N);
3063 if (FoldedVOp.getNode()) return FoldedVOp;
3066 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3067 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3068 return DAG.getConstant(0, VT);
3069 // fold (xor x, undef) -> undef
3070 if (N0.getOpcode() == ISD::UNDEF)
3072 if (N1.getOpcode() == ISD::UNDEF)
3074 // fold (xor c1, c2) -> c1^c2
3076 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3077 // canonicalize constant to RHS
3079 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3080 // fold (xor x, 0) -> x
3081 if (N1C && N1C->isNullValue())
3084 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3085 if (RXOR.getNode() != 0)
3088 // fold !(x cc y) -> (x !cc y)
3089 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3090 bool isInt = LHS.getValueType().isInteger();
3091 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3094 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3095 switch (N0.getOpcode()) {
3097 llvm_unreachable("Unhandled SetCC Equivalent!");
3099 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3100 case ISD::SELECT_CC:
3101 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3102 N0.getOperand(3), NotCC);
3107 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3108 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3109 N0.getNode()->hasOneUse() &&
3110 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3111 SDValue V = N0.getOperand(0);
3112 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3113 DAG.getConstant(1, V.getValueType()));
3114 AddToWorkList(V.getNode());
3115 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3118 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3119 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3120 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3121 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3122 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3123 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3124 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3125 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3126 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3127 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3130 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3131 if (N1C && N1C->isAllOnesValue() &&
3132 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3133 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3134 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3135 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3136 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3137 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3138 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3139 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3142 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3143 if (N1C && N0.getOpcode() == ISD::XOR) {
3144 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3145 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3147 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3148 DAG.getConstant(N1C->getAPIntValue() ^
3149 N00C->getAPIntValue(), VT));
3151 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3152 DAG.getConstant(N1C->getAPIntValue() ^
3153 N01C->getAPIntValue(), VT));
3155 // fold (xor x, x) -> 0
3157 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3159 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3160 if (N0.getOpcode() == N1.getOpcode()) {
3161 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3162 if (Tmp.getNode()) return Tmp;
3165 // Simplify the expression using non-local knowledge.
3166 if (!VT.isVector() &&
3167 SimplifyDemandedBits(SDValue(N, 0)))
3168 return SDValue(N, 0);
3173 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3174 /// the shift amount is a constant.
3175 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3176 SDNode *LHS = N->getOperand(0).getNode();
3177 if (!LHS->hasOneUse()) return SDValue();
3179 // We want to pull some binops through shifts, so that we have (and (shift))
3180 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3181 // thing happens with address calculations, so it's important to canonicalize
3183 bool HighBitSet = false; // Can we transform this if the high bit is set?
3185 switch (LHS->getOpcode()) {
3186 default: return SDValue();
3189 HighBitSet = false; // We can only transform sra if the high bit is clear.
3192 HighBitSet = true; // We can only transform sra if the high bit is set.
3195 if (N->getOpcode() != ISD::SHL)
3196 return SDValue(); // only shl(add) not sr[al](add).
3197 HighBitSet = false; // We can only transform sra if the high bit is clear.
3201 // We require the RHS of the binop to be a constant as well.
3202 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3203 if (!BinOpCst) return SDValue();
3205 // FIXME: disable this unless the input to the binop is a shift by a constant.
3206 // If it is not a shift, it pessimizes some common cases like:
3208 // void foo(int *X, int i) { X[i & 1235] = 1; }
3209 // int bar(int *X, int i) { return X[i & 255]; }
3210 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3211 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3212 BinOpLHSVal->getOpcode() != ISD::SRA &&
3213 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3214 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3217 EVT VT = N->getValueType(0);
3219 // If this is a signed shift right, and the high bit is modified by the
3220 // logical operation, do not perform the transformation. The highBitSet
3221 // boolean indicates the value of the high bit of the constant which would
3222 // cause it to be modified for this operation.
3223 if (N->getOpcode() == ISD::SRA) {
3224 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3225 if (BinOpRHSSignSet != HighBitSet)
3229 // Fold the constants, shifting the binop RHS by the shift amount.
3230 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3232 LHS->getOperand(1), N->getOperand(1));
3234 // Create the new shift.
3235 SDValue NewShift = DAG.getNode(N->getOpcode(),
3236 LHS->getOperand(0).getDebugLoc(),
3237 VT, LHS->getOperand(0), N->getOperand(1));
3239 // Create the new binop.
3240 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3243 SDValue DAGCombiner::visitSHL(SDNode *N) {
3244 SDValue N0 = N->getOperand(0);
3245 SDValue N1 = N->getOperand(1);
3246 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3247 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3248 EVT VT = N0.getValueType();
3249 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3251 // fold (shl c1, c2) -> c1<<c2
3253 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3254 // fold (shl 0, x) -> 0
3255 if (N0C && N0C->isNullValue())
3257 // fold (shl x, c >= size(x)) -> undef
3258 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3259 return DAG.getUNDEF(VT);
3260 // fold (shl x, 0) -> x
3261 if (N1C && N1C->isNullValue())
3263 // fold (shl undef, x) -> 0
3264 if (N0.getOpcode() == ISD::UNDEF)
3265 return DAG.getConstant(0, VT);
3266 // if (shl x, c) is known to be zero, return 0
3267 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3268 APInt::getAllOnesValue(OpSizeInBits)))
3269 return DAG.getConstant(0, VT);
3270 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3271 if (N1.getOpcode() == ISD::TRUNCATE &&
3272 N1.getOperand(0).getOpcode() == ISD::AND &&
3273 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3274 SDValue N101 = N1.getOperand(0).getOperand(1);
3275 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3276 EVT TruncVT = N1.getValueType();
3277 SDValue N100 = N1.getOperand(0).getOperand(0);
3278 APInt TruncC = N101C->getAPIntValue();
3279 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3280 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3281 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3282 DAG.getNode(ISD::TRUNCATE,
3285 DAG.getConstant(TruncC, TruncVT)));
3289 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3290 return SDValue(N, 0);
3292 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3293 if (N1C && N0.getOpcode() == ISD::SHL &&
3294 N0.getOperand(1).getOpcode() == ISD::Constant) {
3295 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3296 uint64_t c2 = N1C->getZExtValue();
3297 if (c1 + c2 >= OpSizeInBits)
3298 return DAG.getConstant(0, VT);
3299 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3300 DAG.getConstant(c1 + c2, N1.getValueType()));
3303 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3304 // For this to be valid, the second form must not preserve any of the bits
3305 // that are shifted out by the inner shift in the first form. This means
3306 // the outer shift size must be >= the number of bits added by the ext.
3307 // As a corollary, we don't care what kind of ext it is.
3308 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3309 N0.getOpcode() == ISD::ANY_EXTEND ||
3310 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3311 N0.getOperand(0).getOpcode() == ISD::SHL &&
3312 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3314 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3315 uint64_t c2 = N1C->getZExtValue();
3316 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3317 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3318 if (c2 >= OpSizeInBits - InnerShiftSize) {
3319 if (c1 + c2 >= OpSizeInBits)
3320 return DAG.getConstant(0, VT);
3321 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3322 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3323 N0.getOperand(0)->getOperand(0)),
3324 DAG.getConstant(c1 + c2, N1.getValueType()));
3328 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3329 // (and (srl x, (sub c1, c2), MASK)
3330 if (N1C && N0.getOpcode() == ISD::SRL &&
3331 N0.getOperand(1).getOpcode() == ISD::Constant) {
3332 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3333 if (c1 < VT.getSizeInBits()) {
3334 uint64_t c2 = N1C->getZExtValue();
3335 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3336 VT.getSizeInBits() - c1);
3339 Mask = Mask.shl(c2-c1);
3340 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3341 DAG.getConstant(c2-c1, N1.getValueType()));
3343 Mask = Mask.lshr(c1-c2);
3344 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3345 DAG.getConstant(c1-c2, N1.getValueType()));
3347 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3348 DAG.getConstant(Mask, VT));
3351 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3352 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3353 SDValue HiBitsMask =
3354 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3355 VT.getSizeInBits() -
3356 N1C->getZExtValue()),
3358 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3363 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3364 if (NewSHL.getNode())
3371 SDValue DAGCombiner::visitSRA(SDNode *N) {
3372 SDValue N0 = N->getOperand(0);
3373 SDValue N1 = N->getOperand(1);
3374 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3375 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3376 EVT VT = N0.getValueType();
3377 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3379 // fold (sra c1, c2) -> (sra c1, c2)
3381 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3382 // fold (sra 0, x) -> 0
3383 if (N0C && N0C->isNullValue())
3385 // fold (sra -1, x) -> -1
3386 if (N0C && N0C->isAllOnesValue())
3388 // fold (sra x, (setge c, size(x))) -> undef
3389 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3390 return DAG.getUNDEF(VT);
3391 // fold (sra x, 0) -> x
3392 if (N1C && N1C->isNullValue())
3394 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3396 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3397 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3398 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3400 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3401 ExtVT, VT.getVectorNumElements());
3402 if ((!LegalOperations ||
3403 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3404 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3405 N0.getOperand(0), DAG.getValueType(ExtVT));
3408 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3409 if (N1C && N0.getOpcode() == ISD::SRA) {
3410 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3411 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3412 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3413 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3414 DAG.getConstant(Sum, N1C->getValueType(0)));
3418 // fold (sra (shl X, m), (sub result_size, n))
3419 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3420 // result_size - n != m.
3421 // If truncate is free for the target sext(shl) is likely to result in better
3423 if (N0.getOpcode() == ISD::SHL) {
3424 // Get the two constanst of the shifts, CN0 = m, CN = n.
3425 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3427 // Determine what the truncate's result bitsize and type would be.
3429 EVT::getIntegerVT(*DAG.getContext(),
3430 OpSizeInBits - N1C->getZExtValue());
3431 // Determine the residual right-shift amount.
3432 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3434 // If the shift is not a no-op (in which case this should be just a sign
3435 // extend already), the truncated to type is legal, sign_extend is legal
3436 // on that type, and the truncate to that type is both legal and free,
3437 // perform the transform.
3438 if ((ShiftAmt > 0) &&
3439 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3440 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3441 TLI.isTruncateFree(VT, TruncVT)) {
3443 SDValue Amt = DAG.getConstant(ShiftAmt,
3444 getShiftAmountTy(N0.getOperand(0).getValueType()));
3445 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3446 N0.getOperand(0), Amt);
3447 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3449 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3450 N->getValueType(0), Trunc);
3455 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3456 if (N1.getOpcode() == ISD::TRUNCATE &&
3457 N1.getOperand(0).getOpcode() == ISD::AND &&
3458 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3459 SDValue N101 = N1.getOperand(0).getOperand(1);
3460 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3461 EVT TruncVT = N1.getValueType();
3462 SDValue N100 = N1.getOperand(0).getOperand(0);
3463 APInt TruncC = N101C->getAPIntValue();
3464 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3465 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3466 DAG.getNode(ISD::AND, N->getDebugLoc(),
3468 DAG.getNode(ISD::TRUNCATE,
3471 DAG.getConstant(TruncC, TruncVT)));
3475 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3476 // if c1 is equal to the number of bits the trunc removes
3477 if (N0.getOpcode() == ISD::TRUNCATE &&
3478 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3479 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3480 N0.getOperand(0).hasOneUse() &&
3481 N0.getOperand(0).getOperand(1).hasOneUse() &&
3482 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3483 EVT LargeVT = N0.getOperand(0).getValueType();
3484 ConstantSDNode *LargeShiftAmt =
3485 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3487 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3488 LargeShiftAmt->getZExtValue()) {
3490 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3491 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3492 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3493 N0.getOperand(0).getOperand(0), Amt);
3494 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3498 // Simplify, based on bits shifted out of the LHS.
3499 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3500 return SDValue(N, 0);
3503 // If the sign bit is known to be zero, switch this to a SRL.
3504 if (DAG.SignBitIsZero(N0))
3505 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3508 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3509 if (NewSRA.getNode())
3516 SDValue DAGCombiner::visitSRL(SDNode *N) {
3517 SDValue N0 = N->getOperand(0);
3518 SDValue N1 = N->getOperand(1);
3519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3521 EVT VT = N0.getValueType();
3522 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3524 // fold (srl c1, c2) -> c1 >>u c2
3526 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3527 // fold (srl 0, x) -> 0
3528 if (N0C && N0C->isNullValue())
3530 // fold (srl x, c >= size(x)) -> undef
3531 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3532 return DAG.getUNDEF(VT);
3533 // fold (srl x, 0) -> x
3534 if (N1C && N1C->isNullValue())
3536 // if (srl x, c) is known to be zero, return 0
3537 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3538 APInt::getAllOnesValue(OpSizeInBits)))
3539 return DAG.getConstant(0, VT);
3541 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3542 if (N1C && N0.getOpcode() == ISD::SRL &&
3543 N0.getOperand(1).getOpcode() == ISD::Constant) {
3544 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3545 uint64_t c2 = N1C->getZExtValue();
3546 if (c1 + c2 >= OpSizeInBits)
3547 return DAG.getConstant(0, VT);
3548 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3549 DAG.getConstant(c1 + c2, N1.getValueType()));
3552 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3553 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3554 N0.getOperand(0).getOpcode() == ISD::SRL &&
3555 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3557 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3558 uint64_t c2 = N1C->getZExtValue();
3559 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3560 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3561 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3562 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3563 if (c1 + OpSizeInBits == InnerShiftSize) {
3564 if (c1 + c2 >= InnerShiftSize)
3565 return DAG.getConstant(0, VT);
3566 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3567 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3568 N0.getOperand(0)->getOperand(0),
3569 DAG.getConstant(c1 + c2, ShiftCountVT)));
3573 // fold (srl (shl x, c), c) -> (and x, cst2)
3574 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3575 N0.getValueSizeInBits() <= 64) {
3576 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3577 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3578 DAG.getConstant(~0ULL >> ShAmt, VT));
3582 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3583 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3584 // Shifting in all undef bits?
3585 EVT SmallVT = N0.getOperand(0).getValueType();
3586 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3587 return DAG.getUNDEF(VT);
3589 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3590 uint64_t ShiftAmt = N1C->getZExtValue();
3591 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3593 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3594 AddToWorkList(SmallShift.getNode());
3595 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3599 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3600 // bit, which is unmodified by sra.
3601 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3602 if (N0.getOpcode() == ISD::SRA)
3603 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3606 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3607 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3608 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3609 APInt KnownZero, KnownOne;
3610 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3611 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3613 // If any of the input bits are KnownOne, then the input couldn't be all
3614 // zeros, thus the result of the srl will always be zero.
3615 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3617 // If all of the bits input the to ctlz node are known to be zero, then
3618 // the result of the ctlz is "32" and the result of the shift is one.
3619 APInt UnknownBits = ~KnownZero & Mask;
3620 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3622 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3623 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3624 // Okay, we know that only that the single bit specified by UnknownBits
3625 // could be set on input to the CTLZ node. If this bit is set, the SRL
3626 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3627 // to an SRL/XOR pair, which is likely to simplify more.
3628 unsigned ShAmt = UnknownBits.countTrailingZeros();
3629 SDValue Op = N0.getOperand(0);
3632 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3633 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3634 AddToWorkList(Op.getNode());
3637 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3638 Op, DAG.getConstant(1, VT));
3642 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3643 if (N1.getOpcode() == ISD::TRUNCATE &&
3644 N1.getOperand(0).getOpcode() == ISD::AND &&
3645 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3646 SDValue N101 = N1.getOperand(0).getOperand(1);
3647 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3648 EVT TruncVT = N1.getValueType();
3649 SDValue N100 = N1.getOperand(0).getOperand(0);
3650 APInt TruncC = N101C->getAPIntValue();
3651 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3652 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3653 DAG.getNode(ISD::AND, N->getDebugLoc(),
3655 DAG.getNode(ISD::TRUNCATE,
3658 DAG.getConstant(TruncC, TruncVT)));
3662 // fold operands of srl based on knowledge that the low bits are not
3664 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3665 return SDValue(N, 0);
3668 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3669 if (NewSRL.getNode())
3673 // Attempt to convert a srl of a load into a narrower zero-extending load.
3674 SDValue NarrowLoad = ReduceLoadWidth(N);
3675 if (NarrowLoad.getNode())
3678 // Here is a common situation. We want to optimize:
3681 // %b = and i32 %a, 2
3682 // %c = srl i32 %b, 1
3683 // brcond i32 %c ...
3689 // %c = setcc eq %b, 0
3692 // However when after the source operand of SRL is optimized into AND, the SRL
3693 // itself may not be optimized further. Look for it and add the BRCOND into
3695 if (N->hasOneUse()) {
3696 SDNode *Use = *N->use_begin();
3697 if (Use->getOpcode() == ISD::BRCOND)
3699 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3700 // Also look pass the truncate.
3701 Use = *Use->use_begin();
3702 if (Use->getOpcode() == ISD::BRCOND)
3710 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3711 SDValue N0 = N->getOperand(0);
3712 EVT VT = N->getValueType(0);
3714 // fold (ctlz c1) -> c2
3715 if (isa<ConstantSDNode>(N0))
3716 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3720 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3721 SDValue N0 = N->getOperand(0);
3722 EVT VT = N->getValueType(0);
3724 // fold (cttz c1) -> c2
3725 if (isa<ConstantSDNode>(N0))
3726 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3730 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3731 SDValue N0 = N->getOperand(0);
3732 EVT VT = N->getValueType(0);
3734 // fold (ctpop c1) -> c2
3735 if (isa<ConstantSDNode>(N0))
3736 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3740 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3741 SDValue N0 = N->getOperand(0);
3742 SDValue N1 = N->getOperand(1);
3743 SDValue N2 = N->getOperand(2);
3744 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3745 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3746 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3747 EVT VT = N->getValueType(0);
3748 EVT VT0 = N0.getValueType();
3750 // fold (select C, X, X) -> X
3753 // fold (select true, X, Y) -> X
3754 if (N0C && !N0C->isNullValue())
3756 // fold (select false, X, Y) -> Y
3757 if (N0C && N0C->isNullValue())
3759 // fold (select C, 1, X) -> (or C, X)
3760 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3761 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3762 // fold (select C, 0, 1) -> (xor C, 1)
3763 if (VT.isInteger() &&
3766 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3767 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3770 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3771 N0, DAG.getConstant(1, VT0));
3772 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3773 N0, DAG.getConstant(1, VT0));
3774 AddToWorkList(XORNode.getNode());
3776 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3777 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3779 // fold (select C, 0, X) -> (and (not C), X)
3780 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3781 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3782 AddToWorkList(NOTNode.getNode());
3783 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3785 // fold (select C, X, 1) -> (or (not C), X)
3786 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3787 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3788 AddToWorkList(NOTNode.getNode());
3789 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3791 // fold (select C, X, 0) -> (and C, X)
3792 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3793 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3794 // fold (select X, X, Y) -> (or X, Y)
3795 // fold (select X, 1, Y) -> (or X, Y)
3796 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3797 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3798 // fold (select X, Y, X) -> (and X, Y)
3799 // fold (select X, Y, 0) -> (and X, Y)
3800 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3801 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3803 // If we can fold this based on the true/false value, do so.
3804 if (SimplifySelectOps(N, N1, N2))
3805 return SDValue(N, 0); // Don't revisit N.
3807 // fold selects based on a setcc into other things, such as min/max/abs
3808 if (N0.getOpcode() == ISD::SETCC) {
3810 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3811 // having to say they don't support SELECT_CC on every type the DAG knows
3812 // about, since there is no way to mark an opcode illegal at all value types
3813 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3814 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3815 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3816 N0.getOperand(0), N0.getOperand(1),
3817 N1, N2, N0.getOperand(2));
3818 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3824 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3825 SDValue N0 = N->getOperand(0);
3826 SDValue N1 = N->getOperand(1);
3827 SDValue N2 = N->getOperand(2);
3828 SDValue N3 = N->getOperand(3);
3829 SDValue N4 = N->getOperand(4);
3830 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3832 // fold select_cc lhs, rhs, x, x, cc -> x
3836 // Determine if the condition we're dealing with is constant
3837 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3838 N0, N1, CC, N->getDebugLoc(), false);
3839 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3841 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3842 if (!SCCC->isNullValue())
3843 return N2; // cond always true -> true val
3845 return N3; // cond always false -> false val
3848 // Fold to a simpler select_cc
3849 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3850 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3851 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3854 // If we can fold this based on the true/false value, do so.
3855 if (SimplifySelectOps(N, N2, N3))
3856 return SDValue(N, 0); // Don't revisit N.
3858 // fold select_cc into other things, such as min/max/abs
3859 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3862 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3863 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3864 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3868 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3869 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3870 // transformation. Returns true if extension are possible and the above
3871 // mentioned transformation is profitable.
3872 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3874 SmallVector<SDNode*, 4> &ExtendNodes,
3875 const TargetLowering &TLI) {
3876 bool HasCopyToRegUses = false;
3877 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3878 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3879 UE = N0.getNode()->use_end();
3884 if (UI.getUse().getResNo() != N0.getResNo())
3886 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3887 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3888 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3889 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3890 // Sign bits will be lost after a zext.
3893 for (unsigned i = 0; i != 2; ++i) {
3894 SDValue UseOp = User->getOperand(i);
3897 if (!isa<ConstantSDNode>(UseOp))
3902 ExtendNodes.push_back(User);
3905 // If truncates aren't free and there are users we can't
3906 // extend, it isn't worthwhile.
3909 // Remember if this value is live-out.
3910 if (User->getOpcode() == ISD::CopyToReg)
3911 HasCopyToRegUses = true;
3914 if (HasCopyToRegUses) {
3915 bool BothLiveOut = false;
3916 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3918 SDUse &Use = UI.getUse();
3919 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3925 // Both unextended and extended values are live out. There had better be
3926 // a good reason for the transformation.
3927 return ExtendNodes.size();
3932 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
3933 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
3934 ISD::NodeType ExtType) {
3935 // Extend SetCC uses if necessary.
3936 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3937 SDNode *SetCC = SetCCs[i];
3938 SmallVector<SDValue, 4> Ops;
3940 for (unsigned j = 0; j != 2; ++j) {
3941 SDValue SOp = SetCC->getOperand(j);
3943 Ops.push_back(ExtLoad);
3945 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
3948 Ops.push_back(SetCC->getOperand(2));
3949 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
3950 &Ops[0], Ops.size()));
3954 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3955 SDValue N0 = N->getOperand(0);
3956 EVT VT = N->getValueType(0);
3958 // fold (sext c1) -> c1
3959 if (isa<ConstantSDNode>(N0))
3960 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3962 // fold (sext (sext x)) -> (sext x)
3963 // fold (sext (aext x)) -> (sext x)
3964 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3965 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3968 if (N0.getOpcode() == ISD::TRUNCATE) {
3969 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3970 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3971 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3972 if (NarrowLoad.getNode()) {
3973 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3974 if (NarrowLoad.getNode() != N0.getNode()) {
3975 CombineTo(N0.getNode(), NarrowLoad);
3976 // CombineTo deleted the truncate, if needed, but not what's under it.
3979 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3982 // See if the value being truncated is already sign extended. If so, just
3983 // eliminate the trunc/sext pair.
3984 SDValue Op = N0.getOperand(0);
3985 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3986 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3987 unsigned DestBits = VT.getScalarType().getSizeInBits();
3988 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3990 if (OpBits == DestBits) {
3991 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3992 // bits, it is already ready.
3993 if (NumSignBits > DestBits-MidBits)
3995 } else if (OpBits < DestBits) {
3996 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3997 // bits, just sext from i32.
3998 if (NumSignBits > OpBits-MidBits)
3999 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4001 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4002 // bits, just truncate to i32.
4003 if (NumSignBits > OpBits-MidBits)
4004 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4007 // fold (sext (truncate x)) -> (sextinreg x).
4008 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4009 N0.getValueType())) {
4010 if (OpBits < DestBits)
4011 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4012 else if (OpBits > DestBits)
4013 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4014 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4015 DAG.getValueType(N0.getValueType()));
4019 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4020 // None of the supported targets knows how to perform load and sign extend
4021 // on vectors in one instruction. We only perform this transformation on
4023 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4024 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4025 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4026 bool DoXform = true;
4027 SmallVector<SDNode*, 4> SetCCs;
4028 if (!N0.hasOneUse())
4029 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4031 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4032 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4034 LN0->getBasePtr(), LN0->getPointerInfo(),
4036 LN0->isVolatile(), LN0->isNonTemporal(),
4037 LN0->getAlignment());
4038 CombineTo(N, ExtLoad);
4039 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4040 N0.getValueType(), ExtLoad);
4041 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4042 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4044 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4048 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4049 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4050 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4051 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4052 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4053 EVT MemVT = LN0->getMemoryVT();
4054 if ((!LegalOperations && !LN0->isVolatile()) ||
4055 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4056 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4058 LN0->getBasePtr(), LN0->getPointerInfo(),
4060 LN0->isVolatile(), LN0->isNonTemporal(),
4061 LN0->getAlignment());
4062 CombineTo(N, ExtLoad);
4063 CombineTo(N0.getNode(),
4064 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4065 N0.getValueType(), ExtLoad),
4066 ExtLoad.getValue(1));
4067 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4071 // fold (sext (and/or/xor (load x), cst)) ->
4072 // (and/or/xor (sextload x), (sext cst))
4073 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4074 N0.getOpcode() == ISD::XOR) &&
4075 isa<LoadSDNode>(N0.getOperand(0)) &&
4076 N0.getOperand(1).getOpcode() == ISD::Constant &&
4077 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4078 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4079 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4080 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4081 bool DoXform = true;
4082 SmallVector<SDNode*, 4> SetCCs;
4083 if (!N0.hasOneUse())
4084 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4087 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4088 LN0->getChain(), LN0->getBasePtr(),
4089 LN0->getPointerInfo(),
4092 LN0->isNonTemporal(),
4093 LN0->getAlignment());
4094 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4095 Mask = Mask.sext(VT.getSizeInBits());
4096 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4097 ExtLoad, DAG.getConstant(Mask, VT));
4098 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4099 N0.getOperand(0).getDebugLoc(),
4100 N0.getOperand(0).getValueType(), ExtLoad);
4102 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4103 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4105 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4110 if (N0.getOpcode() == ISD::SETCC) {
4111 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4112 // Only do this before legalize for now.
4113 if (VT.isVector() && !LegalOperations) {
4114 EVT N0VT = N0.getOperand(0).getValueType();
4115 // We know that the # elements of the results is the same as the
4116 // # elements of the compare (and the # elements of the compare result
4117 // for that matter). Check to see that they are the same size. If so,
4118 // we know that the element size of the sext'd result matches the
4119 // element size of the compare operands.
4120 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4121 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4123 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4124 // If the desired elements are smaller or larger than the source
4125 // elements we can use a matching integer vector type and then
4126 // truncate/sign extend
4128 EVT MatchingElementType =
4129 EVT::getIntegerVT(*DAG.getContext(),
4130 N0VT.getScalarType().getSizeInBits());
4131 EVT MatchingVectorType =
4132 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4133 N0VT.getVectorNumElements());
4135 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4137 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4138 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4142 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4143 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4145 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4147 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4148 NegOne, DAG.getConstant(0, VT),
4149 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4150 if (SCC.getNode()) return SCC;
4151 if (!LegalOperations ||
4152 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4153 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4154 DAG.getSetCC(N->getDebugLoc(),
4155 TLI.getSetCCResultType(VT),
4156 N0.getOperand(0), N0.getOperand(1),
4157 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4158 NegOne, DAG.getConstant(0, VT));
4161 // fold (sext x) -> (zext x) if the sign bit is known zero.
4162 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4163 DAG.SignBitIsZero(N0))
4164 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4169 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4170 SDValue N0 = N->getOperand(0);
4171 EVT VT = N->getValueType(0);
4173 // fold (zext c1) -> c1
4174 if (isa<ConstantSDNode>(N0))
4175 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4176 // fold (zext (zext x)) -> (zext x)
4177 // fold (zext (aext x)) -> (zext x)
4178 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4179 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4182 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4183 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4184 if (N0.getOpcode() == ISD::TRUNCATE) {
4185 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4186 if (NarrowLoad.getNode()) {
4187 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4188 if (NarrowLoad.getNode() != N0.getNode()) {
4189 CombineTo(N0.getNode(), NarrowLoad);
4190 // CombineTo deleted the truncate, if needed, but not what's under it.
4193 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4197 // fold (zext (truncate x)) -> (and x, mask)
4198 if (N0.getOpcode() == ISD::TRUNCATE &&
4199 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4201 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4202 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4203 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4204 if (NarrowLoad.getNode()) {
4205 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4206 if (NarrowLoad.getNode() != N0.getNode()) {
4207 CombineTo(N0.getNode(), NarrowLoad);
4208 // CombineTo deleted the truncate, if needed, but not what's under it.
4211 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4214 SDValue Op = N0.getOperand(0);
4215 if (Op.getValueType().bitsLT(VT)) {
4216 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4217 } else if (Op.getValueType().bitsGT(VT)) {
4218 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4220 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4221 N0.getValueType().getScalarType());
4224 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4225 // if either of the casts is not free.
4226 if (N0.getOpcode() == ISD::AND &&
4227 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4228 N0.getOperand(1).getOpcode() == ISD::Constant &&
4229 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4230 N0.getValueType()) ||
4231 !TLI.isZExtFree(N0.getValueType(), VT))) {
4232 SDValue X = N0.getOperand(0).getOperand(0);
4233 if (X.getValueType().bitsLT(VT)) {
4234 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4235 } else if (X.getValueType().bitsGT(VT)) {
4236 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4238 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4239 Mask = Mask.zext(VT.getSizeInBits());
4240 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4241 X, DAG.getConstant(Mask, VT));
4244 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4245 // None of the supported targets knows how to perform load and vector_zext
4246 // on vectors in one instruction. We only perform this transformation on
4248 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4249 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4250 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4251 bool DoXform = true;
4252 SmallVector<SDNode*, 4> SetCCs;
4253 if (!N0.hasOneUse())
4254 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4256 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4257 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4259 LN0->getBasePtr(), LN0->getPointerInfo(),
4261 LN0->isVolatile(), LN0->isNonTemporal(),
4262 LN0->getAlignment());
4263 CombineTo(N, ExtLoad);
4264 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4265 N0.getValueType(), ExtLoad);
4266 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4268 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4270 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4274 // fold (zext (and/or/xor (load x), cst)) ->
4275 // (and/or/xor (zextload x), (zext cst))
4276 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4277 N0.getOpcode() == ISD::XOR) &&
4278 isa<LoadSDNode>(N0.getOperand(0)) &&
4279 N0.getOperand(1).getOpcode() == ISD::Constant &&
4280 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4281 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4282 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4283 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4284 bool DoXform = true;
4285 SmallVector<SDNode*, 4> SetCCs;
4286 if (!N0.hasOneUse())
4287 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4290 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4291 LN0->getChain(), LN0->getBasePtr(),
4292 LN0->getPointerInfo(),
4295 LN0->isNonTemporal(),
4296 LN0->getAlignment());
4297 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4298 Mask = Mask.zext(VT.getSizeInBits());
4299 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4300 ExtLoad, DAG.getConstant(Mask, VT));
4301 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4302 N0.getOperand(0).getDebugLoc(),
4303 N0.getOperand(0).getValueType(), ExtLoad);
4305 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4306 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4308 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4313 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4314 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4315 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4316 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4317 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4318 EVT MemVT = LN0->getMemoryVT();
4319 if ((!LegalOperations && !LN0->isVolatile()) ||
4320 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4321 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4323 LN0->getBasePtr(), LN0->getPointerInfo(),
4325 LN0->isVolatile(), LN0->isNonTemporal(),
4326 LN0->getAlignment());
4327 CombineTo(N, ExtLoad);
4328 CombineTo(N0.getNode(),
4329 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4331 ExtLoad.getValue(1));
4332 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4336 if (N0.getOpcode() == ISD::SETCC) {
4337 if (!LegalOperations && VT.isVector()) {
4338 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4339 // Only do this before legalize for now.
4340 EVT N0VT = N0.getOperand(0).getValueType();
4341 EVT EltVT = VT.getVectorElementType();
4342 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4343 DAG.getConstant(1, EltVT));
4344 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4345 // We know that the # elements of the results is the same as the
4346 // # elements of the compare (and the # elements of the compare result
4347 // for that matter). Check to see that they are the same size. If so,
4348 // we know that the element size of the sext'd result matches the
4349 // element size of the compare operands.
4350 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4351 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4353 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4354 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4355 &OneOps[0], OneOps.size()));
4357 // If the desired elements are smaller or larger than the source
4358 // elements we can use a matching integer vector type and then
4359 // truncate/sign extend
4360 EVT MatchingElementType =
4361 EVT::getIntegerVT(*DAG.getContext(),
4362 N0VT.getScalarType().getSizeInBits());
4363 EVT MatchingVectorType =
4364 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4365 N0VT.getVectorNumElements());
4367 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4369 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4370 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4371 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4372 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4373 &OneOps[0], OneOps.size()));
4376 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4378 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4379 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4380 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4381 if (SCC.getNode()) return SCC;
4384 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4385 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4386 isa<ConstantSDNode>(N0.getOperand(1)) &&
4387 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4389 SDValue ShAmt = N0.getOperand(1);
4390 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4391 if (N0.getOpcode() == ISD::SHL) {
4392 SDValue InnerZExt = N0.getOperand(0);
4393 // If the original shl may be shifting out bits, do not perform this
4395 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4396 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4397 if (ShAmtVal > KnownZeroBits)
4401 DebugLoc DL = N->getDebugLoc();
4403 // Ensure that the shift amount is wide enough for the shifted value.
4404 if (VT.getSizeInBits() >= 256)
4405 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4407 return DAG.getNode(N0.getOpcode(), DL, VT,
4408 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4415 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4416 SDValue N0 = N->getOperand(0);
4417 EVT VT = N->getValueType(0);
4419 // fold (aext c1) -> c1
4420 if (isa<ConstantSDNode>(N0))
4421 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4422 // fold (aext (aext x)) -> (aext x)
4423 // fold (aext (zext x)) -> (zext x)
4424 // fold (aext (sext x)) -> (sext x)
4425 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4426 N0.getOpcode() == ISD::ZERO_EXTEND ||
4427 N0.getOpcode() == ISD::SIGN_EXTEND)
4428 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4430 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4431 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4432 if (N0.getOpcode() == ISD::TRUNCATE) {
4433 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4434 if (NarrowLoad.getNode()) {
4435 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4436 if (NarrowLoad.getNode() != N0.getNode()) {
4437 CombineTo(N0.getNode(), NarrowLoad);
4438 // CombineTo deleted the truncate, if needed, but not what's under it.
4441 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4445 // fold (aext (truncate x))
4446 if (N0.getOpcode() == ISD::TRUNCATE) {
4447 SDValue TruncOp = N0.getOperand(0);
4448 if (TruncOp.getValueType() == VT)
4449 return TruncOp; // x iff x size == zext size.
4450 if (TruncOp.getValueType().bitsGT(VT))
4451 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4452 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4455 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4456 // if the trunc is not free.
4457 if (N0.getOpcode() == ISD::AND &&
4458 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4459 N0.getOperand(1).getOpcode() == ISD::Constant &&
4460 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4461 N0.getValueType())) {
4462 SDValue X = N0.getOperand(0).getOperand(0);
4463 if (X.getValueType().bitsLT(VT)) {
4464 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4465 } else if (X.getValueType().bitsGT(VT)) {
4466 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4468 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4469 Mask = Mask.zext(VT.getSizeInBits());
4470 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4471 X, DAG.getConstant(Mask, VT));
4474 // fold (aext (load x)) -> (aext (truncate (extload x)))
4475 // None of the supported targets knows how to perform load and any_ext
4476 // on vectors in one instruction. We only perform this transformation on
4478 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4479 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4480 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4481 bool DoXform = true;
4482 SmallVector<SDNode*, 4> SetCCs;
4483 if (!N0.hasOneUse())
4484 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4486 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4487 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4489 LN0->getBasePtr(), LN0->getPointerInfo(),
4491 LN0->isVolatile(), LN0->isNonTemporal(),
4492 LN0->getAlignment());
4493 CombineTo(N, ExtLoad);
4494 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4495 N0.getValueType(), ExtLoad);
4496 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4497 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4499 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4503 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4504 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4505 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4506 if (N0.getOpcode() == ISD::LOAD &&
4507 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4509 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4510 EVT MemVT = LN0->getMemoryVT();
4511 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4512 VT, LN0->getChain(), LN0->getBasePtr(),
4513 LN0->getPointerInfo(), MemVT,
4514 LN0->isVolatile(), LN0->isNonTemporal(),
4515 LN0->getAlignment());
4516 CombineTo(N, ExtLoad);
4517 CombineTo(N0.getNode(),
4518 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4519 N0.getValueType(), ExtLoad),
4520 ExtLoad.getValue(1));
4521 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4524 if (N0.getOpcode() == ISD::SETCC) {
4525 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4526 // Only do this before legalize for now.
4527 if (VT.isVector() && !LegalOperations) {
4528 EVT N0VT = N0.getOperand(0).getValueType();
4529 // We know that the # elements of the results is the same as the
4530 // # elements of the compare (and the # elements of the compare result
4531 // for that matter). Check to see that they are the same size. If so,
4532 // we know that the element size of the sext'd result matches the
4533 // element size of the compare operands.
4534 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4535 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4537 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4538 // If the desired elements are smaller or larger than the source
4539 // elements we can use a matching integer vector type and then
4540 // truncate/sign extend
4542 EVT MatchingElementType =
4543 EVT::getIntegerVT(*DAG.getContext(),
4544 N0VT.getScalarType().getSizeInBits());
4545 EVT MatchingVectorType =
4546 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4547 N0VT.getVectorNumElements());
4549 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4551 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4552 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4556 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4558 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4559 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4560 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4568 /// GetDemandedBits - See if the specified operand can be simplified with the
4569 /// knowledge that only the bits specified by Mask are used. If so, return the
4570 /// simpler operand, otherwise return a null SDValue.
4571 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4572 switch (V.getOpcode()) {
4576 // If the LHS or RHS don't contribute bits to the or, drop them.
4577 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4578 return V.getOperand(1);
4579 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4580 return V.getOperand(0);
4583 // Only look at single-use SRLs.
4584 if (!V.getNode()->hasOneUse())
4586 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4587 // See if we can recursively simplify the LHS.
4588 unsigned Amt = RHSC->getZExtValue();
4590 // Watch out for shift count overflow though.
4591 if (Amt >= Mask.getBitWidth()) break;
4592 APInt NewMask = Mask << Amt;
4593 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4594 if (SimplifyLHS.getNode())
4595 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4596 SimplifyLHS, V.getOperand(1));
4602 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4603 /// bits and then truncated to a narrower type and where N is a multiple
4604 /// of number of bits of the narrower type, transform it to a narrower load
4605 /// from address + N / num of bits of new type. If the result is to be
4606 /// extended, also fold the extension to form a extending load.
4607 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4608 unsigned Opc = N->getOpcode();
4610 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4611 SDValue N0 = N->getOperand(0);
4612 EVT VT = N->getValueType(0);
4615 // This transformation isn't valid for vector loads.
4619 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4621 if (Opc == ISD::SIGN_EXTEND_INREG) {
4622 ExtType = ISD::SEXTLOAD;
4623 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4624 } else if (Opc == ISD::SRL) {
4625 // Another special-case: SRL is basically zero-extending a narrower value.
4626 ExtType = ISD::ZEXTLOAD;
4628 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4629 if (!N01) return SDValue();
4630 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4631 VT.getSizeInBits() - N01->getZExtValue());
4633 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4636 unsigned EVTBits = ExtVT.getSizeInBits();
4638 // Do not generate loads of non-round integer types since these can
4639 // be expensive (and would be wrong if the type is not byte sized).
4640 if (!ExtVT.isRound())
4644 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4645 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4646 ShAmt = N01->getZExtValue();
4647 // Is the shift amount a multiple of size of VT?
4648 if ((ShAmt & (EVTBits-1)) == 0) {
4649 N0 = N0.getOperand(0);
4650 // Is the load width a multiple of size of VT?
4651 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4655 // At this point, we must have a load or else we can't do the transform.
4656 if (!isa<LoadSDNode>(N0)) return SDValue();
4658 // If the shift amount is larger than the input type then we're not
4659 // accessing any of the loaded bytes. If the load was a zextload/extload
4660 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4661 // If the load was a sextload then the result is a splat of the sign bit
4662 // of the extended byte. This is not worth optimizing for.
4663 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4668 // If the load is shifted left (and the result isn't shifted back right),
4669 // we can fold the truncate through the shift.
4670 unsigned ShLeftAmt = 0;
4671 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4672 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4673 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4674 ShLeftAmt = N01->getZExtValue();
4675 N0 = N0.getOperand(0);
4679 // If we haven't found a load, we can't narrow it. Don't transform one with
4680 // multiple uses, this would require adding a new load.
4681 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4682 // Don't change the width of a volatile load.
4683 cast<LoadSDNode>(N0)->isVolatile())
4686 // Verify that we are actually reducing a load width here.
4687 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4690 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4691 EVT PtrType = N0.getOperand(1).getValueType();
4693 // For big endian targets, we need to adjust the offset to the pointer to
4694 // load the correct bytes.
4695 if (TLI.isBigEndian()) {
4696 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4697 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4698 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4701 uint64_t PtrOff = ShAmt / 8;
4702 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4703 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4704 PtrType, LN0->getBasePtr(),
4705 DAG.getConstant(PtrOff, PtrType));
4706 AddToWorkList(NewPtr.getNode());
4709 if (ExtType == ISD::NON_EXTLOAD)
4710 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4711 LN0->getPointerInfo().getWithOffset(PtrOff),
4712 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign);
4714 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4715 LN0->getPointerInfo().getWithOffset(PtrOff),
4716 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4719 // Replace the old load's chain with the new load's chain.
4720 WorkListRemover DeadNodes(*this);
4721 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4724 // Shift the result left, if we've swallowed a left shift.
4725 SDValue Result = Load;
4726 if (ShLeftAmt != 0) {
4727 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4728 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4730 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4731 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4734 // Return the new loaded value.
4738 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4739 SDValue N0 = N->getOperand(0);
4740 SDValue N1 = N->getOperand(1);
4741 EVT VT = N->getValueType(0);
4742 EVT EVT = cast<VTSDNode>(N1)->getVT();
4743 unsigned VTBits = VT.getScalarType().getSizeInBits();
4744 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4746 // fold (sext_in_reg c1) -> c1
4747 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4748 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4750 // If the input is already sign extended, just drop the extension.
4751 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4754 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4755 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4756 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4757 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4758 N0.getOperand(0), N1);
4761 // fold (sext_in_reg (sext x)) -> (sext x)
4762 // fold (sext_in_reg (aext x)) -> (sext x)
4763 // if x is small enough.
4764 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4765 SDValue N00 = N0.getOperand(0);
4766 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4767 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4768 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4771 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4772 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4773 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4775 // fold operands of sext_in_reg based on knowledge that the top bits are not
4777 if (SimplifyDemandedBits(SDValue(N, 0)))
4778 return SDValue(N, 0);
4780 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4781 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4782 SDValue NarrowLoad = ReduceLoadWidth(N);
4783 if (NarrowLoad.getNode())
4786 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4787 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4788 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4789 if (N0.getOpcode() == ISD::SRL) {
4790 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4791 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4792 // We can turn this into an SRA iff the input to the SRL is already sign
4794 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4795 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4796 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4797 N0.getOperand(0), N0.getOperand(1));
4801 // fold (sext_inreg (extload x)) -> (sextload x)
4802 if (ISD::isEXTLoad(N0.getNode()) &&
4803 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4804 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4805 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4806 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4807 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4808 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4810 LN0->getBasePtr(), LN0->getPointerInfo(),
4812 LN0->isVolatile(), LN0->isNonTemporal(),
4813 LN0->getAlignment());
4814 CombineTo(N, ExtLoad);
4815 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4816 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4818 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4819 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4821 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4822 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4823 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4824 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4825 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4827 LN0->getBasePtr(), LN0->getPointerInfo(),
4829 LN0->isVolatile(), LN0->isNonTemporal(),
4830 LN0->getAlignment());
4831 CombineTo(N, ExtLoad);
4832 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4833 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4836 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
4837 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
4838 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
4839 N0.getOperand(1), false);
4840 if (BSwap.getNode() != 0)
4841 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4848 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4849 SDValue N0 = N->getOperand(0);
4850 EVT VT = N->getValueType(0);
4853 if (N0.getValueType() == N->getValueType(0))
4855 // fold (truncate c1) -> c1
4856 if (isa<ConstantSDNode>(N0))
4857 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4858 // fold (truncate (truncate x)) -> (truncate x)
4859 if (N0.getOpcode() == ISD::TRUNCATE)
4860 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4861 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4862 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4863 N0.getOpcode() == ISD::SIGN_EXTEND ||
4864 N0.getOpcode() == ISD::ANY_EXTEND) {
4865 if (N0.getOperand(0).getValueType().bitsLT(VT))
4866 // if the source is smaller than the dest, we still need an extend
4867 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4869 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4870 // if the source is larger than the dest, than we just need the truncate
4871 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4873 // if the source and dest are the same type, we can drop both the extend
4874 // and the truncate.
4875 return N0.getOperand(0);
4878 // See if we can simplify the input to this truncate through knowledge that
4879 // only the low bits are being used.
4880 // For example "trunc (or (shl x, 8), y)" // -> trunc y
4881 // Currently we only perform this optimization on scalars because vectors
4882 // may have different active low bits.
4883 if (!VT.isVector()) {
4885 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4886 VT.getSizeInBits()));
4887 if (Shorter.getNode())
4888 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4890 // fold (truncate (load x)) -> (smaller load x)
4891 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4892 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4893 SDValue Reduced = ReduceLoadWidth(N);
4894 if (Reduced.getNode())
4898 // Simplify the operands using demanded-bits information.
4899 if (!VT.isVector() &&
4900 SimplifyDemandedBits(SDValue(N, 0)))
4901 return SDValue(N, 0);
4906 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4907 SDValue Elt = N->getOperand(i);
4908 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4909 return Elt.getNode();
4910 return Elt.getOperand(Elt.getResNo()).getNode();
4913 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4914 /// if load locations are consecutive.
4915 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4916 assert(N->getOpcode() == ISD::BUILD_PAIR);
4918 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4919 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4920 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4921 LD1->getPointerInfo().getAddrSpace() !=
4922 LD2->getPointerInfo().getAddrSpace())
4924 EVT LD1VT = LD1->getValueType(0);
4926 if (ISD::isNON_EXTLoad(LD2) &&
4928 // If both are volatile this would reduce the number of volatile loads.
4929 // If one is volatile it might be ok, but play conservative and bail out.
4930 !LD1->isVolatile() &&
4931 !LD2->isVolatile() &&
4932 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4933 unsigned Align = LD1->getAlignment();
4934 unsigned NewAlign = TLI.getTargetData()->
4935 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4937 if (NewAlign <= Align &&
4938 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4939 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4940 LD1->getBasePtr(), LD1->getPointerInfo(),
4941 false, false, Align);
4947 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
4948 SDValue N0 = N->getOperand(0);
4949 EVT VT = N->getValueType(0);
4951 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4952 // Only do this before legalize, since afterward the target may be depending
4953 // on the bitconvert.
4954 // First check to see if this is all constant.
4956 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4958 bool isSimple = true;
4959 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4960 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4961 N0.getOperand(i).getOpcode() != ISD::Constant &&
4962 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4967 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4968 assert(!DestEltVT.isVector() &&
4969 "Element type of vector ValueType must not be vector!");
4971 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4974 // If the input is a constant, let getNode fold it.
4975 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4976 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4977 if (Res.getNode() != N) {
4978 if (!LegalOperations ||
4979 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4982 // Folding it resulted in an illegal node, and it's too late to
4983 // do that. Clean up the old node and forego the transformation.
4984 // Ideally this won't happen very often, because instcombine
4985 // and the earlier dagcombine runs (where illegal nodes are
4986 // permitted) should have folded most of them already.
4987 DAG.DeleteNode(Res.getNode());
4991 // (conv (conv x, t1), t2) -> (conv x, t2)
4992 if (N0.getOpcode() == ISD::BITCAST)
4993 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
4996 // fold (conv (load x)) -> (load (conv*)x)
4997 // If the resultant load doesn't need a higher alignment than the original!
4998 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4999 // Do not change the width of a volatile load.
5000 !cast<LoadSDNode>(N0)->isVolatile() &&
5001 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5002 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5003 unsigned Align = TLI.getTargetData()->
5004 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5005 unsigned OrigAlign = LN0->getAlignment();
5007 if (Align <= OrigAlign) {
5008 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5009 LN0->getBasePtr(), LN0->getPointerInfo(),
5010 LN0->isVolatile(), LN0->isNonTemporal(),
5013 CombineTo(N0.getNode(),
5014 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5015 N0.getValueType(), Load),
5021 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5022 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5023 // This often reduces constant pool loads.
5024 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5025 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5026 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5028 AddToWorkList(NewConv.getNode());
5030 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5031 if (N0.getOpcode() == ISD::FNEG)
5032 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5033 NewConv, DAG.getConstant(SignBit, VT));
5034 assert(N0.getOpcode() == ISD::FABS);
5035 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5036 NewConv, DAG.getConstant(~SignBit, VT));
5039 // fold (bitconvert (fcopysign cst, x)) ->
5040 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5041 // Note that we don't handle (copysign x, cst) because this can always be
5042 // folded to an fneg or fabs.
5043 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5044 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5045 VT.isInteger() && !VT.isVector()) {
5046 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5047 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5048 if (isTypeLegal(IntXVT)) {
5049 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5050 IntXVT, N0.getOperand(1));
5051 AddToWorkList(X.getNode());
5053 // If X has a different width than the result/lhs, sext it or truncate it.
5054 unsigned VTWidth = VT.getSizeInBits();
5055 if (OrigXWidth < VTWidth) {
5056 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5057 AddToWorkList(X.getNode());
5058 } else if (OrigXWidth > VTWidth) {
5059 // To get the sign bit in the right place, we have to shift it right
5060 // before truncating.
5061 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5062 X.getValueType(), X,
5063 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5064 AddToWorkList(X.getNode());
5065 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5066 AddToWorkList(X.getNode());
5069 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5070 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5071 X, DAG.getConstant(SignBit, VT));
5072 AddToWorkList(X.getNode());
5074 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5075 VT, N0.getOperand(0));
5076 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5077 Cst, DAG.getConstant(~SignBit, VT));
5078 AddToWorkList(Cst.getNode());
5080 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5084 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5085 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5086 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5087 if (CombineLD.getNode())
5094 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5095 EVT VT = N->getValueType(0);
5096 return CombineConsecutiveLoads(N, VT);
5099 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5100 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5101 /// destination element value type.
5102 SDValue DAGCombiner::
5103 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5104 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5106 // If this is already the right type, we're done.
5107 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5109 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5110 unsigned DstBitSize = DstEltVT.getSizeInBits();
5112 // If this is a conversion of N elements of one type to N elements of another
5113 // type, convert each element. This handles FP<->INT cases.
5114 if (SrcBitSize == DstBitSize) {
5115 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5116 BV->getValueType(0).getVectorNumElements());
5118 // Due to the FP element handling below calling this routine recursively,
5119 // we can end up with a scalar-to-vector node here.
5120 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5121 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5122 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5123 DstEltVT, BV->getOperand(0)));
5125 SmallVector<SDValue, 8> Ops;
5126 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5127 SDValue Op = BV->getOperand(i);
5128 // If the vector element type is not legal, the BUILD_VECTOR operands
5129 // are promoted and implicitly truncated. Make that explicit here.
5130 if (Op.getValueType() != SrcEltVT)
5131 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5132 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5134 AddToWorkList(Ops.back().getNode());
5136 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5137 &Ops[0], Ops.size());
5140 // Otherwise, we're growing or shrinking the elements. To avoid having to
5141 // handle annoying details of growing/shrinking FP values, we convert them to
5143 if (SrcEltVT.isFloatingPoint()) {
5144 // Convert the input float vector to a int vector where the elements are the
5146 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5147 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5148 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5152 // Now we know the input is an integer vector. If the output is a FP type,
5153 // convert to integer first, then to FP of the right size.
5154 if (DstEltVT.isFloatingPoint()) {
5155 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5156 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5157 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5159 // Next, convert to FP elements of the same size.
5160 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5163 // Okay, we know the src/dst types are both integers of differing types.
5164 // Handling growing first.
5165 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5166 if (SrcBitSize < DstBitSize) {
5167 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5169 SmallVector<SDValue, 8> Ops;
5170 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5171 i += NumInputsPerOutput) {
5172 bool isLE = TLI.isLittleEndian();
5173 APInt NewBits = APInt(DstBitSize, 0);
5174 bool EltIsUndef = true;
5175 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5176 // Shift the previously computed bits over.
5177 NewBits <<= SrcBitSize;
5178 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5179 if (Op.getOpcode() == ISD::UNDEF) continue;
5182 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5183 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5187 Ops.push_back(DAG.getUNDEF(DstEltVT));
5189 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5192 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5193 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5194 &Ops[0], Ops.size());
5197 // Finally, this must be the case where we are shrinking elements: each input
5198 // turns into multiple outputs.
5199 bool isS2V = ISD::isScalarToVector(BV);
5200 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5201 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5202 NumOutputsPerInput*BV->getNumOperands());
5203 SmallVector<SDValue, 8> Ops;
5205 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5206 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5207 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5208 Ops.push_back(DAG.getUNDEF(DstEltVT));
5212 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5213 getAPIntValue().zextOrTrunc(SrcBitSize);
5215 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5216 APInt ThisVal = OpVal.trunc(DstBitSize);
5217 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5218 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5219 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5220 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5222 OpVal = OpVal.lshr(DstBitSize);
5225 // For big endian targets, swap the order of the pieces of each element.
5226 if (TLI.isBigEndian())
5227 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5230 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5231 &Ops[0], Ops.size());
5234 SDValue DAGCombiner::visitFADD(SDNode *N) {
5235 SDValue N0 = N->getOperand(0);
5236 SDValue N1 = N->getOperand(1);
5237 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5238 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5239 EVT VT = N->getValueType(0);
5242 if (VT.isVector()) {
5243 SDValue FoldedVOp = SimplifyVBinOp(N);
5244 if (FoldedVOp.getNode()) return FoldedVOp;
5247 // fold (fadd c1, c2) -> (fadd c1, c2)
5248 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5249 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5250 // canonicalize constant to RHS
5251 if (N0CFP && !N1CFP)
5252 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5253 // fold (fadd A, 0) -> A
5254 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5256 // fold (fadd A, (fneg B)) -> (fsub A, B)
5257 if (isNegatibleForFree(N1, LegalOperations) == 2)
5258 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5259 GetNegatedExpression(N1, DAG, LegalOperations));
5260 // fold (fadd (fneg A), B) -> (fsub B, A)
5261 if (isNegatibleForFree(N0, LegalOperations) == 2)
5262 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5263 GetNegatedExpression(N0, DAG, LegalOperations));
5265 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5266 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
5267 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5268 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5269 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5270 N0.getOperand(1), N1));
5275 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5276 SDValue N0 = N->getOperand(0);
5277 SDValue N1 = N->getOperand(1);
5278 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5279 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5280 EVT VT = N->getValueType(0);
5283 if (VT.isVector()) {
5284 SDValue FoldedVOp = SimplifyVBinOp(N);
5285 if (FoldedVOp.getNode()) return FoldedVOp;
5288 // fold (fsub c1, c2) -> c1-c2
5289 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5290 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5291 // fold (fsub A, 0) -> A
5292 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5294 // fold (fsub 0, B) -> -B
5295 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
5296 if (isNegatibleForFree(N1, LegalOperations))
5297 return GetNegatedExpression(N1, DAG, LegalOperations);
5298 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5299 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5301 // fold (fsub A, (fneg B)) -> (fadd A, B)
5302 if (isNegatibleForFree(N1, LegalOperations))
5303 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5304 GetNegatedExpression(N1, DAG, LegalOperations));
5309 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5310 SDValue N0 = N->getOperand(0);
5311 SDValue N1 = N->getOperand(1);
5312 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5313 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5314 EVT VT = N->getValueType(0);
5317 if (VT.isVector()) {
5318 SDValue FoldedVOp = SimplifyVBinOp(N);
5319 if (FoldedVOp.getNode()) return FoldedVOp;
5322 // fold (fmul c1, c2) -> c1*c2
5323 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5324 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5325 // canonicalize constant to RHS
5326 if (N0CFP && !N1CFP)
5327 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5328 // fold (fmul A, 0) -> 0
5329 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5331 // fold (fmul A, 0) -> 0, vector edition.
5332 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
5334 // fold (fmul X, 2.0) -> (fadd X, X)
5335 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5336 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5337 // fold (fmul X, -1.0) -> (fneg X)
5338 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5339 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5340 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5342 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5343 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5344 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5345 // Both can be negated for free, check to see if at least one is cheaper
5347 if (LHSNeg == 2 || RHSNeg == 2)
5348 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5349 GetNegatedExpression(N0, DAG, LegalOperations),
5350 GetNegatedExpression(N1, DAG, LegalOperations));
5354 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5355 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5356 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5357 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5358 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5359 N0.getOperand(1), N1));
5364 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5365 SDValue N0 = N->getOperand(0);
5366 SDValue N1 = N->getOperand(1);
5367 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5368 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5369 EVT VT = N->getValueType(0);
5372 if (VT.isVector()) {
5373 SDValue FoldedVOp = SimplifyVBinOp(N);
5374 if (FoldedVOp.getNode()) return FoldedVOp;
5377 // fold (fdiv c1, c2) -> c1/c2
5378 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5379 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5382 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5383 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5384 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5385 // Both can be negated for free, check to see if at least one is cheaper
5387 if (LHSNeg == 2 || RHSNeg == 2)
5388 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5389 GetNegatedExpression(N0, DAG, LegalOperations),
5390 GetNegatedExpression(N1, DAG, LegalOperations));
5397 SDValue DAGCombiner::visitFREM(SDNode *N) {
5398 SDValue N0 = N->getOperand(0);
5399 SDValue N1 = N->getOperand(1);
5400 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5401 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5402 EVT VT = N->getValueType(0);
5404 // fold (frem c1, c2) -> fmod(c1,c2)
5405 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5406 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5411 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5412 SDValue N0 = N->getOperand(0);
5413 SDValue N1 = N->getOperand(1);
5414 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5415 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5416 EVT VT = N->getValueType(0);
5418 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5419 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5422 const APFloat& V = N1CFP->getValueAPF();
5423 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5424 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5425 if (!V.isNegative()) {
5426 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5427 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5429 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5430 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5431 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5435 // copysign(fabs(x), y) -> copysign(x, y)
5436 // copysign(fneg(x), y) -> copysign(x, y)
5437 // copysign(copysign(x,z), y) -> copysign(x, y)
5438 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5439 N0.getOpcode() == ISD::FCOPYSIGN)
5440 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5441 N0.getOperand(0), N1);
5443 // copysign(x, abs(y)) -> abs(x)
5444 if (N1.getOpcode() == ISD::FABS)
5445 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5447 // copysign(x, copysign(y,z)) -> copysign(x, z)
5448 if (N1.getOpcode() == ISD::FCOPYSIGN)
5449 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5450 N0, N1.getOperand(1));
5452 // copysign(x, fp_extend(y)) -> copysign(x, y)
5453 // copysign(x, fp_round(y)) -> copysign(x, y)
5454 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5455 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5456 N0, N1.getOperand(0));
5461 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5462 SDValue N0 = N->getOperand(0);
5463 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5464 EVT VT = N->getValueType(0);
5465 EVT OpVT = N0.getValueType();
5467 // fold (sint_to_fp c1) -> c1fp
5468 if (N0C && OpVT != MVT::ppcf128 &&
5469 // ...but only if the target supports immediate floating-point values
5470 (Level == llvm::Unrestricted ||
5471 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5472 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5474 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5475 // but UINT_TO_FP is legal on this target, try to convert.
5476 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5477 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5478 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5479 if (DAG.SignBitIsZero(N0))
5480 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5486 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5487 SDValue N0 = N->getOperand(0);
5488 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5489 EVT VT = N->getValueType(0);
5490 EVT OpVT = N0.getValueType();
5492 // fold (uint_to_fp c1) -> c1fp
5493 if (N0C && OpVT != MVT::ppcf128 &&
5494 // ...but only if the target supports immediate floating-point values
5495 (Level == llvm::Unrestricted ||
5496 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5497 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5499 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5500 // but SINT_TO_FP is legal on this target, try to convert.
5501 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5502 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5503 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5504 if (DAG.SignBitIsZero(N0))
5505 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5511 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5512 SDValue N0 = N->getOperand(0);
5513 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5514 EVT VT = N->getValueType(0);
5516 // fold (fp_to_sint c1fp) -> c1
5518 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5523 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5524 SDValue N0 = N->getOperand(0);
5525 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5526 EVT VT = N->getValueType(0);
5528 // fold (fp_to_uint c1fp) -> c1
5529 if (N0CFP && VT != MVT::ppcf128)
5530 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5535 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5536 SDValue N0 = N->getOperand(0);
5537 SDValue N1 = N->getOperand(1);
5538 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5539 EVT VT = N->getValueType(0);
5541 // fold (fp_round c1fp) -> c1fp
5542 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5543 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5545 // fold (fp_round (fp_extend x)) -> x
5546 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5547 return N0.getOperand(0);
5549 // fold (fp_round (fp_round x)) -> (fp_round x)
5550 if (N0.getOpcode() == ISD::FP_ROUND) {
5551 // This is a value preserving truncation if both round's are.
5552 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5553 N0.getNode()->getConstantOperandVal(1) == 1;
5554 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5555 DAG.getIntPtrConstant(IsTrunc));
5558 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5559 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5560 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5561 N0.getOperand(0), N1);
5562 AddToWorkList(Tmp.getNode());
5563 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5564 Tmp, N0.getOperand(1));
5570 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5571 SDValue N0 = N->getOperand(0);
5572 EVT VT = N->getValueType(0);
5573 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5574 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5576 // fold (fp_round_inreg c1fp) -> c1fp
5577 if (N0CFP && isTypeLegal(EVT)) {
5578 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5579 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5585 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5586 SDValue N0 = N->getOperand(0);
5587 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5588 EVT VT = N->getValueType(0);
5590 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5591 if (N->hasOneUse() &&
5592 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5595 // fold (fp_extend c1fp) -> c1fp
5596 if (N0CFP && VT != MVT::ppcf128)
5597 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5599 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5601 if (N0.getOpcode() == ISD::FP_ROUND
5602 && N0.getNode()->getConstantOperandVal(1) == 1) {
5603 SDValue In = N0.getOperand(0);
5604 if (In.getValueType() == VT) return In;
5605 if (VT.bitsLT(In.getValueType()))
5606 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5607 In, N0.getOperand(1));
5608 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5611 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5612 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5613 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5614 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5615 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5616 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5618 LN0->getBasePtr(), LN0->getPointerInfo(),
5620 LN0->isVolatile(), LN0->isNonTemporal(),
5621 LN0->getAlignment());
5622 CombineTo(N, ExtLoad);
5623 CombineTo(N0.getNode(),
5624 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5625 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5626 ExtLoad.getValue(1));
5627 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5633 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5634 SDValue N0 = N->getOperand(0);
5635 EVT VT = N->getValueType(0);
5637 if (isNegatibleForFree(N0, LegalOperations))
5638 return GetNegatedExpression(N0, DAG, LegalOperations);
5640 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5641 // constant pool values.
5642 if (N0.getOpcode() == ISD::BITCAST &&
5644 N0.getNode()->hasOneUse() &&
5645 N0.getOperand(0).getValueType().isInteger()) {
5646 SDValue Int = N0.getOperand(0);
5647 EVT IntVT = Int.getValueType();
5648 if (IntVT.isInteger() && !IntVT.isVector()) {
5649 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5650 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5651 AddToWorkList(Int.getNode());
5652 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5660 SDValue DAGCombiner::visitFABS(SDNode *N) {
5661 SDValue N0 = N->getOperand(0);
5662 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5663 EVT VT = N->getValueType(0);
5665 // fold (fabs c1) -> fabs(c1)
5666 if (N0CFP && VT != MVT::ppcf128)
5667 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5668 // fold (fabs (fabs x)) -> (fabs x)
5669 if (N0.getOpcode() == ISD::FABS)
5670 return N->getOperand(0);
5671 // fold (fabs (fneg x)) -> (fabs x)
5672 // fold (fabs (fcopysign x, y)) -> (fabs x)
5673 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5674 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5676 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5677 // constant pool values.
5678 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5679 N0.getOperand(0).getValueType().isInteger() &&
5680 !N0.getOperand(0).getValueType().isVector()) {
5681 SDValue Int = N0.getOperand(0);
5682 EVT IntVT = Int.getValueType();
5683 if (IntVT.isInteger() && !IntVT.isVector()) {
5684 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5685 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5686 AddToWorkList(Int.getNode());
5687 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5688 N->getValueType(0), Int);
5695 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5696 SDValue Chain = N->getOperand(0);
5697 SDValue N1 = N->getOperand(1);
5698 SDValue N2 = N->getOperand(2);
5700 // If N is a constant we could fold this into a fallthrough or unconditional
5701 // branch. However that doesn't happen very often in normal code, because
5702 // Instcombine/SimplifyCFG should have handled the available opportunities.
5703 // If we did this folding here, it would be necessary to update the
5704 // MachineBasicBlock CFG, which is awkward.
5706 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5708 if (N1.getOpcode() == ISD::SETCC &&
5709 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5710 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5711 Chain, N1.getOperand(2),
5712 N1.getOperand(0), N1.getOperand(1), N2);
5715 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5716 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5717 (N1.getOperand(0).hasOneUse() &&
5718 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5720 if (N1.getOpcode() == ISD::TRUNCATE) {
5721 // Look pass the truncate.
5722 Trunc = N1.getNode();
5723 N1 = N1.getOperand(0);
5726 // Match this pattern so that we can generate simpler code:
5729 // %b = and i32 %a, 2
5730 // %c = srl i32 %b, 1
5731 // brcond i32 %c ...
5736 // %b = and i32 %a, 2
5737 // %c = setcc eq %b, 0
5740 // This applies only when the AND constant value has one bit set and the
5741 // SRL constant is equal to the log2 of the AND constant. The back-end is
5742 // smart enough to convert the result into a TEST/JMP sequence.
5743 SDValue Op0 = N1.getOperand(0);
5744 SDValue Op1 = N1.getOperand(1);
5746 if (Op0.getOpcode() == ISD::AND &&
5747 Op1.getOpcode() == ISD::Constant) {
5748 SDValue AndOp1 = Op0.getOperand(1);
5750 if (AndOp1.getOpcode() == ISD::Constant) {
5751 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5753 if (AndConst.isPowerOf2() &&
5754 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5756 DAG.getSetCC(N->getDebugLoc(),
5757 TLI.getSetCCResultType(Op0.getValueType()),
5758 Op0, DAG.getConstant(0, Op0.getValueType()),
5761 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5762 MVT::Other, Chain, SetCC, N2);
5763 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5764 // will convert it back to (X & C1) >> C2.
5765 CombineTo(N, NewBRCond, false);
5766 // Truncate is dead.
5768 removeFromWorkList(Trunc);
5769 DAG.DeleteNode(Trunc);
5771 // Replace the uses of SRL with SETCC
5772 WorkListRemover DeadNodes(*this);
5773 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5774 removeFromWorkList(N1.getNode());
5775 DAG.DeleteNode(N1.getNode());
5776 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5782 // Restore N1 if the above transformation doesn't match.
5783 N1 = N->getOperand(1);
5786 // Transform br(xor(x, y)) -> br(x != y)
5787 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5788 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5789 SDNode *TheXor = N1.getNode();
5790 SDValue Op0 = TheXor->getOperand(0);
5791 SDValue Op1 = TheXor->getOperand(1);
5792 if (Op0.getOpcode() == Op1.getOpcode()) {
5793 // Avoid missing important xor optimizations.
5794 SDValue Tmp = visitXOR(TheXor);
5795 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5796 DEBUG(dbgs() << "\nReplacing.8 ";
5798 dbgs() << "\nWith: ";
5799 Tmp.getNode()->dump(&DAG);
5801 WorkListRemover DeadNodes(*this);
5802 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5803 removeFromWorkList(TheXor);
5804 DAG.DeleteNode(TheXor);
5805 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5806 MVT::Other, Chain, Tmp, N2);
5810 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5812 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5813 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5814 Op0.getOpcode() == ISD::XOR) {
5815 TheXor = Op0.getNode();
5819 EVT SetCCVT = N1.getValueType();
5821 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5822 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5825 Equal ? ISD::SETEQ : ISD::SETNE);
5826 // Replace the uses of XOR with SETCC
5827 WorkListRemover DeadNodes(*this);
5828 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5829 removeFromWorkList(N1.getNode());
5830 DAG.DeleteNode(N1.getNode());
5831 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5832 MVT::Other, Chain, SetCC, N2);
5839 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5841 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5842 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5843 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5845 // If N is a constant we could fold this into a fallthrough or unconditional
5846 // branch. However that doesn't happen very often in normal code, because
5847 // Instcombine/SimplifyCFG should have handled the available opportunities.
5848 // If we did this folding here, it would be necessary to update the
5849 // MachineBasicBlock CFG, which is awkward.
5851 // Use SimplifySetCC to simplify SETCC's.
5852 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5853 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5855 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5857 // fold to a simpler setcc
5858 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5859 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5860 N->getOperand(0), Simp.getOperand(2),
5861 Simp.getOperand(0), Simp.getOperand(1),
5867 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5868 /// pre-indexed load / store when the base pointer is an add or subtract
5869 /// and it has other uses besides the load / store. After the
5870 /// transformation, the new indexed load / store has effectively folded
5871 /// the add / subtract in and all of its other uses are redirected to the
5872 /// new load / store.
5873 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5874 if (!LegalOperations)
5880 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5881 if (LD->isIndexed())
5883 VT = LD->getMemoryVT();
5884 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5885 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5887 Ptr = LD->getBasePtr();
5888 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5889 if (ST->isIndexed())
5891 VT = ST->getMemoryVT();
5892 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5893 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5895 Ptr = ST->getBasePtr();
5901 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5902 // out. There is no reason to make this a preinc/predec.
5903 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5904 Ptr.getNode()->hasOneUse())
5907 // Ask the target to do addressing mode selection.
5910 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5911 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5913 // Don't create a indexed load / store with zero offset.
5914 if (isa<ConstantSDNode>(Offset) &&
5915 cast<ConstantSDNode>(Offset)->isNullValue())
5918 // Try turning it into a pre-indexed load / store except when:
5919 // 1) The new base ptr is a frame index.
5920 // 2) If N is a store and the new base ptr is either the same as or is a
5921 // predecessor of the value being stored.
5922 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5923 // that would create a cycle.
5924 // 4) All uses are load / store ops that use it as old base ptr.
5926 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5927 // (plus the implicit offset) to a register to preinc anyway.
5928 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5933 SDValue Val = cast<StoreSDNode>(N)->getValue();
5934 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5938 // Now check for #3 and #4.
5939 bool RealUse = false;
5941 // Caches for hasPredecessorHelper
5942 SmallPtrSet<const SDNode *, 32> Visited;
5943 SmallVector<const SDNode *, 16> Worklist;
5945 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5946 E = Ptr.getNode()->use_end(); I != E; ++I) {
5950 if (N->hasPredecessorHelper(Use, Visited, Worklist))
5953 if (!((Use->getOpcode() == ISD::LOAD &&
5954 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5955 (Use->getOpcode() == ISD::STORE &&
5956 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5965 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5966 BasePtr, Offset, AM);
5968 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5969 BasePtr, Offset, AM);
5972 DEBUG(dbgs() << "\nReplacing.4 ";
5974 dbgs() << "\nWith: ";
5975 Result.getNode()->dump(&DAG);
5977 WorkListRemover DeadNodes(*this);
5979 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5981 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5984 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5988 // Finally, since the node is now dead, remove it from the graph.
5991 // Replace the uses of Ptr with uses of the updated base value.
5992 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5994 removeFromWorkList(Ptr.getNode());
5995 DAG.DeleteNode(Ptr.getNode());
6000 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6001 /// add / sub of the base pointer node into a post-indexed load / store.
6002 /// The transformation folded the add / subtract into the new indexed
6003 /// load / store effectively and all of its uses are redirected to the
6004 /// new load / store.
6005 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6006 if (!LegalOperations)
6012 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6013 if (LD->isIndexed())
6015 VT = LD->getMemoryVT();
6016 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6017 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6019 Ptr = LD->getBasePtr();
6020 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6021 if (ST->isIndexed())
6023 VT = ST->getMemoryVT();
6024 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6025 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6027 Ptr = ST->getBasePtr();
6033 if (Ptr.getNode()->hasOneUse())
6036 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6037 E = Ptr.getNode()->use_end(); I != E; ++I) {
6040 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6045 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6046 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6047 // Don't create a indexed load / store with zero offset.
6048 if (isa<ConstantSDNode>(Offset) &&
6049 cast<ConstantSDNode>(Offset)->isNullValue())
6052 // Try turning it into a post-indexed load / store except when
6053 // 1) All uses are load / store ops that use it as base ptr.
6054 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6055 // nor a successor of N. Otherwise, if Op is folded that would
6058 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6062 bool TryNext = false;
6063 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6064 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6066 if (Use == Ptr.getNode())
6069 // If all the uses are load / store addresses, then don't do the
6071 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6072 bool RealUse = false;
6073 for (SDNode::use_iterator III = Use->use_begin(),
6074 EEE = Use->use_end(); III != EEE; ++III) {
6075 SDNode *UseUse = *III;
6076 if (!((UseUse->getOpcode() == ISD::LOAD &&
6077 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
6078 (UseUse->getOpcode() == ISD::STORE &&
6079 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
6094 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6095 SDValue Result = isLoad
6096 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6097 BasePtr, Offset, AM)
6098 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6099 BasePtr, Offset, AM);
6102 DEBUG(dbgs() << "\nReplacing.5 ";
6104 dbgs() << "\nWith: ";
6105 Result.getNode()->dump(&DAG);
6107 WorkListRemover DeadNodes(*this);
6109 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6111 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6114 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6118 // Finally, since the node is now dead, remove it from the graph.
6121 // Replace the uses of Use with uses of the updated base value.
6122 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6123 Result.getValue(isLoad ? 1 : 0),
6125 removeFromWorkList(Op);
6135 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6136 LoadSDNode *LD = cast<LoadSDNode>(N);
6137 SDValue Chain = LD->getChain();
6138 SDValue Ptr = LD->getBasePtr();
6140 // If load is not volatile and there are no uses of the loaded value (and
6141 // the updated indexed value in case of indexed loads), change uses of the
6142 // chain value into uses of the chain input (i.e. delete the dead load).
6143 if (!LD->isVolatile()) {
6144 if (N->getValueType(1) == MVT::Other) {
6146 if (N->hasNUsesOfValue(0, 0)) {
6147 // It's not safe to use the two value CombineTo variant here. e.g.
6148 // v1, chain2 = load chain1, loc
6149 // v2, chain3 = load chain2, loc
6151 // Now we replace use of chain2 with chain1. This makes the second load
6152 // isomorphic to the one we are deleting, and thus makes this load live.
6153 DEBUG(dbgs() << "\nReplacing.6 ";
6155 dbgs() << "\nWith chain: ";
6156 Chain.getNode()->dump(&DAG);
6158 WorkListRemover DeadNodes(*this);
6159 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
6161 if (N->use_empty()) {
6162 removeFromWorkList(N);
6166 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6170 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6171 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
6172 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6173 DEBUG(dbgs() << "\nReplacing.7 ";
6175 dbgs() << "\nWith: ";
6176 Undef.getNode()->dump(&DAG);
6177 dbgs() << " and 2 other values\n");
6178 WorkListRemover DeadNodes(*this);
6179 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
6180 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6181 DAG.getUNDEF(N->getValueType(1)),
6183 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
6184 removeFromWorkList(N);
6186 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6191 // If this load is directly stored, replace the load value with the stored
6193 // TODO: Handle store large -> read small portion.
6194 // TODO: Handle TRUNCSTORE/LOADEXT
6195 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6196 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6197 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6198 if (PrevST->getBasePtr() == Ptr &&
6199 PrevST->getValue().getValueType() == N->getValueType(0))
6200 return CombineTo(N, Chain.getOperand(1), Chain);
6204 // Try to infer better alignment information than the load already has.
6205 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6206 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6207 if (Align > LD->getAlignment())
6208 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6209 LD->getValueType(0),
6210 Chain, Ptr, LD->getPointerInfo(),
6212 LD->isVolatile(), LD->isNonTemporal(), Align);
6217 // Walk up chain skipping non-aliasing memory nodes.
6218 SDValue BetterChain = FindBetterChain(N, Chain);
6220 // If there is a better chain.
6221 if (Chain != BetterChain) {
6224 // Replace the chain to void dependency.
6225 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6226 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6227 BetterChain, Ptr, LD->getPointerInfo(),
6228 LD->isVolatile(), LD->isNonTemporal(),
6229 LD->getAlignment());
6231 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6232 LD->getValueType(0),
6233 BetterChain, Ptr, LD->getPointerInfo(),
6236 LD->isNonTemporal(),
6237 LD->getAlignment());
6240 // Create token factor to keep old chain connected.
6241 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6242 MVT::Other, Chain, ReplLoad.getValue(1));
6244 // Make sure the new and old chains are cleaned up.
6245 AddToWorkList(Token.getNode());
6247 // Replace uses with load result and token factor. Don't add users
6249 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6253 // Try transforming N to an indexed load.
6254 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6255 return SDValue(N, 0);
6260 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6261 /// load is having specific bytes cleared out. If so, return the byte size
6262 /// being masked out and the shift amount.
6263 static std::pair<unsigned, unsigned>
6264 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6265 std::pair<unsigned, unsigned> Result(0, 0);
6267 // Check for the structure we're looking for.
6268 if (V->getOpcode() != ISD::AND ||
6269 !isa<ConstantSDNode>(V->getOperand(1)) ||
6270 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6273 // Check the chain and pointer.
6274 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6275 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6277 // The store should be chained directly to the load or be an operand of a
6279 if (LD == Chain.getNode())
6281 else if (Chain->getOpcode() != ISD::TokenFactor)
6282 return Result; // Fail.
6285 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6286 if (Chain->getOperand(i).getNode() == LD) {
6290 if (!isOk) return Result;
6293 // This only handles simple types.
6294 if (V.getValueType() != MVT::i16 &&
6295 V.getValueType() != MVT::i32 &&
6296 V.getValueType() != MVT::i64)
6299 // Check the constant mask. Invert it so that the bits being masked out are
6300 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6301 // follow the sign bit for uniformity.
6302 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6303 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6304 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6305 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6306 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6307 if (NotMaskLZ == 64) return Result; // All zero mask.
6309 // See if we have a continuous run of bits. If so, we have 0*1+0*
6310 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6313 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6314 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6315 NotMaskLZ -= 64-V.getValueSizeInBits();
6317 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6318 switch (MaskedBytes) {
6322 default: return Result; // All one mask, or 5-byte mask.
6325 // Verify that the first bit starts at a multiple of mask so that the access
6326 // is aligned the same as the access width.
6327 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6329 Result.first = MaskedBytes;
6330 Result.second = NotMaskTZ/8;
6335 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6336 /// provides a value as specified by MaskInfo. If so, replace the specified
6337 /// store with a narrower store of truncated IVal.
6339 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6340 SDValue IVal, StoreSDNode *St,
6342 unsigned NumBytes = MaskInfo.first;
6343 unsigned ByteShift = MaskInfo.second;
6344 SelectionDAG &DAG = DC->getDAG();
6346 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6347 // that uses this. If not, this is not a replacement.
6348 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6349 ByteShift*8, (ByteShift+NumBytes)*8);
6350 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6352 // Check that it is legal on the target to do this. It is legal if the new
6353 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6355 MVT VT = MVT::getIntegerVT(NumBytes*8);
6356 if (!DC->isTypeLegal(VT))
6359 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6360 // shifted by ByteShift and truncated down to NumBytes.
6362 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6363 DAG.getConstant(ByteShift*8,
6364 DC->getShiftAmountTy(IVal.getValueType())));
6366 // Figure out the offset for the store and the alignment of the access.
6368 unsigned NewAlign = St->getAlignment();
6370 if (DAG.getTargetLoweringInfo().isLittleEndian())
6371 StOffset = ByteShift;
6373 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6375 SDValue Ptr = St->getBasePtr();
6377 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6378 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6379 NewAlign = MinAlign(NewAlign, StOffset);
6382 // Truncate down to the new size.
6383 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6386 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6387 St->getPointerInfo().getWithOffset(StOffset),
6388 false, false, NewAlign).getNode();
6392 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6393 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6394 /// of the loaded bits, try narrowing the load and store if it would end up
6395 /// being a win for performance or code size.
6396 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6397 StoreSDNode *ST = cast<StoreSDNode>(N);
6398 if (ST->isVolatile())
6401 SDValue Chain = ST->getChain();
6402 SDValue Value = ST->getValue();
6403 SDValue Ptr = ST->getBasePtr();
6404 EVT VT = Value.getValueType();
6406 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6409 unsigned Opc = Value.getOpcode();
6411 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6412 // is a byte mask indicating a consecutive number of bytes, check to see if
6413 // Y is known to provide just those bytes. If so, we try to replace the
6414 // load + replace + store sequence with a single (narrower) store, which makes
6416 if (Opc == ISD::OR) {
6417 std::pair<unsigned, unsigned> MaskedLoad;
6418 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6419 if (MaskedLoad.first)
6420 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6421 Value.getOperand(1), ST,this))
6422 return SDValue(NewST, 0);
6424 // Or is commutative, so try swapping X and Y.
6425 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6426 if (MaskedLoad.first)
6427 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6428 Value.getOperand(0), ST,this))
6429 return SDValue(NewST, 0);
6432 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6433 Value.getOperand(1).getOpcode() != ISD::Constant)
6436 SDValue N0 = Value.getOperand(0);
6437 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6438 Chain == SDValue(N0.getNode(), 1)) {
6439 LoadSDNode *LD = cast<LoadSDNode>(N0);
6440 if (LD->getBasePtr() != Ptr ||
6441 LD->getPointerInfo().getAddrSpace() !=
6442 ST->getPointerInfo().getAddrSpace())
6445 // Find the type to narrow it the load / op / store to.
6446 SDValue N1 = Value.getOperand(1);
6447 unsigned BitWidth = N1.getValueSizeInBits();
6448 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6449 if (Opc == ISD::AND)
6450 Imm ^= APInt::getAllOnesValue(BitWidth);
6451 if (Imm == 0 || Imm.isAllOnesValue())
6453 unsigned ShAmt = Imm.countTrailingZeros();
6454 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6455 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6456 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6457 while (NewBW < BitWidth &&
6458 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6459 TLI.isNarrowingProfitable(VT, NewVT))) {
6460 NewBW = NextPowerOf2(NewBW);
6461 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6463 if (NewBW >= BitWidth)
6466 // If the lsb changed does not start at the type bitwidth boundary,
6467 // start at the previous one.
6469 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6470 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6471 if ((Imm & Mask) == Imm) {
6472 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6473 if (Opc == ISD::AND)
6474 NewImm ^= APInt::getAllOnesValue(NewBW);
6475 uint64_t PtrOff = ShAmt / 8;
6476 // For big endian targets, we need to adjust the offset to the pointer to
6477 // load the correct bytes.
6478 if (TLI.isBigEndian())
6479 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6481 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6482 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6483 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6486 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6487 Ptr.getValueType(), Ptr,
6488 DAG.getConstant(PtrOff, Ptr.getValueType()));
6489 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6490 LD->getChain(), NewPtr,
6491 LD->getPointerInfo().getWithOffset(PtrOff),
6492 LD->isVolatile(), LD->isNonTemporal(),
6494 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6495 DAG.getConstant(NewImm, NewVT));
6496 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6498 ST->getPointerInfo().getWithOffset(PtrOff),
6499 false, false, NewAlign);
6501 AddToWorkList(NewPtr.getNode());
6502 AddToWorkList(NewLD.getNode());
6503 AddToWorkList(NewVal.getNode());
6504 WorkListRemover DeadNodes(*this);
6505 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6515 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6516 /// if the load value isn't used by any other operations, then consider
6517 /// transforming the pair to integer load / store operations if the target
6518 /// deems the transformation profitable.
6519 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6520 StoreSDNode *ST = cast<StoreSDNode>(N);
6521 SDValue Chain = ST->getChain();
6522 SDValue Value = ST->getValue();
6523 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6524 Value.hasOneUse() &&
6525 Chain == SDValue(Value.getNode(), 1)) {
6526 LoadSDNode *LD = cast<LoadSDNode>(Value);
6527 EVT VT = LD->getMemoryVT();
6528 if (!VT.isFloatingPoint() ||
6529 VT != ST->getMemoryVT() ||
6530 LD->isNonTemporal() ||
6531 ST->isNonTemporal() ||
6532 LD->getPointerInfo().getAddrSpace() != 0 ||
6533 ST->getPointerInfo().getAddrSpace() != 0)
6536 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6537 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6538 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6539 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6540 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6543 unsigned LDAlign = LD->getAlignment();
6544 unsigned STAlign = ST->getAlignment();
6545 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6546 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6547 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6550 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6551 LD->getChain(), LD->getBasePtr(),
6552 LD->getPointerInfo(),
6553 false, false, LDAlign);
6555 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6556 NewLD, ST->getBasePtr(),
6557 ST->getPointerInfo(),
6558 false, false, STAlign);
6560 AddToWorkList(NewLD.getNode());
6561 AddToWorkList(NewST.getNode());
6562 WorkListRemover DeadNodes(*this);
6563 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6572 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6573 StoreSDNode *ST = cast<StoreSDNode>(N);
6574 SDValue Chain = ST->getChain();
6575 SDValue Value = ST->getValue();
6576 SDValue Ptr = ST->getBasePtr();
6578 // If this is a store of a bit convert, store the input value if the
6579 // resultant store does not need a higher alignment than the original.
6580 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6581 ST->isUnindexed()) {
6582 unsigned OrigAlign = ST->getAlignment();
6583 EVT SVT = Value.getOperand(0).getValueType();
6584 unsigned Align = TLI.getTargetData()->
6585 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6586 if (Align <= OrigAlign &&
6587 ((!LegalOperations && !ST->isVolatile()) ||
6588 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6589 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6590 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6591 ST->isNonTemporal(), OrigAlign);
6594 // Turn 'store undef, Ptr' -> nothing.
6595 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6598 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6599 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6600 // NOTE: If the original store is volatile, this transform must not increase
6601 // the number of stores. For example, on x86-32 an f64 can be stored in one
6602 // processor operation but an i64 (which is not legal) requires two. So the
6603 // transform should not be done in this case.
6604 if (Value.getOpcode() != ISD::TargetConstantFP) {
6606 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6607 default: llvm_unreachable("Unknown FP type");
6608 case MVT::f80: // We don't do this for these yet.
6613 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6614 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6615 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6616 bitcastToAPInt().getZExtValue(), MVT::i32);
6617 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6618 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6619 ST->isNonTemporal(), ST->getAlignment());
6623 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6624 !ST->isVolatile()) ||
6625 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6626 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6627 getZExtValue(), MVT::i64);
6628 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6629 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6630 ST->isNonTemporal(), ST->getAlignment());
6633 if (!ST->isVolatile() &&
6634 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6635 // Many FP stores are not made apparent until after legalize, e.g. for
6636 // argument passing. Since this is so common, custom legalize the
6637 // 64-bit integer store into two 32-bit stores.
6638 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6639 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6640 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6641 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6643 unsigned Alignment = ST->getAlignment();
6644 bool isVolatile = ST->isVolatile();
6645 bool isNonTemporal = ST->isNonTemporal();
6647 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6648 Ptr, ST->getPointerInfo(),
6649 isVolatile, isNonTemporal,
6650 ST->getAlignment());
6651 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6652 DAG.getConstant(4, Ptr.getValueType()));
6653 Alignment = MinAlign(Alignment, 4U);
6654 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6655 Ptr, ST->getPointerInfo().getWithOffset(4),
6656 isVolatile, isNonTemporal,
6658 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6667 // Try to infer better alignment information than the store already has.
6668 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6669 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6670 if (Align > ST->getAlignment())
6671 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6672 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6673 ST->isVolatile(), ST->isNonTemporal(), Align);
6677 // Try transforming a pair floating point load / store ops to integer
6678 // load / store ops.
6679 SDValue NewST = TransformFPLoadStorePair(N);
6680 if (NewST.getNode())
6684 // Walk up chain skipping non-aliasing memory nodes.
6685 SDValue BetterChain = FindBetterChain(N, Chain);
6687 // If there is a better chain.
6688 if (Chain != BetterChain) {
6691 // Replace the chain to avoid dependency.
6692 if (ST->isTruncatingStore()) {
6693 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6694 ST->getPointerInfo(),
6695 ST->getMemoryVT(), ST->isVolatile(),
6696 ST->isNonTemporal(), ST->getAlignment());
6698 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6699 ST->getPointerInfo(),
6700 ST->isVolatile(), ST->isNonTemporal(),
6701 ST->getAlignment());
6704 // Create token to keep both nodes around.
6705 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6706 MVT::Other, Chain, ReplStore);
6708 // Make sure the new and old chains are cleaned up.
6709 AddToWorkList(Token.getNode());
6711 // Don't add users to work list.
6712 return CombineTo(N, Token, false);
6716 // Try transforming N to an indexed store.
6717 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6718 return SDValue(N, 0);
6720 // FIXME: is there such a thing as a truncating indexed store?
6721 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6722 Value.getValueType().isInteger()) {
6723 // See if we can simplify the input to this truncstore with knowledge that
6724 // only the low bits are being used. For example:
6725 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6727 GetDemandedBits(Value,
6728 APInt::getLowBitsSet(
6729 Value.getValueType().getScalarType().getSizeInBits(),
6730 ST->getMemoryVT().getScalarType().getSizeInBits()));
6731 AddToWorkList(Value.getNode());
6732 if (Shorter.getNode())
6733 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6734 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6735 ST->isVolatile(), ST->isNonTemporal(),
6736 ST->getAlignment());
6738 // Otherwise, see if we can simplify the operation with
6739 // SimplifyDemandedBits, which only works if the value has a single use.
6740 if (SimplifyDemandedBits(Value,
6741 APInt::getLowBitsSet(
6742 Value.getValueType().getScalarType().getSizeInBits(),
6743 ST->getMemoryVT().getScalarType().getSizeInBits())))
6744 return SDValue(N, 0);
6747 // If this is a load followed by a store to the same location, then the store
6749 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6750 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6751 ST->isUnindexed() && !ST->isVolatile() &&
6752 // There can't be any side effects between the load and store, such as
6754 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6755 // The store is dead, remove it.
6760 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6761 // truncating store. We can do this even if this is already a truncstore.
6762 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6763 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6764 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6765 ST->getMemoryVT())) {
6766 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6767 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6768 ST->isVolatile(), ST->isNonTemporal(),
6769 ST->getAlignment());
6772 return ReduceLoadOpStoreWidth(N);
6775 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6776 SDValue InVec = N->getOperand(0);
6777 SDValue InVal = N->getOperand(1);
6778 SDValue EltNo = N->getOperand(2);
6780 // If the inserted element is an UNDEF, just use the input vector.
6781 if (InVal.getOpcode() == ISD::UNDEF)
6784 EVT VT = InVec.getValueType();
6786 // If we can't generate a legal BUILD_VECTOR, exit
6787 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
6790 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6791 // vector with the inserted element.
6792 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6793 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6794 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6795 InVec.getNode()->op_end());
6796 if (Elt < Ops.size())
6798 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6799 VT, &Ops[0], Ops.size());
6801 // If the invec is an UNDEF and if EltNo is a constant, create a new
6802 // BUILD_VECTOR with undef elements and the inserted element.
6803 if (InVec.getOpcode() == ISD::UNDEF &&
6804 isa<ConstantSDNode>(EltNo)) {
6805 EVT EltVT = VT.getVectorElementType();
6806 unsigned NElts = VT.getVectorNumElements();
6807 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6809 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6810 if (Elt < Ops.size())
6812 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6813 VT, &Ops[0], Ops.size());
6818 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6819 // (vextract (scalar_to_vector val, 0) -> val
6820 SDValue InVec = N->getOperand(0);
6822 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6823 // Check if the result type doesn't match the inserted element type. A
6824 // SCALAR_TO_VECTOR may truncate the inserted element and the
6825 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6826 SDValue InOp = InVec.getOperand(0);
6827 EVT NVT = N->getValueType(0);
6828 if (InOp.getValueType() != NVT) {
6829 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6830 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6835 // Perform only after legalization to ensure build_vector / vector_shuffle
6836 // optimizations have already been done.
6837 if (!LegalOperations) return SDValue();
6839 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6840 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6841 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6842 SDValue EltNo = N->getOperand(1);
6844 if (isa<ConstantSDNode>(EltNo)) {
6845 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6846 bool NewLoad = false;
6847 bool BCNumEltsChanged = false;
6848 EVT VT = InVec.getValueType();
6849 EVT ExtVT = VT.getVectorElementType();
6852 if (InVec.getOpcode() == ISD::BITCAST) {
6853 EVT BCVT = InVec.getOperand(0).getValueType();
6854 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6856 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6857 BCNumEltsChanged = true;
6858 InVec = InVec.getOperand(0);
6859 ExtVT = BCVT.getVectorElementType();
6863 LoadSDNode *LN0 = NULL;
6864 const ShuffleVectorSDNode *SVN = NULL;
6865 if (ISD::isNormalLoad(InVec.getNode())) {
6866 LN0 = cast<LoadSDNode>(InVec);
6867 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6868 InVec.getOperand(0).getValueType() == ExtVT &&
6869 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6870 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6871 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6872 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6874 // (load $addr+1*size)
6876 // If the bit convert changed the number of elements, it is unsafe
6877 // to examine the mask.
6878 if (BCNumEltsChanged)
6881 // Select the input vector, guarding against out of range extract vector.
6882 unsigned NumElems = VT.getVectorNumElements();
6883 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
6884 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6886 if (InVec.getOpcode() == ISD::BITCAST)
6887 InVec = InVec.getOperand(0);
6888 if (ISD::isNormalLoad(InVec.getNode())) {
6889 LN0 = cast<LoadSDNode>(InVec);
6890 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6894 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6897 // If Idx was -1 above, Elt is going to be -1, so just return undef.
6899 return DAG.getUNDEF(LN0->getBasePtr().getValueType());
6901 unsigned Align = LN0->getAlignment();
6903 // Check the resultant load doesn't need a higher alignment than the
6907 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6909 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6915 SDValue NewPtr = LN0->getBasePtr();
6916 unsigned PtrOff = 0;
6919 PtrOff = LVT.getSizeInBits() * Elt / 8;
6920 EVT PtrType = NewPtr.getValueType();
6921 if (TLI.isBigEndian())
6922 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6923 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6924 DAG.getConstant(PtrOff, PtrType));
6927 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6928 LN0->getPointerInfo().getWithOffset(PtrOff),
6929 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6935 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6936 unsigned NumInScalars = N->getNumOperands();
6937 EVT VT = N->getValueType(0);
6939 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6940 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6941 // at most two distinct vectors, turn this into a shuffle node.
6942 SDValue VecIn1, VecIn2;
6943 for (unsigned i = 0; i != NumInScalars; ++i) {
6944 // Ignore undef inputs.
6945 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6947 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6948 // constant index, bail out.
6949 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6950 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6951 VecIn1 = VecIn2 = SDValue(0, 0);
6955 // If the input vector type disagrees with the result of the build_vector,
6956 // we can't make a shuffle.
6957 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6958 if (ExtractedFromVec.getValueType() != VT) {
6959 VecIn1 = VecIn2 = SDValue(0, 0);
6963 // Otherwise, remember this. We allow up to two distinct input vectors.
6964 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6967 if (VecIn1.getNode() == 0) {
6968 VecIn1 = ExtractedFromVec;
6969 } else if (VecIn2.getNode() == 0) {
6970 VecIn2 = ExtractedFromVec;
6973 VecIn1 = VecIn2 = SDValue(0, 0);
6978 // If everything is good, we can make a shuffle operation.
6979 if (VecIn1.getNode()) {
6980 SmallVector<int, 8> Mask;
6981 for (unsigned i = 0; i != NumInScalars; ++i) {
6982 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6987 // If extracting from the first vector, just use the index directly.
6988 SDValue Extract = N->getOperand(i);
6989 SDValue ExtVal = Extract.getOperand(1);
6990 if (Extract.getOperand(0) == VecIn1) {
6991 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6992 if (ExtIndex > VT.getVectorNumElements())
6995 Mask.push_back(ExtIndex);
6999 // Otherwise, use InIdx + VecSize
7000 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7001 Mask.push_back(Idx+NumInScalars);
7004 // Add count and size info.
7005 if (!isTypeLegal(VT))
7008 // Return the new VECTOR_SHUFFLE node.
7011 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7012 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7018 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7019 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7020 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7021 // inputs come from at most two distinct vectors, turn this into a shuffle
7024 // If we only have one input vector, we don't need to do any concatenation.
7025 if (N->getNumOperands() == 1)
7026 return N->getOperand(0);
7031 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7032 EVT VT = N->getValueType(0);
7033 unsigned NumElts = VT.getVectorNumElements();
7035 SDValue N0 = N->getOperand(0);
7037 assert(N0.getValueType().getVectorNumElements() == NumElts &&
7038 "Vector shuffle must be normalized in DAG");
7040 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
7042 // If it is a splat, check if the argument vector is another splat or a
7043 // build_vector with all scalar elements the same.
7044 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7045 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7046 SDNode *V = N0.getNode();
7048 // If this is a bit convert that changes the element type of the vector but
7049 // not the number of vector elements, look through it. Be careful not to
7050 // look though conversions that change things like v4f32 to v2f64.
7051 if (V->getOpcode() == ISD::BITCAST) {
7052 SDValue ConvInput = V->getOperand(0);
7053 if (ConvInput.getValueType().isVector() &&
7054 ConvInput.getValueType().getVectorNumElements() == NumElts)
7055 V = ConvInput.getNode();
7058 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7059 assert(V->getNumOperands() == NumElts &&
7060 "BUILD_VECTOR has wrong number of operands");
7062 bool AllSame = true;
7063 for (unsigned i = 0; i != NumElts; ++i) {
7064 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7065 Base = V->getOperand(i);
7069 // Splat of <u, u, u, u>, return <u, u, u, u>
7070 if (!Base.getNode())
7072 for (unsigned i = 0; i != NumElts; ++i) {
7073 if (V->getOperand(i) != Base) {
7078 // Splat of <x, x, x, x>, return <x, x, x, x>
7086 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7087 if (!TLI.getShouldFoldAtomicFences())
7090 SDValue atomic = N->getOperand(0);
7091 switch (atomic.getOpcode()) {
7092 case ISD::ATOMIC_CMP_SWAP:
7093 case ISD::ATOMIC_SWAP:
7094 case ISD::ATOMIC_LOAD_ADD:
7095 case ISD::ATOMIC_LOAD_SUB:
7096 case ISD::ATOMIC_LOAD_AND:
7097 case ISD::ATOMIC_LOAD_OR:
7098 case ISD::ATOMIC_LOAD_XOR:
7099 case ISD::ATOMIC_LOAD_NAND:
7100 case ISD::ATOMIC_LOAD_MIN:
7101 case ISD::ATOMIC_LOAD_MAX:
7102 case ISD::ATOMIC_LOAD_UMIN:
7103 case ISD::ATOMIC_LOAD_UMAX:
7109 SDValue fence = atomic.getOperand(0);
7110 if (fence.getOpcode() != ISD::MEMBARRIER)
7113 switch (atomic.getOpcode()) {
7114 case ISD::ATOMIC_CMP_SWAP:
7115 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7116 fence.getOperand(0),
7117 atomic.getOperand(1), atomic.getOperand(2),
7118 atomic.getOperand(3)), atomic.getResNo());
7119 case ISD::ATOMIC_SWAP:
7120 case ISD::ATOMIC_LOAD_ADD:
7121 case ISD::ATOMIC_LOAD_SUB:
7122 case ISD::ATOMIC_LOAD_AND:
7123 case ISD::ATOMIC_LOAD_OR:
7124 case ISD::ATOMIC_LOAD_XOR:
7125 case ISD::ATOMIC_LOAD_NAND:
7126 case ISD::ATOMIC_LOAD_MIN:
7127 case ISD::ATOMIC_LOAD_MAX:
7128 case ISD::ATOMIC_LOAD_UMIN:
7129 case ISD::ATOMIC_LOAD_UMAX:
7130 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7131 fence.getOperand(0),
7132 atomic.getOperand(1), atomic.getOperand(2)),
7139 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7140 /// an AND to a vector_shuffle with the destination vector and a zero vector.
7141 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7142 /// vector_shuffle V, Zero, <0, 4, 2, 4>
7143 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7144 EVT VT = N->getValueType(0);
7145 DebugLoc dl = N->getDebugLoc();
7146 SDValue LHS = N->getOperand(0);
7147 SDValue RHS = N->getOperand(1);
7148 if (N->getOpcode() == ISD::AND) {
7149 if (RHS.getOpcode() == ISD::BITCAST)
7150 RHS = RHS.getOperand(0);
7151 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7152 SmallVector<int, 8> Indices;
7153 unsigned NumElts = RHS.getNumOperands();
7154 for (unsigned i = 0; i != NumElts; ++i) {
7155 SDValue Elt = RHS.getOperand(i);
7156 if (!isa<ConstantSDNode>(Elt))
7158 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7159 Indices.push_back(i);
7160 else if (cast<ConstantSDNode>(Elt)->isNullValue())
7161 Indices.push_back(NumElts);
7166 // Let's see if the target supports this vector_shuffle.
7167 EVT RVT = RHS.getValueType();
7168 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7171 // Return the new VECTOR_SHUFFLE node.
7172 EVT EltVT = RVT.getVectorElementType();
7173 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7174 DAG.getConstant(0, EltVT));
7175 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7176 RVT, &ZeroOps[0], ZeroOps.size());
7177 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7178 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7179 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7186 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7187 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7188 // After legalize, the target may be depending on adds and other
7189 // binary ops to provide legal ways to construct constants or other
7190 // things. Simplifying them may result in a loss of legality.
7191 if (LegalOperations) return SDValue();
7193 assert(N->getValueType(0).isVector() &&
7194 "SimplifyVBinOp only works on vectors!");
7196 SDValue LHS = N->getOperand(0);
7197 SDValue RHS = N->getOperand(1);
7198 SDValue Shuffle = XformToShuffleWithZero(N);
7199 if (Shuffle.getNode()) return Shuffle;
7201 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
7203 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
7204 RHS.getOpcode() == ISD::BUILD_VECTOR) {
7205 SmallVector<SDValue, 8> Ops;
7206 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
7207 SDValue LHSOp = LHS.getOperand(i);
7208 SDValue RHSOp = RHS.getOperand(i);
7209 // If these two elements can't be folded, bail out.
7210 if ((LHSOp.getOpcode() != ISD::UNDEF &&
7211 LHSOp.getOpcode() != ISD::Constant &&
7212 LHSOp.getOpcode() != ISD::ConstantFP) ||
7213 (RHSOp.getOpcode() != ISD::UNDEF &&
7214 RHSOp.getOpcode() != ISD::Constant &&
7215 RHSOp.getOpcode() != ISD::ConstantFP))
7218 // Can't fold divide by zero.
7219 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
7220 N->getOpcode() == ISD::FDIV) {
7221 if ((RHSOp.getOpcode() == ISD::Constant &&
7222 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
7223 (RHSOp.getOpcode() == ISD::ConstantFP &&
7224 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
7228 EVT VT = LHSOp.getValueType();
7229 assert(RHSOp.getValueType() == VT &&
7230 "SimplifyVBinOp with different BUILD_VECTOR element types");
7231 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
7233 if (FoldOp.getOpcode() != ISD::UNDEF &&
7234 FoldOp.getOpcode() != ISD::Constant &&
7235 FoldOp.getOpcode() != ISD::ConstantFP)
7237 Ops.push_back(FoldOp);
7238 AddToWorkList(FoldOp.getNode());
7241 if (Ops.size() == LHS.getNumOperands())
7242 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7243 LHS.getValueType(), &Ops[0], Ops.size());
7249 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7250 SDValue N1, SDValue N2){
7251 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7253 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7254 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7256 // If we got a simplified select_cc node back from SimplifySelectCC, then
7257 // break it down into a new SETCC node, and a new SELECT node, and then return
7258 // the SELECT node, since we were called with a SELECT node.
7259 if (SCC.getNode()) {
7260 // Check to see if we got a select_cc back (to turn into setcc/select).
7261 // Otherwise, just return whatever node we got back, like fabs.
7262 if (SCC.getOpcode() == ISD::SELECT_CC) {
7263 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7265 SCC.getOperand(0), SCC.getOperand(1),
7267 AddToWorkList(SETCC.getNode());
7268 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
7269 SCC.getOperand(2), SCC.getOperand(3), SETCC);
7277 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
7278 /// are the two values being selected between, see if we can simplify the
7279 /// select. Callers of this should assume that TheSelect is deleted if this
7280 /// returns true. As such, they should return the appropriate thing (e.g. the
7281 /// node) back to the top-level of the DAG combiner loop to avoid it being
7283 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
7286 // Cannot simplify select with vector condition
7287 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
7289 // If this is a select from two identical things, try to pull the operation
7290 // through the select.
7291 if (LHS.getOpcode() != RHS.getOpcode() ||
7292 !LHS.hasOneUse() || !RHS.hasOneUse())
7295 // If this is a load and the token chain is identical, replace the select
7296 // of two loads with a load through a select of the address to load from.
7297 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7298 // constants have been dropped into the constant pool.
7299 if (LHS.getOpcode() == ISD::LOAD) {
7300 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7301 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7303 // Token chains must be identical.
7304 if (LHS.getOperand(0) != RHS.getOperand(0) ||
7305 // Do not let this transformation reduce the number of volatile loads.
7306 LLD->isVolatile() || RLD->isVolatile() ||
7307 // If this is an EXTLOAD, the VT's must match.
7308 LLD->getMemoryVT() != RLD->getMemoryVT() ||
7309 // If this is an EXTLOAD, the kind of extension must match.
7310 (LLD->getExtensionType() != RLD->getExtensionType() &&
7311 // The only exception is if one of the extensions is anyext.
7312 LLD->getExtensionType() != ISD::EXTLOAD &&
7313 RLD->getExtensionType() != ISD::EXTLOAD) ||
7314 // FIXME: this discards src value information. This is
7315 // over-conservative. It would be beneficial to be able to remember
7316 // both potential memory locations. Since we are discarding
7317 // src value info, don't do the transformation if the memory
7318 // locations are not in the default address space.
7319 LLD->getPointerInfo().getAddrSpace() != 0 ||
7320 RLD->getPointerInfo().getAddrSpace() != 0)
7323 // Check that the select condition doesn't reach either load. If so,
7324 // folding this will induce a cycle into the DAG. If not, this is safe to
7325 // xform, so create a select of the addresses.
7327 if (TheSelect->getOpcode() == ISD::SELECT) {
7328 SDNode *CondNode = TheSelect->getOperand(0).getNode();
7329 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7330 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7332 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7333 LLD->getBasePtr().getValueType(),
7334 TheSelect->getOperand(0), LLD->getBasePtr(),
7336 } else { // Otherwise SELECT_CC
7337 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7338 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7340 if ((LLD->hasAnyUseOfValue(1) &&
7341 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7342 (LLD->hasAnyUseOfValue(1) &&
7343 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7346 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7347 LLD->getBasePtr().getValueType(),
7348 TheSelect->getOperand(0),
7349 TheSelect->getOperand(1),
7350 LLD->getBasePtr(), RLD->getBasePtr(),
7351 TheSelect->getOperand(4));
7355 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7356 Load = DAG.getLoad(TheSelect->getValueType(0),
7357 TheSelect->getDebugLoc(),
7358 // FIXME: Discards pointer info.
7359 LLD->getChain(), Addr, MachinePointerInfo(),
7360 LLD->isVolatile(), LLD->isNonTemporal(),
7361 LLD->getAlignment());
7363 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7364 RLD->getExtensionType() : LLD->getExtensionType(),
7365 TheSelect->getDebugLoc(),
7366 TheSelect->getValueType(0),
7367 // FIXME: Discards pointer info.
7368 LLD->getChain(), Addr, MachinePointerInfo(),
7369 LLD->getMemoryVT(), LLD->isVolatile(),
7370 LLD->isNonTemporal(), LLD->getAlignment());
7373 // Users of the select now use the result of the load.
7374 CombineTo(TheSelect, Load);
7376 // Users of the old loads now use the new load's chain. We know the
7377 // old-load value is dead now.
7378 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7379 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7386 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7387 /// where 'cond' is the comparison specified by CC.
7388 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7389 SDValue N2, SDValue N3,
7390 ISD::CondCode CC, bool NotExtCompare) {
7391 // (x ? y : y) -> y.
7392 if (N2 == N3) return N2;
7394 EVT VT = N2.getValueType();
7395 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7396 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7397 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7399 // Determine if the condition we're dealing with is constant
7400 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7401 N0, N1, CC, DL, false);
7402 if (SCC.getNode()) AddToWorkList(SCC.getNode());
7403 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7405 // fold select_cc true, x, y -> x
7406 if (SCCC && !SCCC->isNullValue())
7408 // fold select_cc false, x, y -> y
7409 if (SCCC && SCCC->isNullValue())
7412 // Check to see if we can simplify the select into an fabs node
7413 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
7414 // Allow either -0.0 or 0.0
7415 if (CFP->getValueAPF().isZero()) {
7416 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
7417 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
7418 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7419 N2 == N3.getOperand(0))
7420 return DAG.getNode(ISD::FABS, DL, VT, N0);
7422 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
7423 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
7424 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7425 N2.getOperand(0) == N3)
7426 return DAG.getNode(ISD::FABS, DL, VT, N3);
7430 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
7431 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
7432 // in it. This is a win when the constant is not otherwise available because
7433 // it replaces two constant pool loads with one. We only do this if the FP
7434 // type is known to be legal, because if it isn't, then we are before legalize
7435 // types an we want the other legalization to happen first (e.g. to avoid
7436 // messing with soft float) and if the ConstantFP is not legal, because if
7437 // it is legal, we may not need to store the FP constant in a constant pool.
7438 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
7439 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
7440 if (TLI.isTypeLegal(N2.getValueType()) &&
7441 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
7442 TargetLowering::Legal) &&
7443 // If both constants have multiple uses, then we won't need to do an
7444 // extra load, they are likely around in registers for other users.
7445 (TV->hasOneUse() || FV->hasOneUse())) {
7446 Constant *Elts[] = {
7447 const_cast<ConstantFP*>(FV->getConstantFPValue()),
7448 const_cast<ConstantFP*>(TV->getConstantFPValue())
7450 const Type *FPTy = Elts[0]->getType();
7451 const TargetData &TD = *TLI.getTargetData();
7453 // Create a ConstantArray of the two constants.
7454 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
7455 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
7456 TD.getPrefTypeAlignment(FPTy));
7457 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
7459 // Get the offsets to the 0 and 1 element of the array so that we can
7460 // select between them.
7461 SDValue Zero = DAG.getIntPtrConstant(0);
7462 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
7463 SDValue One = DAG.getIntPtrConstant(EltSize);
7465 SDValue Cond = DAG.getSetCC(DL,
7466 TLI.getSetCCResultType(N0.getValueType()),
7468 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
7470 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
7472 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
7473 MachinePointerInfo::getConstantPool(), false,
7479 // Check to see if we can perform the "gzip trick", transforming
7480 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
7481 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
7482 N0.getValueType().isInteger() &&
7483 N2.getValueType().isInteger() &&
7484 (N1C->isNullValue() || // (a < 0) ? b : 0
7485 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
7486 EVT XType = N0.getValueType();
7487 EVT AType = N2.getValueType();
7488 if (XType.bitsGE(AType)) {
7489 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7490 // single-bit constant.
7491 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
7492 unsigned ShCtV = N2C->getAPIntValue().logBase2();
7493 ShCtV = XType.getSizeInBits()-ShCtV-1;
7494 SDValue ShCt = DAG.getConstant(ShCtV,
7495 getShiftAmountTy(N0.getValueType()));
7496 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7498 AddToWorkList(Shift.getNode());
7500 if (XType.bitsGT(AType)) {
7501 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7502 AddToWorkList(Shift.getNode());
7505 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7508 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7510 DAG.getConstant(XType.getSizeInBits()-1,
7511 getShiftAmountTy(N0.getValueType())));
7512 AddToWorkList(Shift.getNode());
7514 if (XType.bitsGT(AType)) {
7515 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7516 AddToWorkList(Shift.getNode());
7519 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7523 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
7524 // where y is has a single bit set.
7525 // A plaintext description would be, we can turn the SELECT_CC into an AND
7526 // when the condition can be materialized as an all-ones register. Any
7527 // single bit-test can be materialized as an all-ones register with
7528 // shift-left and shift-right-arith.
7529 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7530 N0->getValueType(0) == VT &&
7531 N1C && N1C->isNullValue() &&
7532 N2C && N2C->isNullValue()) {
7533 SDValue AndLHS = N0->getOperand(0);
7534 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7535 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
7536 // Shift the tested bit over the sign bit.
7537 APInt AndMask = ConstAndRHS->getAPIntValue();
7539 DAG.getConstant(AndMask.countLeadingZeros(),
7540 getShiftAmountTy(AndLHS.getValueType()));
7541 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
7543 // Now arithmetic right shift it all the way over, so the result is either
7544 // all-ones, or zero.
7546 DAG.getConstant(AndMask.getBitWidth()-1,
7547 getShiftAmountTy(Shl.getValueType()));
7548 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
7550 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
7554 // fold select C, 16, 0 -> shl C, 4
7555 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
7556 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
7558 // If the caller doesn't want us to simplify this into a zext of a compare,
7560 if (NotExtCompare && N2C->getAPIntValue() == 1)
7563 // Get a SetCC of the condition
7564 // FIXME: Should probably make sure that setcc is legal if we ever have a
7565 // target where it isn't.
7567 // cast from setcc result type to select result type
7569 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7571 if (N2.getValueType().bitsLT(SCC.getValueType()))
7572 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
7574 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7575 N2.getValueType(), SCC);
7577 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7578 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7579 N2.getValueType(), SCC);
7582 AddToWorkList(SCC.getNode());
7583 AddToWorkList(Temp.getNode());
7585 if (N2C->getAPIntValue() == 1)
7588 // shl setcc result by log2 n2c
7589 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
7590 DAG.getConstant(N2C->getAPIntValue().logBase2(),
7591 getShiftAmountTy(Temp.getValueType())));
7594 // Check to see if this is the equivalent of setcc
7595 // FIXME: Turn all of these into setcc if setcc if setcc is legal
7596 // otherwise, go ahead with the folds.
7597 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
7598 EVT XType = N0.getValueType();
7599 if (!LegalOperations ||
7600 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
7601 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7602 if (Res.getValueType() != VT)
7603 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
7607 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7608 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
7609 (!LegalOperations ||
7610 TLI.isOperationLegal(ISD::CTLZ, XType))) {
7611 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7612 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7613 DAG.getConstant(Log2_32(XType.getSizeInBits()),
7614 getShiftAmountTy(Ctlz.getValueType())));
7616 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7617 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
7618 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7619 XType, DAG.getConstant(0, XType), N0);
7620 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7621 return DAG.getNode(ISD::SRL, DL, XType,
7622 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
7623 DAG.getConstant(XType.getSizeInBits()-1,
7624 getShiftAmountTy(XType)));
7626 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7627 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
7628 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7629 DAG.getConstant(XType.getSizeInBits()-1,
7630 getShiftAmountTy(N0.getValueType())));
7631 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
7635 // Check to see if this is an integer abs.
7636 // select_cc setg[te] X, 0, X, -X ->
7637 // select_cc setgt X, -1, X, -X ->
7638 // select_cc setl[te] X, 0, -X, X ->
7639 // select_cc setlt X, 1, -X, X ->
7640 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
7642 ConstantSDNode *SubC = NULL;
7643 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
7644 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
7645 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7646 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
7647 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
7648 (N1C->isOne() && CC == ISD::SETLT)) &&
7649 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7650 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
7652 EVT XType = N0.getValueType();
7653 if (SubC && SubC->isNullValue() && XType.isInteger()) {
7654 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7656 DAG.getConstant(XType.getSizeInBits()-1,
7657 getShiftAmountTy(N0.getValueType())));
7658 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7660 AddToWorkList(Shift.getNode());
7661 AddToWorkList(Add.getNode());
7662 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
7669 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
7670 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7671 SDValue N1, ISD::CondCode Cond,
7672 DebugLoc DL, bool foldBooleans) {
7673 TargetLowering::DAGCombinerInfo
7674 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
7675 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
7678 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
7679 /// return a DAG expression to select that will generate the same value by
7680 /// multiplying by a magic number. See:
7681 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7682 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
7683 std::vector<SDNode*> Built;
7684 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
7686 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7692 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
7693 /// return a DAG expression to select that will generate the same value by
7694 /// multiplying by a magic number. See:
7695 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7696 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
7697 std::vector<SDNode*> Built;
7698 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7700 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7706 /// FindBaseOffset - Return true if base is a frame index, which is known not
7707 // to alias with anything but itself. Provides base object and offset as
7709 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7710 const GlobalValue *&GV, void *&CV) {
7711 // Assume it is a primitive operation.
7712 Base = Ptr; Offset = 0; GV = 0; CV = 0;
7714 // If it's an adding a simple constant then integrate the offset.
7715 if (Base.getOpcode() == ISD::ADD) {
7716 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7717 Base = Base.getOperand(0);
7718 Offset += C->getZExtValue();
7722 // Return the underlying GlobalValue, and update the Offset. Return false
7723 // for GlobalAddressSDNode since the same GlobalAddress may be represented
7724 // by multiple nodes with different offsets.
7725 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7726 GV = G->getGlobal();
7727 Offset += G->getOffset();
7731 // Return the underlying Constant value, and update the Offset. Return false
7732 // for ConstantSDNodes since the same constant pool entry may be represented
7733 // by multiple nodes with different offsets.
7734 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7735 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7736 : (void *)C->getConstVal();
7737 Offset += C->getOffset();
7740 // If it's any of the following then it can't alias with anything but itself.
7741 return isa<FrameIndexSDNode>(Base);
7744 /// isAlias - Return true if there is any possibility that the two addresses
7746 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7747 const Value *SrcValue1, int SrcValueOffset1,
7748 unsigned SrcValueAlign1,
7749 const MDNode *TBAAInfo1,
7750 SDValue Ptr2, int64_t Size2,
7751 const Value *SrcValue2, int SrcValueOffset2,
7752 unsigned SrcValueAlign2,
7753 const MDNode *TBAAInfo2) const {
7754 // If they are the same then they must be aliases.
7755 if (Ptr1 == Ptr2) return true;
7757 // Gather base node and offset information.
7758 SDValue Base1, Base2;
7759 int64_t Offset1, Offset2;
7760 const GlobalValue *GV1, *GV2;
7762 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7763 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7765 // If they have a same base address then check to see if they overlap.
7766 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7767 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7769 // It is possible for different frame indices to alias each other, mostly
7770 // when tail call optimization reuses return address slots for arguments.
7771 // To catch this case, look up the actual index of frame indices to compute
7772 // the real alias relationship.
7773 if (isFrameIndex1 && isFrameIndex2) {
7774 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7775 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7776 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7777 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7780 // Otherwise, if we know what the bases are, and they aren't identical, then
7781 // we know they cannot alias.
7782 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7785 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7786 // compared to the size and offset of the access, we may be able to prove they
7787 // do not alias. This check is conservative for now to catch cases created by
7788 // splitting vector types.
7789 if ((SrcValueAlign1 == SrcValueAlign2) &&
7790 (SrcValueOffset1 != SrcValueOffset2) &&
7791 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7792 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7793 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7795 // There is no overlap between these relatively aligned accesses of similar
7796 // size, return no alias.
7797 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7801 if (CombinerGlobalAA) {
7802 // Use alias analysis information.
7803 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7804 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7805 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7806 AliasAnalysis::AliasResult AAResult =
7807 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
7808 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
7809 if (AAResult == AliasAnalysis::NoAlias)
7813 // Otherwise we have to assume they alias.
7817 /// FindAliasInfo - Extracts the relevant alias information from the memory
7818 /// node. Returns true if the operand was a load.
7819 bool DAGCombiner::FindAliasInfo(SDNode *N,
7820 SDValue &Ptr, int64_t &Size,
7821 const Value *&SrcValue,
7822 int &SrcValueOffset,
7823 unsigned &SrcValueAlign,
7824 const MDNode *&TBAAInfo) const {
7825 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7826 Ptr = LD->getBasePtr();
7827 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7828 SrcValue = LD->getSrcValue();
7829 SrcValueOffset = LD->getSrcValueOffset();
7830 SrcValueAlign = LD->getOriginalAlignment();
7831 TBAAInfo = LD->getTBAAInfo();
7834 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7835 Ptr = ST->getBasePtr();
7836 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7837 SrcValue = ST->getSrcValue();
7838 SrcValueOffset = ST->getSrcValueOffset();
7839 SrcValueAlign = ST->getOriginalAlignment();
7840 TBAAInfo = ST->getTBAAInfo();
7843 llvm_unreachable("FindAliasInfo expected a memory operand");
7846 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7847 /// looking for aliasing nodes and adding them to the Aliases vector.
7848 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7849 SmallVector<SDValue, 8> &Aliases) {
7850 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7851 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7853 // Get alias information for node.
7856 const Value *SrcValue;
7858 unsigned SrcValueAlign;
7859 const MDNode *SrcTBAAInfo;
7860 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7861 SrcValueAlign, SrcTBAAInfo);
7864 Chains.push_back(OriginalChain);
7867 // Look at each chain and determine if it is an alias. If so, add it to the
7868 // aliases list. If not, then continue up the chain looking for the next
7870 while (!Chains.empty()) {
7871 SDValue Chain = Chains.back();
7874 // For TokenFactor nodes, look at each operand and only continue up the
7875 // chain until we find two aliases. If we've seen two aliases, assume we'll
7876 // find more and revert to original chain since the xform is unlikely to be
7879 // FIXME: The depth check could be made to return the last non-aliasing
7880 // chain we found before we hit a tokenfactor rather than the original
7882 if (Depth > 6 || Aliases.size() == 2) {
7884 Aliases.push_back(OriginalChain);
7888 // Don't bother if we've been before.
7889 if (!Visited.insert(Chain.getNode()))
7892 switch (Chain.getOpcode()) {
7893 case ISD::EntryToken:
7894 // Entry token is ideal chain operand, but handled in FindBetterChain.
7899 // Get alias information for Chain.
7902 const Value *OpSrcValue;
7903 int OpSrcValueOffset;
7904 unsigned OpSrcValueAlign;
7905 const MDNode *OpSrcTBAAInfo;
7906 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7907 OpSrcValue, OpSrcValueOffset,
7911 // If chain is alias then stop here.
7912 if (!(IsLoad && IsOpLoad) &&
7913 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7915 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7916 OpSrcValueAlign, OpSrcTBAAInfo)) {
7917 Aliases.push_back(Chain);
7919 // Look further up the chain.
7920 Chains.push_back(Chain.getOperand(0));
7926 case ISD::TokenFactor:
7927 // We have to check each of the operands of the token factor for "small"
7928 // token factors, so we queue them up. Adding the operands to the queue
7929 // (stack) in reverse order maintains the original order and increases the
7930 // likelihood that getNode will find a matching token factor (CSE.)
7931 if (Chain.getNumOperands() > 16) {
7932 Aliases.push_back(Chain);
7935 for (unsigned n = Chain.getNumOperands(); n;)
7936 Chains.push_back(Chain.getOperand(--n));
7941 // For all other instructions we will just have to take what we can get.
7942 Aliases.push_back(Chain);
7948 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7949 /// for a better chain (aliasing node.)
7950 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7951 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7953 // Accumulate all the aliases to this node.
7954 GatherAllAliases(N, OldChain, Aliases);
7956 // If no operands then chain to entry token.
7957 if (Aliases.size() == 0)
7958 return DAG.getEntryNode();
7960 // If a single operand then chain to it. We don't need to revisit it.
7961 if (Aliases.size() == 1)
7964 // Construct a custom tailored token factor.
7965 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7966 &Aliases[0], Aliases.size());
7969 // SelectionDAG::Combine - This is the entry point for the file.
7971 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7972 CodeGenOpt::Level OptLevel) {
7973 /// run - This is the main entry point to this class.
7975 DAGCombiner(*this, AA, OptLevel).Run(Level);