1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 EVT getSetCCResultType(EVT VT) const {
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
65 // Libcall insertion helpers.
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
73 /// LegalizeOp - Legalizes the given operation.
74 void LegalizeOp(SDNode *Node);
76 SDValue OptimizeFloatStore(StoreSDNode *ST);
78 void LegalizeLoadOps(SDNode *Node);
79 void LegalizeStoreOps(SDNode *Node);
81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
83 /// is necessary to spill the vector being inserted into to memory, perform
84 /// the insert there, and then read the result back.
85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
86 SDValue Idx, SDLoc dl);
87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
88 SDValue Idx, SDLoc dl);
90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
91 /// performs the same shuffe in terms of order or result bytes, but on a type
92 /// whose vector element type is narrower than the original shuffle type.
93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
95 SDValue N1, SDValue N2,
96 ArrayRef<int> Mask) const;
98 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
99 bool &NeedInvert, SDLoc dl);
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
103 unsigned NumOps, bool isSigned, SDLoc dl);
105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
106 SDNode *Node, bool isSigned);
107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
109 RTLIB::Libcall Call_F128,
110 RTLIB::Libcall Call_PPCF128);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
112 RTLIB::Libcall Call_I8,
113 RTLIB::Libcall Call_I16,
114 RTLIB::Libcall Call_I32,
115 RTLIB::Libcall Call_I64,
116 RTLIB::Libcall Call_I128);
117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
121 SDValue ExpandBUILD_VECTOR(SDNode *Node);
122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
124 SmallVectorImpl<SDValue> &Results);
125 SDValue ExpandFCOPYSIGN(SDNode *Node);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
137 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
138 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144 void ExpandNode(SDNode *Node);
145 void PromoteNode(SDNode *Node);
147 void ForgetNode(SDNode *N) {
148 LegalizedNodes.erase(N);
149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
154 // DAGUpdateListener implementation.
155 virtual void NodeDeleted(SDNode *N, SDNode *E) {
158 virtual void NodeUpdated(SDNode *N) {}
160 // Node replacement helpers
161 void ReplacedNode(SDNode *N) {
162 if (N->use_empty()) {
163 DAG.RemoveDeadNode(N);
168 void ReplaceNode(SDNode *Old, SDNode *New) {
169 DAG.ReplaceAllUsesWith(Old, New);
172 void ReplaceNode(SDValue Old, SDValue New) {
173 DAG.ReplaceAllUsesWith(Old, New);
174 ReplacedNode(Old.getNode());
176 void ReplaceNode(SDNode *Old, const SDValue *New) {
177 DAG.ReplaceAllUsesWith(Old, New);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
189 SDValue N1, SDValue N2,
190 ArrayRef<int> Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
216 : SelectionDAG::DAGUpdateListener(dag),
217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
221 void SelectionDAGLegalize::LegalizeDAG() {
222 DAG.AssignTopologicalOrder();
224 // Visit all the nodes. We start in topological order, so that we see
225 // nodes with their original operands intact. Legalization can produce
226 // new nodes which may themselves need to be legalized. Iterate until all
227 // nodes have been legalized.
229 bool AnyLegalized = false;
230 for (LegalizePosition = DAG.allnodes_end();
231 LegalizePosition != DAG.allnodes_begin(); ) {
234 SDNode *N = LegalizePosition;
235 if (LegalizedNodes.insert(N)) {
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
249 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
250 /// a load from the constant pool.
252 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
256 // If a FP immediate is precise when represented as a float and if the
257 // target can do an extending load from float to double, we put it into
258 // the constant pool as a float, even if it's is statically typed as a
259 // double. This shrinks FP constants and canonicalizes them for targets where
260 // an FP extending load is the same cost as a normal load (such as on the x87
261 // fp stack or PPC FP unit).
262 EVT VT = CFP->getValueType(0);
263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
278 TLI.ShouldShrinkFPConstant(OrigVT)) {
279 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292 CPIdx, MachinePointerInfo::getConstantPool(),
293 VT, false, false, Alignment);
297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
298 MachinePointerInfo::getConstantPool(), false, false, false,
303 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
305 const TargetLowering &TLI,
306 SelectionDAGLegalize *DAGLegalize) {
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
308 "unaligned indexed stores not implemented!");
309 SDValue Chain = ST->getChain();
310 SDValue Ptr = ST->getBasePtr();
311 SDValue Val = ST->getValue();
312 EVT VT = Val.getValueType();
313 int Alignment = ST->getAlignment();
314 unsigned AS = ST->getAddressSpace();
317 if (ST->getMemoryVT().isFloatingPoint() ||
318 ST->getMemoryVT().isVector()) {
319 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
320 if (TLI.isTypeLegal(intVT)) {
321 // Expand to a bitconvert of the value to the integer type of the
322 // same size, then a (misaligned) int store.
323 // FIXME: Does not handle truncating floating point stores!
324 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
325 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
326 ST->isVolatile(), ST->isNonTemporal(), Alignment);
327 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
330 // Do a (aligned) store to a stack slot, then copy from the stack slot
331 // to the final destination using (unaligned) integer loads and stores.
332 EVT StoredVT = ST->getMemoryVT();
334 TLI.getRegisterType(*DAG.getContext(),
335 EVT::getIntegerVT(*DAG.getContext(),
336 StoredVT.getSizeInBits()));
337 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
338 unsigned RegBytes = RegVT.getSizeInBits() / 8;
339 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
341 // Make sure the stack slot is also aligned for the register type.
342 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
344 // Perform the original store, only redirected to the stack slot.
345 SDValue Store = DAG.getTruncStore(Chain, dl,
346 Val, StackPtr, MachinePointerInfo(),
347 StoredVT, false, false, 0);
348 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
349 SmallVector<SDValue, 8> Stores;
352 // Do all but one copies using the full register width.
353 for (unsigned i = 1; i < NumRegs; i++) {
354 // Load one integer register's worth from the stack slot.
355 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
356 MachinePointerInfo(),
357 false, false, false, 0);
358 // Store it to the final location. Remember the store.
359 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
360 ST->getPointerInfo().getWithOffset(Offset),
361 ST->isVolatile(), ST->isNonTemporal(),
362 MinAlign(ST->getAlignment(), Offset)));
363 // Increment the pointers.
365 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
367 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
370 // The last store may be partial. Do a truncating store. On big-endian
371 // machines this requires an extending load from the stack slot to ensure
372 // that the bits are in the right place.
373 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
374 8 * (StoredBytes - Offset));
376 // Load from the stack slot.
377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
378 MachinePointerInfo(),
379 MemVT, false, false, 0);
381 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
383 .getWithOffset(Offset),
384 MemVT, ST->isVolatile(),
386 MinAlign(ST->getAlignment(), Offset),
388 // The order of the stores doesn't matter - say it with a TokenFactor.
390 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
392 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
395 assert(ST->getMemoryVT().isInteger() &&
396 !ST->getMemoryVT().isVector() &&
397 "Unaligned store of unknown type.");
398 // Get the half-size VT
399 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
400 int NumBits = NewStoredVT.getSizeInBits();
401 int IncrementSize = NumBits / 8;
403 // Divide the stored value in two parts.
404 SDValue ShiftAmount = DAG.getConstant(NumBits,
405 TLI.getShiftAmountTy(Val.getValueType()));
407 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
409 // Store the two parts
410 SDValue Store1, Store2;
411 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
412 ST->getPointerInfo(), NewStoredVT,
413 ST->isVolatile(), ST->isNonTemporal(), Alignment);
415 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
416 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
417 Alignment = MinAlign(Alignment, IncrementSize);
418 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
419 ST->getPointerInfo().getWithOffset(IncrementSize),
420 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
421 Alignment, ST->getTBAAInfo());
424 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
425 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
428 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
430 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
431 const TargetLowering &TLI,
432 SDValue &ValResult, SDValue &ChainResult) {
433 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
434 "unaligned indexed loads not implemented!");
435 SDValue Chain = LD->getChain();
436 SDValue Ptr = LD->getBasePtr();
437 EVT VT = LD->getValueType(0);
438 EVT LoadedVT = LD->getMemoryVT();
440 if (VT.isFloatingPoint() || VT.isVector()) {
441 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
442 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
443 // Expand to a (misaligned) integer load of the same size,
444 // then bitconvert to floating point or vector.
445 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
446 LD->getMemOperand());
447 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
449 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
450 ISD::ANY_EXTEND, dl, VT, Result);
457 // Copy the value to a (aligned) stack slot using (unaligned) integer
458 // loads and stores, then do a (aligned) load from the stack slot.
459 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
460 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
461 unsigned RegBytes = RegVT.getSizeInBits() / 8;
462 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
464 // Make sure the stack slot is also aligned for the register type.
465 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
467 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
468 SmallVector<SDValue, 8> Stores;
469 SDValue StackPtr = StackBase;
472 // Do all but one copies using the full register width.
473 for (unsigned i = 1; i < NumRegs; i++) {
474 // Load one integer register's worth from the original location.
475 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
476 LD->getPointerInfo().getWithOffset(Offset),
477 LD->isVolatile(), LD->isNonTemporal(),
479 MinAlign(LD->getAlignment(), Offset),
481 // Follow the load with a store to the stack slot. Remember the store.
482 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
483 MachinePointerInfo(), false, false, 0));
484 // Increment the pointers.
486 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
487 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
491 // The last copy may be partial. Do an extending load.
492 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
493 8 * (LoadedBytes - Offset));
494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
495 LD->getPointerInfo().getWithOffset(Offset),
496 MemVT, LD->isVolatile(),
498 MinAlign(LD->getAlignment(), Offset),
500 // Follow the load with a store to the stack slot. Remember the store.
501 // On big-endian machines this requires a truncating store to ensure
502 // that the bits end up in the right place.
503 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
504 MachinePointerInfo(), MemVT,
507 // The order of the stores doesn't matter - say it with a TokenFactor.
508 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
511 // Finally, perform the original load only redirected to the stack slot.
512 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
513 MachinePointerInfo(), LoadedVT, false, false, 0);
515 // Callers expect a MERGE_VALUES node.
520 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
521 "Unaligned load of unsupported type.");
523 // Compute the new VT that is half the size of the old one. This is an
525 unsigned NumBits = LoadedVT.getSizeInBits();
527 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
530 unsigned Alignment = LD->getAlignment();
531 unsigned IncrementSize = NumBits / 8;
532 ISD::LoadExtType HiExtType = LD->getExtensionType();
534 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
535 if (HiExtType == ISD::NON_EXTLOAD)
536 HiExtType = ISD::ZEXTLOAD;
538 // Load the value in two parts
540 if (TLI.isLittleEndian()) {
541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
542 NewLoadedVT, LD->isVolatile(),
543 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
545 DAG.getConstant(IncrementSize, Ptr.getValueType()));
546 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
547 LD->getPointerInfo().getWithOffset(IncrementSize),
548 NewLoadedVT, LD->isVolatile(),
549 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
552 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
553 NewLoadedVT, LD->isVolatile(),
554 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
556 DAG.getConstant(IncrementSize, Ptr.getValueType()));
557 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
558 LD->getPointerInfo().getWithOffset(IncrementSize),
559 NewLoadedVT, LD->isVolatile(),
560 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
564 // aggregate the two parts
565 SDValue ShiftAmount = DAG.getConstant(NumBits,
566 TLI.getShiftAmountTy(Hi.getValueType()));
567 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
568 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
577 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
578 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
579 /// is necessary to spill the vector being inserted into to memory, perform
580 /// the insert there, and then read the result back.
581 SDValue SelectionDAGLegalize::
582 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
588 // If the target doesn't support this, we have to spill the input vector
589 // to a temporary stack slot, update the element, then reload it. This is
590 // badness. We could also load the value into a vector register (either
591 // with a "move to register" or "extload into register" instruction, then
592 // permute it into place, if the idx is a constant and if the idx is
593 // supported by the target.
594 EVT VT = Tmp1.getValueType();
595 EVT EltVT = VT.getVectorElementType();
596 EVT IdxVT = Tmp3.getValueType();
597 EVT PtrVT = TLI.getPointerTy();
598 SDValue StackPtr = DAG.CreateStackTemporary(VT);
600 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
603 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
604 MachinePointerInfo::getFixedStack(SPFI),
607 // Truncate or zero extend offset to target pointer type.
608 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
609 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
610 // Add the offset to the index.
611 unsigned EltSize = EltVT.getSizeInBits()/8;
612 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
613 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
614 // Store the scalar value.
615 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
617 // Load the updated vector.
618 return DAG.getLoad(VT, dl, Ch, StackPtr,
619 MachinePointerInfo::getFixedStack(SPFI), false, false,
624 SDValue SelectionDAGLegalize::
625 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
626 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
627 // SCALAR_TO_VECTOR requires that the type of the value being inserted
628 // match the element type of the vector being created, except for
629 // integers in which case the inserted value can be over width.
630 EVT EltVT = Vec.getValueType().getVectorElementType();
631 if (Val.getValueType() == EltVT ||
632 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
633 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
634 Vec.getValueType(), Val);
636 unsigned NumElts = Vec.getValueType().getVectorNumElements();
637 // We generate a shuffle of InVec and ScVec, so the shuffle mask
638 // should be 0,1,2,3,4,5... with the appropriate element replaced with
640 SmallVector<int, 8> ShufOps;
641 for (unsigned i = 0; i != NumElts; ++i)
642 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
644 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
648 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
651 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
652 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
653 // FIXME: We shouldn't do this for TargetConstantFP's.
654 // FIXME: move this to the DAG Combiner! Note that we can't regress due
655 // to phase ordering between legalized code and the dag combiner. This
656 // probably means that we need to integrate dag combiner and legalizer
658 // We generally can't do this one for long doubles.
659 SDValue Chain = ST->getChain();
660 SDValue Ptr = ST->getBasePtr();
661 unsigned Alignment = ST->getAlignment();
662 bool isVolatile = ST->isVolatile();
663 bool isNonTemporal = ST->isNonTemporal();
664 const MDNode *TBAAInfo = ST->getTBAAInfo();
666 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
667 if (CFP->getValueType(0) == MVT::f32 &&
668 TLI.isTypeLegal(MVT::i32)) {
669 SDValue Con = DAG.getConstant(CFP->getValueAPF().
670 bitcastToAPInt().zextOrTrunc(32),
672 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
673 isVolatile, isNonTemporal, Alignment, TBAAInfo);
676 if (CFP->getValueType(0) == MVT::f64) {
677 // If this target supports 64-bit registers, do a single 64-bit store.
678 if (TLI.isTypeLegal(MVT::i64)) {
679 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
680 zextOrTrunc(64), MVT::i64);
681 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
682 isVolatile, isNonTemporal, Alignment, TBAAInfo);
685 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
686 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
687 // stores. If the target supports neither 32- nor 64-bits, this
688 // xform is certainly not worth it.
689 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
690 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
691 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
692 if (TLI.isBigEndian()) std::swap(Lo, Hi);
694 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
695 isNonTemporal, Alignment, TBAAInfo);
696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
697 DAG.getConstant(4, Ptr.getValueType()));
698 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
699 ST->getPointerInfo().getWithOffset(4),
700 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
703 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
707 return SDValue(0, 0);
710 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
711 StoreSDNode *ST = cast<StoreSDNode>(Node);
712 SDValue Chain = ST->getChain();
713 SDValue Ptr = ST->getBasePtr();
716 unsigned Alignment = ST->getAlignment();
717 bool isVolatile = ST->isVolatile();
718 bool isNonTemporal = ST->isNonTemporal();
719 const MDNode *TBAAInfo = ST->getTBAAInfo();
721 if (!ST->isTruncatingStore()) {
722 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
723 ReplaceNode(ST, OptStore);
728 SDValue Value = ST->getValue();
729 MVT VT = Value.getSimpleValueType();
730 switch (TLI.getOperationAction(ISD::STORE, VT)) {
731 default: llvm_unreachable("This action is not supported yet!");
732 case TargetLowering::Legal:
733 // If this is an unaligned store and the target doesn't support it,
735 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
736 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
737 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
738 if (ST->getAlignment() < ABIAlignment)
739 ExpandUnalignedStore(cast<StoreSDNode>(Node),
743 case TargetLowering::Custom: {
744 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
746 ReplaceNode(SDValue(Node, 0), Res);
749 case TargetLowering::Promote: {
750 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
751 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
752 "Can only promote stores to same size type");
753 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
755 DAG.getStore(Chain, dl, Value, Ptr,
756 ST->getPointerInfo(), isVolatile,
757 isNonTemporal, Alignment, TBAAInfo);
758 ReplaceNode(SDValue(Node, 0), Result);
765 SDValue Value = ST->getValue();
767 EVT StVT = ST->getMemoryVT();
768 unsigned StWidth = StVT.getSizeInBits();
770 if (StWidth != StVT.getStoreSizeInBits()) {
771 // Promote to a byte-sized store with upper bits zero if not
772 // storing an integral number of bytes. For example, promote
773 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
774 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
775 StVT.getStoreSizeInBits());
776 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
778 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
779 NVT, isVolatile, isNonTemporal, Alignment,
781 ReplaceNode(SDValue(Node, 0), Result);
782 } else if (StWidth & (StWidth - 1)) {
783 // If not storing a power-of-2 number of bits, expand as two stores.
784 assert(!StVT.isVector() && "Unsupported truncstore!");
785 unsigned RoundWidth = 1 << Log2_32(StWidth);
786 assert(RoundWidth < StWidth);
787 unsigned ExtraWidth = StWidth - RoundWidth;
788 assert(ExtraWidth < RoundWidth);
789 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
790 "Store size not an integral number of bytes!");
791 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
792 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
794 unsigned IncrementSize;
796 if (TLI.isLittleEndian()) {
797 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
798 // Store the bottom RoundWidth bits.
799 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
801 isVolatile, isNonTemporal, Alignment,
804 // Store the remaining ExtraWidth bits.
805 IncrementSize = RoundWidth / 8;
806 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
807 DAG.getConstant(IncrementSize, Ptr.getValueType()));
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
809 DAG.getConstant(RoundWidth,
810 TLI.getShiftAmountTy(Value.getValueType())));
811 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
812 ST->getPointerInfo().getWithOffset(IncrementSize),
813 ExtraVT, isVolatile, isNonTemporal,
814 MinAlign(Alignment, IncrementSize), TBAAInfo);
816 // Big endian - avoid unaligned stores.
817 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
818 // Store the top RoundWidth bits.
819 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
820 DAG.getConstant(ExtraWidth,
821 TLI.getShiftAmountTy(Value.getValueType())));
822 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
823 RoundVT, isVolatile, isNonTemporal, Alignment,
826 // Store the remaining ExtraWidth bits.
827 IncrementSize = RoundWidth / 8;
828 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
829 DAG.getConstant(IncrementSize, Ptr.getValueType()));
830 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
831 ST->getPointerInfo().getWithOffset(IncrementSize),
832 ExtraVT, isVolatile, isNonTemporal,
833 MinAlign(Alignment, IncrementSize), TBAAInfo);
836 // The order of the stores doesn't matter.
837 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
838 ReplaceNode(SDValue(Node, 0), Result);
840 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
841 StVT.getSimpleVT())) {
842 default: llvm_unreachable("This action is not supported yet!");
843 case TargetLowering::Legal:
844 // If this is an unaligned store and the target doesn't support it,
846 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
847 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
848 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
849 if (ST->getAlignment() < ABIAlignment)
850 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
853 case TargetLowering::Custom: {
854 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
856 ReplaceNode(SDValue(Node, 0), Res);
859 case TargetLowering::Expand:
860 assert(!StVT.isVector() &&
861 "Vector Stores are handled in LegalizeVectorOps");
863 // TRUNCSTORE:i16 i32 -> STORE i16
864 assert(TLI.isTypeLegal(StVT) &&
865 "Do not know how to expand this store!");
866 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
868 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
869 isVolatile, isNonTemporal, Alignment, TBAAInfo);
870 ReplaceNode(SDValue(Node, 0), Result);
877 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
878 LoadSDNode *LD = cast<LoadSDNode>(Node);
879 SDValue Chain = LD->getChain(); // The chain.
880 SDValue Ptr = LD->getBasePtr(); // The base pointer.
881 SDValue Value; // The value returned by the load op.
884 ISD::LoadExtType ExtType = LD->getExtensionType();
885 if (ExtType == ISD::NON_EXTLOAD) {
886 MVT VT = Node->getSimpleValueType(0);
887 SDValue RVal = SDValue(Node, 0);
888 SDValue RChain = SDValue(Node, 1);
890 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
891 default: llvm_unreachable("This action is not supported yet!");
892 case TargetLowering::Legal:
893 // If this is an unaligned load and the target doesn't support it,
895 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
896 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
897 unsigned ABIAlignment =
898 TLI.getDataLayout()->getABITypeAlignment(Ty);
899 if (LD->getAlignment() < ABIAlignment){
900 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
904 case TargetLowering::Custom: {
905 SDValue Res = TLI.LowerOperation(RVal, DAG);
908 RChain = Res.getValue(1);
912 case TargetLowering::Promote: {
913 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
914 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
915 "Can only promote loads to same size type");
917 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
918 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
919 RChain = Res.getValue(1);
923 if (RChain.getNode() != Node) {
924 assert(RVal.getNode() != Node && "Load must be completely replaced");
925 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
926 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
932 EVT SrcVT = LD->getMemoryVT();
933 unsigned SrcWidth = SrcVT.getSizeInBits();
934 unsigned Alignment = LD->getAlignment();
935 bool isVolatile = LD->isVolatile();
936 bool isNonTemporal = LD->isNonTemporal();
937 const MDNode *TBAAInfo = LD->getTBAAInfo();
939 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
940 // Some targets pretend to have an i1 loading operation, and actually
941 // load an i8. This trick is correct for ZEXTLOAD because the top 7
942 // bits are guaranteed to be zero; it helps the optimizers understand
943 // that these bits are zero. It is also useful for EXTLOAD, since it
944 // tells the optimizers that those bits are undefined. It would be
945 // nice to have an effective generic way of getting these benefits...
946 // Until such a way is found, don't insist on promoting i1 here.
948 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
949 // Promote to a byte-sized load if not loading an integral number of
950 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
951 unsigned NewWidth = SrcVT.getStoreSizeInBits();
952 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
955 // The extra bits are guaranteed to be zero, since we stored them that
956 // way. A zext load from NVT thus automatically gives zext from SrcVT.
958 ISD::LoadExtType NewExtType =
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
962 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
963 Chain, Ptr, LD->getPointerInfo(),
964 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
966 Ch = Result.getValue(1); // The chain.
968 if (ExtType == ISD::SEXTLOAD)
969 // Having the top bits zero doesn't help when sign extending.
970 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
971 Result.getValueType(),
972 Result, DAG.getValueType(SrcVT));
973 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
974 // All the top bits are guaranteed to be zero - inform the optimizers.
975 Result = DAG.getNode(ISD::AssertZext, dl,
976 Result.getValueType(), Result,
977 DAG.getValueType(SrcVT));
981 } else if (SrcWidth & (SrcWidth - 1)) {
982 // If not loading a power-of-2 number of bits, expand as two loads.
983 assert(!SrcVT.isVector() && "Unsupported extload!");
984 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
985 assert(RoundWidth < SrcWidth);
986 unsigned ExtraWidth = SrcWidth - RoundWidth;
987 assert(ExtraWidth < RoundWidth);
988 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
989 "Load size not an integral number of bytes!");
990 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
991 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
993 unsigned IncrementSize;
995 if (TLI.isLittleEndian()) {
996 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
997 // Load the bottom RoundWidth bits.
998 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1000 LD->getPointerInfo(), RoundVT, isVolatile,
1001 isNonTemporal, Alignment, TBAAInfo);
1003 // Load the remaining ExtraWidth bits.
1004 IncrementSize = RoundWidth / 8;
1005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1006 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1007 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1008 LD->getPointerInfo().getWithOffset(IncrementSize),
1009 ExtraVT, isVolatile, isNonTemporal,
1010 MinAlign(Alignment, IncrementSize), TBAAInfo);
1012 // Build a factor node to remember that this load is independent of
1014 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1017 // Move the top bits to the right place.
1018 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1019 DAG.getConstant(RoundWidth,
1020 TLI.getShiftAmountTy(Hi.getValueType())));
1022 // Join the hi and lo parts.
1023 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1025 // Big endian - avoid unaligned loads.
1026 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1027 // Load the top RoundWidth bits.
1028 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1029 LD->getPointerInfo(), RoundVT, isVolatile,
1030 isNonTemporal, Alignment, TBAAInfo);
1032 // Load the remaining ExtraWidth bits.
1033 IncrementSize = RoundWidth / 8;
1034 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1035 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1036 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1037 dl, Node->getValueType(0), Chain, Ptr,
1038 LD->getPointerInfo().getWithOffset(IncrementSize),
1039 ExtraVT, isVolatile, isNonTemporal,
1040 MinAlign(Alignment, IncrementSize), TBAAInfo);
1042 // Build a factor node to remember that this load is independent of
1044 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1047 // Move the top bits to the right place.
1048 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1049 DAG.getConstant(ExtraWidth,
1050 TLI.getShiftAmountTy(Hi.getValueType())));
1052 // Join the hi and lo parts.
1053 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1058 bool isCustom = false;
1059 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1060 default: llvm_unreachable("This action is not supported yet!");
1061 case TargetLowering::Custom:
1064 case TargetLowering::Legal: {
1065 Value = SDValue(Node, 0);
1066 Chain = SDValue(Node, 1);
1069 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1070 if (Res.getNode()) {
1072 Chain = Res.getValue(1);
1075 // If this is an unaligned load and the target doesn't support it,
1077 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1079 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1080 unsigned ABIAlignment =
1081 TLI.getDataLayout()->getABITypeAlignment(Ty);
1082 if (LD->getAlignment() < ABIAlignment){
1083 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1084 DAG, TLI, Value, Chain);
1090 case TargetLowering::Expand:
1091 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1092 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1093 LD->getMemOperand());
1097 ExtendOp = (SrcVT.isFloatingPoint() ?
1098 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1100 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1101 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1102 default: llvm_unreachable("Unexpected extend load type!");
1104 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1105 Chain = Load.getValue(1);
1109 assert(!SrcVT.isVector() &&
1110 "Vector Loads are handled in LegalizeVectorOps");
1112 // FIXME: This does not work for vectors on most targets. Sign- and
1113 // zero-extend operations are currently folded into extending loads,
1114 // whether they are legal or not, and then we end up here without any
1115 // support for legalizing them.
1116 assert(ExtType != ISD::EXTLOAD &&
1117 "EXTLOAD should always be supported!");
1118 // Turn the unsupported load into an EXTLOAD followed by an explicit
1119 // zero/sign extend inreg.
1120 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1122 LD->getMemOperand());
1124 if (ExtType == ISD::SEXTLOAD)
1125 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1126 Result.getValueType(),
1127 Result, DAG.getValueType(SrcVT));
1129 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1131 Chain = Result.getValue(1);
1136 // Since loads produce two values, make sure to remember that we legalized
1138 if (Chain.getNode() != Node) {
1139 assert(Value.getNode() != Node && "Load must be completely replaced");
1140 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1141 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1146 /// LegalizeOp - Return a legal replacement for the given operation, with
1147 /// all legal operands.
1148 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1149 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1152 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1153 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1154 TargetLowering::TypeLegal &&
1155 "Unexpected illegal type!");
1157 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1158 assert((TLI.getTypeAction(*DAG.getContext(),
1159 Node->getOperand(i).getValueType()) ==
1160 TargetLowering::TypeLegal ||
1161 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1162 "Unexpected illegal type!");
1164 // Figure out the correct action; the way to query this varies by opcode
1165 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1166 bool SimpleFinishLegalizing = true;
1167 switch (Node->getOpcode()) {
1168 case ISD::INTRINSIC_W_CHAIN:
1169 case ISD::INTRINSIC_WO_CHAIN:
1170 case ISD::INTRINSIC_VOID:
1171 case ISD::STACKSAVE:
1172 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1175 Action = TLI.getOperationAction(Node->getOpcode(),
1176 Node->getValueType(0));
1177 if (Action != TargetLowering::Promote)
1178 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1180 case ISD::SINT_TO_FP:
1181 case ISD::UINT_TO_FP:
1182 case ISD::EXTRACT_VECTOR_ELT:
1183 Action = TLI.getOperationAction(Node->getOpcode(),
1184 Node->getOperand(0).getValueType());
1186 case ISD::FP_ROUND_INREG:
1187 case ISD::SIGN_EXTEND_INREG: {
1188 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1189 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1192 case ISD::ATOMIC_STORE: {
1193 Action = TLI.getOperationAction(Node->getOpcode(),
1194 Node->getOperand(2).getValueType());
1197 case ISD::SELECT_CC:
1200 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1201 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1202 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1203 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1204 ISD::CondCode CCCode =
1205 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1206 Action = TLI.getCondCodeAction(CCCode, OpVT);
1207 if (Action == TargetLowering::Legal) {
1208 if (Node->getOpcode() == ISD::SELECT_CC)
1209 Action = TLI.getOperationAction(Node->getOpcode(),
1210 Node->getValueType(0));
1212 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1218 // FIXME: Model these properly. LOAD and STORE are complicated, and
1219 // STORE expects the unlegalized operand in some cases.
1220 SimpleFinishLegalizing = false;
1222 case ISD::CALLSEQ_START:
1223 case ISD::CALLSEQ_END:
1224 // FIXME: This shouldn't be necessary. These nodes have special properties
1225 // dealing with the recursive nature of legalization. Removing this
1226 // special case should be done as part of making LegalizeDAG non-recursive.
1227 SimpleFinishLegalizing = false;
1229 case ISD::EXTRACT_ELEMENT:
1230 case ISD::FLT_ROUNDS_:
1238 case ISD::MERGE_VALUES:
1239 case ISD::EH_RETURN:
1240 case ISD::FRAME_TO_ARGS_OFFSET:
1241 case ISD::EH_SJLJ_SETJMP:
1242 case ISD::EH_SJLJ_LONGJMP:
1243 // These operations lie about being legal: when they claim to be legal,
1244 // they should actually be expanded.
1245 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1246 if (Action == TargetLowering::Legal)
1247 Action = TargetLowering::Expand;
1249 case ISD::INIT_TRAMPOLINE:
1250 case ISD::ADJUST_TRAMPOLINE:
1251 case ISD::FRAMEADDR:
1252 case ISD::RETURNADDR:
1253 // These operations lie about being legal: when they claim to be legal,
1254 // they should actually be custom-lowered.
1255 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1256 if (Action == TargetLowering::Legal)
1257 Action = TargetLowering::Custom;
1259 case ISD::DEBUGTRAP:
1260 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1261 if (Action == TargetLowering::Expand) {
1262 // replace ISD::DEBUGTRAP with ISD::TRAP
1264 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1265 Node->getOperand(0));
1266 ReplaceNode(Node, NewVal.getNode());
1267 LegalizeOp(NewVal.getNode());
1273 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1274 Action = TargetLowering::Legal;
1276 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1281 if (SimpleFinishLegalizing) {
1282 SDNode *NewNode = Node;
1283 switch (Node->getOpcode()) {
1290 // Legalizing shifts/rotates requires adjusting the shift amount
1291 // to the appropriate width.
1292 if (!Node->getOperand(1).getValueType().isVector()) {
1294 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1295 Node->getOperand(1));
1296 HandleSDNode Handle(SAO);
1297 LegalizeOp(SAO.getNode());
1298 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1302 case ISD::SRL_PARTS:
1303 case ISD::SRA_PARTS:
1304 case ISD::SHL_PARTS:
1305 // Legalizing shifts/rotates requires adjusting the shift amount
1306 // to the appropriate width.
1307 if (!Node->getOperand(2).getValueType().isVector()) {
1309 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1310 Node->getOperand(2));
1311 HandleSDNode Handle(SAO);
1312 LegalizeOp(SAO.getNode());
1313 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1314 Node->getOperand(1),
1320 if (NewNode != Node) {
1321 DAG.ReplaceAllUsesWith(Node, NewNode);
1322 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1323 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1328 case TargetLowering::Legal:
1330 case TargetLowering::Custom: {
1331 // FIXME: The handling for custom lowering with multiple results is
1333 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1334 if (Res.getNode()) {
1335 SmallVector<SDValue, 8> ResultVals;
1336 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1338 ResultVals.push_back(Res);
1340 ResultVals.push_back(Res.getValue(i));
1342 if (Res.getNode() != Node || Res.getResNo() != 0) {
1343 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1344 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1345 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1352 case TargetLowering::Expand:
1355 case TargetLowering::Promote:
1361 switch (Node->getOpcode()) {
1368 llvm_unreachable("Do not know how to legalize this operator!");
1370 case ISD::CALLSEQ_START:
1371 case ISD::CALLSEQ_END:
1374 return LegalizeLoadOps(Node);
1377 return LegalizeStoreOps(Node);
1382 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1383 SDValue Vec = Op.getOperand(0);
1384 SDValue Idx = Op.getOperand(1);
1386 // Store the value to a temporary stack slot, then LOAD the returned part.
1387 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1388 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1389 MachinePointerInfo(), false, false, 0);
1391 // Add the offset to the index.
1393 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1394 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1395 DAG.getConstant(EltSize, Idx.getValueType()));
1397 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1398 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1400 if (Op.getValueType().isVector())
1401 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1402 false, false, false, 0);
1403 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1404 MachinePointerInfo(),
1405 Vec.getValueType().getVectorElementType(),
1409 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1410 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1412 SDValue Vec = Op.getOperand(0);
1413 SDValue Part = Op.getOperand(1);
1414 SDValue Idx = Op.getOperand(2);
1417 // Store the value to a temporary stack slot, then LOAD the returned part.
1419 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1420 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1421 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1423 // First store the whole vector.
1424 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1427 // Then store the inserted part.
1429 // Add the offset to the index.
1431 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1433 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1434 DAG.getConstant(EltSize, Idx.getValueType()));
1435 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1437 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1440 // Store the subvector.
1441 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1442 MachinePointerInfo(), false, false, 0);
1444 // Finally, load the updated vector.
1445 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1446 false, false, false, 0);
1449 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1450 // We can't handle this case efficiently. Allocate a sufficiently
1451 // aligned object on the stack, store each element into it, then load
1452 // the result as a vector.
1453 // Create the stack frame object.
1454 EVT VT = Node->getValueType(0);
1455 EVT EltVT = VT.getVectorElementType();
1457 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1458 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1459 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1461 // Emit a store of each element to the stack slot.
1462 SmallVector<SDValue, 8> Stores;
1463 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1464 // Store (in the right endianness) the elements to memory.
1465 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1466 // Ignore undef elements.
1467 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1469 unsigned Offset = TypeByteSize*i;
1471 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1472 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1474 // If the destination vector element type is narrower than the source
1475 // element type, only store the bits necessary.
1476 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1477 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1478 Node->getOperand(i), Idx,
1479 PtrInfo.getWithOffset(Offset),
1480 EltVT, false, false, 0));
1482 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1483 Node->getOperand(i), Idx,
1484 PtrInfo.getWithOffset(Offset),
1489 if (!Stores.empty()) // Not all undef elements?
1490 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1491 &Stores[0], Stores.size());
1493 StoreChain = DAG.getEntryNode();
1495 // Result is a load from the stack slot.
1496 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1497 false, false, false, 0);
1500 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1502 SDValue Tmp1 = Node->getOperand(0);
1503 SDValue Tmp2 = Node->getOperand(1);
1505 // Get the sign bit of the RHS. First obtain a value that has the same
1506 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1508 EVT FloatVT = Tmp2.getValueType();
1509 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1510 if (TLI.isTypeLegal(IVT)) {
1511 // Convert to an integer with the same sign bit.
1512 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1514 // Store the float to memory, then load the sign part out as an integer.
1515 MVT LoadTy = TLI.getPointerTy();
1516 // First create a temporary that is aligned for both the load and store.
1517 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1518 // Then store the float to it.
1520 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1522 if (TLI.isBigEndian()) {
1523 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1524 // Load out a legal integer with the same sign bit as the float.
1525 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1526 false, false, false, 0);
1527 } else { // Little endian
1528 SDValue LoadPtr = StackPtr;
1529 // The float may be wider than the integer we are going to load. Advance
1530 // the pointer so that the loaded integer will contain the sign bit.
1531 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1532 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1533 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1535 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1536 // Load a legal integer containing the sign bit.
1537 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1538 false, false, false, 0);
1539 // Move the sign bit to the top bit of the loaded integer.
1540 unsigned BitShift = LoadTy.getSizeInBits() -
1541 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1542 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1544 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1545 DAG.getConstant(BitShift,
1546 TLI.getShiftAmountTy(SignBit.getValueType())));
1549 // Now get the sign bit proper, by seeing whether the value is negative.
1550 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1551 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1553 // Get the absolute value of the result.
1554 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1555 // Select between the nabs and abs value based on the sign bit of
1557 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1558 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1562 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1563 SmallVectorImpl<SDValue> &Results) {
1564 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1565 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1566 " not tell us which reg is the stack pointer!");
1568 EVT VT = Node->getValueType(0);
1569 SDValue Tmp1 = SDValue(Node, 0);
1570 SDValue Tmp2 = SDValue(Node, 1);
1571 SDValue Tmp3 = Node->getOperand(2);
1572 SDValue Chain = Tmp1.getOperand(0);
1574 // Chain the dynamic stack allocation so that it doesn't modify the stack
1575 // pointer when other instructions are using the stack.
1576 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1579 SDValue Size = Tmp2.getOperand(1);
1580 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1581 Chain = SP.getValue(1);
1582 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1583 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1584 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1585 if (Align > StackAlign)
1586 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1587 DAG.getConstant(-(uint64_t)Align, VT));
1588 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1590 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1591 DAG.getIntPtrConstant(0, true), SDValue(),
1594 Results.push_back(Tmp1);
1595 Results.push_back(Tmp2);
1598 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1599 /// condition code CC on the current target.
1601 /// If the SETCC has been legalized using AND / OR, then the legalized node
1602 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1603 /// will be set to false.
1605 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1606 /// then the values of LHS and RHS will be swapped, CC will be set to the
1607 /// new condition, and NeedInvert will be set to false.
1609 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1610 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1611 /// will be set to true. The caller must invert the result of the SETCC with
1612 /// SelectionDAG::getNOT() or take equivalent action to swap the effect of a
1613 /// true/false result.
1615 /// \returns true if the SetCC has been legalized, false if it hasn't.
1616 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1617 SDValue &LHS, SDValue &RHS,
1621 MVT OpVT = LHS.getSimpleValueType();
1622 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1624 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1625 default: llvm_unreachable("Unknown condition code action!");
1626 case TargetLowering::Legal:
1629 case TargetLowering::Expand: {
1630 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1631 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1632 std::swap(LHS, RHS);
1633 CC = DAG.getCondCode(InvCC);
1636 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1639 default: llvm_unreachable("Don't know how to expand this condition!");
1641 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1642 == TargetLowering::Legal
1643 && "If SETO is expanded, SETOEQ must be legal!");
1644 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1646 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1647 == TargetLowering::Legal
1648 && "If SETUO is expanded, SETUNE must be legal!");
1649 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1662 // If we are floating point, assign and break, otherwise fall through.
1663 if (!OpVT.isInteger()) {
1664 // We can use the 4th bit to tell if we are the unordered
1665 // or ordered version of the opcode.
1666 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1667 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1668 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1671 // Fallthrough if we are unsigned integer.
1676 // We only support using the inverted operation, which is computed above
1677 // and not a different manner of supporting expanding these cases.
1678 llvm_unreachable("Don't know how to expand this condition!");
1681 // Try inverting the result of the inverse condition.
1682 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1683 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1684 CC = DAG.getCondCode(InvCC);
1688 // If inverting the condition didn't work then we have no means to expand
1690 llvm_unreachable("Don't know how to expand this condition!");
1693 SDValue SetCC1, SetCC2;
1694 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1695 // If we aren't the ordered or unorder operation,
1696 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1697 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1698 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1700 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1701 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1702 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1704 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1713 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1714 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1715 /// a load from the stack slot to DestVT, extending it if needed.
1716 /// The resultant code need not be legal.
1717 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1721 // Create the stack frame object.
1723 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1724 getTypeForEVT(*DAG.getContext()));
1725 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1727 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1728 int SPFI = StackPtrFI->getIndex();
1729 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1731 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1732 unsigned SlotSize = SlotVT.getSizeInBits();
1733 unsigned DestSize = DestVT.getSizeInBits();
1734 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1735 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1737 // Emit a store to the stack slot. Use a truncstore if the input value is
1738 // later than DestVT.
1741 if (SrcSize > SlotSize)
1742 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1743 PtrInfo, SlotVT, false, false, SrcAlign);
1745 assert(SrcSize == SlotSize && "Invalid store");
1746 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1747 PtrInfo, false, false, SrcAlign);
1750 // Result is a load from the stack slot.
1751 if (SlotSize == DestSize)
1752 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1753 false, false, false, DestAlign);
1755 assert(SlotSize < DestSize && "Unknown extension!");
1756 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1757 PtrInfo, SlotVT, false, false, DestAlign);
1760 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1762 // Create a vector sized/aligned stack slot, store the value to element #0,
1763 // then load the whole vector back out.
1764 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1766 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1767 int SPFI = StackPtrFI->getIndex();
1769 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1771 MachinePointerInfo::getFixedStack(SPFI),
1772 Node->getValueType(0).getVectorElementType(),
1774 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1775 MachinePointerInfo::getFixedStack(SPFI),
1776 false, false, false, 0);
1780 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1781 /// support the operation, but do support the resultant vector type.
1782 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1783 unsigned NumElems = Node->getNumOperands();
1784 SDValue Value1, Value2;
1786 EVT VT = Node->getValueType(0);
1787 EVT OpVT = Node->getOperand(0).getValueType();
1788 EVT EltVT = VT.getVectorElementType();
1790 // If the only non-undef value is the low element, turn this into a
1791 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1792 bool isOnlyLowElement = true;
1793 bool MoreThanTwoValues = false;
1794 bool isConstant = true;
1795 for (unsigned i = 0; i < NumElems; ++i) {
1796 SDValue V = Node->getOperand(i);
1797 if (V.getOpcode() == ISD::UNDEF)
1800 isOnlyLowElement = false;
1801 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1804 if (!Value1.getNode()) {
1806 } else if (!Value2.getNode()) {
1809 } else if (V != Value1 && V != Value2) {
1810 MoreThanTwoValues = true;
1814 if (!Value1.getNode())
1815 return DAG.getUNDEF(VT);
1817 if (isOnlyLowElement)
1818 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1820 // If all elements are constants, create a load from the constant pool.
1822 SmallVector<Constant*, 16> CV;
1823 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1824 if (ConstantFPSDNode *V =
1825 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1826 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1827 } else if (ConstantSDNode *V =
1828 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1830 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1832 // If OpVT and EltVT don't match, EltVT is not legal and the
1833 // element values have been promoted/truncated earlier. Undo this;
1834 // we don't want a v16i8 to become a v16i32 for example.
1835 const ConstantInt *CI = V->getConstantIntValue();
1836 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1837 CI->getZExtValue()));
1840 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1841 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1842 CV.push_back(UndefValue::get(OpNTy));
1845 Constant *CP = ConstantVector::get(CV);
1846 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1847 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1848 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1849 MachinePointerInfo::getConstantPool(),
1850 false, false, false, Alignment);
1853 if (!MoreThanTwoValues) {
1854 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1855 for (unsigned i = 0; i < NumElems; ++i) {
1856 SDValue V = Node->getOperand(i);
1857 if (V.getOpcode() == ISD::UNDEF)
1859 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1861 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1862 // Get the splatted value into the low element of a vector register.
1863 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1865 if (Value2.getNode())
1866 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1868 Vec2 = DAG.getUNDEF(VT);
1870 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1871 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1875 // Otherwise, we can't handle this case efficiently.
1876 return ExpandVectorBuildThroughStack(Node);
1879 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1880 // does not fit into a register, return the lo part and set the hi part to the
1881 // by-reg argument. If it does fit into a single register, return the result
1882 // and leave the Hi part unset.
1883 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1885 TargetLowering::ArgListTy Args;
1886 TargetLowering::ArgListEntry Entry;
1887 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1888 EVT ArgVT = Node->getOperand(i).getValueType();
1889 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1890 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1891 Entry.isSExt = isSigned;
1892 Entry.isZExt = !isSigned;
1893 Args.push_back(Entry);
1895 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1896 TLI.getPointerTy());
1898 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1900 // By default, the input chain to this libcall is the entry node of the
1901 // function. If the libcall is going to be emitted as a tail call then
1902 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1903 // node which is being folded has a non-entry input chain.
1904 SDValue InChain = DAG.getEntryNode();
1906 // isTailCall may be true since the callee does not reference caller stack
1907 // frame. Check if it's in the right position.
1908 SDValue TCChain = InChain;
1909 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1914 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1915 0, TLI.getLibcallCallingConv(LC), isTailCall,
1916 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1917 Callee, Args, DAG, SDLoc(Node));
1918 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1921 if (!CallInfo.second.getNode())
1922 // It's a tailcall, return the chain (which is the DAG root).
1923 return DAG.getRoot();
1925 return CallInfo.first;
1928 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1929 /// and returning a result of type RetVT.
1930 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1931 const SDValue *Ops, unsigned NumOps,
1932 bool isSigned, SDLoc dl) {
1933 TargetLowering::ArgListTy Args;
1934 Args.reserve(NumOps);
1936 TargetLowering::ArgListEntry Entry;
1937 for (unsigned i = 0; i != NumOps; ++i) {
1938 Entry.Node = Ops[i];
1939 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1940 Entry.isSExt = isSigned;
1941 Entry.isZExt = !isSigned;
1942 Args.push_back(Entry);
1944 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1945 TLI.getPointerTy());
1947 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1949 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1950 false, 0, TLI.getLibcallCallingConv(LC),
1951 /*isTailCall=*/false,
1952 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1953 Callee, Args, DAG, dl);
1954 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1956 return CallInfo.first;
1959 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1960 // ExpandLibCall except that the first operand is the in-chain.
1961 std::pair<SDValue, SDValue>
1962 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1965 SDValue InChain = Node->getOperand(0);
1967 TargetLowering::ArgListTy Args;
1968 TargetLowering::ArgListEntry Entry;
1969 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1970 EVT ArgVT = Node->getOperand(i).getValueType();
1971 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1972 Entry.Node = Node->getOperand(i);
1974 Entry.isSExt = isSigned;
1975 Entry.isZExt = !isSigned;
1976 Args.push_back(Entry);
1978 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1979 TLI.getPointerTy());
1981 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1983 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1984 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1985 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1986 Callee, Args, DAG, SDLoc(Node));
1987 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1992 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1993 RTLIB::Libcall Call_F32,
1994 RTLIB::Libcall Call_F64,
1995 RTLIB::Libcall Call_F80,
1996 RTLIB::Libcall Call_F128,
1997 RTLIB::Libcall Call_PPCF128) {
1999 switch (Node->getSimpleValueType(0).SimpleTy) {
2000 default: llvm_unreachable("Unexpected request for libcall!");
2001 case MVT::f32: LC = Call_F32; break;
2002 case MVT::f64: LC = Call_F64; break;
2003 case MVT::f80: LC = Call_F80; break;
2004 case MVT::f128: LC = Call_F128; break;
2005 case MVT::ppcf128: LC = Call_PPCF128; break;
2007 return ExpandLibCall(LC, Node, false);
2010 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2011 RTLIB::Libcall Call_I8,
2012 RTLIB::Libcall Call_I16,
2013 RTLIB::Libcall Call_I32,
2014 RTLIB::Libcall Call_I64,
2015 RTLIB::Libcall Call_I128) {
2017 switch (Node->getSimpleValueType(0).SimpleTy) {
2018 default: llvm_unreachable("Unexpected request for libcall!");
2019 case MVT::i8: LC = Call_I8; break;
2020 case MVT::i16: LC = Call_I16; break;
2021 case MVT::i32: LC = Call_I32; break;
2022 case MVT::i64: LC = Call_I64; break;
2023 case MVT::i128: LC = Call_I128; break;
2025 return ExpandLibCall(LC, Node, isSigned);
2028 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2029 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2030 const TargetLowering &TLI) {
2032 switch (Node->getSimpleValueType(0).SimpleTy) {
2033 default: llvm_unreachable("Unexpected request for libcall!");
2034 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2035 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2036 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2037 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2038 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2041 return TLI.getLibcallName(LC) != 0;
2044 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2046 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2047 // The other use might have been replaced with a divrem already.
2048 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2049 unsigned OtherOpcode = 0;
2051 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2053 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2055 SDValue Op0 = Node->getOperand(0);
2056 SDValue Op1 = Node->getOperand(1);
2057 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2058 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2062 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2063 User->getOperand(0) == Op0 &&
2064 User->getOperand(1) == Op1)
2070 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2073 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2074 SmallVectorImpl<SDValue> &Results) {
2075 unsigned Opcode = Node->getOpcode();
2076 bool isSigned = Opcode == ISD::SDIVREM;
2079 switch (Node->getSimpleValueType(0).SimpleTy) {
2080 default: llvm_unreachable("Unexpected request for libcall!");
2081 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2082 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2083 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2084 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2085 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2088 // The input chain to this libcall is the entry node of the function.
2089 // Legalizing the call will automatically add the previous call to the
2091 SDValue InChain = DAG.getEntryNode();
2093 EVT RetVT = Node->getValueType(0);
2094 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2096 TargetLowering::ArgListTy Args;
2097 TargetLowering::ArgListEntry Entry;
2098 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2099 EVT ArgVT = Node->getOperand(i).getValueType();
2100 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2101 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2102 Entry.isSExt = isSigned;
2103 Entry.isZExt = !isSigned;
2104 Args.push_back(Entry);
2107 // Also pass the return address of the remainder.
2108 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2110 Entry.Ty = RetTy->getPointerTo();
2111 Entry.isSExt = isSigned;
2112 Entry.isZExt = !isSigned;
2113 Args.push_back(Entry);
2115 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2116 TLI.getPointerTy());
2120 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2121 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2122 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2123 Callee, Args, DAG, dl);
2124 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2126 // Remainder is loaded back from the stack frame.
2127 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2128 MachinePointerInfo(), false, false, false, 0);
2129 Results.push_back(CallInfo.first);
2130 Results.push_back(Rem);
2133 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2134 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2136 switch (Node->getSimpleValueType(0).SimpleTy) {
2137 default: llvm_unreachable("Unexpected request for libcall!");
2138 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2139 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2140 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2141 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2142 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2144 return TLI.getLibcallName(LC) != 0;
2147 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2148 /// can be used to combine sin and cos.
2149 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2150 const TargetMachine &TM) {
2151 if (!isSinCosLibcallAvailable(Node, TLI))
2153 // GNU sin/cos functions set errno while sincos does not. Therefore
2154 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2155 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2156 if (isGNU && !TM.Options.UnsafeFPMath)
2161 /// useSinCos - Only issue sincos libcall if both sin and cos are
2163 static bool useSinCos(SDNode *Node) {
2164 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2165 ? ISD::FCOS : ISD::FSIN;
2167 SDValue Op0 = Node->getOperand(0);
2168 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2169 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2173 // The other user might have been turned into sincos already.
2174 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2180 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2183 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2184 SmallVectorImpl<SDValue> &Results) {
2186 switch (Node->getSimpleValueType(0).SimpleTy) {
2187 default: llvm_unreachable("Unexpected request for libcall!");
2188 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2189 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2190 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2191 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2192 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2195 // The input chain to this libcall is the entry node of the function.
2196 // Legalizing the call will automatically add the previous call to the
2198 SDValue InChain = DAG.getEntryNode();
2200 EVT RetVT = Node->getValueType(0);
2201 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2203 TargetLowering::ArgListTy Args;
2204 TargetLowering::ArgListEntry Entry;
2206 // Pass the argument.
2207 Entry.Node = Node->getOperand(0);
2209 Entry.isSExt = false;
2210 Entry.isZExt = false;
2211 Args.push_back(Entry);
2213 // Pass the return address of sin.
2214 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2215 Entry.Node = SinPtr;
2216 Entry.Ty = RetTy->getPointerTo();
2217 Entry.isSExt = false;
2218 Entry.isZExt = false;
2219 Args.push_back(Entry);
2221 // Also pass the return address of the cos.
2222 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2223 Entry.Node = CosPtr;
2224 Entry.Ty = RetTy->getPointerTo();
2225 Entry.isSExt = false;
2226 Entry.isZExt = false;
2227 Args.push_back(Entry);
2229 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2230 TLI.getPointerTy());
2234 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2235 false, false, false, false,
2236 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2237 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2238 Callee, Args, DAG, dl);
2239 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2241 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2242 MachinePointerInfo(), false, false, false, 0));
2243 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2244 MachinePointerInfo(), false, false, false, 0));
2247 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2248 /// INT_TO_FP operation of the specified operand when the target requests that
2249 /// we expand it. At this point, we know that the result and operand types are
2250 /// legal for the target.
2251 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2255 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2256 // simple 32-bit [signed|unsigned] integer to float/double expansion
2258 // Get the stack frame index of a 8 byte buffer.
2259 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2261 // word offset constant for Hi/Lo address computation
2262 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2263 // set up Hi and Lo (into buffer) address based on endian
2264 SDValue Hi = StackSlot;
2265 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2266 StackSlot, WordOff);
2267 if (TLI.isLittleEndian())
2270 // if signed map to unsigned space
2273 // constant used to invert sign bit (signed to unsigned mapping)
2274 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2275 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2279 // store the lo of the constructed double - based on integer input
2280 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2281 Op0Mapped, Lo, MachinePointerInfo(),
2283 // initial hi portion of constructed double
2284 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2285 // store the hi of the constructed double - biased exponent
2286 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2287 MachinePointerInfo(),
2289 // load the constructed double
2290 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2291 MachinePointerInfo(), false, false, false, 0);
2292 // FP constant to bias correct the final result
2293 SDValue Bias = DAG.getConstantFP(isSigned ?
2294 BitsToDouble(0x4330000080000000ULL) :
2295 BitsToDouble(0x4330000000000000ULL),
2297 // subtract the bias
2298 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2301 // handle final rounding
2302 if (DestVT == MVT::f64) {
2305 } else if (DestVT.bitsLT(MVT::f64)) {
2306 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2307 DAG.getIntPtrConstant(0));
2308 } else if (DestVT.bitsGT(MVT::f64)) {
2309 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2313 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2314 // Code below here assumes !isSigned without checking again.
2316 // Implementation of unsigned i64 to f64 following the algorithm in
2317 // __floatundidf in compiler_rt. This implementation has the advantage
2318 // of performing rounding correctly, both in the default rounding mode
2319 // and in all alternate rounding modes.
2320 // TODO: Generalize this for use with other types.
2321 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2323 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2324 SDValue TwoP84PlusTwoP52 =
2325 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2327 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2329 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2330 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2331 DAG.getConstant(32, MVT::i64));
2332 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2333 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2334 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2335 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2336 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2338 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2341 // Implementation of unsigned i64 to f32.
2342 // TODO: Generalize this for use with other types.
2343 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2344 // For unsigned conversions, convert them to signed conversions using the
2345 // algorithm from the x86_64 __floatundidf in compiler_rt.
2347 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2349 SDValue ShiftConst =
2350 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2351 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2352 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2353 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2354 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2356 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2357 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2359 // TODO: This really should be implemented using a branch rather than a
2360 // select. We happen to get lucky and machinesink does the right
2361 // thing most of the time. This would be a good candidate for a
2362 //pseudo-op, or, even better, for whole-function isel.
2363 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2364 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2365 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2368 // Otherwise, implement the fully general conversion.
2370 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2371 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2372 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2373 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2374 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2375 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2376 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2377 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2378 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2379 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2380 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2382 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2383 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2385 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2386 DAG.getConstant(32, SHVT));
2387 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2388 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2390 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2391 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2392 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2393 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2394 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2395 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2396 DAG.getIntPtrConstant(0));
2399 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2401 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2402 Op0, DAG.getConstant(0, Op0.getValueType()),
2404 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2405 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2406 SignSet, Four, Zero);
2408 // If the sign bit of the integer is set, the large number will be treated
2409 // as a negative number. To counteract this, the dynamic code adds an
2410 // offset depending on the data type.
2412 switch (Op0.getSimpleValueType().SimpleTy) {
2413 default: llvm_unreachable("Unsupported integer type!");
2414 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2415 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2416 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2417 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2419 if (TLI.isLittleEndian()) FF <<= 32;
2420 Constant *FudgeFactor = ConstantInt::get(
2421 Type::getInt64Ty(*DAG.getContext()), FF);
2423 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2424 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2425 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2426 Alignment = std::min(Alignment, 4u);
2428 if (DestVT == MVT::f32)
2429 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2430 MachinePointerInfo::getConstantPool(),
2431 false, false, false, Alignment);
2433 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2434 DAG.getEntryNode(), CPIdx,
2435 MachinePointerInfo::getConstantPool(),
2436 MVT::f32, false, false, Alignment);
2437 HandleSDNode Handle(Load);
2438 LegalizeOp(Load.getNode());
2439 FudgeInReg = Handle.getValue();
2442 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2445 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2446 /// *INT_TO_FP operation of the specified operand when the target requests that
2447 /// we promote it. At this point, we know that the result and operand types are
2448 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2449 /// operation that takes a larger input.
2450 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2454 // First step, figure out the appropriate *INT_TO_FP operation to use.
2455 EVT NewInTy = LegalOp.getValueType();
2457 unsigned OpToUse = 0;
2459 // Scan for the appropriate larger type to use.
2461 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2462 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2464 // If the target supports SINT_TO_FP of this type, use it.
2465 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2466 OpToUse = ISD::SINT_TO_FP;
2469 if (isSigned) continue;
2471 // If the target supports UINT_TO_FP of this type, use it.
2472 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2473 OpToUse = ISD::UINT_TO_FP;
2477 // Otherwise, try a larger type.
2480 // Okay, we found the operation and type to use. Zero extend our input to the
2481 // desired type then run the operation on it.
2482 return DAG.getNode(OpToUse, dl, DestVT,
2483 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2484 dl, NewInTy, LegalOp));
2487 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2488 /// FP_TO_*INT operation of the specified operand when the target requests that
2489 /// we promote it. At this point, we know that the result and operand types are
2490 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2491 /// operation that returns a larger result.
2492 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2496 // First step, figure out the appropriate FP_TO*INT operation to use.
2497 EVT NewOutTy = DestVT;
2499 unsigned OpToUse = 0;
2501 // Scan for the appropriate larger type to use.
2503 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2504 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2506 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2507 OpToUse = ISD::FP_TO_SINT;
2511 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2512 OpToUse = ISD::FP_TO_UINT;
2516 // Otherwise, try a larger type.
2520 // Okay, we found the operation and type to use.
2521 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2523 // Truncate the result of the extended FP_TO_*INT operation to the desired
2525 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2528 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2530 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2531 EVT VT = Op.getValueType();
2532 EVT SHVT = TLI.getShiftAmountTy(VT);
2533 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2534 switch (VT.getSimpleVT().SimpleTy) {
2535 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2537 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2538 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2539 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2541 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2542 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2543 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2544 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2545 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2546 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2547 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2548 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2549 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2551 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2552 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2553 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2554 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2555 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2556 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2557 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2558 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2559 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2560 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2561 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2562 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2563 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2564 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2565 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2566 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2567 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2568 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2569 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2570 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2571 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2575 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2577 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2580 default: llvm_unreachable("Cannot expand this yet!");
2582 EVT VT = Op.getValueType();
2583 EVT ShVT = TLI.getShiftAmountTy(VT);
2584 unsigned Len = VT.getSizeInBits();
2586 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2587 "CTPOP not implemented for this type.");
2589 // This is the "best" algorithm from
2590 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2592 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2593 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2594 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2595 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2597 // v = v - ((v >> 1) & 0x55555555...)
2598 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2599 DAG.getNode(ISD::AND, dl, VT,
2600 DAG.getNode(ISD::SRL, dl, VT, Op,
2601 DAG.getConstant(1, ShVT)),
2603 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2604 Op = DAG.getNode(ISD::ADD, dl, VT,
2605 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2606 DAG.getNode(ISD::AND, dl, VT,
2607 DAG.getNode(ISD::SRL, dl, VT, Op,
2608 DAG.getConstant(2, ShVT)),
2610 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2611 Op = DAG.getNode(ISD::AND, dl, VT,
2612 DAG.getNode(ISD::ADD, dl, VT, Op,
2613 DAG.getNode(ISD::SRL, dl, VT, Op,
2614 DAG.getConstant(4, ShVT))),
2616 // v = (v * 0x01010101...) >> (Len - 8)
2617 Op = DAG.getNode(ISD::SRL, dl, VT,
2618 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2619 DAG.getConstant(Len - 8, ShVT));
2623 case ISD::CTLZ_ZERO_UNDEF:
2624 // This trivially expands to CTLZ.
2625 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2627 // for now, we do this:
2628 // x = x | (x >> 1);
2629 // x = x | (x >> 2);
2631 // x = x | (x >>16);
2632 // x = x | (x >>32); // for 64-bit input
2633 // return popcount(~x);
2635 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2636 EVT VT = Op.getValueType();
2637 EVT ShVT = TLI.getShiftAmountTy(VT);
2638 unsigned len = VT.getSizeInBits();
2639 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2640 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2641 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2642 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2644 Op = DAG.getNOT(dl, Op, VT);
2645 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2647 case ISD::CTTZ_ZERO_UNDEF:
2648 // This trivially expands to CTTZ.
2649 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2651 // for now, we use: { return popcount(~x & (x - 1)); }
2652 // unless the target has ctlz but not ctpop, in which case we use:
2653 // { return 32 - nlz(~x & (x-1)); }
2654 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2655 EVT VT = Op.getValueType();
2656 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2657 DAG.getNOT(dl, Op, VT),
2658 DAG.getNode(ISD::SUB, dl, VT, Op,
2659 DAG.getConstant(1, VT)));
2660 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2661 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2662 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2663 return DAG.getNode(ISD::SUB, dl, VT,
2664 DAG.getConstant(VT.getSizeInBits(), VT),
2665 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2666 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2671 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2672 unsigned Opc = Node->getOpcode();
2673 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2678 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2679 case ISD::ATOMIC_SWAP:
2680 switch (VT.SimpleTy) {
2681 default: llvm_unreachable("Unexpected value type for atomic!");
2682 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2683 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2684 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2685 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2686 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2689 case ISD::ATOMIC_CMP_SWAP:
2690 switch (VT.SimpleTy) {
2691 default: llvm_unreachable("Unexpected value type for atomic!");
2692 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2693 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2694 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2695 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2696 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2699 case ISD::ATOMIC_LOAD_ADD:
2700 switch (VT.SimpleTy) {
2701 default: llvm_unreachable("Unexpected value type for atomic!");
2702 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2703 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2704 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2705 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2706 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2709 case ISD::ATOMIC_LOAD_SUB:
2710 switch (VT.SimpleTy) {
2711 default: llvm_unreachable("Unexpected value type for atomic!");
2712 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2713 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2714 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2715 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2716 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2719 case ISD::ATOMIC_LOAD_AND:
2720 switch (VT.SimpleTy) {
2721 default: llvm_unreachable("Unexpected value type for atomic!");
2722 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2723 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2724 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2725 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2726 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2729 case ISD::ATOMIC_LOAD_OR:
2730 switch (VT.SimpleTy) {
2731 default: llvm_unreachable("Unexpected value type for atomic!");
2732 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2733 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2734 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2735 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2736 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2739 case ISD::ATOMIC_LOAD_XOR:
2740 switch (VT.SimpleTy) {
2741 default: llvm_unreachable("Unexpected value type for atomic!");
2742 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2743 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2744 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2745 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2746 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2749 case ISD::ATOMIC_LOAD_NAND:
2750 switch (VT.SimpleTy) {
2751 default: llvm_unreachable("Unexpected value type for atomic!");
2752 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2753 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2754 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2755 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2756 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2759 case ISD::ATOMIC_LOAD_MAX:
2760 switch (VT.SimpleTy) {
2761 default: llvm_unreachable("Unexpected value type for atomic!");
2762 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2763 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2764 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2765 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2766 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2769 case ISD::ATOMIC_LOAD_UMAX:
2770 switch (VT.SimpleTy) {
2771 default: llvm_unreachable("Unexpected value type for atomic!");
2772 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2773 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2774 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2775 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2776 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2779 case ISD::ATOMIC_LOAD_MIN:
2780 switch (VT.SimpleTy) {
2781 default: llvm_unreachable("Unexpected value type for atomic!");
2782 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2783 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2784 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2785 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2786 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2789 case ISD::ATOMIC_LOAD_UMIN:
2790 switch (VT.SimpleTy) {
2791 default: llvm_unreachable("Unexpected value type for atomic!");
2792 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2793 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2794 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2795 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2796 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2801 return ExpandChainLibCall(LC, Node, false);
2804 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2805 SmallVector<SDValue, 8> Results;
2807 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2809 switch (Node->getOpcode()) {
2812 case ISD::CTLZ_ZERO_UNDEF:
2814 case ISD::CTTZ_ZERO_UNDEF:
2815 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2816 Results.push_back(Tmp1);
2819 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2821 case ISD::FRAMEADDR:
2822 case ISD::RETURNADDR:
2823 case ISD::FRAME_TO_ARGS_OFFSET:
2824 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2826 case ISD::FLT_ROUNDS_:
2827 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2829 case ISD::EH_RETURN:
2833 case ISD::EH_SJLJ_LONGJMP:
2834 // If the target didn't expand these, there's nothing to do, so just
2835 // preserve the chain and be done.
2836 Results.push_back(Node->getOperand(0));
2838 case ISD::EH_SJLJ_SETJMP:
2839 // If the target didn't expand this, just return 'zero' and preserve the
2841 Results.push_back(DAG.getConstant(0, MVT::i32));
2842 Results.push_back(Node->getOperand(0));
2844 case ISD::ATOMIC_FENCE: {
2845 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2846 // FIXME: handle "fence singlethread" more efficiently.
2847 TargetLowering::ArgListTy Args;
2849 CallLoweringInfo CLI(Node->getOperand(0),
2850 Type::getVoidTy(*DAG.getContext()),
2851 false, false, false, false, 0, CallingConv::C,
2852 /*isTailCall=*/false,
2853 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2854 DAG.getExternalSymbol("__sync_synchronize",
2855 TLI.getPointerTy()),
2857 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2859 Results.push_back(CallResult.second);
2862 case ISD::ATOMIC_LOAD: {
2863 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2864 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2865 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2866 cast<AtomicSDNode>(Node)->getMemoryVT(),
2867 Node->getOperand(0),
2868 Node->getOperand(1), Zero, Zero,
2869 cast<AtomicSDNode>(Node)->getMemOperand(),
2870 cast<AtomicSDNode>(Node)->getOrdering(),
2871 cast<AtomicSDNode>(Node)->getSynchScope());
2872 Results.push_back(Swap.getValue(0));
2873 Results.push_back(Swap.getValue(1));
2876 case ISD::ATOMIC_STORE: {
2877 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2878 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2879 cast<AtomicSDNode>(Node)->getMemoryVT(),
2880 Node->getOperand(0),
2881 Node->getOperand(1), Node->getOperand(2),
2882 cast<AtomicSDNode>(Node)->getMemOperand(),
2883 cast<AtomicSDNode>(Node)->getOrdering(),
2884 cast<AtomicSDNode>(Node)->getSynchScope());
2885 Results.push_back(Swap.getValue(1));
2888 // By default, atomic intrinsics are marked Legal and lowered. Targets
2889 // which don't support them directly, however, may want libcalls, in which
2890 // case they mark them Expand, and we get here.
2891 case ISD::ATOMIC_SWAP:
2892 case ISD::ATOMIC_LOAD_ADD:
2893 case ISD::ATOMIC_LOAD_SUB:
2894 case ISD::ATOMIC_LOAD_AND:
2895 case ISD::ATOMIC_LOAD_OR:
2896 case ISD::ATOMIC_LOAD_XOR:
2897 case ISD::ATOMIC_LOAD_NAND:
2898 case ISD::ATOMIC_LOAD_MIN:
2899 case ISD::ATOMIC_LOAD_MAX:
2900 case ISD::ATOMIC_LOAD_UMIN:
2901 case ISD::ATOMIC_LOAD_UMAX:
2902 case ISD::ATOMIC_CMP_SWAP: {
2903 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2904 Results.push_back(Tmp.first);
2905 Results.push_back(Tmp.second);
2908 case ISD::DYNAMIC_STACKALLOC:
2909 ExpandDYNAMIC_STACKALLOC(Node, Results);
2911 case ISD::MERGE_VALUES:
2912 for (unsigned i = 0; i < Node->getNumValues(); i++)
2913 Results.push_back(Node->getOperand(i));
2916 EVT VT = Node->getValueType(0);
2918 Results.push_back(DAG.getConstant(0, VT));
2920 assert(VT.isFloatingPoint() && "Unknown value type!");
2921 Results.push_back(DAG.getConstantFP(0, VT));
2926 // If this operation is not supported, lower it to 'abort()' call
2927 TargetLowering::ArgListTy Args;
2929 CallLoweringInfo CLI(Node->getOperand(0),
2930 Type::getVoidTy(*DAG.getContext()),
2931 false, false, false, false, 0, CallingConv::C,
2932 /*isTailCall=*/false,
2933 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2934 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2936 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2938 Results.push_back(CallResult.second);
2943 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2944 Node->getValueType(0), dl);
2945 Results.push_back(Tmp1);
2947 case ISD::FP_EXTEND:
2948 Tmp1 = EmitStackConvert(Node->getOperand(0),
2949 Node->getOperand(0).getValueType(),
2950 Node->getValueType(0), dl);
2951 Results.push_back(Tmp1);
2953 case ISD::SIGN_EXTEND_INREG: {
2954 // NOTE: we could fall back on load/store here too for targets without
2955 // SAR. However, it is doubtful that any exist.
2956 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2957 EVT VT = Node->getValueType(0);
2958 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2961 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2962 ExtraVT.getScalarType().getSizeInBits();
2963 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2964 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2965 Node->getOperand(0), ShiftCst);
2966 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2967 Results.push_back(Tmp1);
2970 case ISD::FP_ROUND_INREG: {
2971 // The only way we can lower this is to turn it into a TRUNCSTORE,
2972 // EXTLOAD pair, targeting a temporary location (a stack slot).
2974 // NOTE: there is a choice here between constantly creating new stack
2975 // slots and always reusing the same one. We currently always create
2976 // new ones, as reuse may inhibit scheduling.
2977 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2978 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2979 Node->getValueType(0), dl);
2980 Results.push_back(Tmp1);
2983 case ISD::SINT_TO_FP:
2984 case ISD::UINT_TO_FP:
2985 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2986 Node->getOperand(0), Node->getValueType(0), dl);
2987 Results.push_back(Tmp1);
2989 case ISD::FP_TO_UINT: {
2990 SDValue True, False;
2991 EVT VT = Node->getOperand(0).getValueType();
2992 EVT NVT = Node->getValueType(0);
2993 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2994 APInt::getNullValue(VT.getSizeInBits()));
2995 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2996 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2997 Tmp1 = DAG.getConstantFP(apf, VT);
2998 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
2999 Node->getOperand(0),
3001 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3002 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3003 DAG.getNode(ISD::FSUB, dl, VT,
3004 Node->getOperand(0), Tmp1));
3005 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3006 DAG.getConstant(x, NVT));
3007 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3008 Results.push_back(Tmp1);
3012 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3013 EVT VT = Node->getValueType(0);
3014 Tmp1 = Node->getOperand(0);
3015 Tmp2 = Node->getOperand(1);
3016 unsigned Align = Node->getConstantOperandVal(3);
3018 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3019 MachinePointerInfo(V),
3020 false, false, false, 0);
3021 SDValue VAList = VAListLoad;
3023 if (Align > TLI.getMinStackArgumentAlignment()) {
3024 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3026 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3027 DAG.getConstant(Align - 1,
3028 VAList.getValueType()));
3030 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3031 DAG.getConstant(-(int64_t)Align,
3032 VAList.getValueType()));
3035 // Increment the pointer, VAList, to the next vaarg
3036 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3037 DAG.getConstant(TLI.getDataLayout()->
3038 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3039 VAList.getValueType()));
3040 // Store the incremented VAList to the legalized pointer
3041 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3042 MachinePointerInfo(V), false, false, 0);
3043 // Load the actual argument out of the pointer VAList
3044 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3045 false, false, false, 0));
3046 Results.push_back(Results[0].getValue(1));
3050 // This defaults to loading a pointer from the input and storing it to the
3051 // output, returning the chain.
3052 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3053 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3054 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3055 Node->getOperand(2), MachinePointerInfo(VS),
3056 false, false, false, 0);
3057 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3058 MachinePointerInfo(VD), false, false, 0);
3059 Results.push_back(Tmp1);
3062 case ISD::EXTRACT_VECTOR_ELT:
3063 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3064 // This must be an access of the only element. Return it.
3065 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3066 Node->getOperand(0));
3068 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3069 Results.push_back(Tmp1);
3071 case ISD::EXTRACT_SUBVECTOR:
3072 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3074 case ISD::INSERT_SUBVECTOR:
3075 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3077 case ISD::CONCAT_VECTORS: {
3078 Results.push_back(ExpandVectorBuildThroughStack(Node));
3081 case ISD::SCALAR_TO_VECTOR:
3082 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3084 case ISD::INSERT_VECTOR_ELT:
3085 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3086 Node->getOperand(1),
3087 Node->getOperand(2), dl));
3089 case ISD::VECTOR_SHUFFLE: {
3090 SmallVector<int, 32> NewMask;
3091 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3093 EVT VT = Node->getValueType(0);
3094 EVT EltVT = VT.getVectorElementType();
3095 SDValue Op0 = Node->getOperand(0);
3096 SDValue Op1 = Node->getOperand(1);
3097 if (!TLI.isTypeLegal(EltVT)) {
3099 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3101 // BUILD_VECTOR operands are allowed to be wider than the element type.
3102 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
3103 if (NewEltVT.bitsLT(EltVT)) {
3105 // Convert shuffle node.
3106 // If original node was v4i64 and the new EltVT is i32,
3107 // cast operands to v8i32 and re-build the mask.
3109 // Calculate new VT, the size of the new VT should be equal to original.
3110 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3111 VT.getSizeInBits()/NewEltVT.getSizeInBits());
3112 assert(NewVT.bitsEq(VT));
3114 // cast operands to new VT
3115 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3116 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3118 // Convert the shuffle mask
3119 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
3121 // EltVT gets smaller
3124 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3126 for (unsigned fi = 0; fi < factor; ++fi)
3127 NewMask.push_back(Mask[i]);
3130 for (unsigned fi = 0; fi < factor; ++fi)
3131 NewMask.push_back(Mask[i]*factor+fi);
3139 unsigned NumElems = VT.getVectorNumElements();
3140 SmallVector<SDValue, 16> Ops;
3141 for (unsigned i = 0; i != NumElems; ++i) {
3143 Ops.push_back(DAG.getUNDEF(EltVT));
3146 unsigned Idx = Mask[i];
3148 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3150 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3152 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3154 DAG.getConstant(Idx - NumElems,
3155 TLI.getVectorIdxTy())));
3158 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3159 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3160 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3161 Results.push_back(Tmp1);
3164 case ISD::EXTRACT_ELEMENT: {
3165 EVT OpTy = Node->getOperand(0).getValueType();
3166 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3168 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3169 DAG.getConstant(OpTy.getSizeInBits()/2,
3170 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3171 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3174 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3175 Node->getOperand(0));
3177 Results.push_back(Tmp1);
3180 case ISD::STACKSAVE:
3181 // Expand to CopyFromReg if the target set
3182 // StackPointerRegisterToSaveRestore.
3183 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3184 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3185 Node->getValueType(0)));
3186 Results.push_back(Results[0].getValue(1));
3188 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3189 Results.push_back(Node->getOperand(0));
3192 case ISD::STACKRESTORE:
3193 // Expand to CopyToReg if the target set
3194 // StackPointerRegisterToSaveRestore.
3195 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3196 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3197 Node->getOperand(1)));
3199 Results.push_back(Node->getOperand(0));
3202 case ISD::FCOPYSIGN:
3203 Results.push_back(ExpandFCOPYSIGN(Node));
3206 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3207 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3208 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3209 Node->getOperand(0));
3210 Results.push_back(Tmp1);
3213 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3214 EVT VT = Node->getValueType(0);
3215 Tmp1 = Node->getOperand(0);
3216 Tmp2 = DAG.getConstantFP(0.0, VT);
3217 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3218 Tmp1, Tmp2, ISD::SETUGT);
3219 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3220 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3221 Results.push_back(Tmp1);
3225 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3226 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3227 RTLIB::SQRT_PPCF128));
3231 EVT VT = Node->getValueType(0);
3232 bool isSIN = Node->getOpcode() == ISD::FSIN;
3233 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3234 // fcos which share the same operand and both are used.
3235 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3236 canCombineSinCosLibcall(Node, TLI, TM))
3237 && useSinCos(Node)) {
3238 SDVTList VTs = DAG.getVTList(VT, VT);
3239 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3241 Tmp1 = Tmp1.getValue(1);
3242 Results.push_back(Tmp1);
3244 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3245 RTLIB::SIN_F80, RTLIB::SIN_F128,
3246 RTLIB::SIN_PPCF128));
3248 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3249 RTLIB::COS_F80, RTLIB::COS_F128,
3250 RTLIB::COS_PPCF128));
3255 // Expand into sincos libcall.
3256 ExpandSinCosLibCall(Node, Results);
3259 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3260 RTLIB::LOG_F80, RTLIB::LOG_F128,
3261 RTLIB::LOG_PPCF128));
3264 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3265 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3266 RTLIB::LOG2_PPCF128));
3269 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3270 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3271 RTLIB::LOG10_PPCF128));
3274 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3275 RTLIB::EXP_F80, RTLIB::EXP_F128,
3276 RTLIB::EXP_PPCF128));
3279 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3280 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3281 RTLIB::EXP2_PPCF128));
3284 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3285 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3286 RTLIB::TRUNC_PPCF128));
3289 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3290 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3291 RTLIB::FLOOR_PPCF128));
3294 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3295 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3296 RTLIB::CEIL_PPCF128));
3299 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3300 RTLIB::RINT_F80, RTLIB::RINT_F128,
3301 RTLIB::RINT_PPCF128));
3303 case ISD::FNEARBYINT:
3304 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3305 RTLIB::NEARBYINT_F64,
3306 RTLIB::NEARBYINT_F80,
3307 RTLIB::NEARBYINT_F128,
3308 RTLIB::NEARBYINT_PPCF128));
3311 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3315 RTLIB::ROUND_PPCF128));
3318 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3319 RTLIB::POWI_F80, RTLIB::POWI_F128,
3320 RTLIB::POWI_PPCF128));
3323 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3324 RTLIB::POW_F80, RTLIB::POW_F128,
3325 RTLIB::POW_PPCF128));
3328 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3329 RTLIB::DIV_F80, RTLIB::DIV_F128,
3330 RTLIB::DIV_PPCF128));
3333 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3334 RTLIB::REM_F80, RTLIB::REM_F128,
3335 RTLIB::REM_PPCF128));
3338 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3339 RTLIB::FMA_F80, RTLIB::FMA_F128,
3340 RTLIB::FMA_PPCF128));
3342 case ISD::FP16_TO_FP32:
3343 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3345 case ISD::FP32_TO_FP16:
3346 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3348 case ISD::ConstantFP: {
3349 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3350 // Check to see if this FP immediate is already legal.
3351 // If this is a legal constant, turn it into a TargetConstantFP node.
3352 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3353 Results.push_back(ExpandConstantFP(CFP, true));
3357 EVT VT = Node->getValueType(0);
3358 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3359 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3360 "Don't know how to expand this FP subtraction!");
3361 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3362 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3363 Results.push_back(Tmp1);
3367 EVT VT = Node->getValueType(0);
3368 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3369 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3370 "Don't know how to expand this subtraction!");
3371 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3372 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3373 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3374 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3379 EVT VT = Node->getValueType(0);
3380 bool isSigned = Node->getOpcode() == ISD::SREM;
3381 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3382 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3383 Tmp2 = Node->getOperand(0);
3384 Tmp3 = Node->getOperand(1);
3385 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3386 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3387 // If div is legal, it's better to do the normal expansion
3388 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3389 useDivRem(Node, isSigned, false))) {
3390 SDVTList VTs = DAG.getVTList(VT, VT);
3391 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3392 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3394 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3395 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3396 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3397 } else if (isSigned)
3398 Tmp1 = ExpandIntLibCall(Node, true,
3400 RTLIB::SREM_I16, RTLIB::SREM_I32,
3401 RTLIB::SREM_I64, RTLIB::SREM_I128);
3403 Tmp1 = ExpandIntLibCall(Node, false,
3405 RTLIB::UREM_I16, RTLIB::UREM_I32,
3406 RTLIB::UREM_I64, RTLIB::UREM_I128);
3407 Results.push_back(Tmp1);
3412 bool isSigned = Node->getOpcode() == ISD::SDIV;
3413 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3414 EVT VT = Node->getValueType(0);
3415 SDVTList VTs = DAG.getVTList(VT, VT);
3416 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3417 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3418 useDivRem(Node, isSigned, true)))
3419 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3420 Node->getOperand(1));
3422 Tmp1 = ExpandIntLibCall(Node, true,
3424 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3425 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3427 Tmp1 = ExpandIntLibCall(Node, false,
3429 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3430 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3431 Results.push_back(Tmp1);
3436 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3438 EVT VT = Node->getValueType(0);
3439 SDVTList VTs = DAG.getVTList(VT, VT);
3440 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3441 "If this wasn't legal, it shouldn't have been created!");
3442 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3443 Node->getOperand(1));
3444 Results.push_back(Tmp1.getValue(1));
3449 // Expand into divrem libcall
3450 ExpandDivRemLibCall(Node, Results);
3453 EVT VT = Node->getValueType(0);
3454 SDVTList VTs = DAG.getVTList(VT, VT);
3455 // See if multiply or divide can be lowered using two-result operations.
3456 // We just need the low half of the multiply; try both the signed
3457 // and unsigned forms. If the target supports both SMUL_LOHI and
3458 // UMUL_LOHI, form a preference by checking which forms of plain
3459 // MULH it supports.
3460 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3461 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3462 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3463 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3464 unsigned OpToUse = 0;
3465 if (HasSMUL_LOHI && !HasMULHS) {
3466 OpToUse = ISD::SMUL_LOHI;
3467 } else if (HasUMUL_LOHI && !HasMULHU) {
3468 OpToUse = ISD::UMUL_LOHI;
3469 } else if (HasSMUL_LOHI) {
3470 OpToUse = ISD::SMUL_LOHI;
3471 } else if (HasUMUL_LOHI) {
3472 OpToUse = ISD::UMUL_LOHI;
3475 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3476 Node->getOperand(1)));
3479 Tmp1 = ExpandIntLibCall(Node, false,
3481 RTLIB::MUL_I16, RTLIB::MUL_I32,
3482 RTLIB::MUL_I64, RTLIB::MUL_I128);
3483 Results.push_back(Tmp1);
3488 SDValue LHS = Node->getOperand(0);
3489 SDValue RHS = Node->getOperand(1);
3490 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3491 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3493 Results.push_back(Sum);
3494 EVT OType = Node->getValueType(1);
3496 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3498 // LHSSign -> LHS >= 0
3499 // RHSSign -> RHS >= 0
3500 // SumSign -> Sum >= 0
3503 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3505 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3507 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3508 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3509 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3510 Node->getOpcode() == ISD::SADDO ?
3511 ISD::SETEQ : ISD::SETNE);
3513 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3514 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3516 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3517 Results.push_back(Cmp);
3522 SDValue LHS = Node->getOperand(0);
3523 SDValue RHS = Node->getOperand(1);
3524 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3525 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3527 Results.push_back(Sum);
3528 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3529 Node->getOpcode () == ISD::UADDO ?
3530 ISD::SETULT : ISD::SETUGT));
3535 EVT VT = Node->getValueType(0);
3536 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3537 SDValue LHS = Node->getOperand(0);
3538 SDValue RHS = Node->getOperand(1);
3541 static const unsigned Ops[2][3] =
3542 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3543 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3544 bool isSigned = Node->getOpcode() == ISD::SMULO;
3545 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3546 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3547 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3548 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3549 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3551 TopHalf = BottomHalf.getValue(1);
3552 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3553 VT.getSizeInBits() * 2))) {
3554 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3555 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3556 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3557 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3558 DAG.getIntPtrConstant(0));
3559 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3560 DAG.getIntPtrConstant(1));
3562 // We can fall back to a libcall with an illegal type for the MUL if we
3563 // have a libcall big enough.
3564 // Also, we can fall back to a division in some cases, but that's a big
3565 // performance hit in the general case.
3566 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3567 if (WideVT == MVT::i16)
3568 LC = RTLIB::MUL_I16;
3569 else if (WideVT == MVT::i32)
3570 LC = RTLIB::MUL_I32;
3571 else if (WideVT == MVT::i64)
3572 LC = RTLIB::MUL_I64;
3573 else if (WideVT == MVT::i128)
3574 LC = RTLIB::MUL_I128;
3575 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3577 // The high part is obtained by SRA'ing all but one of the bits of low
3579 unsigned LoSize = VT.getSizeInBits();
3580 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3581 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3582 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3583 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3585 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3586 // pre-lowered to the correct types. This all depends upon WideVT not
3587 // being a legal type for the architecture and thus has to be split to
3589 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3590 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3591 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3592 DAG.getIntPtrConstant(0));
3593 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3594 DAG.getIntPtrConstant(1));
3595 // Ret is a node with an illegal type. Because such things are not
3596 // generally permitted during this phase of legalization, delete the
3597 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3598 DAG.DeleteNode(Ret.getNode());
3602 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3603 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3604 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3605 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3608 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3609 DAG.getConstant(0, VT), ISD::SETNE);
3611 Results.push_back(BottomHalf);
3612 Results.push_back(TopHalf);
3615 case ISD::BUILD_PAIR: {
3616 EVT PairTy = Node->getValueType(0);
3617 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3618 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3619 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3620 DAG.getConstant(PairTy.getSizeInBits()/2,
3621 TLI.getShiftAmountTy(PairTy)));
3622 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3626 Tmp1 = Node->getOperand(0);
3627 Tmp2 = Node->getOperand(1);
3628 Tmp3 = Node->getOperand(2);
3629 if (Tmp1.getOpcode() == ISD::SETCC) {
3630 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3632 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3634 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3635 DAG.getConstant(0, Tmp1.getValueType()),
3636 Tmp2, Tmp3, ISD::SETNE);
3638 Results.push_back(Tmp1);
3641 SDValue Chain = Node->getOperand(0);
3642 SDValue Table = Node->getOperand(1);
3643 SDValue Index = Node->getOperand(2);
3645 EVT PTy = TLI.getPointerTy();
3647 const DataLayout &TD = *TLI.getDataLayout();
3648 unsigned EntrySize =
3649 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3651 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3652 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3653 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3656 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3657 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3658 MachinePointerInfo::getJumpTable(), MemVT,
3661 if (TM.getRelocationModel() == Reloc::PIC_) {
3662 // For PIC, the sequence is:
3663 // BRIND(load(Jumptable + index) + RelocBase)
3664 // RelocBase can be JumpTable, GOT or some sort of global base.
3665 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3666 TLI.getPICJumpTableRelocBase(Table, DAG));
3668 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3669 Results.push_back(Tmp1);
3673 // Expand brcond's setcc into its constituent parts and create a BR_CC
3675 Tmp1 = Node->getOperand(0);
3676 Tmp2 = Node->getOperand(1);
3677 if (Tmp2.getOpcode() == ISD::SETCC) {
3678 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3679 Tmp1, Tmp2.getOperand(2),
3680 Tmp2.getOperand(0), Tmp2.getOperand(1),
3681 Node->getOperand(2));
3683 // We test only the i1 bit. Skip the AND if UNDEF.
3684 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3685 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3686 DAG.getConstant(1, Tmp2.getValueType()));
3687 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3688 DAG.getCondCode(ISD::SETNE), Tmp3,
3689 DAG.getConstant(0, Tmp3.getValueType()),
3690 Node->getOperand(2));
3692 Results.push_back(Tmp1);
3695 Tmp1 = Node->getOperand(0);
3696 Tmp2 = Node->getOperand(1);
3697 Tmp3 = Node->getOperand(2);
3698 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3699 Tmp3, NeedInvert, dl);
3702 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3703 // condition code, create a new SETCC node.
3705 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3708 // If we expanded the SETCC by inverting the condition code, then wrap
3709 // the existing SETCC in a NOT to restore the intended condition.
3711 Tmp1 = DAG.getNOT(dl, Tmp1, Tmp1->getValueType(0));
3713 Results.push_back(Tmp1);
3717 // Otherwise, SETCC for the given comparison type must be completely
3718 // illegal; expand it into a SELECT_CC.
3719 EVT VT = Node->getValueType(0);
3721 switch (TLI.getBooleanContents(VT.isVector())) {
3722 case TargetLowering::ZeroOrOneBooleanContent:
3723 case TargetLowering::UndefinedBooleanContent:
3726 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3730 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3731 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3733 Results.push_back(Tmp1);
3736 case ISD::SELECT_CC: {
3737 Tmp1 = Node->getOperand(0); // LHS
3738 Tmp2 = Node->getOperand(1); // RHS
3739 Tmp3 = Node->getOperand(2); // True
3740 Tmp4 = Node->getOperand(3); // False
3741 SDValue CC = Node->getOperand(4);
3743 bool Legalized = false;
3744 // Try to legalize by inverting the condition. This is for targets that
3745 // might support an ordered version of a condition, but not the unordered
3746 // version (or vice versa).
3747 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3748 Tmp1.getValueType().isInteger());
3749 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3750 // Use the new condition code and swap true and false
3752 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3754 // If The inverse is not legal, then try to swap the arguments using
3755 // the inverse condition code.
3756 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3757 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3758 // The swapped inverse condition is legal, so swap true and false,
3761 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3766 Legalized = LegalizeSetCCCondCode(
3767 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3770 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3772 // If we expanded the SETCC by inverting the condition code, then swap
3773 // the True/False operands to match.
3775 std::swap(Tmp3, Tmp4);
3777 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3778 // condition code, create a new SELECT_CC node.
3780 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3781 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3783 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3784 CC = DAG.getCondCode(ISD::SETNE);
3785 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3789 Results.push_back(Tmp1);
3793 Tmp1 = Node->getOperand(0); // Chain
3794 Tmp2 = Node->getOperand(2); // LHS
3795 Tmp3 = Node->getOperand(3); // RHS
3796 Tmp4 = Node->getOperand(1); // CC
3798 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3799 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3801 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3803 // If we expanded the SETCC by inverting the condition code, then wrap
3804 // the existing SETCC in a NOT to restore the intended condition.
3806 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3808 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3810 if (Tmp4.getNode()) {
3811 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3812 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3814 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3815 Tmp4 = DAG.getCondCode(ISD::SETNE);
3816 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3817 Tmp3, Node->getOperand(4));
3819 Results.push_back(Tmp1);
3822 case ISD::BUILD_VECTOR:
3823 Results.push_back(ExpandBUILD_VECTOR(Node));
3828 // Scalarize vector SRA/SRL/SHL.
3829 EVT VT = Node->getValueType(0);
3830 assert(VT.isVector() && "Unable to legalize non-vector shift");
3831 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3832 unsigned NumElem = VT.getVectorNumElements();
3834 SmallVector<SDValue, 8> Scalars;
3835 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3836 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3838 Node->getOperand(0), DAG.getConstant(Idx,
3839 TLI.getVectorIdxTy()));
3840 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3842 Node->getOperand(1), DAG.getConstant(Idx,
3843 TLI.getVectorIdxTy()));
3844 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3845 VT.getScalarType(), Ex, Sh));
3848 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3849 &Scalars[0], Scalars.size());
3850 ReplaceNode(SDValue(Node, 0), Result);
3853 case ISD::GLOBAL_OFFSET_TABLE:
3854 case ISD::GlobalAddress:
3855 case ISD::GlobalTLSAddress:
3856 case ISD::ExternalSymbol:
3857 case ISD::ConstantPool:
3858 case ISD::JumpTable:
3859 case ISD::INTRINSIC_W_CHAIN:
3860 case ISD::INTRINSIC_WO_CHAIN:
3861 case ISD::INTRINSIC_VOID:
3862 // FIXME: Custom lowering for these operations shouldn't return null!
3866 // Replace the original node with the legalized result.
3867 if (!Results.empty())
3868 ReplaceNode(Node, Results.data());
3871 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3872 SmallVector<SDValue, 8> Results;
3873 MVT OVT = Node->getSimpleValueType(0);
3874 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3875 Node->getOpcode() == ISD::SINT_TO_FP ||
3876 Node->getOpcode() == ISD::SETCC) {
3877 OVT = Node->getOperand(0).getSimpleValueType();
3879 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3881 SDValue Tmp1, Tmp2, Tmp3;
3882 switch (Node->getOpcode()) {
3884 case ISD::CTTZ_ZERO_UNDEF:
3886 case ISD::CTLZ_ZERO_UNDEF:
3888 // Zero extend the argument.
3889 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3890 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3891 // already the correct result.
3892 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3893 if (Node->getOpcode() == ISD::CTTZ) {
3894 // FIXME: This should set a bit in the zero extended value instead.
3895 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3896 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3898 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
3899 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3900 } else if (Node->getOpcode() == ISD::CTLZ ||
3901 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3902 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3903 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3904 DAG.getConstant(NVT.getSizeInBits() -
3905 OVT.getSizeInBits(), NVT));
3907 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3910 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3911 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3912 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3913 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3914 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3915 Results.push_back(Tmp1);
3918 case ISD::FP_TO_UINT:
3919 case ISD::FP_TO_SINT:
3920 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3921 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3922 Results.push_back(Tmp1);
3924 case ISD::UINT_TO_FP:
3925 case ISD::SINT_TO_FP:
3926 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3927 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3928 Results.push_back(Tmp1);
3931 SDValue Chain = Node->getOperand(0); // Get the chain.
3932 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3935 if (OVT.isVector()) {
3936 TruncOp = ISD::BITCAST;
3938 assert(OVT.isInteger()
3939 && "VAARG promotion is supported only for vectors or integer types");
3940 TruncOp = ISD::TRUNCATE;
3943 // Perform the larger operation, then convert back
3944 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3945 Node->getConstantOperandVal(3));
3946 Chain = Tmp1.getValue(1);
3948 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3950 // Modified the chain result - switch anything that used the old chain to
3952 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3953 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3960 unsigned ExtOp, TruncOp;
3961 if (OVT.isVector()) {
3962 ExtOp = ISD::BITCAST;
3963 TruncOp = ISD::BITCAST;
3965 assert(OVT.isInteger() && "Cannot promote logic operation");
3966 ExtOp = ISD::ANY_EXTEND;
3967 TruncOp = ISD::TRUNCATE;
3969 // Promote each of the values to the new type.
3970 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3971 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3972 // Perform the larger operation, then convert back
3973 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3974 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3978 unsigned ExtOp, TruncOp;
3979 if (Node->getValueType(0).isVector()) {
3980 ExtOp = ISD::BITCAST;
3981 TruncOp = ISD::BITCAST;
3982 } else if (Node->getValueType(0).isInteger()) {
3983 ExtOp = ISD::ANY_EXTEND;
3984 TruncOp = ISD::TRUNCATE;
3986 ExtOp = ISD::FP_EXTEND;
3987 TruncOp = ISD::FP_ROUND;
3989 Tmp1 = Node->getOperand(0);
3990 // Promote each of the values to the new type.
3991 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3992 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3993 // Perform the larger operation, then round down.
3994 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
3995 if (TruncOp != ISD::FP_ROUND)
3996 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3998 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3999 DAG.getIntPtrConstant(0));
4000 Results.push_back(Tmp1);
4003 case ISD::VECTOR_SHUFFLE: {
4004 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4006 // Cast the two input vectors.
4007 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4008 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4010 // Convert the shuffle mask to the right # elements.
4011 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4012 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4013 Results.push_back(Tmp1);
4017 unsigned ExtOp = ISD::FP_EXTEND;
4018 if (NVT.isInteger()) {
4019 ISD::CondCode CCCode =
4020 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4021 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4023 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4024 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4025 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4026 Tmp1, Tmp2, Node->getOperand(2)));
4032 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4033 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4034 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4035 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4036 Tmp3, DAG.getIntPtrConstant(0)));
4043 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4044 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4045 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4046 Tmp2, DAG.getIntPtrConstant(0)));
4051 // Replace the original node with the legalized result.
4052 if (!Results.empty())
4053 ReplaceNode(Node, Results.data());
4056 // SelectionDAG::Legalize - This is the entry point for the file.
4058 void SelectionDAG::Legalize() {
4059 /// run - This is the main entry point to this class.
4061 SelectionDAGLegalize(*this).LegalizeDAG();