1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
59 case ISD::CTLZ_ZERO_UNDEF:
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
62 case ISD::CTTZ_ZERO_UNDEF:
63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
64 case ISD::EXTRACT_VECTOR_ELT:
65 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
80 case ISD::EXTRACT_SUBVECTOR:
81 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
82 case ISD::VECTOR_SHUFFLE:
83 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
84 case ISD::INSERT_VECTOR_ELT:
85 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
86 case ISD::BUILD_VECTOR:
87 Res = PromoteIntRes_BUILD_VECTOR(N); break;
88 case ISD::SCALAR_TO_VECTOR:
89 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
90 case ISD::CONCAT_VECTORS:
91 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
93 case ISD::SIGN_EXTEND:
94 case ISD::ZERO_EXTEND:
95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
122 case ISD::ATOMIC_LOAD:
123 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
125 case ISD::ATOMIC_LOAD_ADD:
126 case ISD::ATOMIC_LOAD_SUB:
127 case ISD::ATOMIC_LOAD_AND:
128 case ISD::ATOMIC_LOAD_OR:
129 case ISD::ATOMIC_LOAD_XOR:
130 case ISD::ATOMIC_LOAD_NAND:
131 case ISD::ATOMIC_LOAD_MIN:
132 case ISD::ATOMIC_LOAD_MAX:
133 case ISD::ATOMIC_LOAD_UMIN:
134 case ISD::ATOMIC_LOAD_UMAX:
135 case ISD::ATOMIC_SWAP:
136 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
138 case ISD::ATOMIC_CMP_SWAP:
139 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
142 // If the result is null then the sub-method took care of registering it.
144 SetPromotedInteger(SDValue(N, ResNo), Res);
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
150 return GetPromotedInteger(Op);
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
154 // Sign-extend the new bits, and continue the assertion.
155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
156 return DAG.getNode(ISD::AssertSext, SDLoc(N),
157 Op.getValueType(), Op, N->getOperand(1));
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
161 // Zero the new bits, and continue the assertion.
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
163 return DAG.getNode(ISD::AssertZext, SDLoc(N),
164 Op.getValueType(), Op, N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
170 N->getMemoryVT(), ResVT,
171 N->getChain(), N->getBasePtr(),
172 N->getMemOperand(), N->getOrdering(),
174 // Legalized the chain result - switch anything that used the old chain to
176 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
182 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
184 N->getChain(), N->getBasePtr(),
185 Op2, N->getMemOperand(), N->getOrdering(),
187 // Legalized the chain result - switch anything that used the old chain to
189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
196 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
197 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
198 Op2, Op3, N->getMemOperand(), N->getOrdering(),
200 // Legalized the chain result - switch anything that used the old chain to
202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
207 SDValue InOp = N->getOperand(0);
208 EVT InVT = InOp.getValueType();
209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
210 EVT OutVT = N->getValueType(0);
211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
214 switch (getTypeAction(InVT)) {
215 case TargetLowering::TypeLegal:
217 case TargetLowering::TypePromoteInteger:
218 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
219 // The input promotes to the same size. Convert the promoted value.
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
222 case TargetLowering::TypeSoftenFloat:
223 // Promote the integer operand by hand.
224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
225 case TargetLowering::TypeExpandInteger:
226 case TargetLowering::TypeExpandFloat:
228 case TargetLowering::TypeScalarizeVector:
229 // Convert the element to an integer and promote it by hand.
230 if (!NOutVT.isVector())
231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
232 BitConvertToInteger(GetScalarizedVector(InOp)));
234 case TargetLowering::TypeSplitVector: {
235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
236 // pieces of the input into integers and reassemble in the final type.
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
240 Hi = BitConvertToInteger(Hi);
242 if (TLI.isBigEndian())
245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
246 EVT::getIntegerVT(*DAG.getContext(),
247 NOutVT.getSizeInBits()),
248 JoinIntegers(Lo, Hi));
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
251 case TargetLowering::TypeWidenVector:
252 // The input is widened to the same size. Convert to the widened value.
253 // Make sure that the outgoing value is not a vector, because this would
254 // make us bitcast between two vectors which are legalized in different ways.
255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260 CreateStackStoreLoad(InOp, OutVT));
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
264 SDValue Op = GetPromotedInteger(N->getOperand(0));
265 EVT OVT = N->getValueType(0);
266 EVT NVT = Op.getValueType();
269 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
271 DAG.getConstant(DiffBits, TLI.getPointerTy()));
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
275 // The pair element type may be legal, or may not promote to the same type as
276 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
277 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
278 TLI.getTypeToTransformTo(*DAG.getContext(),
279 N->getValueType(0)), JoinIntegers(N->getOperand(0),
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
284 EVT VT = N->getValueType(0);
285 // FIXME there is no actual debug info here
287 // Zero extend things like i1, sign extend everything else. It shouldn't
288 // matter in theory which one we pick, but this tends to give better code?
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
290 SDValue Result = DAG.getNode(Opc, dl,
291 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
293 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
298 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
299 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
300 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
301 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
302 "can only promote integers");
303 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
305 N->getOperand(1), N->getOperand(2),
306 N->getOperand(3), N->getOperand(4), CvtCode);
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
310 // Zero extend to the promoted type and do the count there.
311 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
313 EVT OVT = N->getValueType(0);
314 EVT NVT = Op.getValueType();
315 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
316 // Subtract off the extra leading bits in the bigger type.
317 return DAG.getNode(ISD::SUB, dl, NVT, Op,
318 DAG.getConstant(NVT.getSizeInBits() -
319 OVT.getSizeInBits(), NVT));
322 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
323 // Zero extend to the promoted type and do the count there.
324 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
325 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
328 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
329 SDValue Op = GetPromotedInteger(N->getOperand(0));
330 EVT OVT = N->getValueType(0);
331 EVT NVT = Op.getValueType();
333 if (N->getOpcode() == ISD::CTTZ) {
334 // The count is the same in the promoted type except if the original
335 // value was zero. This can be handled by setting the bit just off
336 // the top of the original type.
337 APInt TopBit(NVT.getSizeInBits(), 0);
338 TopBit.setBit(OVT.getSizeInBits());
339 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
341 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
344 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
346 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
351 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
352 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
353 unsigned NewOpc = N->getOpcode();
356 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
358 // and SINT conversions are Custom, there is no way to tell which is
359 // preferable. We choose SINT because that's the right thing on PPC.)
360 if (N->getOpcode() == ISD::FP_TO_UINT &&
361 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
367 // Assert that the converted value fits in the original type. If it doesn't
368 // (eg: because the value being converted is too big), then the result of the
369 // original operation was undefined anyway, so the assert is still correct.
370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
372 DAG.getValueType(N->getValueType(0).getScalarType()));
375 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
376 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
379 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
381 return DAG.getNode(ISD::AssertZext, dl,
382 NVT, Res, DAG.getValueType(N->getValueType(0)));
385 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
389 if (getTypeAction(N->getOperand(0).getValueType())
390 == TargetLowering::TypePromoteInteger) {
391 SDValue Res = GetPromotedInteger(N->getOperand(0));
392 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
394 // If the result and operand types are the same after promotion, simplify
395 // to an in-register extension.
396 if (NVT == Res.getValueType()) {
397 // The high bits are not guaranteed to be anything. Insert an extend.
398 if (N->getOpcode() == ISD::SIGN_EXTEND)
399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
400 DAG.getValueType(N->getOperand(0).getValueType()));
401 if (N->getOpcode() == ISD::ZERO_EXTEND)
402 return DAG.getZeroExtendInReg(Res, dl,
403 N->getOperand(0).getValueType().getScalarType());
404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
409 // Otherwise, just extend the original operand all the way to the larger type.
410 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
413 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
416 ISD::LoadExtType ExtType =
417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
419 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
420 N->getMemoryVT(), N->getMemOperand());
422 // Legalized the chain result - switch anything that used the old chain to
424 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
428 /// Promote the overflow flag of an overflowing arithmetic node.
429 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
430 // Simply change the return type of the boolean result.
431 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
432 EVT ValueVTs[] = { N->getValueType(0), NVT };
433 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
434 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
435 DAG.getVTList(ValueVTs, 2), Ops, 2);
437 // Modified the sum result - switch anything that used the old sum to use
439 ReplaceValueWith(SDValue(N, 0), Res);
441 return SDValue(Res.getNode(), 1);
444 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
446 return PromoteIntRes_Overflow(N);
448 // The operation overflowed iff the result in the larger type is not the
449 // sign extension of its truncation to the original type.
450 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
451 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
452 EVT OVT = N->getOperand(0).getValueType();
453 EVT NVT = LHS.getValueType();
456 // Do the arithmetic in the larger type.
457 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
458 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
460 // Calculate the overflow flag: sign extend the arithmetic result from
461 // the original type.
462 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
463 DAG.getValueType(OVT));
464 // Overflowed if and only if this is not equal to Res.
465 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
467 // Use the calculated overflow everywhere.
468 ReplaceValueWith(SDValue(N, 1), Ofl);
473 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
474 // Sign extend the input.
475 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
476 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
477 return DAG.getNode(N->getOpcode(), SDLoc(N),
478 LHS.getValueType(), LHS, RHS);
481 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
482 SDValue LHS = GetPromotedInteger(N->getOperand(1));
483 SDValue RHS = GetPromotedInteger(N->getOperand(2));
484 return DAG.getSelect(SDLoc(N),
485 LHS.getValueType(), N->getOperand(0), LHS, RHS);
488 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
489 SDValue Mask = N->getOperand(0);
490 EVT OpTy = N->getOperand(1).getValueType();
492 // Promote all the way up to the canonical SetCC type.
493 Mask = PromoteTargetBoolean(Mask, getSetCCResultType(OpTy));
494 SDValue LHS = GetPromotedInteger(N->getOperand(1));
495 SDValue RHS = GetPromotedInteger(N->getOperand(2));
496 return DAG.getNode(ISD::VSELECT, SDLoc(N),
497 LHS.getValueType(), Mask, LHS, RHS);
500 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
501 SDValue LHS = GetPromotedInteger(N->getOperand(2));
502 SDValue RHS = GetPromotedInteger(N->getOperand(3));
503 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
504 LHS.getValueType(), N->getOperand(0),
505 N->getOperand(1), LHS, RHS, N->getOperand(4));
508 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
509 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
511 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
513 // Only use the result of getSetCCResultType if it is legal,
514 // otherwise just use the promoted result type (NVT).
515 if (!TLI.isTypeLegal(SVT))
519 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
520 "Vector compare must return a vector result!");
522 SDValue LHS = N->getOperand(0);
523 SDValue RHS = N->getOperand(1);
524 if (LHS.getValueType() != RHS.getValueType()) {
525 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
526 !LHS.getValueType().isVector())
527 LHS = GetPromotedInteger(LHS);
528 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
529 !RHS.getValueType().isVector())
530 RHS = GetPromotedInteger(RHS);
533 // Get the SETCC result using the canonical SETCC type.
534 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
537 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
538 // Convert to the expected type.
539 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
542 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
543 SDValue Res = GetPromotedInteger(N->getOperand(0));
544 SDValue Amt = N->getOperand(1);
545 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
546 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
549 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
550 SDValue Op = GetPromotedInteger(N->getOperand(0));
551 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
552 Op.getValueType(), Op, N->getOperand(1));
555 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
556 // The input may have strange things in the top bits of the registers, but
557 // these operations don't care. They may have weird bits going out, but
558 // that too is okay if they are integer operations.
559 SDValue LHS = GetPromotedInteger(N->getOperand(0));
560 SDValue RHS = GetPromotedInteger(N->getOperand(1));
561 return DAG.getNode(N->getOpcode(), SDLoc(N),
562 LHS.getValueType(), LHS, RHS);
565 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
566 // The input value must be properly sign extended.
567 SDValue Res = SExtPromotedInteger(N->getOperand(0));
568 SDValue Amt = N->getOperand(1);
569 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
570 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
573 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
574 // The input value must be properly zero extended.
575 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
576 SDValue Amt = N->getOperand(1);
577 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
578 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
581 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
582 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
584 SDValue InOp = N->getOperand(0);
587 switch (getTypeAction(InOp.getValueType())) {
588 default: llvm_unreachable("Unknown type action!");
589 case TargetLowering::TypeLegal:
590 case TargetLowering::TypeExpandInteger:
593 case TargetLowering::TypePromoteInteger:
594 Res = GetPromotedInteger(InOp);
596 case TargetLowering::TypeSplitVector:
597 EVT InVT = InOp.getValueType();
598 assert(InVT.isVector() && "Cannot split scalar types");
599 unsigned NumElts = InVT.getVectorNumElements();
600 assert(NumElts == NVT.getVectorNumElements() &&
601 "Dst and Src must have the same number of elements");
602 assert(isPowerOf2_32(NumElts) &&
603 "Promoted vector type must be a power of two");
606 GetSplitVector(InOp, EOp1, EOp2);
608 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
610 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
611 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
613 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
616 // Truncate to NVT instead of VT
617 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
620 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
622 return PromoteIntRes_Overflow(N);
624 // The operation overflowed iff the result in the larger type is not the
625 // zero extension of its truncation to the original type.
626 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
627 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
628 EVT OVT = N->getOperand(0).getValueType();
629 EVT NVT = LHS.getValueType();
632 // Do the arithmetic in the larger type.
633 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
634 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
636 // Calculate the overflow flag: zero extend the arithmetic result from
637 // the original type.
638 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
639 // Overflowed if and only if this is not equal to Res.
640 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
642 // Use the calculated overflow everywhere.
643 ReplaceValueWith(SDValue(N, 1), Ofl);
648 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
649 // Promote the overflow bit trivially.
651 return PromoteIntRes_Overflow(N);
653 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
655 EVT SmallVT = LHS.getValueType();
657 // To determine if the result overflowed in a larger type, we extend the
658 // input to the larger type, do the multiply (checking if it overflows),
659 // then also check the high bits of the result to see if overflow happened
661 if (N->getOpcode() == ISD::SMULO) {
662 LHS = SExtPromotedInteger(LHS);
663 RHS = SExtPromotedInteger(RHS);
665 LHS = ZExtPromotedInteger(LHS);
666 RHS = ZExtPromotedInteger(RHS);
668 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
669 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
671 // Overflow occurred if it occurred in the larger type, or if the high part
672 // of the result does not zero/sign-extend the low part. Check this second
673 // possibility first.
675 if (N->getOpcode() == ISD::UMULO) {
676 // Unsigned overflow occurred if the high part is non-zero.
677 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
678 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
679 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
680 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
682 // Signed overflow occurred if the high part does not sign extend the low.
683 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
684 Mul, DAG.getValueType(SmallVT));
685 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
688 // The only other way for overflow to occur is if the multiplication in the
689 // larger type itself overflowed.
690 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
691 SDValue(Mul.getNode(), 1));
693 // Use the calculated overflow everywhere.
694 ReplaceValueWith(SDValue(N, 1), Overflow);
698 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
699 // Zero extend the input.
700 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
701 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
702 return DAG.getNode(N->getOpcode(), SDLoc(N),
703 LHS.getValueType(), LHS, RHS);
706 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
707 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
708 N->getValueType(0)));
711 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
712 SDValue Chain = N->getOperand(0); // Get the chain.
713 SDValue Ptr = N->getOperand(1); // Get the pointer.
714 EVT VT = N->getValueType(0);
717 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
718 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
719 // The argument is passed as NumRegs registers of type RegVT.
721 SmallVector<SDValue, 8> Parts(NumRegs);
722 for (unsigned i = 0; i < NumRegs; ++i) {
723 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
724 N->getConstantOperandVal(3));
725 Chain = Parts[i].getValue(1);
728 // Handle endianness of the load.
729 if (TLI.isBigEndian())
730 std::reverse(Parts.begin(), Parts.end());
732 // Assemble the parts in the promoted type.
733 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
734 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
735 for (unsigned i = 1; i < NumRegs; ++i) {
736 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
737 // Shift it to the right position and "or" it in.
738 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
739 DAG.getConstant(i * RegVT.getSizeInBits(),
740 TLI.getPointerTy()));
741 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
744 // Modified the chain result - switch anything that used the old chain to
746 ReplaceValueWith(SDValue(N, 1), Chain);
751 //===----------------------------------------------------------------------===//
752 // Integer Operand Promotion
753 //===----------------------------------------------------------------------===//
755 /// PromoteIntegerOperand - This method is called when the specified operand of
756 /// the specified node is found to need promotion. At this point, all of the
757 /// result types of the node are known to be legal, but other operands of the
758 /// node may need promotion or expansion as well as the specified one.
759 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
760 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
761 SDValue Res = SDValue();
763 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
766 switch (N->getOpcode()) {
769 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
770 N->dump(&DAG); dbgs() << "\n";
772 llvm_unreachable("Do not know how to promote this operator's operand!");
774 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
775 case ISD::ATOMIC_STORE:
776 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
778 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
779 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
780 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
781 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
782 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
783 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
784 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
785 case ISD::CONVERT_RNDSAT:
786 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
787 case ISD::INSERT_VECTOR_ELT:
788 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
789 case ISD::SCALAR_TO_VECTOR:
790 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
792 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
793 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
794 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
795 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
796 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
797 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
799 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
800 case ISD::FP16_TO_FP32:
801 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
802 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
808 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
811 // If the result is null, the sub-method took care of registering results etc.
812 if (!Res.getNode()) return false;
814 // If the result is N, the sub-method updated N in place. Tell the legalizer
816 if (Res.getNode() == N)
819 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
820 "Invalid operand expansion");
822 ReplaceValueWith(SDValue(N, 0), Res);
826 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
827 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
828 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
829 ISD::CondCode CCCode) {
830 // We have to insert explicit sign or zero extends. Note that we could
831 // insert sign extends for ALL conditions, but zero extend is cheaper on
832 // many machines (an AND instead of two shifts), so prefer it.
834 default: llvm_unreachable("Unknown integer comparison!");
841 // ALL of these operations will work if we either sign or zero extend
842 // the operands (including the unsigned comparisons!). Zero extend is
843 // usually a simpler/cheaper operation, so prefer it.
844 NewLHS = ZExtPromotedInteger(NewLHS);
845 NewRHS = ZExtPromotedInteger(NewRHS);
851 NewLHS = SExtPromotedInteger(NewLHS);
852 NewRHS = SExtPromotedInteger(NewRHS);
857 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
858 SDValue Op = GetPromotedInteger(N->getOperand(0));
859 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
862 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
863 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
864 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
865 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
866 N->getOrdering(), N->getSynchScope());
869 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
870 // This should only occur in unusual situations like bitcasting to an
871 // x86_fp80, so just turn it into a store+load
872 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
875 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
876 assert(OpNo == 2 && "Don't know how to promote this operand!");
878 SDValue LHS = N->getOperand(2);
879 SDValue RHS = N->getOperand(3);
880 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
882 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
884 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
885 N->getOperand(1), LHS, RHS, N->getOperand(4)),
889 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
890 assert(OpNo == 1 && "only know how to promote condition");
892 // Promote all the way up to the canonical SetCC type.
893 EVT SVT = getSetCCResultType(MVT::Other);
894 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
896 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
897 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
898 N->getOperand(2)), 0);
901 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
902 // Since the result type is legal, the operands must promote to it.
903 EVT OVT = N->getOperand(0).getValueType();
904 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
905 SDValue Hi = GetPromotedInteger(N->getOperand(1));
906 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
909 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
910 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
911 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
914 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
915 // The vector type is legal but the element type is not. This implies
916 // that the vector is a power-of-two in length and that the element
917 // type does not have a strange size (eg: it is not i1).
918 EVT VecVT = N->getValueType(0);
919 unsigned NumElts = VecVT.getVectorNumElements();
920 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
921 "Legal vector of one illegal element?");
923 // Promote the inserted value. The type does not need to match the
924 // vector element type. Check that any extra bits introduced will be
926 assert(N->getOperand(0).getValueType().getSizeInBits() >=
927 N->getValueType(0).getVectorElementType().getSizeInBits() &&
928 "Type of inserted value narrower than vector element type!");
930 SmallVector<SDValue, 16> NewOps;
931 for (unsigned i = 0; i < NumElts; ++i)
932 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
934 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
937 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
938 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
939 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
940 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
941 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
942 "can only promote integer arguments");
943 SDValue InOp = GetPromotedInteger(N->getOperand(0));
944 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
945 N->getOperand(1), N->getOperand(2),
946 N->getOperand(3), N->getOperand(4), CvtCode);
949 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
952 // Promote the inserted value. This is valid because the type does not
953 // have to match the vector element type.
955 // Check that any extra bits introduced will be truncated away.
956 assert(N->getOperand(1).getValueType().getSizeInBits() >=
957 N->getValueType(0).getVectorElementType().getSizeInBits() &&
958 "Type of inserted value narrower than vector element type!");
959 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
960 GetPromotedInteger(N->getOperand(1)),
965 assert(OpNo == 2 && "Different operand and result vector types?");
967 // Promote the index.
968 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
969 TLI.getVectorIdxTy());
970 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
971 N->getOperand(1), Idx), 0);
974 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
975 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
976 // the operand in place.
977 return SDValue(DAG.UpdateNodeOperands(N,
978 GetPromotedInteger(N->getOperand(0))), 0);
981 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
982 assert(OpNo == 0 && "Only know how to promote the condition!");
983 SDValue Cond = N->getOperand(0);
984 EVT OpTy = N->getOperand(1).getValueType();
986 // Promote all the way up to the canonical SetCC type.
987 EVT SVT = getSetCCResultType(N->getOpcode() == ISD::SELECT ?
988 OpTy.getScalarType() : OpTy);
989 Cond = PromoteTargetBoolean(Cond, SVT);
991 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
992 N->getOperand(2)), 0);
995 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
996 assert(OpNo == 0 && "Don't know how to promote this operand!");
998 SDValue LHS = N->getOperand(0);
999 SDValue RHS = N->getOperand(1);
1000 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1002 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1003 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1004 N->getOperand(3), N->getOperand(4)), 0);
1007 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1008 assert(OpNo == 0 && "Don't know how to promote this operand!");
1010 SDValue LHS = N->getOperand(0);
1011 SDValue RHS = N->getOperand(1);
1012 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1014 // The CC (#2) is always legal.
1015 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1018 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1019 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1020 ZExtPromotedInteger(N->getOperand(1))), 0);
1023 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1024 SDValue Op = GetPromotedInteger(N->getOperand(0));
1026 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1027 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1028 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1031 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1032 return SDValue(DAG.UpdateNodeOperands(N,
1033 SExtPromotedInteger(N->getOperand(0))), 0);
1036 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1037 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1038 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1041 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1043 // Truncate the value and store the result.
1044 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1045 N->getMemoryVT(), N->getMemOperand());
1048 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1049 SDValue Op = GetPromotedInteger(N->getOperand(0));
1050 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1053 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1054 return SDValue(DAG.UpdateNodeOperands(N,
1055 ZExtPromotedInteger(N->getOperand(0))), 0);
1058 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1060 SDValue Op = GetPromotedInteger(N->getOperand(0));
1061 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1062 return DAG.getZeroExtendInReg(Op, dl,
1063 N->getOperand(0).getValueType().getScalarType());
1067 //===----------------------------------------------------------------------===//
1068 // Integer Result Expansion
1069 //===----------------------------------------------------------------------===//
1071 /// ExpandIntegerResult - This method is called when the specified result of the
1072 /// specified node is found to need expansion. At this point, the node may also
1073 /// have invalid operands or may have other results that need promotion, we just
1074 /// know that (at least) one result needs expansion.
1075 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1076 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1078 Lo = Hi = SDValue();
1080 // See if the target wants to custom expand this node.
1081 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1084 switch (N->getOpcode()) {
1087 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1088 N->dump(&DAG); dbgs() << "\n";
1090 llvm_unreachable("Do not know how to expand the result of this operator!");
1092 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1093 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1094 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1095 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1097 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1098 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1099 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1100 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1101 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1103 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1104 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1105 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1106 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1107 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1108 case ISD::CTLZ_ZERO_UNDEF:
1109 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1110 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1111 case ISD::CTTZ_ZERO_UNDEF:
1112 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1113 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1114 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1115 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1116 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1117 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1118 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1119 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1120 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1121 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1122 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1123 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1124 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1125 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1127 case ISD::ATOMIC_LOAD_ADD:
1128 case ISD::ATOMIC_LOAD_SUB:
1129 case ISD::ATOMIC_LOAD_AND:
1130 case ISD::ATOMIC_LOAD_OR:
1131 case ISD::ATOMIC_LOAD_XOR:
1132 case ISD::ATOMIC_LOAD_NAND:
1133 case ISD::ATOMIC_LOAD_MIN:
1134 case ISD::ATOMIC_LOAD_MAX:
1135 case ISD::ATOMIC_LOAD_UMIN:
1136 case ISD::ATOMIC_LOAD_UMAX:
1137 case ISD::ATOMIC_SWAP:
1138 case ISD::ATOMIC_CMP_SWAP: {
1139 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1140 SplitInteger(Tmp.first, Lo, Hi);
1141 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1147 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1150 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1153 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1156 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1160 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1163 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1165 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1167 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1170 // If Lo/Hi is null, the sub-method took care of registering results etc.
1172 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1175 /// Lower an atomic node to the appropriate builtin call.
1176 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1177 unsigned Opc = Node->getOpcode();
1178 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1183 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1184 case ISD::ATOMIC_SWAP:
1185 switch (VT.SimpleTy) {
1186 default: llvm_unreachable("Unexpected value type for atomic!");
1187 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1188 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1189 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1190 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1191 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
1194 case ISD::ATOMIC_CMP_SWAP:
1195 switch (VT.SimpleTy) {
1196 default: llvm_unreachable("Unexpected value type for atomic!");
1197 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1198 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1199 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1200 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1201 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
1204 case ISD::ATOMIC_LOAD_ADD:
1205 switch (VT.SimpleTy) {
1206 default: llvm_unreachable("Unexpected value type for atomic!");
1207 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1208 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1209 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1210 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1211 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
1214 case ISD::ATOMIC_LOAD_SUB:
1215 switch (VT.SimpleTy) {
1216 default: llvm_unreachable("Unexpected value type for atomic!");
1217 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1218 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1219 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1220 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1221 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
1224 case ISD::ATOMIC_LOAD_AND:
1225 switch (VT.SimpleTy) {
1226 default: llvm_unreachable("Unexpected value type for atomic!");
1227 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1228 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1229 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1230 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1231 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
1234 case ISD::ATOMIC_LOAD_OR:
1235 switch (VT.SimpleTy) {
1236 default: llvm_unreachable("Unexpected value type for atomic!");
1237 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1238 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1239 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1240 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1241 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
1244 case ISD::ATOMIC_LOAD_XOR:
1245 switch (VT.SimpleTy) {
1246 default: llvm_unreachable("Unexpected value type for atomic!");
1247 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1248 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1249 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1250 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1251 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
1254 case ISD::ATOMIC_LOAD_NAND:
1255 switch (VT.SimpleTy) {
1256 default: llvm_unreachable("Unexpected value type for atomic!");
1257 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1258 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1259 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1260 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1261 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
1266 return ExpandChainLibCall(LC, Node, false);
1269 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1270 /// and the shift amount is a constant 'Amt'. Expand the operation.
1271 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1272 SDValue &Lo, SDValue &Hi) {
1274 // Expand the incoming operand to be shifted, so that we have its parts
1276 GetExpandedInteger(N->getOperand(0), InL, InH);
1278 EVT NVT = InL.getValueType();
1279 unsigned VTBits = N->getValueType(0).getSizeInBits();
1280 unsigned NVTBits = NVT.getSizeInBits();
1281 EVT ShTy = N->getOperand(1).getValueType();
1283 if (N->getOpcode() == ISD::SHL) {
1285 Lo = Hi = DAG.getConstant(0, NVT);
1286 } else if (Amt > NVTBits) {
1287 Lo = DAG.getConstant(0, NVT);
1288 Hi = DAG.getNode(ISD::SHL, DL,
1289 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1290 } else if (Amt == NVTBits) {
1291 Lo = DAG.getConstant(0, NVT);
1293 } else if (Amt == 1 &&
1294 TLI.isOperationLegalOrCustom(ISD::ADDC,
1295 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1296 // Emit this X << 1 as X+X.
1297 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1298 SDValue LoOps[2] = { InL, InL };
1299 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1300 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1301 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1303 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1304 Hi = DAG.getNode(ISD::OR, DL, NVT,
1305 DAG.getNode(ISD::SHL, DL, NVT, InH,
1306 DAG.getConstant(Amt, ShTy)),
1307 DAG.getNode(ISD::SRL, DL, NVT, InL,
1308 DAG.getConstant(NVTBits-Amt, ShTy)));
1313 if (N->getOpcode() == ISD::SRL) {
1315 Lo = DAG.getConstant(0, NVT);
1316 Hi = DAG.getConstant(0, NVT);
1317 } else if (Amt > NVTBits) {
1318 Lo = DAG.getNode(ISD::SRL, DL,
1319 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1320 Hi = DAG.getConstant(0, NVT);
1321 } else if (Amt == NVTBits) {
1323 Hi = DAG.getConstant(0, NVT);
1325 Lo = DAG.getNode(ISD::OR, DL, NVT,
1326 DAG.getNode(ISD::SRL, DL, NVT, InL,
1327 DAG.getConstant(Amt, ShTy)),
1328 DAG.getNode(ISD::SHL, DL, NVT, InH,
1329 DAG.getConstant(NVTBits-Amt, ShTy)));
1330 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1335 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1337 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1338 DAG.getConstant(NVTBits-1, ShTy));
1339 } else if (Amt > NVTBits) {
1340 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1341 DAG.getConstant(Amt-NVTBits, ShTy));
1342 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1343 DAG.getConstant(NVTBits-1, ShTy));
1344 } else if (Amt == NVTBits) {
1346 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1347 DAG.getConstant(NVTBits-1, ShTy));
1349 Lo = DAG.getNode(ISD::OR, DL, NVT,
1350 DAG.getNode(ISD::SRL, DL, NVT, InL,
1351 DAG.getConstant(Amt, ShTy)),
1352 DAG.getNode(ISD::SHL, DL, NVT, InH,
1353 DAG.getConstant(NVTBits-Amt, ShTy)));
1354 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1358 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1359 /// this shift based on knowledge of the high bit of the shift amount. If we
1360 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1362 bool DAGTypeLegalizer::
1363 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1364 SDValue Amt = N->getOperand(1);
1365 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1366 EVT ShTy = Amt.getValueType();
1367 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1368 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1369 assert(isPowerOf2_32(NVTBits) &&
1370 "Expanded integer type size not a power of two!");
1373 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1374 APInt KnownZero, KnownOne;
1375 DAG.ComputeMaskedBits(N->getOperand(1), KnownZero, KnownOne);
1377 // If we don't know anything about the high bits, exit.
1378 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1381 // Get the incoming operand to be shifted.
1383 GetExpandedInteger(N->getOperand(0), InL, InH);
1385 // If we know that any of the high bits of the shift amount are one, then we
1386 // can do this as a couple of simple shifts.
1387 if (KnownOne.intersects(HighBitMask)) {
1388 // Mask out the high bit, which we know is set.
1389 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1390 DAG.getConstant(~HighBitMask, ShTy));
1392 switch (N->getOpcode()) {
1393 default: llvm_unreachable("Unknown shift");
1395 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1396 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1399 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1400 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1403 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1404 DAG.getConstant(NVTBits-1, ShTy));
1405 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1410 // If we know that all of the high bits of the shift amount are zero, then we
1411 // can do this as a couple of simple shifts.
1412 if ((KnownZero & HighBitMask) == HighBitMask) {
1413 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1414 // shift if x is zero. We can use XOR here because x is known to be smaller
1416 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1417 DAG.getConstant(NVTBits-1, ShTy));
1420 switch (N->getOpcode()) {
1421 default: llvm_unreachable("Unknown shift");
1422 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1424 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1427 // When shifting right the arithmetic for Lo and Hi is swapped.
1428 if (N->getOpcode() != ISD::SHL)
1429 std::swap(InL, InH);
1431 // Use a little trick to get the bits that move from Lo to Hi. First
1432 // shift by one bit.
1433 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1434 // Then compute the remaining shift with amount-1.
1435 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1437 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1438 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1440 if (N->getOpcode() != ISD::SHL)
1448 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1450 bool DAGTypeLegalizer::
1451 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1452 SDValue Amt = N->getOperand(1);
1453 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1454 EVT ShTy = Amt.getValueType();
1455 unsigned NVTBits = NVT.getSizeInBits();
1456 assert(isPowerOf2_32(NVTBits) &&
1457 "Expanded integer type size not a power of two!");
1460 // Get the incoming operand to be shifted.
1462 GetExpandedInteger(N->getOperand(0), InL, InH);
1464 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1465 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1466 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1467 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1468 Amt, NVBitsNode, ISD::SETULT);
1470 SDValue LoS, HiS, LoL, HiL;
1471 switch (N->getOpcode()) {
1472 default: llvm_unreachable("Unknown shift");
1474 // Short: ShAmt < NVTBits
1475 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1476 HiS = DAG.getNode(ISD::OR, dl, NVT,
1477 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1478 // FIXME: If Amt is zero, the following shift generates an undefined result
1479 // on some architectures.
1480 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1482 // Long: ShAmt >= NVTBits
1483 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1484 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1486 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1487 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1490 // Short: ShAmt < NVTBits
1491 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1492 LoS = DAG.getNode(ISD::OR, dl, NVT,
1493 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1494 // FIXME: If Amt is zero, the following shift generates an undefined result
1495 // on some architectures.
1496 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1498 // Long: ShAmt >= NVTBits
1499 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1500 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1502 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1503 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1506 // Short: ShAmt < NVTBits
1507 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1508 LoS = DAG.getNode(ISD::OR, dl, NVT,
1509 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1510 // FIXME: If Amt is zero, the following shift generates an undefined result
1511 // on some architectures.
1512 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1514 // Long: ShAmt >= NVTBits
1515 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1516 DAG.getConstant(NVTBits-1, ShTy));
1517 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1519 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1520 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1525 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1526 SDValue &Lo, SDValue &Hi) {
1528 // Expand the subcomponents.
1529 SDValue LHSL, LHSH, RHSL, RHSH;
1530 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1531 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1533 EVT NVT = LHSL.getValueType();
1534 SDValue LoOps[2] = { LHSL, RHSL };
1535 SDValue HiOps[3] = { LHSH, RHSH };
1537 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1538 // them. TODO: Teach operation legalization how to expand unsupported
1539 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1540 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1541 // generate a value of this type in the expanded code sequence.
1543 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1544 ISD::ADDC : ISD::SUBC,
1545 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1548 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1549 if (N->getOpcode() == ISD::ADD) {
1550 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1551 HiOps[2] = Lo.getValue(1);
1552 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1554 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1555 HiOps[2] = Lo.getValue(1);
1556 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1561 if (N->getOpcode() == ISD::ADD) {
1562 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1563 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1564 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1566 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1567 DAG.getConstant(1, NVT),
1568 DAG.getConstant(0, NVT));
1569 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1571 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1572 DAG.getConstant(1, NVT), Carry1);
1573 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1575 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1576 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1578 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1579 LoOps[0], LoOps[1], ISD::SETULT);
1580 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1581 DAG.getConstant(1, NVT),
1582 DAG.getConstant(0, NVT));
1583 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1587 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1588 SDValue &Lo, SDValue &Hi) {
1589 // Expand the subcomponents.
1590 SDValue LHSL, LHSH, RHSL, RHSH;
1592 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1593 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1594 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1595 SDValue LoOps[2] = { LHSL, RHSL };
1596 SDValue HiOps[3] = { LHSH, RHSH };
1598 if (N->getOpcode() == ISD::ADDC) {
1599 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1600 HiOps[2] = Lo.getValue(1);
1601 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1603 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1604 HiOps[2] = Lo.getValue(1);
1605 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1608 // Legalized the flag result - switch anything that used the old flag to
1610 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1613 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1614 SDValue &Lo, SDValue &Hi) {
1615 // Expand the subcomponents.
1616 SDValue LHSL, LHSH, RHSL, RHSH;
1618 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1619 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1620 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1621 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1622 SDValue HiOps[3] = { LHSH, RHSH };
1624 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1625 HiOps[2] = Lo.getValue(1);
1626 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1628 // Legalized the flag result - switch anything that used the old flag to
1630 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1633 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1634 SDValue &Lo, SDValue &Hi) {
1635 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1636 SplitInteger(Res, Lo, Hi);
1639 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1640 SDValue &Lo, SDValue &Hi) {
1641 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1643 SDValue Op = N->getOperand(0);
1644 if (Op.getValueType().bitsLE(NVT)) {
1645 // The low part is any extension of the input (which degenerates to a copy).
1646 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1647 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1649 // For example, extension of an i48 to an i64. The operand type necessarily
1650 // promotes to the result type, so will end up being expanded too.
1651 assert(getTypeAction(Op.getValueType()) ==
1652 TargetLowering::TypePromoteInteger &&
1653 "Only know how to promote this result!");
1654 SDValue Res = GetPromotedInteger(Op);
1655 assert(Res.getValueType() == N->getValueType(0) &&
1656 "Operand over promoted?");
1657 // Split the promoted operand. This will simplify when it is expanded.
1658 SplitInteger(Res, Lo, Hi);
1662 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1663 SDValue &Lo, SDValue &Hi) {
1665 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1666 EVT NVT = Lo.getValueType();
1667 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1668 unsigned NVTBits = NVT.getSizeInBits();
1669 unsigned EVTBits = EVT.getSizeInBits();
1671 if (NVTBits < EVTBits) {
1672 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1673 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1674 EVTBits - NVTBits)));
1676 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1677 // The high part replicates the sign bit of Lo, make it explicit.
1678 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1679 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1683 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1684 SDValue &Lo, SDValue &Hi) {
1686 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1687 EVT NVT = Lo.getValueType();
1688 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1689 unsigned NVTBits = NVT.getSizeInBits();
1690 unsigned EVTBits = EVT.getSizeInBits();
1692 if (NVTBits < EVTBits) {
1693 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1694 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1695 EVTBits - NVTBits)));
1697 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1698 // The high part must be zero, make it explicit.
1699 Hi = DAG.getConstant(0, NVT);
1703 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1704 SDValue &Lo, SDValue &Hi) {
1706 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1707 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1708 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1711 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1712 SDValue &Lo, SDValue &Hi) {
1713 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1714 unsigned NBitWidth = NVT.getSizeInBits();
1715 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1716 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1717 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1720 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1721 SDValue &Lo, SDValue &Hi) {
1723 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1724 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1725 EVT NVT = Lo.getValueType();
1727 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1728 DAG.getConstant(0, NVT), ISD::SETNE);
1730 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1731 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1733 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1734 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1735 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1736 Hi = DAG.getConstant(0, NVT);
1739 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1740 SDValue &Lo, SDValue &Hi) {
1742 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1743 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1744 EVT NVT = Lo.getValueType();
1745 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1746 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1747 Hi = DAG.getConstant(0, NVT);
1750 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1751 SDValue &Lo, SDValue &Hi) {
1753 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1754 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1755 EVT NVT = Lo.getValueType();
1757 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1758 DAG.getConstant(0, NVT), ISD::SETNE);
1760 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1761 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1763 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1764 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1765 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1766 Hi = DAG.getConstant(0, NVT);
1769 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1772 EVT VT = N->getValueType(0);
1773 SDValue Op = N->getOperand(0);
1774 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1775 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1776 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1781 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1784 EVT VT = N->getValueType(0);
1785 SDValue Op = N->getOperand(0);
1786 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1787 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1788 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1793 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1794 SDValue &Lo, SDValue &Hi) {
1795 if (ISD::isNormalLoad(N)) {
1796 ExpandRes_NormalLoad(N, Lo, Hi);
1800 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1802 EVT VT = N->getValueType(0);
1803 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1804 SDValue Ch = N->getChain();
1805 SDValue Ptr = N->getBasePtr();
1806 ISD::LoadExtType ExtType = N->getExtensionType();
1807 unsigned Alignment = N->getAlignment();
1808 bool isVolatile = N->isVolatile();
1809 bool isNonTemporal = N->isNonTemporal();
1810 bool isInvariant = N->isInvariant();
1811 const MDNode *TBAAInfo = N->getTBAAInfo();
1814 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1816 if (N->getMemoryVT().bitsLE(NVT)) {
1817 EVT MemVT = N->getMemoryVT();
1819 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1820 MemVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
1822 // Remember the chain.
1823 Ch = Lo.getValue(1);
1825 if (ExtType == ISD::SEXTLOAD) {
1826 // The high part is obtained by SRA'ing all but one of the bits of the
1828 unsigned LoSize = Lo.getValueType().getSizeInBits();
1829 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1830 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1831 } else if (ExtType == ISD::ZEXTLOAD) {
1832 // The high part is just a zero.
1833 Hi = DAG.getConstant(0, NVT);
1835 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1836 // The high part is undefined.
1837 Hi = DAG.getUNDEF(NVT);
1839 } else if (TLI.isLittleEndian()) {
1840 // Little-endian - low bits are at low addresses.
1841 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1842 isVolatile, isNonTemporal, isInvariant, Alignment,
1845 unsigned ExcessBits =
1846 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1847 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1849 // Increment the pointer to the other half.
1850 unsigned IncrementSize = NVT.getSizeInBits()/8;
1851 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1852 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1853 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1854 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1855 isVolatile, isNonTemporal,
1856 MinAlign(Alignment, IncrementSize), TBAAInfo);
1858 // Build a factor node to remember that this load is independent of the
1860 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1863 // Big-endian - high bits are at low addresses. Favor aligned loads at
1864 // the cost of some bit-fiddling.
1865 EVT MemVT = N->getMemoryVT();
1866 unsigned EBytes = MemVT.getStoreSize();
1867 unsigned IncrementSize = NVT.getSizeInBits()/8;
1868 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1870 // Load both the high bits and maybe some of the low bits.
1871 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1872 EVT::getIntegerVT(*DAG.getContext(),
1873 MemVT.getSizeInBits() - ExcessBits),
1874 isVolatile, isNonTemporal, Alignment, TBAAInfo);
1876 // Increment the pointer to the other half.
1877 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1878 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1879 // Load the rest of the low bits.
1880 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1881 N->getPointerInfo().getWithOffset(IncrementSize),
1882 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1883 isVolatile, isNonTemporal,
1884 MinAlign(Alignment, IncrementSize), TBAAInfo);
1886 // Build a factor node to remember that this load is independent of the
1888 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1891 if (ExcessBits < NVT.getSizeInBits()) {
1892 // Transfer low bits from the bottom of Hi to the top of Lo.
1893 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1894 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1895 DAG.getConstant(ExcessBits,
1896 TLI.getPointerTy())));
1897 // Move high bits to the right position in Hi.
1898 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1900 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1901 TLI.getPointerTy()));
1905 // Legalized the chain result - switch anything that used the old chain to
1907 ReplaceValueWith(SDValue(N, 1), Ch);
1910 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1911 SDValue &Lo, SDValue &Hi) {
1913 SDValue LL, LH, RL, RH;
1914 GetExpandedInteger(N->getOperand(0), LL, LH);
1915 GetExpandedInteger(N->getOperand(1), RL, RH);
1916 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1917 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1920 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1921 SDValue &Lo, SDValue &Hi) {
1922 EVT VT = N->getValueType(0);
1923 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1926 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1927 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1928 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1929 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1930 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1931 SDValue LL, LH, RL, RH;
1932 GetExpandedInteger(N->getOperand(0), LL, LH);
1933 GetExpandedInteger(N->getOperand(1), RL, RH);
1934 unsigned OuterBitSize = VT.getSizeInBits();
1935 unsigned InnerBitSize = NVT.getSizeInBits();
1936 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1937 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1939 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1940 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1941 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1942 // The inputs are both zero-extended.
1944 // We can emit a umul_lohi.
1945 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1946 Hi = SDValue(Lo.getNode(), 1);
1950 // We can emit a mulhu+mul.
1951 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1952 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1956 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1957 // The input values are both sign-extended.
1959 // We can emit a smul_lohi.
1960 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1961 Hi = SDValue(Lo.getNode(), 1);
1965 // We can emit a mulhs+mul.
1966 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1967 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1972 // Lo,Hi = umul LHS, RHS.
1973 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1974 DAG.getVTList(NVT, NVT), LL, RL);
1976 Hi = UMulLOHI.getValue(1);
1977 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1978 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1979 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1980 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1984 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1985 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1986 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1987 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1988 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1989 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1994 // If nothing else, we can make a libcall.
1995 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1997 LC = RTLIB::MUL_I16;
1998 else if (VT == MVT::i32)
1999 LC = RTLIB::MUL_I32;
2000 else if (VT == MVT::i64)
2001 LC = RTLIB::MUL_I64;
2002 else if (VT == MVT::i128)
2003 LC = RTLIB::MUL_I128;
2004 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2006 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2007 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2012 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2013 SDValue &Lo, SDValue &Hi) {
2014 SDValue LHS = Node->getOperand(0);
2015 SDValue RHS = Node->getOperand(1);
2018 // Expand the result by simply replacing it with the equivalent
2019 // non-overflow-checking operation.
2020 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2021 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2023 SplitInteger(Sum, Lo, Hi);
2025 // Compute the overflow.
2027 // LHSSign -> LHS >= 0
2028 // RHSSign -> RHS >= 0
2029 // SumSign -> Sum >= 0
2032 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2034 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2036 EVT OType = Node->getValueType(1);
2037 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2039 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2040 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2041 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2042 Node->getOpcode() == ISD::SADDO ?
2043 ISD::SETEQ : ISD::SETNE);
2045 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2046 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2048 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2050 // Use the calculated overflow everywhere.
2051 ReplaceValueWith(SDValue(Node, 1), Cmp);
2054 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2055 SDValue &Lo, SDValue &Hi) {
2056 EVT VT = N->getValueType(0);
2059 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2061 LC = RTLIB::SDIV_I16;
2062 else if (VT == MVT::i32)
2063 LC = RTLIB::SDIV_I32;
2064 else if (VT == MVT::i64)
2065 LC = RTLIB::SDIV_I64;
2066 else if (VT == MVT::i128)
2067 LC = RTLIB::SDIV_I128;
2068 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2070 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2071 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2074 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2075 SDValue &Lo, SDValue &Hi) {
2076 EVT VT = N->getValueType(0);
2079 // If we can emit an efficient shift operation, do so now. Check to see if
2080 // the RHS is a constant.
2081 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2082 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2084 // If we can determine that the high bit of the shift is zero or one, even if
2085 // the low bits are variable, emit this shift in an optimized form.
2086 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2089 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2091 if (N->getOpcode() == ISD::SHL) {
2092 PartsOpc = ISD::SHL_PARTS;
2093 } else if (N->getOpcode() == ISD::SRL) {
2094 PartsOpc = ISD::SRL_PARTS;
2096 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2097 PartsOpc = ISD::SRA_PARTS;
2100 // Next check to see if the target supports this SHL_PARTS operation or if it
2101 // will custom expand it.
2102 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2103 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2104 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2105 Action == TargetLowering::Custom) {
2106 // Expand the subcomponents.
2108 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2109 EVT VT = LHSL.getValueType();
2111 // If the shift amount operand is coming from a vector legalization it may
2112 // have an illegal type. Fix that first by casting the operand, otherwise
2113 // the new SHL_PARTS operation would need further legalization.
2114 SDValue ShiftOp = N->getOperand(1);
2115 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2116 assert(ShiftTy.getScalarType().getSizeInBits() >=
2117 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2118 "ShiftAmountTy is too small to cover the range of this type!");
2119 if (ShiftOp.getValueType() != ShiftTy)
2120 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2122 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2123 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
2124 Hi = Lo.getValue(1);
2128 // Otherwise, emit a libcall.
2129 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2131 if (N->getOpcode() == ISD::SHL) {
2132 isSigned = false; /*sign irrelevant*/
2134 LC = RTLIB::SHL_I16;
2135 else if (VT == MVT::i32)
2136 LC = RTLIB::SHL_I32;
2137 else if (VT == MVT::i64)
2138 LC = RTLIB::SHL_I64;
2139 else if (VT == MVT::i128)
2140 LC = RTLIB::SHL_I128;
2141 } else if (N->getOpcode() == ISD::SRL) {
2144 LC = RTLIB::SRL_I16;
2145 else if (VT == MVT::i32)
2146 LC = RTLIB::SRL_I32;
2147 else if (VT == MVT::i64)
2148 LC = RTLIB::SRL_I64;
2149 else if (VT == MVT::i128)
2150 LC = RTLIB::SRL_I128;
2152 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2155 LC = RTLIB::SRA_I16;
2156 else if (VT == MVT::i32)
2157 LC = RTLIB::SRA_I32;
2158 else if (VT == MVT::i64)
2159 LC = RTLIB::SRA_I64;
2160 else if (VT == MVT::i128)
2161 LC = RTLIB::SRA_I128;
2164 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2165 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2166 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2171 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2172 llvm_unreachable("Unsupported shift!");
2175 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2176 SDValue &Lo, SDValue &Hi) {
2177 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2179 SDValue Op = N->getOperand(0);
2180 if (Op.getValueType().bitsLE(NVT)) {
2181 // The low part is sign extension of the input (degenerates to a copy).
2182 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2183 // The high part is obtained by SRA'ing all but one of the bits of low part.
2184 unsigned LoSize = NVT.getSizeInBits();
2185 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2186 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2188 // For example, extension of an i48 to an i64. The operand type necessarily
2189 // promotes to the result type, so will end up being expanded too.
2190 assert(getTypeAction(Op.getValueType()) ==
2191 TargetLowering::TypePromoteInteger &&
2192 "Only know how to promote this result!");
2193 SDValue Res = GetPromotedInteger(Op);
2194 assert(Res.getValueType() == N->getValueType(0) &&
2195 "Operand over promoted?");
2196 // Split the promoted operand. This will simplify when it is expanded.
2197 SplitInteger(Res, Lo, Hi);
2198 unsigned ExcessBits =
2199 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2200 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2201 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2206 void DAGTypeLegalizer::
2207 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2209 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2210 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2212 if (EVT.bitsLE(Lo.getValueType())) {
2213 // sext_inreg the low part if needed.
2214 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2217 // The high part gets the sign extension from the lo-part. This handles
2218 // things like sextinreg V:i64 from i8.
2219 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2220 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2221 TLI.getPointerTy()));
2223 // For example, extension of an i48 to an i64. Leave the low part alone,
2224 // sext_inreg the high part.
2225 unsigned ExcessBits =
2226 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2227 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2228 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2233 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2234 SDValue &Lo, SDValue &Hi) {
2235 EVT VT = N->getValueType(0);
2238 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2240 LC = RTLIB::SREM_I16;
2241 else if (VT == MVT::i32)
2242 LC = RTLIB::SREM_I32;
2243 else if (VT == MVT::i64)
2244 LC = RTLIB::SREM_I64;
2245 else if (VT == MVT::i128)
2246 LC = RTLIB::SREM_I128;
2247 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2249 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2250 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2253 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2254 SDValue &Lo, SDValue &Hi) {
2255 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2257 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2258 Hi = DAG.getNode(ISD::SRL, dl,
2259 N->getOperand(0).getValueType(), N->getOperand(0),
2260 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2261 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2264 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2265 SDValue &Lo, SDValue &Hi) {
2266 SDValue LHS = N->getOperand(0);
2267 SDValue RHS = N->getOperand(1);
2270 // Expand the result by simply replacing it with the equivalent
2271 // non-overflow-checking operation.
2272 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2273 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2275 SplitInteger(Sum, Lo, Hi);
2277 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2278 // overflows iff a - b > a.
2279 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2280 N->getOpcode () == ISD::UADDO ?
2281 ISD::SETULT : ISD::SETUGT);
2283 // Use the calculated overflow everywhere.
2284 ReplaceValueWith(SDValue(N, 1), Ofl);
2287 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2288 SDValue &Lo, SDValue &Hi) {
2289 EVT VT = N->getValueType(0);
2292 // A divide for UMULO should be faster than a function call.
2293 if (N->getOpcode() == ISD::UMULO) {
2294 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2296 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2297 SplitInteger(MUL, Lo, Hi);
2299 // A divide for UMULO will be faster than a function call. Select to
2300 // make sure we aren't using 0.
2301 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2302 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2303 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2304 DAG.getConstant(1, VT), RHS);
2305 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2306 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2308 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2309 DAG.getConstant(0, N->getValueType(1)),
2311 ReplaceValueWith(SDValue(N, 1), Overflow);
2315 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2316 EVT PtrVT = TLI.getPointerTy();
2317 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2319 // Replace this with a libcall that will check overflow.
2320 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2322 LC = RTLIB::MULO_I32;
2323 else if (VT == MVT::i64)
2324 LC = RTLIB::MULO_I64;
2325 else if (VT == MVT::i128)
2326 LC = RTLIB::MULO_I128;
2327 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2329 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2330 // Temporary for the overflow value, default it to zero.
2331 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2332 DAG.getConstant(0, PtrVT), Temp,
2333 MachinePointerInfo(), false, false, 0);
2335 TargetLowering::ArgListTy Args;
2336 TargetLowering::ArgListEntry Entry;
2337 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2338 EVT ArgVT = N->getOperand(i).getValueType();
2339 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2340 Entry.Node = N->getOperand(i);
2342 Entry.isSExt = true;
2343 Entry.isZExt = false;
2344 Args.push_back(Entry);
2347 // Also pass the address of the overflow check.
2349 Entry.Ty = PtrTy->getPointerTo();
2350 Entry.isSExt = true;
2351 Entry.isZExt = false;
2352 Args.push_back(Entry);
2354 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2356 CallLoweringInfo CLI(Chain, RetTy, true, false, false, false,
2357 0, TLI.getLibcallCallingConv(LC),
2358 /*isTailCall=*/false,
2359 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2360 Func, Args, DAG, dl);
2361 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2363 SplitInteger(CallInfo.first, Lo, Hi);
2364 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2365 MachinePointerInfo(), false, false, false, 0);
2366 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2367 DAG.getConstant(0, PtrVT),
2369 // Use the overflow from the libcall everywhere.
2370 ReplaceValueWith(SDValue(N, 1), Ofl);
2373 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2374 SDValue &Lo, SDValue &Hi) {
2375 EVT VT = N->getValueType(0);
2378 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2380 LC = RTLIB::UDIV_I16;
2381 else if (VT == MVT::i32)
2382 LC = RTLIB::UDIV_I32;
2383 else if (VT == MVT::i64)
2384 LC = RTLIB::UDIV_I64;
2385 else if (VT == MVT::i128)
2386 LC = RTLIB::UDIV_I128;
2387 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2389 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2390 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2393 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2394 SDValue &Lo, SDValue &Hi) {
2395 EVT VT = N->getValueType(0);
2398 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2400 LC = RTLIB::UREM_I16;
2401 else if (VT == MVT::i32)
2402 LC = RTLIB::UREM_I32;
2403 else if (VT == MVT::i64)
2404 LC = RTLIB::UREM_I64;
2405 else if (VT == MVT::i128)
2406 LC = RTLIB::UREM_I128;
2407 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2409 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2410 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2413 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2414 SDValue &Lo, SDValue &Hi) {
2415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2417 SDValue Op = N->getOperand(0);
2418 if (Op.getValueType().bitsLE(NVT)) {
2419 // The low part is zero extension of the input (degenerates to a copy).
2420 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2421 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2423 // For example, extension of an i48 to an i64. The operand type necessarily
2424 // promotes to the result type, so will end up being expanded too.
2425 assert(getTypeAction(Op.getValueType()) ==
2426 TargetLowering::TypePromoteInteger &&
2427 "Only know how to promote this result!");
2428 SDValue Res = GetPromotedInteger(Op);
2429 assert(Res.getValueType() == N->getValueType(0) &&
2430 "Operand over promoted?");
2431 // Split the promoted operand. This will simplify when it is expanded.
2432 SplitInteger(Res, Lo, Hi);
2433 unsigned ExcessBits =
2434 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2435 Hi = DAG.getZeroExtendInReg(Hi, dl,
2436 EVT::getIntegerVT(*DAG.getContext(),
2441 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2442 SDValue &Lo, SDValue &Hi) {
2444 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2445 SDValue Zero = DAG.getConstant(0, VT);
2446 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
2448 N->getOperand(1), Zero, Zero,
2449 cast<AtomicSDNode>(N)->getMemOperand(),
2450 cast<AtomicSDNode>(N)->getOrdering(),
2451 cast<AtomicSDNode>(N)->getSynchScope());
2452 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2453 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1));
2456 //===----------------------------------------------------------------------===//
2457 // Integer Operand Expansion
2458 //===----------------------------------------------------------------------===//
2460 /// ExpandIntegerOperand - This method is called when the specified operand of
2461 /// the specified node is found to need expansion. At this point, all of the
2462 /// result types of the node are known to be legal, but other operands of the
2463 /// node may need promotion or expansion as well as the specified one.
2464 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2465 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2466 SDValue Res = SDValue();
2468 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2471 switch (N->getOpcode()) {
2474 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2475 N->dump(&DAG); dbgs() << "\n";
2477 llvm_unreachable("Do not know how to expand this operator's operand!");
2479 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2480 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2481 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2482 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2483 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2484 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2485 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2486 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2487 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2488 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2489 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2490 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2496 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2497 case ISD::RETURNADDR:
2498 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2500 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2503 // If the result is null, the sub-method took care of registering results etc.
2504 if (!Res.getNode()) return false;
2506 // If the result is N, the sub-method updated N in place. Tell the legalizer
2508 if (Res.getNode() == N)
2511 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2512 "Invalid operand expansion");
2514 ReplaceValueWith(SDValue(N, 0), Res);
2518 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2519 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2520 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2522 ISD::CondCode &CCCode,
2524 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2525 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2526 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2528 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2529 if (RHSLo == RHSHi) {
2530 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2531 if (RHSCST->isAllOnesValue()) {
2532 // Equality comparison to -1.
2533 NewLHS = DAG.getNode(ISD::AND, dl,
2534 LHSLo.getValueType(), LHSLo, LHSHi);
2541 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2542 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2543 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2544 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2548 // If this is a comparison of the sign bit, just look at the top part.
2550 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2551 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2552 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2558 // FIXME: This generated code sucks.
2559 ISD::CondCode LowCC;
2561 default: llvm_unreachable("Unknown integer setcc!");
2563 case ISD::SETULT: LowCC = ISD::SETULT; break;
2565 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2567 case ISD::SETULE: LowCC = ISD::SETULE; break;
2569 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2572 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2573 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2574 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2576 // NOTE: on targets without efficient SELECT of bools, we can always use
2577 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2578 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true, NULL);
2580 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2581 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2582 if (!Tmp1.getNode())
2583 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2584 LHSLo, RHSLo, LowCC);
2585 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2586 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2587 if (!Tmp2.getNode())
2588 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2589 getSetCCResultType(LHSHi.getValueType()),
2590 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2592 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2593 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2594 if ((Tmp1C && Tmp1C->isNullValue()) ||
2595 (Tmp2C && Tmp2C->isNullValue() &&
2596 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2597 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2598 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2599 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2600 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2601 // low part is known false, returns high part.
2602 // For LE / GE, if high part is known false, ignore the low part.
2603 // For LT / GT, if high part is known true, ignore the low part.
2609 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2610 LHSHi, RHSHi, ISD::SETEQ, false,
2611 DagCombineInfo, dl);
2612 if (!NewLHS.getNode())
2613 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2614 LHSHi, RHSHi, ISD::SETEQ);
2615 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2616 NewLHS, Tmp1, Tmp2);
2620 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2621 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2622 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2623 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2625 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2626 // against zero to select between true and false values.
2627 if (NewRHS.getNode() == 0) {
2628 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2629 CCCode = ISD::SETNE;
2632 // Update N to have the operands specified.
2633 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2634 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2635 N->getOperand(4)), 0);
2638 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2639 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2640 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2641 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2643 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2644 // against zero to select between true and false values.
2645 if (NewRHS.getNode() == 0) {
2646 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2647 CCCode = ISD::SETNE;
2650 // Update N to have the operands specified.
2651 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2652 N->getOperand(2), N->getOperand(3),
2653 DAG.getCondCode(CCCode)), 0);
2656 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2657 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2658 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2659 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2661 // If ExpandSetCCOperands returned a scalar, use it.
2662 if (NewRHS.getNode() == 0) {
2663 assert(NewLHS.getValueType() == N->getValueType(0) &&
2664 "Unexpected setcc expansion!");
2668 // Otherwise, update N to have the operands specified.
2669 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2670 DAG.getCondCode(CCCode)), 0);
2673 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2674 // The value being shifted is legal, but the shift amount is too big.
2675 // It follows that either the result of the shift is undefined, or the
2676 // upper half of the shift amount is zero. Just use the lower half.
2678 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2679 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2682 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2683 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2684 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2685 // constant to valid type.
2687 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2688 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2691 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2692 SDValue Op = N->getOperand(0);
2693 EVT DstVT = N->getValueType(0);
2694 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2695 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2696 "Don't know how to expand this SINT_TO_FP!");
2697 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2700 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2701 if (ISD::isNormalStore(N))
2702 return ExpandOp_NormalStore(N, OpNo);
2704 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2705 assert(OpNo == 1 && "Can only expand the stored value so far");
2707 EVT VT = N->getOperand(1).getValueType();
2708 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2709 SDValue Ch = N->getChain();
2710 SDValue Ptr = N->getBasePtr();
2711 unsigned Alignment = N->getAlignment();
2712 bool isVolatile = N->isVolatile();
2713 bool isNonTemporal = N->isNonTemporal();
2714 const MDNode *TBAAInfo = N->getTBAAInfo();
2718 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2720 if (N->getMemoryVT().bitsLE(NVT)) {
2721 GetExpandedInteger(N->getValue(), Lo, Hi);
2722 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2723 N->getMemoryVT(), isVolatile, isNonTemporal,
2724 Alignment, TBAAInfo);
2727 if (TLI.isLittleEndian()) {
2728 // Little-endian - low bits are at low addresses.
2729 GetExpandedInteger(N->getValue(), Lo, Hi);
2731 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2732 isVolatile, isNonTemporal, Alignment, TBAAInfo);
2734 unsigned ExcessBits =
2735 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2736 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2738 // Increment the pointer to the other half.
2739 unsigned IncrementSize = NVT.getSizeInBits()/8;
2740 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2741 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2742 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2743 N->getPointerInfo().getWithOffset(IncrementSize),
2744 NEVT, isVolatile, isNonTemporal,
2745 MinAlign(Alignment, IncrementSize), TBAAInfo);
2746 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2749 // Big-endian - high bits are at low addresses. Favor aligned stores at
2750 // the cost of some bit-fiddling.
2751 GetExpandedInteger(N->getValue(), Lo, Hi);
2753 EVT ExtVT = N->getMemoryVT();
2754 unsigned EBytes = ExtVT.getStoreSize();
2755 unsigned IncrementSize = NVT.getSizeInBits()/8;
2756 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2757 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2758 ExtVT.getSizeInBits() - ExcessBits);
2760 if (ExcessBits < NVT.getSizeInBits()) {
2761 // Transfer high bits from the top of Lo to the bottom of Hi.
2762 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2763 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2764 TLI.getPointerTy()));
2765 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2766 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2767 DAG.getConstant(ExcessBits,
2768 TLI.getPointerTy())));
2771 // Store both the high bits and maybe some of the low bits.
2772 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2773 HiVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
2775 // Increment the pointer to the other half.
2776 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2777 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2778 // Store the lowest ExcessBits bits in the second half.
2779 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2780 N->getPointerInfo().getWithOffset(IncrementSize),
2781 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2782 isVolatile, isNonTemporal,
2783 MinAlign(Alignment, IncrementSize), TBAAInfo);
2784 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2787 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2789 GetExpandedInteger(N->getOperand(0), InL, InH);
2790 // Just truncate the low part of the source.
2791 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2794 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2795 SDValue Op = N->getOperand(0);
2796 EVT SrcVT = Op.getValueType();
2797 EVT DstVT = N->getValueType(0);
2800 // The following optimization is valid only if every value in SrcVT (when
2801 // treated as signed) is representable in DstVT. Check that the mantissa
2802 // size of DstVT is >= than the number of bits in SrcVT -1.
2803 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2804 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2805 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2806 // Do a signed conversion then adjust the result.
2807 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2808 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2810 // The result of the signed conversion needs adjusting if the 'sign bit' of
2811 // the incoming integer was set. To handle this, we dynamically test to see
2812 // if it is set, and, if so, add a fudge factor.
2814 const uint64_t F32TwoE32 = 0x4F800000ULL;
2815 const uint64_t F32TwoE64 = 0x5F800000ULL;
2816 const uint64_t F32TwoE128 = 0x7F800000ULL;
2819 if (SrcVT == MVT::i32)
2820 FF = APInt(32, F32TwoE32);
2821 else if (SrcVT == MVT::i64)
2822 FF = APInt(32, F32TwoE64);
2823 else if (SrcVT == MVT::i128)
2824 FF = APInt(32, F32TwoE128);
2826 llvm_unreachable("Unsupported UINT_TO_FP!");
2828 // Check whether the sign bit is set.
2830 GetExpandedInteger(Op, Lo, Hi);
2831 SDValue SignSet = DAG.getSetCC(dl,
2832 getSetCCResultType(Hi.getValueType()),
2833 Hi, DAG.getConstant(0, Hi.getValueType()),
2836 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2837 SDValue FudgePtr = DAG.getConstantPool(
2838 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2839 TLI.getPointerTy());
2841 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2842 SDValue Zero = DAG.getIntPtrConstant(0);
2843 SDValue Four = DAG.getIntPtrConstant(4);
2844 if (TLI.isBigEndian()) std::swap(Zero, Four);
2845 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2847 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2848 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2850 Alignment = std::min(Alignment, 4u);
2852 // Load the value out, extending it from f32 to the destination float type.
2853 // FIXME: Avoid the extend by constructing the right constant pool?
2854 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2856 MachinePointerInfo::getConstantPool(),
2858 false, false, Alignment);
2859 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2862 // Otherwise, use a libcall.
2863 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2864 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2865 "Don't know how to expand this UINT_TO_FP!");
2866 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2869 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2871 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2872 cast<AtomicSDNode>(N)->getMemoryVT(),
2874 N->getOperand(1), N->getOperand(2),
2875 cast<AtomicSDNode>(N)->getMemOperand(),
2876 cast<AtomicSDNode>(N)->getOrdering(),
2877 cast<AtomicSDNode>(N)->getSynchScope());
2878 return Swap.getValue(1);
2882 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2883 SDValue InOp0 = N->getOperand(0);
2884 EVT InVT = InOp0.getValueType();
2886 EVT OutVT = N->getValueType(0);
2887 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2888 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2889 unsigned OutNumElems = OutVT.getVectorNumElements();
2890 EVT NOutVTElem = NOutVT.getVectorElementType();
2893 SDValue BaseIdx = N->getOperand(1);
2895 SmallVector<SDValue, 8> Ops;
2896 Ops.reserve(OutNumElems);
2897 for (unsigned i = 0; i != OutNumElems; ++i) {
2899 // Extract the element from the original vector.
2900 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2901 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
2902 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2903 InVT.getVectorElementType(), N->getOperand(0), Index);
2905 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2906 // Insert the converted element to the new vector.
2910 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2914 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2915 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2916 EVT VT = N->getValueType(0);
2919 unsigned NumElts = VT.getVectorNumElements();
2920 SmallVector<int, 8> NewMask;
2921 for (unsigned i = 0; i != NumElts; ++i) {
2922 NewMask.push_back(SV->getMaskElt(i));
2925 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2926 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2927 EVT OutVT = V0.getValueType();
2929 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2933 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2934 EVT OutVT = N->getValueType(0);
2935 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2936 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2937 unsigned NumElems = N->getNumOperands();
2938 EVT NOutVTElem = NOutVT.getVectorElementType();
2942 SmallVector<SDValue, 8> Ops;
2943 Ops.reserve(NumElems);
2944 for (unsigned i = 0; i != NumElems; ++i) {
2946 // BUILD_VECTOR integer operand types are allowed to be larger than the
2947 // result's element type. This may still be true after the promotion. For
2948 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
2949 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
2950 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
2951 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2953 Op = N->getOperand(i);
2957 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2960 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2964 assert(!N->getOperand(0).getValueType().isVector() &&
2965 "Input must be a scalar");
2967 EVT OutVT = N->getValueType(0);
2968 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2969 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2970 EVT NOutVTElem = NOutVT.getVectorElementType();
2972 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2974 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2977 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
2980 EVT OutVT = N->getValueType(0);
2981 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2982 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2984 EVT InElemTy = OutVT.getVectorElementType();
2985 EVT OutElemTy = NOutVT.getVectorElementType();
2987 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
2988 unsigned NumOutElem = NOutVT.getVectorNumElements();
2989 unsigned NumOperands = N->getNumOperands();
2990 assert(NumElem * NumOperands == NumOutElem &&
2991 "Unexpected number of elements");
2993 // Take the elements from the first vector.
2994 SmallVector<SDValue, 8> Ops(NumOutElem);
2995 for (unsigned i = 0; i < NumOperands; ++i) {
2996 SDValue Op = N->getOperand(i);
2997 for (unsigned j = 0; j < NumElem; ++j) {
2998 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2999 InElemTy, Op, DAG.getConstant(j,
3000 TLI.getVectorIdxTy()));
3001 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3005 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
3008 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3009 EVT OutVT = N->getValueType(0);
3010 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3011 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3013 EVT NOutVTElem = NOutVT.getVectorElementType();
3016 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3018 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3019 NOutVTElem, N->getOperand(1));
3020 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3021 V0, ConvElem, N->getOperand(2));
3024 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3026 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3027 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3028 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3029 V0->getValueType(0).getScalarType(), V0, V1);
3031 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3032 // element types. If this is the case then we need to expand the outgoing
3033 // value and not truncate it.
3034 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3037 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3039 unsigned NumElems = N->getNumOperands();
3041 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3043 SmallVector<SDValue, 8> NewOps;
3044 NewOps.reserve(NumElems);
3046 // For each incoming vector
3047 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3048 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3049 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3050 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3052 for (unsigned i=0; i<NumElem; ++i) {
3053 // Extract element from incoming vector
3054 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3055 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3056 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3057 NewOps.push_back(Tr);
3061 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
3062 &NewOps[0], NewOps.size());