1 //=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code =//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/AArch64FixupKinds.h"
16 #include "MCTargetDesc/AArch64MCExpr.h"
17 #include "MCTargetDesc/AArch64MCTargetDesc.h"
18 #include "Utils/AArch64BaseInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
31 class AArch64MCCodeEmitter : public MCCodeEmitter {
32 AArch64MCCodeEmitter(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 AArch64MCCodeEmitter(MCContext &ctx) : Ctx(ctx) {}
39 ~AArch64MCCodeEmitter() {}
41 unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
42 SmallVectorImpl<MCFixup> &Fixups) const;
44 unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
45 SmallVectorImpl<MCFixup> &Fixups) const;
48 unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
49 SmallVectorImpl<MCFixup> &Fixups) const {
50 return getOffsetUImm12OpValue(MI, OpIdx, Fixups, MemSize);
53 unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
54 SmallVectorImpl<MCFixup> &Fixups,
57 unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
58 SmallVectorImpl<MCFixup> &Fixups) const;
59 unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
60 SmallVectorImpl<MCFixup> &Fixups) const;
62 unsigned getShiftRightImm8(const MCInst &MI, unsigned Op,
63 SmallVectorImpl<MCFixup> &Fixups) const;
64 unsigned getShiftRightImm16(const MCInst &MI, unsigned Op,
65 SmallVectorImpl<MCFixup> &Fixups) const;
66 unsigned getShiftRightImm32(const MCInst &MI, unsigned Op,
67 SmallVectorImpl<MCFixup> &Fixups) const;
68 unsigned getShiftRightImm64(const MCInst &MI, unsigned Op,
69 SmallVectorImpl<MCFixup> &Fixups) const;
71 unsigned getShiftLeftImm8(const MCInst &MI, unsigned Op,
72 SmallVectorImpl<MCFixup> &Fixups) const;
73 unsigned getShiftLeftImm16(const MCInst &MI, unsigned Op,
74 SmallVectorImpl<MCFixup> &Fixups) const;
75 unsigned getShiftLeftImm32(const MCInst &MI, unsigned Op,
76 SmallVectorImpl<MCFixup> &Fixups) const;
77 unsigned getShiftLeftImm64(const MCInst &MI, unsigned Op,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 // Labels are handled mostly the same way: a symbol is needed, and
81 // just gets some fixup attached.
82 template<AArch64::Fixups fixupDesired>
83 unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx,
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx,
87 SmallVectorImpl<MCFixup> &Fixups) const;
90 unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
91 SmallVectorImpl<MCFixup> &Fixups) const;
94 unsigned getAddressWithFixup(const MCOperand &MO,
96 SmallVectorImpl<MCFixup> &Fixups) const;
99 // getBinaryCodeForInstr - TableGen'erated function for getting the
100 // binary encoding for an instruction.
101 uint64_t getBinaryCodeForInstr(const MCInst &MI,
102 SmallVectorImpl<MCFixup> &Fixups) const;
104 /// getMachineOpValue - Return binary encoding of operand. If the machine
105 /// operand requires relocation, record the relocation and return zero.
106 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
107 SmallVectorImpl<MCFixup> &Fixups) const;
110 void EmitByte(unsigned char C, raw_ostream &OS) const {
114 void EmitInstruction(uint32_t Val, raw_ostream &OS) const {
115 // Output the constant in little endian byte order.
116 for (unsigned i = 0; i != 4; ++i) {
117 EmitByte(Val & 0xff, OS);
123 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
124 SmallVectorImpl<MCFixup> &Fixups) const;
126 template<int hasRs, int hasRt2> unsigned
127 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const;
129 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue) const;
131 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue) const;
136 } // end anonymous namespace
138 unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO,
140 SmallVectorImpl<MCFixup> &Fixups) const {
142 // This can occur for manually decoded or constructed MCInsts, but neither
143 // the assembly-parser nor instruction selection will currently produce an
144 // MCInst that's not a symbol reference.
145 assert(MO.isImm() && "Unexpected address requested");
149 const MCExpr *Expr = MO.getExpr();
150 MCFixupKind Kind = MCFixupKind(FixupKind);
151 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
156 unsigned AArch64MCCodeEmitter::
157 getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
158 SmallVectorImpl<MCFixup> &Fixups,
160 const MCOperand &ImmOp = MI.getOperand(OpIdx);
162 return ImmOp.getImm();
164 assert(ImmOp.isExpr() && "Unexpected operand type");
165 const AArch64MCExpr *Expr = cast<AArch64MCExpr>(ImmOp.getExpr());
169 switch (Expr->getKind()) {
170 default: llvm_unreachable("Unexpected operand modifier");
171 case AArch64MCExpr::VK_AARCH64_LO12: {
172 static const unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_lo12,
173 AArch64::fixup_a64_ldst16_lo12,
174 AArch64::fixup_a64_ldst32_lo12,
175 AArch64::fixup_a64_ldst64_lo12,
176 AArch64::fixup_a64_ldst128_lo12 };
177 assert(MemSize <= 16 && "Invalid fixup for operation");
178 FixupKind = FixupsBySize[Log2_32(MemSize)];
181 case AArch64MCExpr::VK_AARCH64_GOT_LO12:
182 assert(MemSize == 8 && "Invalid fixup for operation");
183 FixupKind = AArch64::fixup_a64_ld64_got_lo12_nc;
185 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12: {
186 static const unsigned FixupsBySize[] = {
187 AArch64::fixup_a64_ldst8_dtprel_lo12,
188 AArch64::fixup_a64_ldst16_dtprel_lo12,
189 AArch64::fixup_a64_ldst32_dtprel_lo12,
190 AArch64::fixup_a64_ldst64_dtprel_lo12
192 assert(MemSize <= 8 && "Invalid fixup for operation");
193 FixupKind = FixupsBySize[Log2_32(MemSize)];
196 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC: {
197 static const unsigned FixupsBySize[] = {
198 AArch64::fixup_a64_ldst8_dtprel_lo12_nc,
199 AArch64::fixup_a64_ldst16_dtprel_lo12_nc,
200 AArch64::fixup_a64_ldst32_dtprel_lo12_nc,
201 AArch64::fixup_a64_ldst64_dtprel_lo12_nc
203 assert(MemSize <= 8 && "Invalid fixup for operation");
204 FixupKind = FixupsBySize[Log2_32(MemSize)];
207 case AArch64MCExpr::VK_AARCH64_GOTTPREL_LO12:
208 assert(MemSize == 8 && "Invalid fixup for operation");
209 FixupKind = AArch64::fixup_a64_ld64_gottprel_lo12_nc;
211 case AArch64MCExpr::VK_AARCH64_TPREL_LO12:{
212 static const unsigned FixupsBySize[] = {
213 AArch64::fixup_a64_ldst8_tprel_lo12,
214 AArch64::fixup_a64_ldst16_tprel_lo12,
215 AArch64::fixup_a64_ldst32_tprel_lo12,
216 AArch64::fixup_a64_ldst64_tprel_lo12
218 assert(MemSize <= 8 && "Invalid fixup for operation");
219 FixupKind = FixupsBySize[Log2_32(MemSize)];
222 case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC: {
223 static const unsigned FixupsBySize[] = {
224 AArch64::fixup_a64_ldst8_tprel_lo12_nc,
225 AArch64::fixup_a64_ldst16_tprel_lo12_nc,
226 AArch64::fixup_a64_ldst32_tprel_lo12_nc,
227 AArch64::fixup_a64_ldst64_tprel_lo12_nc
229 assert(MemSize <= 8 && "Invalid fixup for operation");
230 FixupKind = FixupsBySize[Log2_32(MemSize)];
233 case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12:
234 assert(MemSize == 8 && "Invalid fixup for operation");
235 FixupKind = AArch64::fixup_a64_tlsdesc_ld64_lo12_nc;
239 return getAddressWithFixup(ImmOp, FixupKind, Fixups);
243 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
244 SmallVectorImpl<MCFixup> &Fixups) const {
245 const MCOperand &MO = MI.getOperand(OpIdx);
247 return static_cast<unsigned>(MO.getImm());
251 unsigned FixupKind = 0;
252 switch(cast<AArch64MCExpr>(MO.getExpr())->getKind()) {
253 default: llvm_unreachable("Invalid expression modifier");
254 case AArch64MCExpr::VK_AARCH64_LO12:
255 FixupKind = AArch64::fixup_a64_add_lo12; break;
256 case AArch64MCExpr::VK_AARCH64_DTPREL_HI12:
257 FixupKind = AArch64::fixup_a64_add_dtprel_hi12; break;
258 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12:
259 FixupKind = AArch64::fixup_a64_add_dtprel_lo12; break;
260 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC:
261 FixupKind = AArch64::fixup_a64_add_dtprel_lo12_nc; break;
262 case AArch64MCExpr::VK_AARCH64_TPREL_HI12:
263 FixupKind = AArch64::fixup_a64_add_tprel_hi12; break;
264 case AArch64MCExpr::VK_AARCH64_TPREL_LO12:
265 FixupKind = AArch64::fixup_a64_add_tprel_lo12; break;
266 case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC:
267 FixupKind = AArch64::fixup_a64_add_tprel_lo12_nc; break;
268 case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12:
269 FixupKind = AArch64::fixup_a64_tlsdesc_add_lo12_nc; break;
272 return getAddressWithFixup(MO, FixupKind, Fixups);
276 AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
277 SmallVectorImpl<MCFixup> &Fixups) const {
279 const MCOperand &MO = MI.getOperand(OpIdx);
281 return static_cast<unsigned>(MO.getImm());
285 unsigned Modifier = AArch64MCExpr::VK_AARCH64_None;
286 if (const AArch64MCExpr *Expr = dyn_cast<AArch64MCExpr>(MO.getExpr()))
287 Modifier = Expr->getKind();
289 unsigned FixupKind = 0;
291 case AArch64MCExpr::VK_AARCH64_None:
292 FixupKind = AArch64::fixup_a64_adr_prel_page;
294 case AArch64MCExpr::VK_AARCH64_GOT:
295 FixupKind = AArch64::fixup_a64_adr_prel_got_page;
297 case AArch64MCExpr::VK_AARCH64_GOTTPREL:
298 FixupKind = AArch64::fixup_a64_adr_gottprel_page;
300 case AArch64MCExpr::VK_AARCH64_TLSDESC:
301 FixupKind = AArch64::fixup_a64_tlsdesc_adr_page;
304 llvm_unreachable("Unknown symbol reference kind for ADRP instruction");
307 return getAddressWithFixup(MO, FixupKind, Fixups);
311 AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
312 SmallVectorImpl<MCFixup> &Fixups) const {
314 const MCOperand &MO = MI.getOperand(OpIdx);
315 assert(MO.isImm() && "Only immediate expected for shift");
317 return ((32 - MO.getImm()) & 0x1f) | (31 - MO.getImm()) << 6;
321 AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
322 SmallVectorImpl<MCFixup> &Fixups) const {
324 const MCOperand &MO = MI.getOperand(OpIdx);
325 assert(MO.isImm() && "Only immediate expected for shift");
327 return ((64 - MO.getImm()) & 0x3f) | (63 - MO.getImm()) << 6;
330 unsigned AArch64MCCodeEmitter::getShiftRightImm8(
331 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
332 return 8 - MI.getOperand(Op).getImm();
335 unsigned AArch64MCCodeEmitter::getShiftRightImm16(
336 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
337 return 16 - MI.getOperand(Op).getImm();
340 unsigned AArch64MCCodeEmitter::getShiftRightImm32(
341 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
342 return 32 - MI.getOperand(Op).getImm();
345 unsigned AArch64MCCodeEmitter::getShiftRightImm64(
346 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
347 return 64 - MI.getOperand(Op).getImm();
350 unsigned AArch64MCCodeEmitter::getShiftLeftImm8(
351 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
352 return MI.getOperand(Op).getImm() - 8;
355 unsigned AArch64MCCodeEmitter::getShiftLeftImm16(
356 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
357 return MI.getOperand(Op).getImm() - 16;
360 unsigned AArch64MCCodeEmitter::getShiftLeftImm32(
361 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
362 return MI.getOperand(Op).getImm() - 32;
365 unsigned AArch64MCCodeEmitter::getShiftLeftImm64(
366 const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const {
367 return MI.getOperand(Op).getImm() - 64;
370 template<AArch64::Fixups fixupDesired> unsigned
371 AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI,
373 SmallVectorImpl<MCFixup> &Fixups) const {
374 const MCOperand &MO = MI.getOperand(OpIdx);
377 return getAddressWithFixup(MO, fixupDesired, Fixups);
384 AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI,
386 SmallVectorImpl<MCFixup> &Fixups) const {
387 const MCOperand &MO = MI.getOperand(OpIdx);
395 if (isa<AArch64MCExpr>(MO.getExpr())) {
396 assert(dyn_cast<AArch64MCExpr>(MO.getExpr())->getKind()
397 == AArch64MCExpr::VK_AARCH64_GOTTPREL
398 && "Invalid symbol modifier for literal load");
399 FixupKind = AArch64::fixup_a64_ld_gottprel_prel19;
401 FixupKind = AArch64::fixup_a64_ld_prel;
404 return getAddressWithFixup(MO, FixupKind, Fixups);
409 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
411 SmallVectorImpl<MCFixup> &Fixups) const {
413 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
414 } else if (MO.isImm()) {
415 return static_cast<unsigned>(MO.getImm());
418 llvm_unreachable("Unable to encode MCOperand!");
423 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
424 SmallVectorImpl<MCFixup> &Fixups) const {
425 const MCOperand &UImm16MO = MI.getOperand(OpIdx);
426 const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1);
428 unsigned Result = static_cast<unsigned>(ShiftMO.getImm()) << 16;
430 if (UImm16MO.isImm()) {
431 Result |= UImm16MO.getImm();
435 const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
436 AArch64::Fixups requestedFixup;
437 switch (A64E->getKind()) {
438 default: llvm_unreachable("unexpected expression modifier");
439 case AArch64MCExpr::VK_AARCH64_ABS_G0:
440 requestedFixup = AArch64::fixup_a64_movw_uabs_g0; break;
441 case AArch64MCExpr::VK_AARCH64_ABS_G0_NC:
442 requestedFixup = AArch64::fixup_a64_movw_uabs_g0_nc; break;
443 case AArch64MCExpr::VK_AARCH64_ABS_G1:
444 requestedFixup = AArch64::fixup_a64_movw_uabs_g1; break;
445 case AArch64MCExpr::VK_AARCH64_ABS_G1_NC:
446 requestedFixup = AArch64::fixup_a64_movw_uabs_g1_nc; break;
447 case AArch64MCExpr::VK_AARCH64_ABS_G2:
448 requestedFixup = AArch64::fixup_a64_movw_uabs_g2; break;
449 case AArch64MCExpr::VK_AARCH64_ABS_G2_NC:
450 requestedFixup = AArch64::fixup_a64_movw_uabs_g2_nc; break;
451 case AArch64MCExpr::VK_AARCH64_ABS_G3:
452 requestedFixup = AArch64::fixup_a64_movw_uabs_g3; break;
453 case AArch64MCExpr::VK_AARCH64_SABS_G0:
454 requestedFixup = AArch64::fixup_a64_movw_sabs_g0; break;
455 case AArch64MCExpr::VK_AARCH64_SABS_G1:
456 requestedFixup = AArch64::fixup_a64_movw_sabs_g1; break;
457 case AArch64MCExpr::VK_AARCH64_SABS_G2:
458 requestedFixup = AArch64::fixup_a64_movw_sabs_g2; break;
459 case AArch64MCExpr::VK_AARCH64_DTPREL_G2:
460 requestedFixup = AArch64::fixup_a64_movw_dtprel_g2; break;
461 case AArch64MCExpr::VK_AARCH64_DTPREL_G1:
462 requestedFixup = AArch64::fixup_a64_movw_dtprel_g1; break;
463 case AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC:
464 requestedFixup = AArch64::fixup_a64_movw_dtprel_g1_nc; break;
465 case AArch64MCExpr::VK_AARCH64_DTPREL_G0:
466 requestedFixup = AArch64::fixup_a64_movw_dtprel_g0; break;
467 case AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC:
468 requestedFixup = AArch64::fixup_a64_movw_dtprel_g0_nc; break;
469 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1:
470 requestedFixup = AArch64::fixup_a64_movw_gottprel_g1; break;
471 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC:
472 requestedFixup = AArch64::fixup_a64_movw_gottprel_g0_nc; break;
473 case AArch64MCExpr::VK_AARCH64_TPREL_G2:
474 requestedFixup = AArch64::fixup_a64_movw_tprel_g2; break;
475 case AArch64MCExpr::VK_AARCH64_TPREL_G1:
476 requestedFixup = AArch64::fixup_a64_movw_tprel_g1; break;
477 case AArch64MCExpr::VK_AARCH64_TPREL_G1_NC:
478 requestedFixup = AArch64::fixup_a64_movw_tprel_g1_nc; break;
479 case AArch64MCExpr::VK_AARCH64_TPREL_G0:
480 requestedFixup = AArch64::fixup_a64_movw_tprel_g0; break;
481 case AArch64MCExpr::VK_AARCH64_TPREL_G0_NC:
482 requestedFixup = AArch64::fixup_a64_movw_tprel_g0_nc; break;
485 return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups);
488 template<int hasRs, int hasRt2> unsigned
489 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
490 unsigned EncodedValue) const {
491 if (!hasRs) EncodedValue |= 0x001F0000;
492 if (!hasRt2) EncodedValue |= 0x00007C00;
498 AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue) const {
499 // If one of the signed fixup kinds is applied to a MOVZ instruction, the
500 // eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
501 // job to ensure that any bits possibly affected by this are 0. This means we
502 // must zero out bit 30 (essentially emitting a MOVN).
503 MCOperand UImm16MO = MI.getOperand(1);
505 // Nothing to do if there's no fixup.
506 if (UImm16MO.isImm())
509 const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
510 switch (A64E->getKind()) {
511 case AArch64MCExpr::VK_AARCH64_SABS_G0:
512 case AArch64MCExpr::VK_AARCH64_SABS_G1:
513 case AArch64MCExpr::VK_AARCH64_SABS_G2:
514 case AArch64MCExpr::VK_AARCH64_DTPREL_G2:
515 case AArch64MCExpr::VK_AARCH64_DTPREL_G1:
516 case AArch64MCExpr::VK_AARCH64_DTPREL_G0:
517 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1:
518 case AArch64MCExpr::VK_AARCH64_TPREL_G2:
519 case AArch64MCExpr::VK_AARCH64_TPREL_G1:
520 case AArch64MCExpr::VK_AARCH64_TPREL_G0:
521 return EncodedValue & ~(1u << 30);
523 // Nothing to do for an unsigned fixup.
527 llvm_unreachable("Should have returned by now");
531 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
532 unsigned EncodedValue) const {
533 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
534 // (i.e. all bits 1) but is ignored by the processor.
535 EncodedValue |= 0x1f << 10;
539 MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
540 const MCRegisterInfo &MRI,
541 const MCSubtargetInfo &STI,
543 return new AArch64MCCodeEmitter(Ctx);
546 void AArch64MCCodeEmitter::
547 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
548 SmallVectorImpl<MCFixup> &Fixups) const {
549 if (MI.getOpcode() == AArch64::TLSDESCCALL) {
550 // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
551 // following (BLR) instruction. It doesn't emit any code itself so it
552 // doesn't go through the normal TableGenerated channels.
553 MCFixupKind Fixup = MCFixupKind(AArch64::fixup_a64_tlsdesc_call);
555 Expr = AArch64MCExpr::CreateTLSDesc(MI.getOperand(0).getExpr(), Ctx);
556 Fixups.push_back(MCFixup::Create(0, Expr, Fixup));
560 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
562 EmitInstruction(Binary, OS);
566 #include "AArch64GenMCCodeEmitter.inc"