1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The Cortex-A15 processor employs a tracking scheme in its register renaming
11 // in order to process each instruction's micro-ops speculatively and
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
13 // instructions to read and write 32-bit S-registers. Each S-register
14 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
16 // There are several instruction patterns which can be used to provide this
17 // capability which can provide higher performance than other, potentially more
18 // direct patterns, specifically around when one micro-op reads a D-register
19 // operand that has recently been written as one or more S-register results.
21 // This file defines a pre-regalloc pass which looks for SPR producers which
22 // are going to be used by a DPR (or QPR) consumers and creates the more
23 // optimized access pattern.
25 //===----------------------------------------------------------------------===//
27 #define DEBUG_TYPE "a15-sd-optimizer"
29 #include "ARMBaseInstrInfo.h"
30 #include "ARMSubtarget.h"
31 #include "ARMISelLowering.h"
32 #include "ARMTargetMachine.h"
34 #include "llvm/ADT/SmallPtrSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
50 struct A15SDOptimizer : public MachineFunctionPass {
52 A15SDOptimizer() : MachineFunctionPass(ID) {}
54 virtual bool runOnMachineFunction(MachineFunction &Fn);
56 virtual const char *getPassName() const {
57 return "ARM A15 S->D optimizer";
61 const ARMBaseInstrInfo *TII;
62 const TargetRegisterInfo *TRI;
63 MachineRegisterInfo *MRI;
65 bool runOnInstruction(MachineInstr *MI);
68 // Instruction builder helpers
70 unsigned createDupLane(MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator InsertBefore,
73 unsigned Reg, unsigned Lane,
76 unsigned createExtractSubreg(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator InsertBefore,
79 unsigned DReg, unsigned Lane,
80 const TargetRegisterClass *TRC);
82 unsigned createVExt(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator InsertBefore,
85 unsigned Ssub0, unsigned Ssub1);
87 unsigned createRegSequence(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator InsertBefore,
90 unsigned Reg1, unsigned Reg2);
92 unsigned createInsertSubreg(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator InsertBefore,
94 DebugLoc DL, unsigned DReg, unsigned Lane,
97 unsigned createImplicitDef(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator InsertBefore,
102 // Various property checkers
104 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
105 bool hasPartialWrite(MachineInstr *MI);
106 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
107 unsigned getDPRLaneFromSPR(unsigned SReg);
110 // Methods used for getting the definitions of partial registers
113 MachineInstr *elideCopies(MachineInstr *MI);
114 void elideCopiesAndPHIs(MachineInstr *MI,
115 SmallVectorImpl<MachineInstr*> &Outs);
118 // Pattern optimization methods
120 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
121 unsigned optimizeSDPattern(MachineInstr *MI);
122 unsigned getPrefSPRLane(unsigned SReg);
125 // Sanitizing method - used to make sure if don't leave dead code around.
127 void eraseInstrWithNoUses(MachineInstr *MI);
130 // A map used to track the changes done by this pass.
132 std::map<MachineInstr*, unsigned> Replacements;
133 std::set<MachineInstr *> DeadInstr;
135 char A15SDOptimizer::ID = 0;
136 } // end anonymous namespace
138 // Returns true if this is a use of a SPR register.
139 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
140 const TargetRegisterClass *TRC) {
143 unsigned Reg = MO.getReg();
145 if (TargetRegisterInfo::isVirtualRegister(Reg))
146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
148 return TRC->contains(Reg);
151 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
152 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
154 if (DReg != ARM::NoRegister) return ARM::ssub_1;
158 // Get the subreg type that is most likely to be coalesced
159 // for an SPR register that will be used in VDUP32d pseudo.
160 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
161 if (!TRI->isVirtualRegister(SReg))
162 return getDPRLaneFromSPR(SReg);
164 MachineInstr *MI = MRI->getVRegDef(SReg);
165 if (!MI) return ARM::ssub_0;
166 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
168 assert(MO->isReg() && "Non register operand found!");
169 if (!MO) return ARM::ssub_0;
171 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
172 &ARM::SPRRegClass)) {
173 SReg = MI->getOperand(1).getReg();
176 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
177 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
180 return getDPRLaneFromSPR(SReg);
183 // MI is known to be dead. Figure out what instructions
184 // are also made dead by this and mark them for removal.
185 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
186 SmallVector<MachineInstr *, 8> Front;
187 DeadInstr.insert(MI);
189 DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
192 while (Front.size() != 0) {
196 // MI is already known to be dead. We need to see
197 // if other instructions can also be removed.
198 for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
199 MachineOperand &MO = MI->getOperand(i);
200 if ((!MO.isReg()) || (!MO.isUse()))
202 unsigned Reg = MO.getReg();
203 if (!TRI->isVirtualRegister(Reg))
205 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
210 MachineInstr *Def = Op->getParent();
212 // We don't need to do anything if we have already marked
213 // this instruction as being dead.
214 if (DeadInstr.find(Def) != DeadInstr.end())
217 // Check if all the uses of this instruction are marked as
218 // dead. If so, we can also mark this instruction as being
221 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
222 MachineOperand &MODef = Def->getOperand(j);
223 if ((!MODef.isReg()) || (!MODef.isDef()))
225 unsigned DefReg = MODef.getReg();
226 if (!TRI->isVirtualRegister(DefReg)) {
230 for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg),
233 // We don't care about self references.
236 if (DeadInstr.find(&*II) == DeadInstr.end()) {
243 if (!IsDead) continue;
245 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
246 DeadInstr.insert(Def);
251 // Creates the more optimized patterns and generally does all the code
252 // transformations in this pass.
253 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
255 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
258 if (MI->isInsertSubreg()) {
259 unsigned DPRReg = MI->getOperand(1).getReg();
260 unsigned SPRReg = MI->getOperand(2).getReg();
262 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
266 if (DPRMI && SPRMI) {
267 // See if the first operand of this insert_subreg is IMPLICIT_DEF
268 MachineInstr *ECDef = elideCopies(DPRMI);
269 if (ECDef != 0 && ECDef->isImplicitDef()) {
270 // Another corner case - if we're inserting something that is purely
271 // a subreg copy of a DPR, just use that DPR.
273 MachineInstr *EC = elideCopies(SPRMI);
274 // Is it a subreg copy of ssub_0?
275 if (EC && EC->isCopy() &&
276 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
277 DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
279 // Find the thing we're subreg copying out of - is it of the same
280 // regclass as DPRMI? (i.e. a DPR or QPR).
281 unsigned FullReg = SPRMI->getOperand(1).getReg();
282 const TargetRegisterClass *TRC =
283 MRI->getRegClass(MI->getOperand(1).getReg());
284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
285 DEBUG(dbgs() << "Subreg copy is compatible - returning ");
286 DEBUG(dbgs() << PrintReg(FullReg) << "\n");
287 eraseInstrWithNoUses(MI);
292 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
296 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
299 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
300 &ARM::SPRRegClass)) {
301 // See if all bar one of the operands are IMPLICIT_DEF and insert the
302 // optimizer pattern accordingly.
303 unsigned NumImplicit = 0, NumTotal = 0;
304 unsigned NonImplicitReg = ~0U;
306 for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
307 if (!MI->getOperand(I).isReg())
310 unsigned OpReg = MI->getOperand(I).getReg();
312 if (!TRI->isVirtualRegister(OpReg))
315 MachineInstr *Def = MRI->getVRegDef(OpReg);
318 if (Def->isImplicitDef())
321 NonImplicitReg = MI->getOperand(I).getReg();
324 if (NumImplicit == NumTotal - 1)
325 return optimizeAllLanesPattern(MI, NonImplicitReg);
327 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
330 assert(0 && "Unhandled update pattern!");
334 // Return true if this MachineInstr inserts a scalar (SPR) value into
335 // a D or Q register.
336 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
337 // The only way we can do a partial register update is through a COPY,
338 // INSERT_SUBREG or REG_SEQUENCE.
339 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
342 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
346 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
352 // Looks through full copies to get the instruction that defines the input
354 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
355 if (!MI->isFullCopy())
357 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
359 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
362 return elideCopies(Def);
365 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
366 // that can produce MI.
367 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
368 SmallVectorImpl<MachineInstr*> &Outs) {
369 // Looking through PHIs may create loops so we need to track what
370 // instructions we have visited before.
371 std::set<MachineInstr *> Reached;
372 SmallVector<MachineInstr *, 8> Front;
374 while (Front.size() != 0) {
378 // If we have already explored this MachineInstr, ignore it.
379 if (Reached.find(MI) != Reached.end())
383 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
384 unsigned Reg = MI->getOperand(I).getReg();
385 if (!TRI->isVirtualRegister(Reg)) {
388 MachineInstr *NewMI = MRI->getVRegDef(Reg);
391 Front.push_back(NewMI);
393 } else if (MI->isFullCopy()) {
394 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
396 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
399 Front.push_back(NewMI);
401 DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
407 // Return the DPR virtual registers that are read by this machine instruction
409 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
410 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
412 return SmallVector<unsigned, 8>();
414 SmallVector<unsigned, 8> Defs;
415 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
416 MachineOperand &MO = MI->getOperand(i);
418 if (!MO.isReg() || !MO.isUse())
420 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
421 !usesRegClass(MO, &ARM::QPRRegClass) &&
422 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
425 Defs.push_back(MO.getReg());
430 // Creates a DPR register from an SPR one by using a VDUP.
432 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
433 MachineBasicBlock::iterator InsertBefore,
435 unsigned Reg, unsigned Lane, bool QPR) {
436 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
438 AddDefaultPred(BuildMI(MBB,
441 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
449 // Creates a SPR register from a DPR by copying the value in lane 0.
451 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator InsertBefore,
454 unsigned DReg, unsigned Lane,
455 const TargetRegisterClass *TRC) {
456 unsigned Out = MRI->createVirtualRegister(TRC);
460 TII->get(TargetOpcode::COPY), Out)
461 .addReg(DReg, 0, Lane);
466 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
468 A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
469 MachineBasicBlock::iterator InsertBefore,
471 unsigned Reg1, unsigned Reg2) {
472 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
476 TII->get(TargetOpcode::REG_SEQUENCE), Out)
480 .addImm(ARM::dsub_1);
484 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
485 // and merges them into one DPR register.
487 A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
488 MachineBasicBlock::iterator InsertBefore,
490 unsigned Ssub0, unsigned Ssub1) {
491 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
492 AddDefaultPred(BuildMI(MBB,
495 TII->get(ARM::VEXTd32), Out)
503 A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
504 MachineBasicBlock::iterator InsertBefore,
505 DebugLoc DL, unsigned DReg, unsigned Lane,
507 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
511 TII->get(TargetOpcode::INSERT_SUBREG), Out)
520 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
521 MachineBasicBlock::iterator InsertBefore,
523 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
527 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
531 // This function inserts instructions in order to optimize interactions between
532 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
533 // lanes, and the using VEXT instructions to recompose the result.
535 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
536 MachineBasicBlock::iterator InsertPt(MI);
537 DebugLoc DL = MI->getDebugLoc();
538 MachineBasicBlock &MBB = *MI->getParent();
542 // DPair has the same length as QPR and also has two DPRs as subreg.
543 // Treat DPair as QPR.
544 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
545 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
546 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
547 ARM::dsub_0, &ARM::DPRRegClass);
548 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
549 ARM::dsub_1, &ARM::DPRRegClass);
551 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
552 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
553 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
555 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
556 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
557 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
559 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
561 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
562 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
563 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
564 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
567 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
568 "Found unexpected regclass!");
570 unsigned PrefLane = getPrefSPRLane(Reg);
573 case ARM::ssub_0: Lane = 0; break;
574 case ARM::ssub_1: Lane = 1; break;
575 default: llvm_unreachable("Unknown preferred lane!");
578 // Treat DPair as QPR
579 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
580 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
582 Out = createImplicitDef(MBB, InsertPt, DL);
583 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
584 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
585 eraseInstrWithNoUses(MI);
590 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
591 // We look for instructions that write S registers that are then read as
592 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
593 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
594 // merge two SPR values to form a DPR register. In order avoid false
595 // positives we make sure that there is an SPR producer so we look past
596 // COPY and PHI nodes to find it.
598 // The best code pattern for when an SPR producer is going to be used by a
599 // DPR or QPR consumer depends on whether the other lanes of the
600 // corresponding DPR/QPR are currently defined.
602 // We can handle these efficiently, depending on the type of
603 // pseudo-instruction that is producing the pattern
605 // * COPY: * VDUP all lanes and merge the results together
608 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
609 // lane, and the other lane(s) of the DPR/QPR register
610 // that we are inserting in are undefined, use the
611 // original DPR/QPR value.
612 // * Otherwise, fall back on the same stategy as COPY.
614 // * REG_SEQUENCE: * If all except one of the input operands are
615 // IMPLICIT_DEFs, insert the VDUP pattern for just the
616 // defined input operand
617 // * Otherwise, fall back on the same stategy as COPY.
620 // First, get all the reads of D-registers done by this instruction.
621 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
622 bool Modified = false;
624 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
626 // Follow the def-use chain for this DPR through COPYs, and also through
627 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
628 // we can end up with multiple defs of this DPR.
630 SmallVector<MachineInstr *, 8> DefSrcs;
631 if (!TRI->isVirtualRegister(*I))
633 MachineInstr *Def = MRI->getVRegDef(*I);
637 elideCopiesAndPHIs(Def, DefSrcs);
639 for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
640 EE = DefSrcs.end(); II != EE; ++II) {
641 MachineInstr *MI = *II;
643 // If we've already analyzed and replaced this operand, don't do
645 if (Replacements.find(MI) != Replacements.end())
648 // Now, work out if the instruction causes a SPR->DPR dependency.
649 if (!hasPartialWrite(MI))
652 // Collect all the uses of this MI's DPR def for updating later.
653 SmallVector<MachineOperand*, 8> Uses;
654 unsigned DPRDefReg = MI->getOperand(0).getReg();
655 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
656 E = MRI->use_end(); I != E; ++I)
657 Uses.push_back(&I.getOperand());
659 // We can optimize this.
660 unsigned NewReg = optimizeSDPattern(MI);
664 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
665 E = Uses.end(); I != E; ++I) {
666 // Make sure to constrain the register class of the new register to
667 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
668 // reference into a plain DPR, and that will end poorly. NewReg is
669 // always virtual here, so there will always be a matching subclass
671 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
673 DEBUG(dbgs() << "Replacing operand "
675 << PrintReg(NewReg) << "\n");
676 (*I)->substVirtReg(NewReg, 0, *TRI);
679 Replacements[MI] = NewReg;
685 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
686 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
687 TRI = Fn.getTarget().getRegisterInfo();
688 MRI = &Fn.getRegInfo();
689 bool Modified = false;
691 DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
694 Replacements.clear();
696 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
699 for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
701 Modified |= runOnInstruction(MI++);
706 for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
709 (*I)->eraseFromParent();
715 FunctionPass *llvm::createA15SDOptimizerPass() {
716 return new A15SDOptimizer();