1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFPUName.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/ADT/SetVector.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/DebugInfo.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DataLayout.h"
36 #include "llvm/IR/Module.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCAssembler.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCELFStreamer.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCObjectStreamer.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/MC/MCStreamer.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/Mangler.h"
55 #include "llvm/Target/TargetMachine.h"
59 /// EmitDwarfRegOp - Emit dwarf register operation.
60 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
61 bool Indirect) const {
62 const TargetRegisterInfo *RI = TM.getRegisterInfo();
63 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
64 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
67 assert(MLoc.isReg() && !Indirect &&
68 "This doesn't support offset/indirection - implement it if needed");
69 unsigned Reg = MLoc.getReg();
70 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
71 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
72 // S registers are described as bit-pieces of a register
73 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
74 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
76 unsigned SReg = Reg - ARM::S0;
77 bool odd = SReg & 0x1;
78 unsigned Rx = 256 + (SReg >> 1);
80 OutStreamer.AddComment("DW_OP_regx for S register");
81 EmitInt8(dwarf::DW_OP_regx);
83 OutStreamer.AddComment(Twine(SReg));
87 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
88 EmitInt8(dwarf::DW_OP_bit_piece);
92 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
93 EmitInt8(dwarf::DW_OP_bit_piece);
97 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
98 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
99 // Q registers Q0-Q15 are described by composing two D registers together.
100 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
103 unsigned QReg = Reg - ARM::Q0;
104 unsigned D1 = 256 + 2 * QReg;
105 unsigned D2 = D1 + 1;
107 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
108 EmitInt8(dwarf::DW_OP_regx);
110 OutStreamer.AddComment("DW_OP_piece 8");
111 EmitInt8(dwarf::DW_OP_piece);
114 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
115 EmitInt8(dwarf::DW_OP_regx);
117 OutStreamer.AddComment("DW_OP_piece 8");
118 EmitInt8(dwarf::DW_OP_piece);
123 void ARMAsmPrinter::EmitFunctionBodyEnd() {
124 // Make sure to terminate any constant pools that were at the end
128 InConstantPool = false;
129 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
132 void ARMAsmPrinter::EmitFunctionEntryLabel() {
133 if (AFI->isThumbFunction()) {
134 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
135 OutStreamer.EmitThumbFunc(CurrentFnSym);
138 OutStreamer.EmitLabel(CurrentFnSym);
141 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
142 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
143 assert(Size && "C++ constructor pointer had zero size!");
145 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
146 assert(GV && "C++ constructor pointer was not a GlobalValue!");
148 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
149 (Subtarget->isTargetDarwin()
150 ? MCSymbolRefExpr::VK_None
151 : MCSymbolRefExpr::VK_ARM_TARGET1),
154 OutStreamer.EmitValue(E, Size);
157 /// runOnMachineFunction - This uses the EmitInstruction()
158 /// method to print assembly for each instruction.
160 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
161 AFI = MF.getInfo<ARMFunctionInfo>();
162 MCP = MF.getConstantPool();
164 return AsmPrinter::runOnMachineFunction(MF);
167 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
168 raw_ostream &O, const char *Modifier) {
169 const MachineOperand &MO = MI->getOperand(OpNum);
170 unsigned TF = MO.getTargetFlags();
172 switch (MO.getType()) {
173 default: llvm_unreachable("<unknown operand type>");
174 case MachineOperand::MO_Register: {
175 unsigned Reg = MO.getReg();
176 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
177 assert(!MO.getSubReg() && "Subregs should be eliminated!");
178 if(ARM::GPRPairRegClass.contains(Reg)) {
179 const MachineFunction &MF = *MI->getParent()->getParent();
180 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
181 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
183 O << ARMInstPrinter::getRegisterName(Reg);
186 case MachineOperand::MO_Immediate: {
187 int64_t Imm = MO.getImm();
189 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
190 (TF == ARMII::MO_LO16))
192 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
193 (TF == ARMII::MO_HI16))
198 case MachineOperand::MO_MachineBasicBlock:
199 O << *MO.getMBB()->getSymbol();
201 case MachineOperand::MO_GlobalAddress: {
202 const GlobalValue *GV = MO.getGlobal();
203 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
204 (TF & ARMII::MO_LO16))
206 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
207 (TF & ARMII::MO_HI16))
211 printOffset(MO.getOffset(), O);
212 if (TF == ARMII::MO_PLT)
216 case MachineOperand::MO_ExternalSymbol: {
217 O << *GetExternalSymbolSymbol(MO.getSymbolName());
218 if (TF == ARMII::MO_PLT)
222 case MachineOperand::MO_ConstantPoolIndex:
223 O << *GetCPISymbol(MO.getIndex());
225 case MachineOperand::MO_JumpTableIndex:
226 O << *GetJTISymbol(MO.getIndex());
231 //===--------------------------------------------------------------------===//
233 MCSymbol *ARMAsmPrinter::
234 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
235 SmallString<60> Name;
236 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
237 << getFunctionNumber() << '_' << uid << '_' << uid2;
238 return OutContext.GetOrCreateSymbol(Name.str());
242 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
243 SmallString<60> Name;
244 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
245 << getFunctionNumber();
246 return OutContext.GetOrCreateSymbol(Name.str());
249 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
250 unsigned AsmVariant, const char *ExtraCode,
252 // Does this asm operand have a single letter operand modifier?
253 if (ExtraCode && ExtraCode[0]) {
254 if (ExtraCode[1] != 0) return true; // Unknown modifier.
256 switch (ExtraCode[0]) {
258 // See if this is a generic print operand
259 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
260 case 'a': // Print as a memory address.
261 if (MI->getOperand(OpNum).isReg()) {
263 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
268 case 'c': // Don't print "#" before an immediate operand.
269 if (!MI->getOperand(OpNum).isImm())
271 O << MI->getOperand(OpNum).getImm();
273 case 'P': // Print a VFP double precision register.
274 case 'q': // Print a NEON quad precision register.
275 printOperand(MI, OpNum, O);
277 case 'y': // Print a VFP single precision register as indexed double.
278 if (MI->getOperand(OpNum).isReg()) {
279 unsigned Reg = MI->getOperand(OpNum).getReg();
280 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
281 // Find the 'd' register that has this 's' register as a sub-register,
282 // and determine the lane number.
283 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
284 if (!ARM::DPRRegClass.contains(*SR))
286 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
287 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
292 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
293 if (!MI->getOperand(OpNum).isImm())
295 O << ~(MI->getOperand(OpNum).getImm());
297 case 'L': // The low 16 bits of an immediate constant.
298 if (!MI->getOperand(OpNum).isImm())
300 O << (MI->getOperand(OpNum).getImm() & 0xffff);
302 case 'M': { // A register range suitable for LDM/STM.
303 if (!MI->getOperand(OpNum).isReg())
305 const MachineOperand &MO = MI->getOperand(OpNum);
306 unsigned RegBegin = MO.getReg();
307 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
308 // already got the operands in registers that are operands to the
309 // inline asm statement.
311 if (ARM::GPRPairRegClass.contains(RegBegin)) {
312 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
313 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
314 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
315 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
317 O << ARMInstPrinter::getRegisterName(RegBegin);
319 // FIXME: The register allocator not only may not have given us the
320 // registers in sequence, but may not be in ascending registers. This
321 // will require changes in the register allocator that'll need to be
322 // propagated down here if the operands change.
323 unsigned RegOps = OpNum + 1;
324 while (MI->getOperand(RegOps).isReg()) {
326 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
334 case 'R': // The most significant register of a pair.
335 case 'Q': { // The least significant register of a pair.
338 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
339 if (!FlagsOP.isImm())
341 unsigned Flags = FlagsOP.getImm();
343 // This operand may not be the one that actually provides the register. If
344 // it's tied to a previous one then we should refer instead to that one
345 // for registers and their classes.
347 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
348 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
349 unsigned OpFlags = MI->getOperand(OpNum).getImm();
350 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
352 Flags = MI->getOperand(OpNum).getImm();
354 // Later code expects OpNum to be pointing at the register rather than
359 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
361 InlineAsm::hasRegClassConstraint(Flags, RC);
362 if (RC == ARM::GPRPairRegClassID) {
365 const MachineOperand &MO = MI->getOperand(OpNum);
368 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
369 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
370 ARM::gsub_0 : ARM::gsub_1);
371 O << ARMInstPrinter::getRegisterName(Reg);
376 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
377 if (RegOp >= MI->getNumOperands())
379 const MachineOperand &MO = MI->getOperand(RegOp);
382 unsigned Reg = MO.getReg();
383 O << ARMInstPrinter::getRegisterName(Reg);
387 case 'e': // The low doubleword register of a NEON quad register.
388 case 'f': { // The high doubleword register of a NEON quad register.
389 if (!MI->getOperand(OpNum).isReg())
391 unsigned Reg = MI->getOperand(OpNum).getReg();
392 if (!ARM::QPRRegClass.contains(Reg))
394 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
395 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
396 ARM::dsub_0 : ARM::dsub_1);
397 O << ARMInstPrinter::getRegisterName(SubReg);
401 // This modifier is not yet supported.
402 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
404 case 'H': { // The highest-numbered register of a pair.
405 const MachineOperand &MO = MI->getOperand(OpNum);
408 const MachineFunction &MF = *MI->getParent()->getParent();
409 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
410 unsigned Reg = MO.getReg();
411 if(!ARM::GPRPairRegClass.contains(Reg))
413 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
414 O << ARMInstPrinter::getRegisterName(Reg);
420 printOperand(MI, OpNum, O);
424 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
425 unsigned OpNum, unsigned AsmVariant,
426 const char *ExtraCode,
428 // Does this asm operand have a single letter operand modifier?
429 if (ExtraCode && ExtraCode[0]) {
430 if (ExtraCode[1] != 0) return true; // Unknown modifier.
432 switch (ExtraCode[0]) {
433 case 'A': // A memory operand for a VLD1/VST1 instruction.
434 default: return true; // Unknown modifier.
435 case 'm': // The base register of a memory operand.
436 if (!MI->getOperand(OpNum).isReg())
438 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
443 const MachineOperand &MO = MI->getOperand(OpNum);
444 assert(MO.isReg() && "unexpected inline asm memory operand");
445 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
449 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
450 if (Subtarget->isTargetDarwin()) {
451 Reloc::Model RelocM = TM.getRelocationModel();
452 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
453 // Declare all the text sections up front (before the DWARF sections
454 // emitted by AsmPrinter::doInitialization) so the assembler will keep
455 // them together at the beginning of the object file. This helps
456 // avoid out-of-range branches that are due a fundamental limitation of
457 // the way symbol offsets are encoded with the current Darwin ARM
459 const TargetLoweringObjectFileMachO &TLOFMacho =
460 static_cast<const TargetLoweringObjectFileMachO &>(
461 getObjFileLowering());
463 // Collect the set of sections our functions will go into.
464 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
465 SmallPtrSet<const MCSection *, 8> > TextSections;
466 // Default text section comes first.
467 TextSections.insert(TLOFMacho.getTextSection());
468 // Now any user defined text sections from function attributes.
469 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
470 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
471 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
472 // Now the coalescable sections.
473 TextSections.insert(TLOFMacho.getTextCoalSection());
474 TextSections.insert(TLOFMacho.getConstTextCoalSection());
476 // Emit the sections in the .s file header to fix the order.
477 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
478 OutStreamer.SwitchSection(TextSections[i]);
480 if (RelocM == Reloc::DynamicNoPIC) {
481 const MCSection *sect =
482 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
483 MCSectionMachO::S_SYMBOL_STUBS,
484 12, SectionKind::getText());
485 OutStreamer.SwitchSection(sect);
487 const MCSection *sect =
488 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
489 MCSectionMachO::S_SYMBOL_STUBS,
490 16, SectionKind::getText());
491 OutStreamer.SwitchSection(sect);
493 const MCSection *StaticInitSect =
494 OutContext.getMachOSection("__TEXT", "__StaticInit",
495 MCSectionMachO::S_REGULAR |
496 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
497 SectionKind::getText());
498 OutStreamer.SwitchSection(StaticInitSect);
502 // Use unified assembler syntax.
503 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
505 // Emit ARM Build Attributes
506 if (Subtarget->isTargetELF())
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512 if (Subtarget->isTargetDarwin()) {
513 // All darwin targets use mach-o.
514 const TargetLoweringObjectFileMachO &TLOFMacho =
515 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516 MachineModuleInfoMachO &MMIMacho =
517 MMI->getObjFileInfo<MachineModuleInfoMachO>();
519 // Output non-lazy-pointers for external and common global variables.
520 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
522 if (!Stubs.empty()) {
523 // Switch with ".non_lazy_symbol_pointer" directive.
524 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
526 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
528 OutStreamer.EmitLabel(Stubs[i].first);
529 // .indirect_symbol _foo
530 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
531 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
534 // External to current translation unit.
535 OutStreamer.EmitIntValue(0, 4/*size*/);
537 // Internal to current translation unit.
539 // When we place the LSDA into the TEXT section, the type info
540 // pointers need to be indirect and pc-rel. We accomplish this by
541 // using NLPs; however, sometimes the types are local to the file.
542 // We need to fill in the value for the NLP in those cases.
543 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
549 OutStreamer.AddBlankLine();
552 Stubs = MMIMacho.GetHiddenGVStubList();
553 if (!Stubs.empty()) {
554 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
556 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
558 OutStreamer.EmitLabel(Stubs[i].first);
560 OutStreamer.EmitValue(MCSymbolRefExpr::
561 Create(Stubs[i].second.getPointer(),
567 OutStreamer.AddBlankLine();
570 // Funny Darwin hack: This flag tells the linker that no global symbols
571 // contain code that falls through to other global symbols (e.g. the obvious
572 // implementation of multiple entry points). If this doesn't occur, the
573 // linker can safely perform dead code stripping. Since LLVM never
574 // generates code that does this, it is always safe to set.
575 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
579 //===----------------------------------------------------------------------===//
580 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
582 // The following seem like one-off assembler flags, but they actually need
583 // to appear in the .ARM.attributes section in ELF.
584 // Instead of subclassing the MCELFStreamer, we do the work here.
586 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
587 const ARMSubtarget *Subtarget) {
589 return ARMBuildAttrs::v5TEJ;
591 if (Subtarget->hasV8Ops())
592 return ARMBuildAttrs::v8;
593 else if (Subtarget->hasV7Ops()) {
594 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
595 return ARMBuildAttrs::v7E_M;
596 return ARMBuildAttrs::v7;
597 } else if (Subtarget->hasV6T2Ops())
598 return ARMBuildAttrs::v6T2;
599 else if (Subtarget->hasV6MOps())
600 return ARMBuildAttrs::v6S_M;
601 else if (Subtarget->hasV6Ops())
602 return ARMBuildAttrs::v6;
603 else if (Subtarget->hasV5TEOps())
604 return ARMBuildAttrs::v5TE;
605 else if (Subtarget->hasV5TOps())
606 return ARMBuildAttrs::v5T;
607 else if (Subtarget->hasV4TOps())
608 return ARMBuildAttrs::v4T;
610 return ARMBuildAttrs::v4;
613 void ARMAsmPrinter::emitAttributes() {
614 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
615 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
617 ATS.switchVendor("aeabi");
619 std::string CPUString = Subtarget->getCPUString();
621 if (CPUString != "generic")
622 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
624 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
625 getArchForCPU(CPUString, Subtarget));
627 if (Subtarget->isAClass()) {
628 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
629 ARMBuildAttrs::ApplicationProfile);
630 } else if (Subtarget->isRClass()) {
631 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
632 ARMBuildAttrs::RealTimeProfile);
633 } else if (Subtarget->isMClass()){
634 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
635 ARMBuildAttrs::MicroControllerProfile);
638 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
639 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
640 if (Subtarget->isThumb1Only()) {
641 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
642 ARMBuildAttrs::Allowed);
643 } else if (Subtarget->hasThumb2()) {
644 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
645 ARMBuildAttrs::AllowThumb32);
648 if (Subtarget->hasNEON()) {
649 /* NEON is not exactly a VFP architecture, but GAS emit one of
650 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
651 if (Subtarget->hasFPARMv8()) {
652 if (Subtarget->hasCrypto())
653 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
655 ATS.emitFPU(ARM::NEON_FP_ARMV8);
657 else if (Subtarget->hasVFP4())
658 ATS.emitFPU(ARM::NEON_VFPV4);
660 ATS.emitFPU(ARM::NEON);
661 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
662 if (Subtarget->hasV8Ops())
663 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
664 ARMBuildAttrs::AllowNeonARMv8);
666 if (Subtarget->hasFPARMv8())
667 ATS.emitFPU(ARM::FP_ARMV8);
668 else if (Subtarget->hasVFP4())
669 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
670 else if (Subtarget->hasVFP3())
671 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
672 else if (Subtarget->hasVFP2())
673 ATS.emitFPU(ARM::VFPV2);
676 // Signal various FP modes.
677 if (!TM.Options.UnsafeFPMath) {
678 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
679 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
680 ARMBuildAttrs::Allowed);
683 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
684 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
685 ARMBuildAttrs::Allowed);
687 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
688 ARMBuildAttrs::AllowIEE754);
690 // FIXME: add more flags to ARMBuildAttrs.h
691 // 8-bytes alignment stuff.
692 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
693 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
695 // ABI_HardFP_use attribute to indicate single precision FP.
696 if (Subtarget->isFPOnlySP())
697 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
698 ARMBuildAttrs::HardFPSinglePrecision);
700 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
701 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
702 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
704 // FIXME: Should we signal R9 usage?
706 if (Subtarget->hasFP16())
707 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
709 if (Subtarget->hasMPExtension())
710 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
712 if (Subtarget->hasDivide()) {
713 // Check if hardware divide is only available in thumb2 or ARM as well.
714 ATS.emitAttribute(ARMBuildAttrs::DIV_use,
715 Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
716 ARMBuildAttrs::AllowDIVIfExists);
719 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
720 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
721 ARMBuildAttrs::AllowTZVirtualization);
722 else if (Subtarget->hasTrustZone())
723 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
724 ARMBuildAttrs::AllowTZ);
725 else if (Subtarget->hasVirtualization())
726 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
727 ARMBuildAttrs::AllowVirtualization);
729 ATS.finishAttributeSection();
732 void ARMAsmPrinter::emitARMAttributeSection() {
734 // [ <section-length> "vendor-name"
735 // [ <file-tag> <size> <attribute>*
736 // | <section-tag> <size> <section-number>* 0 <attribute>*
737 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
741 if (OutStreamer.hasRawTextSupport())
744 const ARMElfTargetObjectFile &TLOFELF =
745 static_cast<const ARMElfTargetObjectFile &>
746 (getObjFileLowering());
748 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
751 OutStreamer.EmitIntValue(0x41, 1);
754 //===----------------------------------------------------------------------===//
756 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
757 unsigned LabelId, MCContext &Ctx) {
759 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
760 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
764 static MCSymbolRefExpr::VariantKind
765 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
767 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
768 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
769 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
770 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
771 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
772 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
774 llvm_unreachable("Invalid ARMCPModifier!");
777 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
778 bool isIndirect = Subtarget->isTargetDarwin() &&
779 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
781 return getSymbol(GV);
783 // FIXME: Remove this when Darwin transition to @GOT like syntax.
784 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
785 MachineModuleInfoMachO &MMIMachO =
786 MMI->getObjFileInfo<MachineModuleInfoMachO>();
787 MachineModuleInfoImpl::StubValueTy &StubSym =
788 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
789 MMIMachO.getGVStubEntry(MCSym);
790 if (StubSym.getPointer() == 0)
791 StubSym = MachineModuleInfoImpl::
792 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
797 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
798 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
800 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
803 if (ACPV->isLSDA()) {
804 SmallString<128> Str;
805 raw_svector_ostream OS(Str);
806 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
807 MCSym = OutContext.GetOrCreateSymbol(OS.str());
808 } else if (ACPV->isBlockAddress()) {
809 const BlockAddress *BA =
810 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
811 MCSym = GetBlockAddressSymbol(BA);
812 } else if (ACPV->isGlobalValue()) {
813 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
814 MCSym = GetARMGVSymbol(GV);
815 } else if (ACPV->isMachineBasicBlock()) {
816 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
817 MCSym = MBB->getSymbol();
819 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
820 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
821 MCSym = GetExternalSymbolSymbol(Sym);
824 // Create an MCSymbol for the reference.
826 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
829 if (ACPV->getPCAdjustment()) {
830 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
834 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
836 MCBinaryExpr::CreateAdd(PCRelExpr,
837 MCConstantExpr::Create(ACPV->getPCAdjustment(),
840 if (ACPV->mustAddCurrentAddress()) {
841 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
842 // label, so just emit a local label end reference that instead.
843 MCSymbol *DotSym = OutContext.CreateTempSymbol();
844 OutStreamer.EmitLabel(DotSym);
845 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
846 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
848 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
850 OutStreamer.EmitValue(Expr, Size);
853 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
854 unsigned Opcode = MI->getOpcode();
856 if (Opcode == ARM::BR_JTadd)
858 else if (Opcode == ARM::BR_JTm)
861 const MachineOperand &MO1 = MI->getOperand(OpNum);
862 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
863 unsigned JTI = MO1.getIndex();
865 // Emit a label for the jump table.
866 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
867 OutStreamer.EmitLabel(JTISymbol);
869 // Mark the jump table as data-in-code.
870 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
872 // Emit each entry of the table.
873 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
874 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
875 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
877 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
878 MachineBasicBlock *MBB = JTBBs[i];
879 // Construct an MCExpr for the entry. We want a value of the form:
880 // (BasicBlockAddr - TableBeginAddr)
882 // For example, a table with entries jumping to basic blocks BB0 and BB1
885 // .word (LBB0 - LJTI_0_0)
886 // .word (LBB1 - LJTI_0_0)
887 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
889 if (TM.getRelocationModel() == Reloc::PIC_)
890 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
893 // If we're generating a table of Thumb addresses in static relocation
894 // model, we need to add one to keep interworking correctly.
895 else if (AFI->isThumbFunction())
896 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
898 OutStreamer.EmitValue(Expr, 4);
900 // Mark the end of jump table data-in-code region.
901 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
904 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
905 unsigned Opcode = MI->getOpcode();
906 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
907 const MachineOperand &MO1 = MI->getOperand(OpNum);
908 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
909 unsigned JTI = MO1.getIndex();
911 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
912 OutStreamer.EmitLabel(JTISymbol);
914 // Emit each entry of the table.
915 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
916 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
917 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
918 unsigned OffsetWidth = 4;
919 if (MI->getOpcode() == ARM::t2TBB_JT) {
921 // Mark the jump table as data-in-code.
922 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
923 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
925 // Mark the jump table as data-in-code.
926 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
929 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
930 MachineBasicBlock *MBB = JTBBs[i];
931 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
933 // If this isn't a TBB or TBH, the entries are direct branch instructions.
934 if (OffsetWidth == 4) {
935 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
936 .addExpr(MBBSymbolExpr)
941 // Otherwise it's an offset from the dispatch instruction. Construct an
942 // MCExpr for the entry. We want a value of the form:
943 // (BasicBlockAddr - TableBeginAddr) / 2
945 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
948 // .byte (LBB0 - LJTI_0_0) / 2
949 // .byte (LBB1 - LJTI_0_0) / 2
951 MCBinaryExpr::CreateSub(MBBSymbolExpr,
952 MCSymbolRefExpr::Create(JTISymbol, OutContext),
954 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
956 OutStreamer.EmitValue(Expr, OffsetWidth);
958 // Mark the end of jump table data-in-code region. 32-bit offsets use
959 // actual branch instructions here, so we don't mark those as a data-region
961 if (OffsetWidth != 4)
962 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
965 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
966 assert(MI->getFlag(MachineInstr::FrameSetup) &&
967 "Only instruction which are involved into frame setup code are allowed");
969 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
970 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
971 const MachineFunction &MF = *MI->getParent()->getParent();
972 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
973 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
975 unsigned FramePtr = RegInfo->getFrameRegister(MF);
976 unsigned Opc = MI->getOpcode();
977 unsigned SrcReg, DstReg;
979 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
980 // Two special cases:
981 // 1) tPUSH does not have src/dst regs.
982 // 2) for Thumb1 code we sometimes materialize the constant via constpool
983 // load. Yes, this is pretty fragile, but for now I don't see better
985 SrcReg = DstReg = ARM::SP;
987 SrcReg = MI->getOperand(1).getReg();
988 DstReg = MI->getOperand(0).getReg();
991 // Try to figure out the unwinding opcode out of src / dst regs.
992 if (MI->mayStore()) {
994 assert(DstReg == ARM::SP &&
995 "Only stack pointer as a destination reg is supported");
997 SmallVector<unsigned, 4> RegList;
998 // Skip src & dst reg, and pred ops.
999 unsigned StartOp = 2 + 2;
1000 // Use all the operands.
1001 unsigned NumOffset = 0;
1006 llvm_unreachable("Unsupported opcode for unwinding information");
1008 // Special case here: no src & dst reg, but two extra imp ops.
1009 StartOp = 2; NumOffset = 2;
1010 case ARM::STMDB_UPD:
1011 case ARM::t2STMDB_UPD:
1012 case ARM::VSTMDDB_UPD:
1013 assert(SrcReg == ARM::SP &&
1014 "Only stack pointer as a source reg is supported");
1015 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1017 const MachineOperand &MO = MI->getOperand(i);
1018 // Actually, there should never be any impdef stuff here. Skip it
1019 // temporary to workaround PR11902.
1020 if (MO.isImplicit())
1022 RegList.push_back(MO.getReg());
1025 case ARM::STR_PRE_IMM:
1026 case ARM::STR_PRE_REG:
1027 case ARM::t2STR_PRE:
1028 assert(MI->getOperand(2).getReg() == ARM::SP &&
1029 "Only stack pointer as a source reg is supported");
1030 RegList.push_back(SrcReg);
1033 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1035 // Changes of stack / frame pointer.
1036 if (SrcReg == ARM::SP) {
1041 llvm_unreachable("Unsupported opcode for unwinding information");
1047 Offset = -MI->getOperand(2).getImm();
1051 Offset = MI->getOperand(2).getImm();
1054 Offset = MI->getOperand(2).getImm()*4;
1058 Offset = -MI->getOperand(2).getImm()*4;
1060 case ARM::tLDRpci: {
1061 // Grab the constpool index and check, whether it corresponds to
1062 // original or cloned constpool entry.
1063 unsigned CPI = MI->getOperand(1).getIndex();
1064 const MachineConstantPool *MCP = MF.getConstantPool();
1065 if (CPI >= MCP->getConstants().size())
1066 CPI = AFI.getOriginalCPIdx(CPI);
1067 assert(CPI != -1U && "Invalid constpool index");
1069 // Derive the actual offset.
1070 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1071 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1072 // FIXME: Check for user, it should be "add" instruction!
1073 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1078 if (DstReg == FramePtr && FramePtr != ARM::SP)
1079 // Set-up of the frame pointer. Positive values correspond to "add"
1081 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1082 else if (DstReg == ARM::SP) {
1083 // Change of SP by an offset. Positive values correspond to "sub"
1085 ATS.emitPad(Offset);
1088 llvm_unreachable("Unsupported opcode for unwinding information");
1090 } else if (DstReg == ARM::SP) {
1091 // FIXME: .movsp goes here
1093 llvm_unreachable("Unsupported opcode for unwinding information");
1097 llvm_unreachable("Unsupported opcode for unwinding information");
1102 extern cl::opt<bool> EnableARMEHABI;
1104 // Simple pseudo-instructions have their lowering (with expansion to real
1105 // instructions) auto-generated.
1106 #include "ARMGenMCPseudoLowering.inc"
1108 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1109 // If we just ended a constant pool, mark it as such.
1110 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1111 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1112 InConstantPool = false;
1115 // Emit unwinding stuff for frame-related instructions
1116 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1117 EmitUnwindingInstruction(MI);
1119 // Do any auto-generated pseudo lowerings.
1120 if (emitPseudoExpansionLowering(OutStreamer, MI))
1123 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1124 "Pseudo flag setting opcode should be expanded early");
1126 // Check for manual lowerings.
1127 unsigned Opc = MI->getOpcode();
1129 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1130 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1132 case ARM::tLEApcrel:
1133 case ARM::t2LEApcrel: {
1134 // FIXME: Need to also handle globals and externals
1135 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1136 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1137 ARM::t2LEApcrel ? ARM::t2ADR
1138 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1140 .addReg(MI->getOperand(0).getReg())
1141 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1142 // Add predicate operands.
1143 .addImm(MI->getOperand(2).getImm())
1144 .addReg(MI->getOperand(3).getReg()));
1147 case ARM::LEApcrelJT:
1148 case ARM::tLEApcrelJT:
1149 case ARM::t2LEApcrelJT: {
1150 MCSymbol *JTIPICSymbol =
1151 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1152 MI->getOperand(2).getImm());
1153 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1154 ARM::t2LEApcrelJT ? ARM::t2ADR
1155 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1157 .addReg(MI->getOperand(0).getReg())
1158 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1159 // Add predicate operands.
1160 .addImm(MI->getOperand(3).getImm())
1161 .addReg(MI->getOperand(4).getReg()));
1164 // Darwin call instructions are just normal call instructions with different
1165 // clobber semantics (they clobber R9).
1166 case ARM::BX_CALL: {
1167 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1170 // Add predicate operands.
1173 // Add 's' bit operand (always reg0 for this)
1176 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1177 .addReg(MI->getOperand(0).getReg()));
1180 case ARM::tBX_CALL: {
1181 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1184 // Add predicate operands.
1188 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1189 .addReg(MI->getOperand(0).getReg())
1190 // Add predicate operands.
1195 case ARM::BMOVPCRX_CALL: {
1196 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1199 // Add predicate operands.
1202 // Add 's' bit operand (always reg0 for this)
1205 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1207 .addReg(MI->getOperand(0).getReg())
1208 // Add predicate operands.
1211 // Add 's' bit operand (always reg0 for this)
1215 case ARM::BMOVPCB_CALL: {
1216 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1219 // Add predicate operands.
1222 // Add 's' bit operand (always reg0 for this)
1225 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1226 MCSymbol *GVSym = getSymbol(GV);
1227 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1228 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1230 // Add predicate operands.
1235 case ARM::MOVi16_ga_pcrel:
1236 case ARM::t2MOVi16_ga_pcrel: {
1238 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1239 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1241 unsigned TF = MI->getOperand(1).getTargetFlags();
1242 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1243 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1244 MCSymbol *GVSym = GetARMGVSymbol(GV);
1245 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1247 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1248 getFunctionNumber(),
1249 MI->getOperand(2).getImm(), OutContext);
1250 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1251 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1252 const MCExpr *PCRelExpr =
1253 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1254 MCBinaryExpr::CreateAdd(LabelSymExpr,
1255 MCConstantExpr::Create(PCAdj, OutContext),
1256 OutContext), OutContext), OutContext);
1257 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1259 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1260 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1263 // Add predicate operands.
1264 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1265 TmpInst.addOperand(MCOperand::CreateReg(0));
1266 // Add 's' bit operand (always reg0 for this)
1267 TmpInst.addOperand(MCOperand::CreateReg(0));
1268 OutStreamer.EmitInstruction(TmpInst);
1271 case ARM::MOVTi16_ga_pcrel:
1272 case ARM::t2MOVTi16_ga_pcrel: {
1274 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1275 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1276 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1277 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1279 unsigned TF = MI->getOperand(2).getTargetFlags();
1280 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1281 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1282 MCSymbol *GVSym = GetARMGVSymbol(GV);
1283 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1285 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1286 getFunctionNumber(),
1287 MI->getOperand(3).getImm(), OutContext);
1288 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1289 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1290 const MCExpr *PCRelExpr =
1291 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1292 MCBinaryExpr::CreateAdd(LabelSymExpr,
1293 MCConstantExpr::Create(PCAdj, OutContext),
1294 OutContext), OutContext), OutContext);
1295 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1297 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1298 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1300 // Add predicate operands.
1301 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1302 TmpInst.addOperand(MCOperand::CreateReg(0));
1303 // Add 's' bit operand (always reg0 for this)
1304 TmpInst.addOperand(MCOperand::CreateReg(0));
1305 OutStreamer.EmitInstruction(TmpInst);
1308 case ARM::tPICADD: {
1309 // This is a pseudo op for a label + instruction sequence, which looks like:
1312 // This adds the address of LPC0 to r0.
1315 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1316 getFunctionNumber(), MI->getOperand(2).getImm(),
1319 // Form and emit the add.
1320 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1321 .addReg(MI->getOperand(0).getReg())
1322 .addReg(MI->getOperand(0).getReg())
1324 // Add predicate operands.
1330 // This is a pseudo op for a label + instruction sequence, which looks like:
1333 // This adds the address of LPC0 to r0.
1336 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1337 getFunctionNumber(), MI->getOperand(2).getImm(),
1340 // Form and emit the add.
1341 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1342 .addReg(MI->getOperand(0).getReg())
1344 .addReg(MI->getOperand(1).getReg())
1345 // Add predicate operands.
1346 .addImm(MI->getOperand(3).getImm())
1347 .addReg(MI->getOperand(4).getReg())
1348 // Add 's' bit operand (always reg0 for this)
1359 case ARM::PICLDRSH: {
1360 // This is a pseudo op for a label + instruction sequence, which looks like:
1363 // The LCP0 label is referenced by a constant pool entry in order to get
1364 // a PC-relative address at the ldr instruction.
1367 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1368 getFunctionNumber(), MI->getOperand(2).getImm(),
1371 // Form and emit the load
1373 switch (MI->getOpcode()) {
1375 llvm_unreachable("Unexpected opcode!");
1376 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1377 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1378 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1379 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1380 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1381 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1382 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1383 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1385 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1386 .addReg(MI->getOperand(0).getReg())
1388 .addReg(MI->getOperand(1).getReg())
1390 // Add predicate operands.
1391 .addImm(MI->getOperand(3).getImm())
1392 .addReg(MI->getOperand(4).getReg()));
1396 case ARM::CONSTPOOL_ENTRY: {
1397 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1398 /// in the function. The first operand is the ID# for this instruction, the
1399 /// second is the index into the MachineConstantPool that this is, the third
1400 /// is the size in bytes of this constant pool entry.
1401 /// The required alignment is specified on the basic block holding this MI.
1402 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1403 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1405 // If this is the first entry of the pool, mark it.
1406 if (!InConstantPool) {
1407 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1408 InConstantPool = true;
1411 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1413 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1414 if (MCPE.isMachineConstantPoolEntry())
1415 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1417 EmitGlobalConstant(MCPE.Val.ConstVal);
1420 case ARM::t2BR_JT: {
1421 // Lower and emit the instruction itself, then the jump table following it.
1422 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1424 .addReg(MI->getOperand(0).getReg())
1425 // Add predicate operands.
1429 // Output the data for the jump table itself
1433 case ARM::t2TBB_JT: {
1434 // Lower and emit the instruction itself, then the jump table following it.
1435 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1437 .addReg(MI->getOperand(0).getReg())
1438 // Add predicate operands.
1442 // Output the data for the jump table itself
1444 // Make sure the next instruction is 2-byte aligned.
1448 case ARM::t2TBH_JT: {
1449 // Lower and emit the instruction itself, then the jump table following it.
1450 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1452 .addReg(MI->getOperand(0).getReg())
1453 // Add predicate operands.
1457 // Output the data for the jump table itself
1463 // Lower and emit the instruction itself, then the jump table following it.
1466 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1467 ARM::MOVr : ARM::tMOVr;
1468 TmpInst.setOpcode(Opc);
1469 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1470 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1471 // Add predicate operands.
1472 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1473 TmpInst.addOperand(MCOperand::CreateReg(0));
1474 // Add 's' bit operand (always reg0 for this)
1475 if (Opc == ARM::MOVr)
1476 TmpInst.addOperand(MCOperand::CreateReg(0));
1477 OutStreamer.EmitInstruction(TmpInst);
1479 // Make sure the Thumb jump table is 4-byte aligned.
1480 if (Opc == ARM::tMOVr)
1483 // Output the data for the jump table itself
1488 // Lower and emit the instruction itself, then the jump table following it.
1491 if (MI->getOperand(1).getReg() == 0) {
1493 TmpInst.setOpcode(ARM::LDRi12);
1494 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1495 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1496 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1498 TmpInst.setOpcode(ARM::LDRrs);
1499 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1500 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1501 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1502 TmpInst.addOperand(MCOperand::CreateImm(0));
1504 // Add predicate operands.
1505 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1506 TmpInst.addOperand(MCOperand::CreateReg(0));
1507 OutStreamer.EmitInstruction(TmpInst);
1509 // Output the data for the jump table itself
1513 case ARM::BR_JTadd: {
1514 // Lower and emit the instruction itself, then the jump table following it.
1515 // add pc, target, idx
1516 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1518 .addReg(MI->getOperand(0).getReg())
1519 .addReg(MI->getOperand(1).getReg())
1520 // Add predicate operands.
1523 // Add 's' bit operand (always reg0 for this)
1526 // Output the data for the jump table itself
1531 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1532 // FIXME: Remove this special case when they do.
1533 if (!Subtarget->isTargetDarwin()) {
1534 //.long 0xe7ffdefe @ trap
1535 uint32_t Val = 0xe7ffdefeUL;
1536 OutStreamer.AddComment("trap");
1537 OutStreamer.EmitIntValue(Val, 4);
1542 case ARM::TRAPNaCl: {
1543 //.long 0xe7fedef0 @ trap
1544 uint32_t Val = 0xe7fedef0UL;
1545 OutStreamer.AddComment("trap");
1546 OutStreamer.EmitIntValue(Val, 4);
1550 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1551 // FIXME: Remove this special case when they do.
1552 if (!Subtarget->isTargetDarwin()) {
1553 //.short 57086 @ trap
1554 uint16_t Val = 0xdefe;
1555 OutStreamer.AddComment("trap");
1556 OutStreamer.EmitIntValue(Val, 2);
1561 case ARM::t2Int_eh_sjlj_setjmp:
1562 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1563 case ARM::tInt_eh_sjlj_setjmp: {
1564 // Two incoming args: GPR:$src, GPR:$val
1567 // str $val, [$src, #4]
1572 unsigned SrcReg = MI->getOperand(0).getReg();
1573 unsigned ValReg = MI->getOperand(1).getReg();
1574 MCSymbol *Label = GetARMSJLJEHLabel();
1575 OutStreamer.AddComment("eh_setjmp begin");
1576 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1583 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1593 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1596 // The offset immediate is #4. The operand value is scaled by 4 for the
1597 // tSTR instruction.
1603 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1611 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1612 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1613 .addExpr(SymbolExpr)
1617 OutStreamer.AddComment("eh_setjmp end");
1618 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1626 OutStreamer.EmitLabel(Label);
1630 case ARM::Int_eh_sjlj_setjmp_nofp:
1631 case ARM::Int_eh_sjlj_setjmp: {
1632 // Two incoming args: GPR:$src, GPR:$val
1634 // str $val, [$src, #+4]
1638 unsigned SrcReg = MI->getOperand(0).getReg();
1639 unsigned ValReg = MI->getOperand(1).getReg();
1641 OutStreamer.AddComment("eh_setjmp begin");
1642 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1649 // 's' bit operand (always reg0 for this).
1652 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1660 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1666 // 's' bit operand (always reg0 for this).
1669 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1676 // 's' bit operand (always reg0 for this).
1679 OutStreamer.AddComment("eh_setjmp end");
1680 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1686 // 's' bit operand (always reg0 for this).
1690 case ARM::Int_eh_sjlj_longjmp: {
1691 // ldr sp, [$src, #8]
1692 // ldr $scratch, [$src, #4]
1695 unsigned SrcReg = MI->getOperand(0).getReg();
1696 unsigned ScratchReg = MI->getOperand(1).getReg();
1697 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1705 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1713 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1721 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1728 case ARM::tInt_eh_sjlj_longjmp: {
1729 // ldr $scratch, [$src, #8]
1731 // ldr $scratch, [$src, #4]
1734 unsigned SrcReg = MI->getOperand(0).getReg();
1735 unsigned ScratchReg = MI->getOperand(1).getReg();
1736 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1739 // The offset immediate is #8. The operand value is scaled by 4 for the
1740 // tLDR instruction.
1746 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1753 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1761 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1769 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1779 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1781 OutStreamer.EmitInstruction(TmpInst);
1784 //===----------------------------------------------------------------------===//
1785 // Target Registry Stuff
1786 //===----------------------------------------------------------------------===//
1788 // Force static initialization.
1789 extern "C" void LLVMInitializeARMAsmPrinter() {
1790 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1791 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);