1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "llvm/MC/MCDisassembler.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/LEB128.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI) :
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr,
103 const MemoryObject ®ion,
105 raw_ostream &vStream,
106 raw_ostream &cStream) const;
109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
110 class ThumbDisassembler : public MCDisassembler {
112 /// Constructor - Initializes the disassembler.
114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
118 ~ThumbDisassembler() {
121 /// getInstruction - See MCDisassembler.
122 DecodeStatus getInstruction(MCInst &instr,
124 const MemoryObject ®ion,
126 raw_ostream &vStream,
127 raw_ostream &cStream) const;
130 mutable ITStatus ITBlock;
131 DecodeStatus AddThumbPredicate(MCInst&) const;
132 void UpdateThumbVFPPredicate(MCInst&) const;
136 static bool Check(DecodeStatus &Out, DecodeStatus In) {
138 case MCDisassembler::Success:
139 // Out stays the same.
141 case MCDisassembler::SoftFail:
144 case MCDisassembler::Fail:
148 llvm_unreachable("Invalid DecodeStatus!");
152 // Forward declare these because the autogenerated code will reference them.
153 // Definitions are further down.
154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
157 unsigned RegNo, uint64_t Address,
158 const void *Decoder);
159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
160 unsigned RegNo, uint64_t Address,
161 const void *Decoder);
162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
179 const void *Decoder);
180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
221 const void *Decoder);
222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
325 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
349 uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void* Decoder);
356 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
398 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
399 uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
402 uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
404 uint64_t Address, const void *Decoder);
405 #include "ARMGenDisassemblerTables.inc"
407 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
408 return new ARMDisassembler(STI);
411 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
412 return new ThumbDisassembler(STI);
415 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
416 const MemoryObject &Region,
419 raw_ostream &cs) const {
424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
425 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
427 // We want to read exactly 4 bytes of data.
428 if (Region.readBytes(Address, 4, bytes) == -1) {
430 return MCDisassembler::Fail;
433 // Encoded as a small-endian 32-bit word in the stream.
434 uint32_t insn = (bytes[3] << 24) |
439 // Calling the auto-generated decoder function.
440 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
442 if (result != MCDisassembler::Fail) {
447 // VFP and NEON instructions, similarly, are shared between ARM
450 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
451 if (result != MCDisassembler::Fail) {
457 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
458 if (result != MCDisassembler::Fail) {
464 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
466 if (result != MCDisassembler::Fail) {
468 // Add a fake predicate operand, because we share these instruction
469 // definitions with Thumb2 where these instructions are predicable.
470 if (!DecodePredicateOperand(MI, 0xE, Address, this))
471 return MCDisassembler::Fail;
476 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
478 if (result != MCDisassembler::Fail) {
480 // Add a fake predicate operand, because we share these instruction
481 // definitions with Thumb2 where these instructions are predicable.
482 if (!DecodePredicateOperand(MI, 0xE, Address, this))
483 return MCDisassembler::Fail;
488 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
490 if (result != MCDisassembler::Fail) {
492 // Add a fake predicate operand, because we share these instruction
493 // definitions with Thumb2 where these instructions are predicable.
494 if (!DecodePredicateOperand(MI, 0xE, Address, this))
495 return MCDisassembler::Fail;
500 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
502 if (result != MCDisassembler::Fail) {
508 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
510 if (result != MCDisassembler::Fail) {
517 return MCDisassembler::Fail;
521 extern const MCInstrDesc ARMInsts[];
524 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
525 /// immediate Value in the MCInst. The immediate Value has had any PC
526 /// adjustment made by the caller. If the instruction is a branch instruction
527 /// then isBranch is true, else false. If the getOpInfo() function was set as
528 /// part of the setupForSymbolicDisassembly() call then that function is called
529 /// to get any symbolic information at the Address for this instruction. If
530 /// that returns non-zero then the symbolic information it returns is used to
531 /// create an MCExpr and that is added as an operand to the MCInst. If
532 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
533 /// Value is done and if a symbol is found an MCExpr is created with that, else
534 /// an MCExpr with Value is created. This function returns true if it adds an
535 /// operand to the MCInst and false otherwise.
536 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
537 bool isBranch, uint64_t InstSize,
538 MCInst &MI, const void *Decoder) {
539 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
540 // FIXME: Does it make sense for value to be negative?
541 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
542 /* Offset */ 0, InstSize);
545 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
546 /// referenced by a load instruction with the base register that is the Pc.
547 /// These can often be values in a literal pool near the Address of the
548 /// instruction. The Address of the instruction and its immediate Value are
549 /// used as a possible literal pool entry. The SymbolLookUp call back will
550 /// return the name of a symbol referenced by the literal pool's entry if
551 /// the referenced address is that of a symbol. Or it will return a pointer to
552 /// a literal 'C' string if the referenced address of the literal pool's entry
553 /// is an address into a section with 'C' string literals.
554 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
555 const void *Decoder) {
556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
557 Dis->tryAddingPcLoadReferenceComment(Value, Address);
560 // Thumb1 instructions don't have explicit S bits. Rather, they
561 // implicitly set CPSR. Since it's not represented in the encoding, the
562 // auto-generated decoder won't inject the CPSR operand. We need to fix
563 // that as a post-pass.
564 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
565 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
566 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
567 MCInst::iterator I = MI.begin();
568 for (unsigned i = 0; i < NumOps; ++i, ++I) {
569 if (I == MI.end()) break;
570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
571 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
580 // Most Thumb instructions don't have explicit predicates in the
581 // encoding, but rather get their predicates from IT context. We need
582 // to fix up the predicate operands using this context information as a
584 MCDisassembler::DecodeStatus
585 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
586 MCDisassembler::DecodeStatus S = Success;
588 // A few instructions actually have predicates encoded in them. Don't
589 // try to overwrite it if we're seeing one of those.
590 switch (MI.getOpcode()) {
601 // Some instructions (mostly conditional branches) are not
602 // allowed in IT blocks.
603 if (ITBlock.instrInITBlock())
612 // Some instructions (mostly unconditional branches) can
613 // only appears at the end of, or outside of, an IT.
614 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
621 // If we're in an IT block, base the predicate on that. Otherwise,
622 // assume a predicate of AL.
624 CC = ITBlock.getITCC();
627 if (ITBlock.instrInITBlock())
628 ITBlock.advanceITState();
630 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
631 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
632 MCInst::iterator I = MI.begin();
633 for (unsigned i = 0; i < NumOps; ++i, ++I) {
634 if (I == MI.end()) break;
635 if (OpInfo[i].isPredicate()) {
636 I = MI.insert(I, MCOperand::CreateImm(CC));
639 MI.insert(I, MCOperand::CreateReg(0));
641 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
646 I = MI.insert(I, MCOperand::CreateImm(CC));
649 MI.insert(I, MCOperand::CreateReg(0));
651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
656 // Thumb VFP instructions are a special case. Because we share their
657 // encodings between ARM and Thumb modes, and they are predicable in ARM
658 // mode, the auto-generated decoder will give them an (incorrect)
659 // predicate operand. We need to rewrite these operands based on the IT
660 // context as a post-pass.
661 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
663 CC = ITBlock.getITCC();
664 if (ITBlock.instrInITBlock())
665 ITBlock.advanceITState();
667 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
668 MCInst::iterator I = MI.begin();
669 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
670 for (unsigned i = 0; i < NumOps; ++i, ++I) {
671 if (OpInfo[i].isPredicate() ) {
677 I->setReg(ARM::CPSR);
683 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
684 const MemoryObject &Region,
687 raw_ostream &cs) const {
692 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
693 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
695 // We want to read exactly 2 bytes of data.
696 if (Region.readBytes(Address, 2, bytes) == -1) {
698 return MCDisassembler::Fail;
701 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
702 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
704 if (result != MCDisassembler::Fail) {
706 Check(result, AddThumbPredicate(MI));
711 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
715 bool InITBlock = ITBlock.instrInITBlock();
716 Check(result, AddThumbPredicate(MI));
717 AddThumb1SBit(MI, InITBlock);
722 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
724 if (result != MCDisassembler::Fail) {
727 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
728 // the Thumb predicate.
729 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
730 result = MCDisassembler::SoftFail;
732 Check(result, AddThumbPredicate(MI));
734 // If we find an IT instruction, we need to parse its condition
735 // code and mask operands so that we can apply them correctly
736 // to the subsequent instructions.
737 if (MI.getOpcode() == ARM::t2IT) {
739 unsigned Firstcond = MI.getOperand(0).getImm();
740 unsigned Mask = MI.getOperand(1).getImm();
741 ITBlock.setITState(Firstcond, Mask);
747 // We want to read exactly 4 bytes of data.
748 if (Region.readBytes(Address, 4, bytes) == -1) {
750 return MCDisassembler::Fail;
753 uint32_t insn32 = (bytes[3] << 8) |
758 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
760 if (result != MCDisassembler::Fail) {
762 bool InITBlock = ITBlock.instrInITBlock();
763 Check(result, AddThumbPredicate(MI));
764 AddThumb1SBit(MI, InITBlock);
769 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
771 if (result != MCDisassembler::Fail) {
773 Check(result, AddThumbPredicate(MI));
777 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
779 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
780 if (result != MCDisassembler::Fail) {
782 UpdateThumbVFPPredicate(MI);
788 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
789 if (result != MCDisassembler::Fail) {
794 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
796 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
798 if (result != MCDisassembler::Fail) {
800 Check(result, AddThumbPredicate(MI));
805 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
807 uint32_t NEONLdStInsn = insn32;
808 NEONLdStInsn &= 0xF0FFFFFF;
809 NEONLdStInsn |= 0x04000000;
810 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
812 if (result != MCDisassembler::Fail) {
814 Check(result, AddThumbPredicate(MI));
819 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
821 uint32_t NEONDataInsn = insn32;
822 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
823 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
824 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
825 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
827 if (result != MCDisassembler::Fail) {
829 Check(result, AddThumbPredicate(MI));
834 uint32_t NEONCryptoInsn = insn32;
835 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
836 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
837 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
838 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
840 if (result != MCDisassembler::Fail) {
846 uint32_t NEONv8Insn = insn32;
847 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
848 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
850 if (result != MCDisassembler::Fail) {
858 return MCDisassembler::Fail;
862 extern "C" void LLVMInitializeARMDisassembler() {
863 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
864 createARMDisassembler);
865 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
866 createThumbDisassembler);
869 static const uint16_t GPRDecoderTable[] = {
870 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
871 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
872 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
873 ARM::R12, ARM::SP, ARM::LR, ARM::PC
876 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
877 uint64_t Address, const void *Decoder) {
879 return MCDisassembler::Fail;
881 unsigned Register = GPRDecoderTable[RegNo];
882 Inst.addOperand(MCOperand::CreateReg(Register));
883 return MCDisassembler::Success;
887 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
888 uint64_t Address, const void *Decoder) {
889 DecodeStatus S = MCDisassembler::Success;
892 S = MCDisassembler::SoftFail;
894 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
900 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
901 uint64_t Address, const void *Decoder) {
902 DecodeStatus S = MCDisassembler::Success;
906 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
907 return MCDisassembler::Success;
910 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
914 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
915 uint64_t Address, const void *Decoder) {
917 return MCDisassembler::Fail;
918 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
921 static const uint16_t GPRPairDecoderTable[] = {
922 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
923 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
926 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
927 uint64_t Address, const void *Decoder) {
928 DecodeStatus S = MCDisassembler::Success;
931 return MCDisassembler::Fail;
933 if ((RegNo & 1) || RegNo == 0xe)
934 S = MCDisassembler::SoftFail;
936 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
937 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
941 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
942 uint64_t Address, const void *Decoder) {
943 unsigned Register = 0;
964 return MCDisassembler::Fail;
967 Inst.addOperand(MCOperand::CreateReg(Register));
968 return MCDisassembler::Success;
971 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
972 uint64_t Address, const void *Decoder) {
973 DecodeStatus S = MCDisassembler::Success;
974 if (RegNo == 13 || RegNo == 15)
975 S = MCDisassembler::SoftFail;
976 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
980 static const uint16_t SPRDecoderTable[] = {
981 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
982 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
983 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
984 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
985 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
986 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
987 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
988 ARM::S28, ARM::S29, ARM::S30, ARM::S31
991 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
992 uint64_t Address, const void *Decoder) {
994 return MCDisassembler::Fail;
996 unsigned Register = SPRDecoderTable[RegNo];
997 Inst.addOperand(MCOperand::CreateReg(Register));
998 return MCDisassembler::Success;
1001 static const uint16_t DPRDecoderTable[] = {
1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1012 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1013 uint64_t Address, const void *Decoder) {
1015 return MCDisassembler::Fail;
1017 unsigned Register = DPRDecoderTable[RegNo];
1018 Inst.addOperand(MCOperand::CreateReg(Register));
1019 return MCDisassembler::Success;
1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1023 uint64_t Address, const void *Decoder) {
1025 return MCDisassembler::Fail;
1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1031 uint64_t Address, const void *Decoder) {
1033 return MCDisassembler::Fail;
1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1037 static const uint16_t QPRDecoderTable[] = {
1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1046 uint64_t Address, const void *Decoder) {
1047 if (RegNo > 31 || (RegNo & 1) != 0)
1048 return MCDisassembler::Fail;
1051 unsigned Register = QPRDecoderTable[RegNo];
1052 Inst.addOperand(MCOperand::CreateReg(Register));
1053 return MCDisassembler::Success;
1056 static const uint16_t DPairDecoderTable[] = {
1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1066 uint64_t Address, const void *Decoder) {
1068 return MCDisassembler::Fail;
1070 unsigned Register = DPairDecoderTable[RegNo];
1071 Inst.addOperand(MCOperand::CreateReg(Register));
1072 return MCDisassembler::Success;
1075 static const uint16_t DPairSpacedDecoderTable[] = {
1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1083 ARM::D28_D30, ARM::D29_D31
1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1089 const void *Decoder) {
1091 return MCDisassembler::Fail;
1093 unsigned Register = DPairSpacedDecoderTable[RegNo];
1094 Inst.addOperand(MCOperand::CreateReg(Register));
1095 return MCDisassembler::Success;
1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1099 uint64_t Address, const void *Decoder) {
1100 if (Val == 0xF) return MCDisassembler::Fail;
1101 // AL predicate is not allowed on Thumb1 branches.
1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1103 return MCDisassembler::Fail;
1104 Inst.addOperand(MCOperand::CreateImm(Val));
1105 if (Val == ARMCC::AL) {
1106 Inst.addOperand(MCOperand::CreateReg(0));
1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1109 return MCDisassembler::Success;
1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1113 uint64_t Address, const void *Decoder) {
1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1117 Inst.addOperand(MCOperand::CreateReg(0));
1118 return MCDisassembler::Success;
1121 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1122 uint64_t Address, const void *Decoder) {
1123 uint32_t imm = Val & 0xFF;
1124 uint32_t rot = (Val & 0xF00) >> 7;
1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1126 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1127 return MCDisassembler::Success;
1130 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1131 uint64_t Address, const void *Decoder) {
1132 DecodeStatus S = MCDisassembler::Success;
1134 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1135 unsigned type = fieldFromInstruction(Val, 5, 2);
1136 unsigned imm = fieldFromInstruction(Val, 7, 5);
1138 // Register-immediate
1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1140 return MCDisassembler::Fail;
1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1145 Shift = ARM_AM::lsl;
1148 Shift = ARM_AM::lsr;
1151 Shift = ARM_AM::asr;
1154 Shift = ARM_AM::ror;
1158 if (Shift == ARM_AM::ror && imm == 0)
1159 Shift = ARM_AM::rrx;
1161 unsigned Op = Shift | (imm << 3);
1162 Inst.addOperand(MCOperand::CreateImm(Op));
1167 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1168 uint64_t Address, const void *Decoder) {
1169 DecodeStatus S = MCDisassembler::Success;
1171 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1172 unsigned type = fieldFromInstruction(Val, 5, 2);
1173 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1175 // Register-register
1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1177 return MCDisassembler::Fail;
1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1179 return MCDisassembler::Fail;
1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1184 Shift = ARM_AM::lsl;
1187 Shift = ARM_AM::lsr;
1190 Shift = ARM_AM::asr;
1193 Shift = ARM_AM::ror;
1197 Inst.addOperand(MCOperand::CreateImm(Shift));
1202 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1203 uint64_t Address, const void *Decoder) {
1204 DecodeStatus S = MCDisassembler::Success;
1206 bool NeedDisjointWriteback = false;
1207 unsigned WritebackReg = 0;
1208 switch (Inst.getOpcode()) {
1211 case ARM::LDMIA_UPD:
1212 case ARM::LDMDB_UPD:
1213 case ARM::LDMIB_UPD:
1214 case ARM::LDMDA_UPD:
1215 case ARM::t2LDMIA_UPD:
1216 case ARM::t2LDMDB_UPD:
1217 case ARM::t2STMIA_UPD:
1218 case ARM::t2STMDB_UPD:
1219 NeedDisjointWriteback = true;
1220 WritebackReg = Inst.getOperand(0).getReg();
1224 // Empty register lists are not allowed.
1225 if (Val == 0) return MCDisassembler::Fail;
1226 for (unsigned i = 0; i < 16; ++i) {
1227 if (Val & (1 << i)) {
1228 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1229 return MCDisassembler::Fail;
1230 // Writeback not allowed if Rn is in the target list.
1231 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1232 Check(S, MCDisassembler::SoftFail);
1239 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1240 uint64_t Address, const void *Decoder) {
1241 DecodeStatus S = MCDisassembler::Success;
1243 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1244 unsigned regs = fieldFromInstruction(Val, 0, 8);
1246 // In case of unpredictable encoding, tweak the operands.
1247 if (regs == 0 || (Vd + regs) > 32) {
1248 regs = Vd + regs > 32 ? 32 - Vd : regs;
1249 regs = std::max( 1u, regs);
1250 S = MCDisassembler::SoftFail;
1253 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1254 return MCDisassembler::Fail;
1255 for (unsigned i = 0; i < (regs - 1); ++i) {
1256 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1257 return MCDisassembler::Fail;
1263 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1264 uint64_t Address, const void *Decoder) {
1265 DecodeStatus S = MCDisassembler::Success;
1267 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1268 unsigned regs = fieldFromInstruction(Val, 1, 7);
1270 // In case of unpredictable encoding, tweak the operands.
1271 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1272 regs = Vd + regs > 32 ? 32 - Vd : regs;
1273 regs = std::max( 1u, regs);
1274 regs = std::min(16u, regs);
1275 S = MCDisassembler::SoftFail;
1278 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1279 return MCDisassembler::Fail;
1280 for (unsigned i = 0; i < (regs - 1); ++i) {
1281 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1282 return MCDisassembler::Fail;
1288 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1289 uint64_t Address, const void *Decoder) {
1290 // This operand encodes a mask of contiguous zeros between a specified MSB
1291 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1292 // the mask of all bits LSB-and-lower, and then xor them to create
1293 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1294 // create the final mask.
1295 unsigned msb = fieldFromInstruction(Val, 5, 5);
1296 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1298 DecodeStatus S = MCDisassembler::Success;
1300 Check(S, MCDisassembler::SoftFail);
1301 // The check above will cause the warning for the "potentially undefined
1302 // instruction encoding" but we can't build a bad MCOperand value here
1303 // with a lsb > msb or else printing the MCInst will cause a crash.
1307 uint32_t msb_mask = 0xFFFFFFFF;
1308 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1309 uint32_t lsb_mask = (1U << lsb) - 1;
1311 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1315 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1316 uint64_t Address, const void *Decoder) {
1317 DecodeStatus S = MCDisassembler::Success;
1319 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1320 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1321 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1322 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1324 unsigned U = fieldFromInstruction(Insn, 23, 1);
1326 switch (Inst.getOpcode()) {
1327 case ARM::LDC_OFFSET:
1330 case ARM::LDC_OPTION:
1331 case ARM::LDCL_OFFSET:
1333 case ARM::LDCL_POST:
1334 case ARM::LDCL_OPTION:
1335 case ARM::STC_OFFSET:
1338 case ARM::STC_OPTION:
1339 case ARM::STCL_OFFSET:
1341 case ARM::STCL_POST:
1342 case ARM::STCL_OPTION:
1343 case ARM::t2LDC_OFFSET:
1344 case ARM::t2LDC_PRE:
1345 case ARM::t2LDC_POST:
1346 case ARM::t2LDC_OPTION:
1347 case ARM::t2LDCL_OFFSET:
1348 case ARM::t2LDCL_PRE:
1349 case ARM::t2LDCL_POST:
1350 case ARM::t2LDCL_OPTION:
1351 case ARM::t2STC_OFFSET:
1352 case ARM::t2STC_PRE:
1353 case ARM::t2STC_POST:
1354 case ARM::t2STC_OPTION:
1355 case ARM::t2STCL_OFFSET:
1356 case ARM::t2STCL_PRE:
1357 case ARM::t2STCL_POST:
1358 case ARM::t2STCL_OPTION:
1359 if (coproc == 0xA || coproc == 0xB)
1360 return MCDisassembler::Fail;
1366 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1368 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1369 return MCDisassembler::Fail;
1371 Inst.addOperand(MCOperand::CreateImm(coproc));
1372 Inst.addOperand(MCOperand::CreateImm(CRd));
1373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1374 return MCDisassembler::Fail;
1376 switch (Inst.getOpcode()) {
1377 case ARM::t2LDC2_OFFSET:
1378 case ARM::t2LDC2L_OFFSET:
1379 case ARM::t2LDC2_PRE:
1380 case ARM::t2LDC2L_PRE:
1381 case ARM::t2STC2_OFFSET:
1382 case ARM::t2STC2L_OFFSET:
1383 case ARM::t2STC2_PRE:
1384 case ARM::t2STC2L_PRE:
1385 case ARM::LDC2_OFFSET:
1386 case ARM::LDC2L_OFFSET:
1388 case ARM::LDC2L_PRE:
1389 case ARM::STC2_OFFSET:
1390 case ARM::STC2L_OFFSET:
1392 case ARM::STC2L_PRE:
1393 case ARM::t2LDC_OFFSET:
1394 case ARM::t2LDCL_OFFSET:
1395 case ARM::t2LDC_PRE:
1396 case ARM::t2LDCL_PRE:
1397 case ARM::t2STC_OFFSET:
1398 case ARM::t2STCL_OFFSET:
1399 case ARM::t2STC_PRE:
1400 case ARM::t2STCL_PRE:
1401 case ARM::LDC_OFFSET:
1402 case ARM::LDCL_OFFSET:
1405 case ARM::STC_OFFSET:
1406 case ARM::STCL_OFFSET:
1409 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1410 Inst.addOperand(MCOperand::CreateImm(imm));
1412 case ARM::t2LDC2_POST:
1413 case ARM::t2LDC2L_POST:
1414 case ARM::t2STC2_POST:
1415 case ARM::t2STC2L_POST:
1416 case ARM::LDC2_POST:
1417 case ARM::LDC2L_POST:
1418 case ARM::STC2_POST:
1419 case ARM::STC2L_POST:
1420 case ARM::t2LDC_POST:
1421 case ARM::t2LDCL_POST:
1422 case ARM::t2STC_POST:
1423 case ARM::t2STCL_POST:
1425 case ARM::LDCL_POST:
1427 case ARM::STCL_POST:
1431 // The 'option' variant doesn't encode 'U' in the immediate since
1432 // the immediate is unsigned [0,255].
1433 Inst.addOperand(MCOperand::CreateImm(imm));
1437 switch (Inst.getOpcode()) {
1438 case ARM::LDC_OFFSET:
1441 case ARM::LDC_OPTION:
1442 case ARM::LDCL_OFFSET:
1444 case ARM::LDCL_POST:
1445 case ARM::LDCL_OPTION:
1446 case ARM::STC_OFFSET:
1449 case ARM::STC_OPTION:
1450 case ARM::STCL_OFFSET:
1452 case ARM::STCL_POST:
1453 case ARM::STCL_OPTION:
1454 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1455 return MCDisassembler::Fail;
1465 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1466 uint64_t Address, const void *Decoder) {
1467 DecodeStatus S = MCDisassembler::Success;
1469 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1470 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1471 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1472 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1473 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1474 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1475 unsigned P = fieldFromInstruction(Insn, 24, 1);
1476 unsigned W = fieldFromInstruction(Insn, 21, 1);
1478 // On stores, the writeback operand precedes Rt.
1479 switch (Inst.getOpcode()) {
1480 case ARM::STR_POST_IMM:
1481 case ARM::STR_POST_REG:
1482 case ARM::STRB_POST_IMM:
1483 case ARM::STRB_POST_REG:
1484 case ARM::STRT_POST_REG:
1485 case ARM::STRT_POST_IMM:
1486 case ARM::STRBT_POST_REG:
1487 case ARM::STRBT_POST_IMM:
1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1489 return MCDisassembler::Fail;
1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1496 return MCDisassembler::Fail;
1498 // On loads, the writeback operand comes after Rt.
1499 switch (Inst.getOpcode()) {
1500 case ARM::LDR_POST_IMM:
1501 case ARM::LDR_POST_REG:
1502 case ARM::LDRB_POST_IMM:
1503 case ARM::LDRB_POST_REG:
1504 case ARM::LDRBT_POST_REG:
1505 case ARM::LDRBT_POST_IMM:
1506 case ARM::LDRT_POST_REG:
1507 case ARM::LDRT_POST_IMM:
1508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1509 return MCDisassembler::Fail;
1515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1516 return MCDisassembler::Fail;
1518 ARM_AM::AddrOpc Op = ARM_AM::add;
1519 if (!fieldFromInstruction(Insn, 23, 1))
1522 bool writeback = (P == 0) || (W == 1);
1523 unsigned idx_mode = 0;
1525 idx_mode = ARMII::IndexModePre;
1526 else if (!P && writeback)
1527 idx_mode = ARMII::IndexModePost;
1529 if (writeback && (Rn == 15 || Rn == Rt))
1530 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1533 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1534 return MCDisassembler::Fail;
1535 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1536 switch( fieldFromInstruction(Insn, 5, 2)) {
1550 return MCDisassembler::Fail;
1552 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1553 if (Opc == ARM_AM::ror && amt == 0)
1555 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1557 Inst.addOperand(MCOperand::CreateImm(imm));
1559 Inst.addOperand(MCOperand::CreateReg(0));
1560 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1561 Inst.addOperand(MCOperand::CreateImm(tmp));
1564 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1565 return MCDisassembler::Fail;
1570 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1571 uint64_t Address, const void *Decoder) {
1572 DecodeStatus S = MCDisassembler::Success;
1574 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1575 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1576 unsigned type = fieldFromInstruction(Val, 5, 2);
1577 unsigned imm = fieldFromInstruction(Val, 7, 5);
1578 unsigned U = fieldFromInstruction(Val, 12, 1);
1580 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1596 if (ShOp == ARM_AM::ror && imm == 0)
1599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1600 return MCDisassembler::Fail;
1601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1602 return MCDisassembler::Fail;
1605 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1607 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1608 Inst.addOperand(MCOperand::CreateImm(shift));
1614 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1615 uint64_t Address, const void *Decoder) {
1616 DecodeStatus S = MCDisassembler::Success;
1618 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1619 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1620 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1621 unsigned type = fieldFromInstruction(Insn, 22, 1);
1622 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1623 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1624 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1625 unsigned W = fieldFromInstruction(Insn, 21, 1);
1626 unsigned P = fieldFromInstruction(Insn, 24, 1);
1627 unsigned Rt2 = Rt + 1;
1629 bool writeback = (W == 1) | (P == 0);
1631 // For {LD,ST}RD, Rt must be even, else undefined.
1632 switch (Inst.getOpcode()) {
1635 case ARM::STRD_POST:
1638 case ARM::LDRD_POST:
1639 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1644 switch (Inst.getOpcode()) {
1647 case ARM::STRD_POST:
1648 if (P == 0 && W == 1)
1649 S = MCDisassembler::SoftFail;
1651 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1652 S = MCDisassembler::SoftFail;
1653 if (type && Rm == 15)
1654 S = MCDisassembler::SoftFail;
1656 S = MCDisassembler::SoftFail;
1657 if (!type && fieldFromInstruction(Insn, 8, 4))
1658 S = MCDisassembler::SoftFail;
1662 case ARM::STRH_POST:
1664 S = MCDisassembler::SoftFail;
1665 if (writeback && (Rn == 15 || Rn == Rt))
1666 S = MCDisassembler::SoftFail;
1667 if (!type && Rm == 15)
1668 S = MCDisassembler::SoftFail;
1672 case ARM::LDRD_POST:
1673 if (type && Rn == 15){
1675 S = MCDisassembler::SoftFail;
1678 if (P == 0 && W == 1)
1679 S = MCDisassembler::SoftFail;
1680 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1681 S = MCDisassembler::SoftFail;
1682 if (!type && writeback && Rn == 15)
1683 S = MCDisassembler::SoftFail;
1684 if (writeback && (Rn == Rt || Rn == Rt2))
1685 S = MCDisassembler::SoftFail;
1689 case ARM::LDRH_POST:
1690 if (type && Rn == 15){
1692 S = MCDisassembler::SoftFail;
1696 S = MCDisassembler::SoftFail;
1697 if (!type && Rm == 15)
1698 S = MCDisassembler::SoftFail;
1699 if (!type && writeback && (Rn == 15 || Rn == Rt))
1700 S = MCDisassembler::SoftFail;
1703 case ARM::LDRSH_PRE:
1704 case ARM::LDRSH_POST:
1706 case ARM::LDRSB_PRE:
1707 case ARM::LDRSB_POST:
1708 if (type && Rn == 15){
1710 S = MCDisassembler::SoftFail;
1713 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1714 S = MCDisassembler::SoftFail;
1715 if (!type && (Rt == 15 || Rm == 15))
1716 S = MCDisassembler::SoftFail;
1717 if (!type && writeback && (Rn == 15 || Rn == Rt))
1718 S = MCDisassembler::SoftFail;
1724 if (writeback) { // Writeback
1726 U |= ARMII::IndexModePre << 9;
1728 U |= ARMII::IndexModePost << 9;
1730 // On stores, the writeback operand precedes Rt.
1731 switch (Inst.getOpcode()) {
1734 case ARM::STRD_POST:
1737 case ARM::STRH_POST:
1738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1739 return MCDisassembler::Fail;
1746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1747 return MCDisassembler::Fail;
1748 switch (Inst.getOpcode()) {
1751 case ARM::STRD_POST:
1754 case ARM::LDRD_POST:
1755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1756 return MCDisassembler::Fail;
1763 // On loads, the writeback operand comes after Rt.
1764 switch (Inst.getOpcode()) {
1767 case ARM::LDRD_POST:
1770 case ARM::LDRH_POST:
1772 case ARM::LDRSH_PRE:
1773 case ARM::LDRSH_POST:
1775 case ARM::LDRSB_PRE:
1776 case ARM::LDRSB_POST:
1779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1780 return MCDisassembler::Fail;
1787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1788 return MCDisassembler::Fail;
1791 Inst.addOperand(MCOperand::CreateReg(0));
1792 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1795 return MCDisassembler::Fail;
1796 Inst.addOperand(MCOperand::CreateImm(U));
1799 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1800 return MCDisassembler::Fail;
1805 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1806 uint64_t Address, const void *Decoder) {
1807 DecodeStatus S = MCDisassembler::Success;
1809 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1810 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1827 Inst.addOperand(MCOperand::CreateImm(mode));
1828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1829 return MCDisassembler::Fail;
1834 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1835 uint64_t Address, const void *Decoder) {
1836 DecodeStatus S = MCDisassembler::Success;
1838 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1839 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1840 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1841 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1844 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1849 return MCDisassembler::Fail;
1850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1851 return MCDisassembler::Fail;
1852 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1853 return MCDisassembler::Fail;
1857 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1859 uint64_t Address, const void *Decoder) {
1860 DecodeStatus S = MCDisassembler::Success;
1862 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1863 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1864 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1867 // Ambiguous with RFE and SRS
1868 switch (Inst.getOpcode()) {
1870 Inst.setOpcode(ARM::RFEDA);
1872 case ARM::LDMDA_UPD:
1873 Inst.setOpcode(ARM::RFEDA_UPD);
1876 Inst.setOpcode(ARM::RFEDB);
1878 case ARM::LDMDB_UPD:
1879 Inst.setOpcode(ARM::RFEDB_UPD);
1882 Inst.setOpcode(ARM::RFEIA);
1884 case ARM::LDMIA_UPD:
1885 Inst.setOpcode(ARM::RFEIA_UPD);
1888 Inst.setOpcode(ARM::RFEIB);
1890 case ARM::LDMIB_UPD:
1891 Inst.setOpcode(ARM::RFEIB_UPD);
1894 Inst.setOpcode(ARM::SRSDA);
1896 case ARM::STMDA_UPD:
1897 Inst.setOpcode(ARM::SRSDA_UPD);
1900 Inst.setOpcode(ARM::SRSDB);
1902 case ARM::STMDB_UPD:
1903 Inst.setOpcode(ARM::SRSDB_UPD);
1906 Inst.setOpcode(ARM::SRSIA);
1908 case ARM::STMIA_UPD:
1909 Inst.setOpcode(ARM::SRSIA_UPD);
1912 Inst.setOpcode(ARM::SRSIB);
1914 case ARM::STMIB_UPD:
1915 Inst.setOpcode(ARM::SRSIB_UPD);
1918 return MCDisassembler::Fail;
1921 // For stores (which become SRS's, the only operand is the mode.
1922 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1923 // Check SRS encoding constraints
1924 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1925 fieldFromInstruction(Insn, 20, 1) == 0))
1926 return MCDisassembler::Fail;
1929 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1933 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1937 return MCDisassembler::Fail;
1938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1939 return MCDisassembler::Fail; // Tied
1940 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1941 return MCDisassembler::Fail;
1942 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1943 return MCDisassembler::Fail;
1948 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1949 uint64_t Address, const void *Decoder) {
1950 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1951 unsigned M = fieldFromInstruction(Insn, 17, 1);
1952 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1953 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1955 DecodeStatus S = MCDisassembler::Success;
1957 // This decoder is called from multiple location that do not check
1958 // the full encoding is valid before they do.
1959 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1960 fieldFromInstruction(Insn, 16, 1) != 0 ||
1961 fieldFromInstruction(Insn, 20, 8) != 0x10)
1962 return MCDisassembler::Fail;
1964 // imod == '01' --> UNPREDICTABLE
1965 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1966 // return failure here. The '01' imod value is unprintable, so there's
1967 // nothing useful we could do even if we returned UNPREDICTABLE.
1969 if (imod == 1) return MCDisassembler::Fail;
1972 Inst.setOpcode(ARM::CPS3p);
1973 Inst.addOperand(MCOperand::CreateImm(imod));
1974 Inst.addOperand(MCOperand::CreateImm(iflags));
1975 Inst.addOperand(MCOperand::CreateImm(mode));
1976 } else if (imod && !M) {
1977 Inst.setOpcode(ARM::CPS2p);
1978 Inst.addOperand(MCOperand::CreateImm(imod));
1979 Inst.addOperand(MCOperand::CreateImm(iflags));
1980 if (mode) S = MCDisassembler::SoftFail;
1981 } else if (!imod && M) {
1982 Inst.setOpcode(ARM::CPS1p);
1983 Inst.addOperand(MCOperand::CreateImm(mode));
1984 if (iflags) S = MCDisassembler::SoftFail;
1986 // imod == '00' && M == '0' --> UNPREDICTABLE
1987 Inst.setOpcode(ARM::CPS1p);
1988 Inst.addOperand(MCOperand::CreateImm(mode));
1989 S = MCDisassembler::SoftFail;
1995 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1996 uint64_t Address, const void *Decoder) {
1997 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1998 unsigned M = fieldFromInstruction(Insn, 8, 1);
1999 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2000 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2002 DecodeStatus S = MCDisassembler::Success;
2004 // imod == '01' --> UNPREDICTABLE
2005 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2006 // return failure here. The '01' imod value is unprintable, so there's
2007 // nothing useful we could do even if we returned UNPREDICTABLE.
2009 if (imod == 1) return MCDisassembler::Fail;
2012 Inst.setOpcode(ARM::t2CPS3p);
2013 Inst.addOperand(MCOperand::CreateImm(imod));
2014 Inst.addOperand(MCOperand::CreateImm(iflags));
2015 Inst.addOperand(MCOperand::CreateImm(mode));
2016 } else if (imod && !M) {
2017 Inst.setOpcode(ARM::t2CPS2p);
2018 Inst.addOperand(MCOperand::CreateImm(imod));
2019 Inst.addOperand(MCOperand::CreateImm(iflags));
2020 if (mode) S = MCDisassembler::SoftFail;
2021 } else if (!imod && M) {
2022 Inst.setOpcode(ARM::t2CPS1p);
2023 Inst.addOperand(MCOperand::CreateImm(mode));
2024 if (iflags) S = MCDisassembler::SoftFail;
2026 // imod == '00' && M == '0' --> this is a HINT instruction
2027 int imm = fieldFromInstruction(Insn, 0, 8);
2028 // HINT are defined only for immediate in [0..4]
2029 if(imm > 4) return MCDisassembler::Fail;
2030 Inst.setOpcode(ARM::t2HINT);
2031 Inst.addOperand(MCOperand::CreateImm(imm));
2037 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2038 uint64_t Address, const void *Decoder) {
2039 DecodeStatus S = MCDisassembler::Success;
2041 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2044 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2045 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2046 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2047 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2049 if (Inst.getOpcode() == ARM::t2MOVTi16)
2050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2051 return MCDisassembler::Fail;
2052 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2053 return MCDisassembler::Fail;
2055 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2056 Inst.addOperand(MCOperand::CreateImm(imm));
2061 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2062 uint64_t Address, const void *Decoder) {
2063 DecodeStatus S = MCDisassembler::Success;
2065 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2066 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2069 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2070 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2072 if (Inst.getOpcode() == ARM::MOVTi16)
2073 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2074 return MCDisassembler::Fail;
2076 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2077 return MCDisassembler::Fail;
2079 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2080 Inst.addOperand(MCOperand::CreateImm(imm));
2082 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2083 return MCDisassembler::Fail;
2088 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2089 uint64_t Address, const void *Decoder) {
2090 DecodeStatus S = MCDisassembler::Success;
2092 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2093 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2094 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2095 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2096 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2099 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2102 return MCDisassembler::Fail;
2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2104 return MCDisassembler::Fail;
2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2106 return MCDisassembler::Fail;
2107 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2108 return MCDisassembler::Fail;
2110 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2111 return MCDisassembler::Fail;
2116 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2117 uint64_t Address, const void *Decoder) {
2118 DecodeStatus S = MCDisassembler::Success;
2120 unsigned add = fieldFromInstruction(Val, 12, 1);
2121 unsigned imm = fieldFromInstruction(Val, 0, 12);
2122 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2125 return MCDisassembler::Fail;
2127 if (!add) imm *= -1;
2128 if (imm == 0 && !add) imm = INT32_MIN;
2129 Inst.addOperand(MCOperand::CreateImm(imm));
2131 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2136 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2137 uint64_t Address, const void *Decoder) {
2138 DecodeStatus S = MCDisassembler::Success;
2140 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2141 unsigned U = fieldFromInstruction(Val, 8, 1);
2142 unsigned imm = fieldFromInstruction(Val, 0, 8);
2144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2145 return MCDisassembler::Fail;
2148 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2150 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2155 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2156 uint64_t Address, const void *Decoder) {
2157 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2161 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2162 uint64_t Address, const void *Decoder) {
2163 DecodeStatus Status = MCDisassembler::Success;
2165 // Note the J1 and J2 values are from the encoded instruction. So here
2166 // change them to I1 and I2 values via as documented:
2167 // I1 = NOT(J1 EOR S);
2168 // I2 = NOT(J2 EOR S);
2169 // and build the imm32 with one trailing zero as documented:
2170 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2171 unsigned S = fieldFromInstruction(Insn, 26, 1);
2172 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2173 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2174 unsigned I1 = !(J1 ^ S);
2175 unsigned I2 = !(J2 ^ S);
2176 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2177 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2178 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2179 int imm32 = SignExtend32<25>(tmp << 1);
2180 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2181 true, 4, Inst, Decoder))
2182 Inst.addOperand(MCOperand::CreateImm(imm32));
2188 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2189 uint64_t Address, const void *Decoder) {
2190 DecodeStatus S = MCDisassembler::Success;
2192 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2193 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2196 Inst.setOpcode(ARM::BLXi);
2197 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2198 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2199 true, 4, Inst, Decoder))
2200 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2204 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2205 true, 4, Inst, Decoder))
2206 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2207 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2208 return MCDisassembler::Fail;
2214 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2215 uint64_t Address, const void *Decoder) {
2216 DecodeStatus S = MCDisassembler::Success;
2218 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2219 unsigned align = fieldFromInstruction(Val, 4, 2);
2221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2222 return MCDisassembler::Fail;
2224 Inst.addOperand(MCOperand::CreateImm(0));
2226 Inst.addOperand(MCOperand::CreateImm(4 << align));
2231 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2232 uint64_t Address, const void *Decoder) {
2233 DecodeStatus S = MCDisassembler::Success;
2235 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2236 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2237 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2238 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2239 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2240 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2242 // First output register
2243 switch (Inst.getOpcode()) {
2244 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2245 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2246 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2247 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2248 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2249 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2250 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2251 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2252 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2253 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2254 return MCDisassembler::Fail;
2259 case ARM::VLD2b16wb_fixed:
2260 case ARM::VLD2b16wb_register:
2261 case ARM::VLD2b32wb_fixed:
2262 case ARM::VLD2b32wb_register:
2263 case ARM::VLD2b8wb_fixed:
2264 case ARM::VLD2b8wb_register:
2265 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2266 return MCDisassembler::Fail;
2269 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2270 return MCDisassembler::Fail;
2273 // Second output register
2274 switch (Inst.getOpcode()) {
2278 case ARM::VLD3d8_UPD:
2279 case ARM::VLD3d16_UPD:
2280 case ARM::VLD3d32_UPD:
2284 case ARM::VLD4d8_UPD:
2285 case ARM::VLD4d16_UPD:
2286 case ARM::VLD4d32_UPD:
2287 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2288 return MCDisassembler::Fail;
2293 case ARM::VLD3q8_UPD:
2294 case ARM::VLD3q16_UPD:
2295 case ARM::VLD3q32_UPD:
2299 case ARM::VLD4q8_UPD:
2300 case ARM::VLD4q16_UPD:
2301 case ARM::VLD4q32_UPD:
2302 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2303 return MCDisassembler::Fail;
2308 // Third output register
2309 switch(Inst.getOpcode()) {
2313 case ARM::VLD3d8_UPD:
2314 case ARM::VLD3d16_UPD:
2315 case ARM::VLD3d32_UPD:
2319 case ARM::VLD4d8_UPD:
2320 case ARM::VLD4d16_UPD:
2321 case ARM::VLD4d32_UPD:
2322 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2323 return MCDisassembler::Fail;
2328 case ARM::VLD3q8_UPD:
2329 case ARM::VLD3q16_UPD:
2330 case ARM::VLD3q32_UPD:
2334 case ARM::VLD4q8_UPD:
2335 case ARM::VLD4q16_UPD:
2336 case ARM::VLD4q32_UPD:
2337 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2338 return MCDisassembler::Fail;
2344 // Fourth output register
2345 switch (Inst.getOpcode()) {
2349 case ARM::VLD4d8_UPD:
2350 case ARM::VLD4d16_UPD:
2351 case ARM::VLD4d32_UPD:
2352 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2353 return MCDisassembler::Fail;
2358 case ARM::VLD4q8_UPD:
2359 case ARM::VLD4q16_UPD:
2360 case ARM::VLD4q32_UPD:
2361 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2362 return MCDisassembler::Fail;
2368 // Writeback operand
2369 switch (Inst.getOpcode()) {
2370 case ARM::VLD1d8wb_fixed:
2371 case ARM::VLD1d16wb_fixed:
2372 case ARM::VLD1d32wb_fixed:
2373 case ARM::VLD1d64wb_fixed:
2374 case ARM::VLD1d8wb_register:
2375 case ARM::VLD1d16wb_register:
2376 case ARM::VLD1d32wb_register:
2377 case ARM::VLD1d64wb_register:
2378 case ARM::VLD1q8wb_fixed:
2379 case ARM::VLD1q16wb_fixed:
2380 case ARM::VLD1q32wb_fixed:
2381 case ARM::VLD1q64wb_fixed:
2382 case ARM::VLD1q8wb_register:
2383 case ARM::VLD1q16wb_register:
2384 case ARM::VLD1q32wb_register:
2385 case ARM::VLD1q64wb_register:
2386 case ARM::VLD1d8Twb_fixed:
2387 case ARM::VLD1d8Twb_register:
2388 case ARM::VLD1d16Twb_fixed:
2389 case ARM::VLD1d16Twb_register:
2390 case ARM::VLD1d32Twb_fixed:
2391 case ARM::VLD1d32Twb_register:
2392 case ARM::VLD1d64Twb_fixed:
2393 case ARM::VLD1d64Twb_register:
2394 case ARM::VLD1d8Qwb_fixed:
2395 case ARM::VLD1d8Qwb_register:
2396 case ARM::VLD1d16Qwb_fixed:
2397 case ARM::VLD1d16Qwb_register:
2398 case ARM::VLD1d32Qwb_fixed:
2399 case ARM::VLD1d32Qwb_register:
2400 case ARM::VLD1d64Qwb_fixed:
2401 case ARM::VLD1d64Qwb_register:
2402 case ARM::VLD2d8wb_fixed:
2403 case ARM::VLD2d16wb_fixed:
2404 case ARM::VLD2d32wb_fixed:
2405 case ARM::VLD2q8wb_fixed:
2406 case ARM::VLD2q16wb_fixed:
2407 case ARM::VLD2q32wb_fixed:
2408 case ARM::VLD2d8wb_register:
2409 case ARM::VLD2d16wb_register:
2410 case ARM::VLD2d32wb_register:
2411 case ARM::VLD2q8wb_register:
2412 case ARM::VLD2q16wb_register:
2413 case ARM::VLD2q32wb_register:
2414 case ARM::VLD2b8wb_fixed:
2415 case ARM::VLD2b16wb_fixed:
2416 case ARM::VLD2b32wb_fixed:
2417 case ARM::VLD2b8wb_register:
2418 case ARM::VLD2b16wb_register:
2419 case ARM::VLD2b32wb_register:
2420 Inst.addOperand(MCOperand::CreateImm(0));
2422 case ARM::VLD3d8_UPD:
2423 case ARM::VLD3d16_UPD:
2424 case ARM::VLD3d32_UPD:
2425 case ARM::VLD3q8_UPD:
2426 case ARM::VLD3q16_UPD:
2427 case ARM::VLD3q32_UPD:
2428 case ARM::VLD4d8_UPD:
2429 case ARM::VLD4d16_UPD:
2430 case ARM::VLD4d32_UPD:
2431 case ARM::VLD4q8_UPD:
2432 case ARM::VLD4q16_UPD:
2433 case ARM::VLD4q32_UPD:
2434 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2435 return MCDisassembler::Fail;
2441 // AddrMode6 Base (register+alignment)
2442 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2443 return MCDisassembler::Fail;
2445 // AddrMode6 Offset (register)
2446 switch (Inst.getOpcode()) {
2448 // The below have been updated to have explicit am6offset split
2449 // between fixed and register offset. For those instructions not
2450 // yet updated, we need to add an additional reg0 operand for the
2453 // The fixed offset encodes as Rm == 0xd, so we check for that.
2455 Inst.addOperand(MCOperand::CreateReg(0));
2458 // Fall through to handle the register offset variant.
2459 case ARM::VLD1d8wb_fixed:
2460 case ARM::VLD1d16wb_fixed:
2461 case ARM::VLD1d32wb_fixed:
2462 case ARM::VLD1d64wb_fixed:
2463 case ARM::VLD1d8Twb_fixed:
2464 case ARM::VLD1d16Twb_fixed:
2465 case ARM::VLD1d32Twb_fixed:
2466 case ARM::VLD1d64Twb_fixed:
2467 case ARM::VLD1d8Qwb_fixed:
2468 case ARM::VLD1d16Qwb_fixed:
2469 case ARM::VLD1d32Qwb_fixed:
2470 case ARM::VLD1d64Qwb_fixed:
2471 case ARM::VLD1d8wb_register:
2472 case ARM::VLD1d16wb_register:
2473 case ARM::VLD1d32wb_register:
2474 case ARM::VLD1d64wb_register:
2475 case ARM::VLD1q8wb_fixed:
2476 case ARM::VLD1q16wb_fixed:
2477 case ARM::VLD1q32wb_fixed:
2478 case ARM::VLD1q64wb_fixed:
2479 case ARM::VLD1q8wb_register:
2480 case ARM::VLD1q16wb_register:
2481 case ARM::VLD1q32wb_register:
2482 case ARM::VLD1q64wb_register:
2483 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2484 // variant encodes Rm == 0xf. Anything else is a register offset post-
2485 // increment and we need to add the register operand to the instruction.
2486 if (Rm != 0xD && Rm != 0xF &&
2487 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2488 return MCDisassembler::Fail;
2490 case ARM::VLD2d8wb_fixed:
2491 case ARM::VLD2d16wb_fixed:
2492 case ARM::VLD2d32wb_fixed:
2493 case ARM::VLD2b8wb_fixed:
2494 case ARM::VLD2b16wb_fixed:
2495 case ARM::VLD2b32wb_fixed:
2496 case ARM::VLD2q8wb_fixed:
2497 case ARM::VLD2q16wb_fixed:
2498 case ARM::VLD2q32wb_fixed:
2505 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2506 uint64_t Address, const void *Decoder) {
2507 unsigned type = fieldFromInstruction(Insn, 8, 4);
2508 unsigned align = fieldFromInstruction(Insn, 4, 2);
2509 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2510 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2511 if (type == 10 && align == 3) return MCDisassembler::Fail;
2513 unsigned load = fieldFromInstruction(Insn, 21, 1);
2514 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2515 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2518 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2519 uint64_t Address, const void *Decoder) {
2520 unsigned size = fieldFromInstruction(Insn, 6, 2);
2521 if (size == 3) return MCDisassembler::Fail;
2523 unsigned type = fieldFromInstruction(Insn, 8, 4);
2524 unsigned align = fieldFromInstruction(Insn, 4, 2);
2525 if (type == 8 && align == 3) return MCDisassembler::Fail;
2526 if (type == 9 && align == 3) return MCDisassembler::Fail;
2528 unsigned load = fieldFromInstruction(Insn, 21, 1);
2529 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2530 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2533 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2534 uint64_t Address, const void *Decoder) {
2535 unsigned size = fieldFromInstruction(Insn, 6, 2);
2536 if (size == 3) return MCDisassembler::Fail;
2538 unsigned align = fieldFromInstruction(Insn, 4, 2);
2539 if (align & 2) return MCDisassembler::Fail;
2541 unsigned load = fieldFromInstruction(Insn, 21, 1);
2542 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2543 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2546 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2547 uint64_t Address, const void *Decoder) {
2548 unsigned size = fieldFromInstruction(Insn, 6, 2);
2549 if (size == 3) return MCDisassembler::Fail;
2551 unsigned load = fieldFromInstruction(Insn, 21, 1);
2552 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2553 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2556 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2557 uint64_t Address, const void *Decoder) {
2558 DecodeStatus S = MCDisassembler::Success;
2560 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2561 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2562 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2563 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2564 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2565 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2567 // Writeback Operand
2568 switch (Inst.getOpcode()) {
2569 case ARM::VST1d8wb_fixed:
2570 case ARM::VST1d16wb_fixed:
2571 case ARM::VST1d32wb_fixed:
2572 case ARM::VST1d64wb_fixed:
2573 case ARM::VST1d8wb_register:
2574 case ARM::VST1d16wb_register:
2575 case ARM::VST1d32wb_register:
2576 case ARM::VST1d64wb_register:
2577 case ARM::VST1q8wb_fixed:
2578 case ARM::VST1q16wb_fixed:
2579 case ARM::VST1q32wb_fixed:
2580 case ARM::VST1q64wb_fixed:
2581 case ARM::VST1q8wb_register:
2582 case ARM::VST1q16wb_register:
2583 case ARM::VST1q32wb_register:
2584 case ARM::VST1q64wb_register:
2585 case ARM::VST1d8Twb_fixed:
2586 case ARM::VST1d16Twb_fixed:
2587 case ARM::VST1d32Twb_fixed:
2588 case ARM::VST1d64Twb_fixed:
2589 case ARM::VST1d8Twb_register:
2590 case ARM::VST1d16Twb_register:
2591 case ARM::VST1d32Twb_register:
2592 case ARM::VST1d64Twb_register:
2593 case ARM::VST1d8Qwb_fixed:
2594 case ARM::VST1d16Qwb_fixed:
2595 case ARM::VST1d32Qwb_fixed:
2596 case ARM::VST1d64Qwb_fixed:
2597 case ARM::VST1d8Qwb_register:
2598 case ARM::VST1d16Qwb_register:
2599 case ARM::VST1d32Qwb_register:
2600 case ARM::VST1d64Qwb_register:
2601 case ARM::VST2d8wb_fixed:
2602 case ARM::VST2d16wb_fixed:
2603 case ARM::VST2d32wb_fixed:
2604 case ARM::VST2d8wb_register:
2605 case ARM::VST2d16wb_register:
2606 case ARM::VST2d32wb_register:
2607 case ARM::VST2q8wb_fixed:
2608 case ARM::VST2q16wb_fixed:
2609 case ARM::VST2q32wb_fixed:
2610 case ARM::VST2q8wb_register:
2611 case ARM::VST2q16wb_register:
2612 case ARM::VST2q32wb_register:
2613 case ARM::VST2b8wb_fixed:
2614 case ARM::VST2b16wb_fixed:
2615 case ARM::VST2b32wb_fixed:
2616 case ARM::VST2b8wb_register:
2617 case ARM::VST2b16wb_register:
2618 case ARM::VST2b32wb_register:
2620 return MCDisassembler::Fail;
2621 Inst.addOperand(MCOperand::CreateImm(0));
2623 case ARM::VST3d8_UPD:
2624 case ARM::VST3d16_UPD:
2625 case ARM::VST3d32_UPD:
2626 case ARM::VST3q8_UPD:
2627 case ARM::VST3q16_UPD:
2628 case ARM::VST3q32_UPD:
2629 case ARM::VST4d8_UPD:
2630 case ARM::VST4d16_UPD:
2631 case ARM::VST4d32_UPD:
2632 case ARM::VST4q8_UPD:
2633 case ARM::VST4q16_UPD:
2634 case ARM::VST4q32_UPD:
2635 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2636 return MCDisassembler::Fail;
2642 // AddrMode6 Base (register+alignment)
2643 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2644 return MCDisassembler::Fail;
2646 // AddrMode6 Offset (register)
2647 switch (Inst.getOpcode()) {
2650 Inst.addOperand(MCOperand::CreateReg(0));
2651 else if (Rm != 0xF) {
2652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2653 return MCDisassembler::Fail;
2656 case ARM::VST1d8wb_fixed:
2657 case ARM::VST1d16wb_fixed:
2658 case ARM::VST1d32wb_fixed:
2659 case ARM::VST1d64wb_fixed:
2660 case ARM::VST1q8wb_fixed:
2661 case ARM::VST1q16wb_fixed:
2662 case ARM::VST1q32wb_fixed:
2663 case ARM::VST1q64wb_fixed:
2664 case ARM::VST1d8Twb_fixed:
2665 case ARM::VST1d16Twb_fixed:
2666 case ARM::VST1d32Twb_fixed:
2667 case ARM::VST1d64Twb_fixed:
2668 case ARM::VST1d8Qwb_fixed:
2669 case ARM::VST1d16Qwb_fixed:
2670 case ARM::VST1d32Qwb_fixed:
2671 case ARM::VST1d64Qwb_fixed:
2672 case ARM::VST2d8wb_fixed:
2673 case ARM::VST2d16wb_fixed:
2674 case ARM::VST2d32wb_fixed:
2675 case ARM::VST2q8wb_fixed:
2676 case ARM::VST2q16wb_fixed:
2677 case ARM::VST2q32wb_fixed:
2678 case ARM::VST2b8wb_fixed:
2679 case ARM::VST2b16wb_fixed:
2680 case ARM::VST2b32wb_fixed:
2685 // First input register
2686 switch (Inst.getOpcode()) {
2691 case ARM::VST1q16wb_fixed:
2692 case ARM::VST1q16wb_register:
2693 case ARM::VST1q32wb_fixed:
2694 case ARM::VST1q32wb_register:
2695 case ARM::VST1q64wb_fixed:
2696 case ARM::VST1q64wb_register:
2697 case ARM::VST1q8wb_fixed:
2698 case ARM::VST1q8wb_register:
2702 case ARM::VST2d16wb_fixed:
2703 case ARM::VST2d16wb_register:
2704 case ARM::VST2d32wb_fixed:
2705 case ARM::VST2d32wb_register:
2706 case ARM::VST2d8wb_fixed:
2707 case ARM::VST2d8wb_register:
2708 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2709 return MCDisassembler::Fail;
2714 case ARM::VST2b16wb_fixed:
2715 case ARM::VST2b16wb_register:
2716 case ARM::VST2b32wb_fixed:
2717 case ARM::VST2b32wb_register:
2718 case ARM::VST2b8wb_fixed:
2719 case ARM::VST2b8wb_register:
2720 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2721 return MCDisassembler::Fail;
2724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2725 return MCDisassembler::Fail;
2728 // Second input register
2729 switch (Inst.getOpcode()) {
2733 case ARM::VST3d8_UPD:
2734 case ARM::VST3d16_UPD:
2735 case ARM::VST3d32_UPD:
2739 case ARM::VST4d8_UPD:
2740 case ARM::VST4d16_UPD:
2741 case ARM::VST4d32_UPD:
2742 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2743 return MCDisassembler::Fail;
2748 case ARM::VST3q8_UPD:
2749 case ARM::VST3q16_UPD:
2750 case ARM::VST3q32_UPD:
2754 case ARM::VST4q8_UPD:
2755 case ARM::VST4q16_UPD:
2756 case ARM::VST4q32_UPD:
2757 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2758 return MCDisassembler::Fail;
2764 // Third input register
2765 switch (Inst.getOpcode()) {
2769 case ARM::VST3d8_UPD:
2770 case ARM::VST3d16_UPD:
2771 case ARM::VST3d32_UPD:
2775 case ARM::VST4d8_UPD:
2776 case ARM::VST4d16_UPD:
2777 case ARM::VST4d32_UPD:
2778 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2779 return MCDisassembler::Fail;
2784 case ARM::VST3q8_UPD:
2785 case ARM::VST3q16_UPD:
2786 case ARM::VST3q32_UPD:
2790 case ARM::VST4q8_UPD:
2791 case ARM::VST4q16_UPD:
2792 case ARM::VST4q32_UPD:
2793 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2794 return MCDisassembler::Fail;
2800 // Fourth input register
2801 switch (Inst.getOpcode()) {
2805 case ARM::VST4d8_UPD:
2806 case ARM::VST4d16_UPD:
2807 case ARM::VST4d32_UPD:
2808 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2809 return MCDisassembler::Fail;
2814 case ARM::VST4q8_UPD:
2815 case ARM::VST4q16_UPD:
2816 case ARM::VST4q32_UPD:
2817 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2818 return MCDisassembler::Fail;
2827 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2828 uint64_t Address, const void *Decoder) {
2829 DecodeStatus S = MCDisassembler::Success;
2831 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2832 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2833 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2834 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2835 unsigned align = fieldFromInstruction(Insn, 4, 1);
2836 unsigned size = fieldFromInstruction(Insn, 6, 2);
2838 if (size == 0 && align == 1)
2839 return MCDisassembler::Fail;
2840 align *= (1 << size);
2842 switch (Inst.getOpcode()) {
2843 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2844 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2845 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2846 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2847 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2848 return MCDisassembler::Fail;
2851 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2852 return MCDisassembler::Fail;
2856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2857 return MCDisassembler::Fail;
2860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2861 return MCDisassembler::Fail;
2862 Inst.addOperand(MCOperand::CreateImm(align));
2864 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2865 // variant encodes Rm == 0xf. Anything else is a register offset post-
2866 // increment and we need to add the register operand to the instruction.
2867 if (Rm != 0xD && Rm != 0xF &&
2868 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2869 return MCDisassembler::Fail;
2874 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2875 uint64_t Address, const void *Decoder) {
2876 DecodeStatus S = MCDisassembler::Success;
2878 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2879 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2880 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2881 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2882 unsigned align = fieldFromInstruction(Insn, 4, 1);
2883 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2886 switch (Inst.getOpcode()) {
2887 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2888 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2889 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2890 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2891 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2892 return MCDisassembler::Fail;
2894 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2895 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2896 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2897 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2898 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2899 return MCDisassembler::Fail;
2902 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2903 return MCDisassembler::Fail;
2908 Inst.addOperand(MCOperand::CreateImm(0));
2910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2911 return MCDisassembler::Fail;
2912 Inst.addOperand(MCOperand::CreateImm(align));
2914 if (Rm != 0xD && Rm != 0xF) {
2915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2916 return MCDisassembler::Fail;
2922 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2923 uint64_t Address, const void *Decoder) {
2924 DecodeStatus S = MCDisassembler::Success;
2926 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2927 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2928 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2929 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2930 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2933 return MCDisassembler::Fail;
2934 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2935 return MCDisassembler::Fail;
2936 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2937 return MCDisassembler::Fail;
2939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2940 return MCDisassembler::Fail;
2943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2944 return MCDisassembler::Fail;
2945 Inst.addOperand(MCOperand::CreateImm(0));
2948 Inst.addOperand(MCOperand::CreateReg(0));
2949 else if (Rm != 0xF) {
2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2951 return MCDisassembler::Fail;
2957 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2958 uint64_t Address, const void *Decoder) {
2959 DecodeStatus S = MCDisassembler::Success;
2961 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2962 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2963 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2964 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2965 unsigned size = fieldFromInstruction(Insn, 6, 2);
2966 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2967 unsigned align = fieldFromInstruction(Insn, 4, 1);
2971 return MCDisassembler::Fail;
2984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2985 return MCDisassembler::Fail;
2986 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2987 return MCDisassembler::Fail;
2988 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2989 return MCDisassembler::Fail;
2990 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2991 return MCDisassembler::Fail;
2993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2994 return MCDisassembler::Fail;
2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2998 return MCDisassembler::Fail;
2999 Inst.addOperand(MCOperand::CreateImm(align));
3002 Inst.addOperand(MCOperand::CreateReg(0));
3003 else if (Rm != 0xF) {
3004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3005 return MCDisassembler::Fail;
3012 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3013 uint64_t Address, const void *Decoder) {
3014 DecodeStatus S = MCDisassembler::Success;
3016 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3017 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3018 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3019 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3020 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3021 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3022 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3023 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3026 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3027 return MCDisassembler::Fail;
3029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3030 return MCDisassembler::Fail;
3033 Inst.addOperand(MCOperand::CreateImm(imm));
3035 switch (Inst.getOpcode()) {
3036 case ARM::VORRiv4i16:
3037 case ARM::VORRiv2i32:
3038 case ARM::VBICiv4i16:
3039 case ARM::VBICiv2i32:
3040 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3041 return MCDisassembler::Fail;
3043 case ARM::VORRiv8i16:
3044 case ARM::VORRiv4i32:
3045 case ARM::VBICiv8i16:
3046 case ARM::VBICiv4i32:
3047 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3048 return MCDisassembler::Fail;
3057 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3058 uint64_t Address, const void *Decoder) {
3059 DecodeStatus S = MCDisassembler::Success;
3061 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3062 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3063 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3064 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3065 unsigned size = fieldFromInstruction(Insn, 18, 2);
3067 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3068 return MCDisassembler::Fail;
3069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3070 return MCDisassembler::Fail;
3071 Inst.addOperand(MCOperand::CreateImm(8 << size));
3076 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3077 uint64_t Address, const void *Decoder) {
3078 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3079 return MCDisassembler::Success;
3082 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3083 uint64_t Address, const void *Decoder) {
3084 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3085 return MCDisassembler::Success;
3088 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3089 uint64_t Address, const void *Decoder) {
3090 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3091 return MCDisassembler::Success;
3094 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3095 uint64_t Address, const void *Decoder) {
3096 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3097 return MCDisassembler::Success;
3100 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3101 uint64_t Address, const void *Decoder) {
3102 DecodeStatus S = MCDisassembler::Success;
3104 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3105 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3106 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3107 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3108 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3109 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3110 unsigned op = fieldFromInstruction(Insn, 6, 1);
3112 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3113 return MCDisassembler::Fail;
3115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3116 return MCDisassembler::Fail; // Writeback
3119 switch (Inst.getOpcode()) {
3122 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3123 return MCDisassembler::Fail;
3126 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3127 return MCDisassembler::Fail;
3130 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3131 return MCDisassembler::Fail;
3136 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3137 uint64_t Address, const void *Decoder) {
3138 DecodeStatus S = MCDisassembler::Success;
3140 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3141 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3143 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3144 return MCDisassembler::Fail;
3146 switch(Inst.getOpcode()) {
3148 return MCDisassembler::Fail;
3150 break; // tADR does not explicitly represent the PC as an operand.
3152 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3156 Inst.addOperand(MCOperand::CreateImm(imm));
3160 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3161 uint64_t Address, const void *Decoder) {
3162 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3163 true, 2, Inst, Decoder))
3164 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3165 return MCDisassembler::Success;
3168 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3169 uint64_t Address, const void *Decoder) {
3170 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3171 true, 4, Inst, Decoder))
3172 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3173 return MCDisassembler::Success;
3176 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3177 uint64_t Address, const void *Decoder) {
3178 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3179 true, 2, Inst, Decoder))
3180 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3181 return MCDisassembler::Success;
3184 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3185 uint64_t Address, const void *Decoder) {
3186 DecodeStatus S = MCDisassembler::Success;
3188 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3189 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3191 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3192 return MCDisassembler::Fail;
3193 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3194 return MCDisassembler::Fail;
3199 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3200 uint64_t Address, const void *Decoder) {
3201 DecodeStatus S = MCDisassembler::Success;
3203 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3204 unsigned imm = fieldFromInstruction(Val, 3, 5);
3206 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3207 return MCDisassembler::Fail;
3208 Inst.addOperand(MCOperand::CreateImm(imm));
3213 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3214 uint64_t Address, const void *Decoder) {
3215 unsigned imm = Val << 2;
3217 Inst.addOperand(MCOperand::CreateImm(imm));
3218 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3220 return MCDisassembler::Success;
3223 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3224 uint64_t Address, const void *Decoder) {
3225 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3226 Inst.addOperand(MCOperand::CreateImm(Val));
3228 return MCDisassembler::Success;
3231 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3232 uint64_t Address, const void *Decoder) {
3233 DecodeStatus S = MCDisassembler::Success;
3235 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3236 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3237 unsigned imm = fieldFromInstruction(Val, 0, 2);
3239 // Thumb stores cannot use PC as dest register.
3240 switch (Inst.getOpcode()) {
3245 return MCDisassembler::Fail;
3250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3251 return MCDisassembler::Fail;
3252 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3253 return MCDisassembler::Fail;
3254 Inst.addOperand(MCOperand::CreateImm(imm));
3259 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3260 uint64_t Address, const void *Decoder) {
3261 DecodeStatus S = MCDisassembler::Success;
3263 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3264 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3267 switch (Inst.getOpcode()) {
3269 Inst.setOpcode(ARM::t2LDRBpci);
3272 Inst.setOpcode(ARM::t2LDRHpci);
3275 Inst.setOpcode(ARM::t2LDRSHpci);
3278 Inst.setOpcode(ARM::t2LDRSBpci);
3281 Inst.setOpcode(ARM::t2LDRpci);
3284 Inst.setOpcode(ARM::t2PLDpci);
3287 Inst.setOpcode(ARM::t2PLIpci);
3290 return MCDisassembler::Fail;
3293 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3297 switch (Inst.getOpcode()) {
3299 return MCDisassembler::Fail;
3301 // FIXME: this instruction is only available with MP extensions,
3302 // this should be checked first but we don't have access to the
3303 // feature bits here.
3304 Inst.setOpcode(ARM::t2PLDWs);
3311 switch (Inst.getOpcode()) {
3317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3318 return MCDisassembler::Fail;
3321 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3322 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3323 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3324 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3325 return MCDisassembler::Fail;
3330 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3331 uint64_t Address, const void* Decoder) {
3332 DecodeStatus S = MCDisassembler::Success;
3334 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3335 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3336 unsigned U = fieldFromInstruction(Insn, 9, 1);
3337 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3342 switch (Inst.getOpcode()) {
3344 Inst.setOpcode(ARM::t2LDRpci);
3347 Inst.setOpcode(ARM::t2LDRBpci);
3349 case ARM::t2LDRSBi8:
3350 Inst.setOpcode(ARM::t2LDRSBpci);
3353 Inst.setOpcode(ARM::t2LDRHpci);
3355 case ARM::t2LDRSHi8:
3356 Inst.setOpcode(ARM::t2LDRSHpci);
3359 Inst.setOpcode(ARM::t2PLDpci);
3362 Inst.setOpcode(ARM::t2PLIpci);
3365 return MCDisassembler::Fail;
3367 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3371 switch (Inst.getOpcode()) {
3372 case ARM::t2LDRSHi8:
3373 return MCDisassembler::Fail;
3379 switch (Inst.getOpcode()) {
3385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3386 return MCDisassembler::Fail;
3389 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3390 return MCDisassembler::Fail;
3394 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3395 uint64_t Address, const void* Decoder) {
3396 DecodeStatus S = MCDisassembler::Success;
3398 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3399 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3400 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3404 switch (Inst.getOpcode()) {
3406 Inst.setOpcode(ARM::t2LDRpci);
3408 case ARM::t2LDRHi12:
3409 Inst.setOpcode(ARM::t2LDRHpci);
3411 case ARM::t2LDRSHi12:
3412 Inst.setOpcode(ARM::t2LDRSHpci);
3414 case ARM::t2LDRBi12:
3415 Inst.setOpcode(ARM::t2LDRBpci);
3417 case ARM::t2LDRSBi12:
3418 Inst.setOpcode(ARM::t2LDRSBpci);
3421 Inst.setOpcode(ARM::t2PLDpci);
3424 Inst.setOpcode(ARM::t2PLIpci);
3427 return MCDisassembler::Fail;
3429 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3433 switch (Inst.getOpcode()) {
3434 case ARM::t2LDRSHi12:
3435 return MCDisassembler::Fail;
3436 case ARM::t2LDRHi12:
3437 Inst.setOpcode(ARM::t2PLDi12);
3444 switch (Inst.getOpcode()) {
3446 case ARM::t2PLDWi12:
3450 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3451 return MCDisassembler::Fail;
3454 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3455 return MCDisassembler::Fail;
3459 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3460 uint64_t Address, const void* Decoder) {
3461 DecodeStatus S = MCDisassembler::Success;
3463 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3464 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3465 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3469 switch (Inst.getOpcode()) {
3471 Inst.setOpcode(ARM::t2LDRpci);
3474 Inst.setOpcode(ARM::t2LDRBpci);
3477 Inst.setOpcode(ARM::t2LDRHpci);
3480 Inst.setOpcode(ARM::t2LDRSBpci);
3483 Inst.setOpcode(ARM::t2LDRSHpci);
3486 return MCDisassembler::Fail;
3488 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3491 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3492 return MCDisassembler::Fail;
3493 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3494 return MCDisassembler::Fail;
3498 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3499 uint64_t Address, const void* Decoder) {
3500 DecodeStatus S = MCDisassembler::Success;
3502 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3503 unsigned U = fieldFromInstruction(Insn, 23, 1);
3504 int imm = fieldFromInstruction(Insn, 0, 12);
3507 switch (Inst.getOpcode()) {
3508 case ARM::t2LDRBpci:
3509 case ARM::t2LDRHpci:
3510 Inst.setOpcode(ARM::t2PLDpci);
3512 case ARM::t2LDRSBpci:
3513 Inst.setOpcode(ARM::t2PLIpci);
3515 case ARM::t2LDRSHpci:
3516 return MCDisassembler::Fail;
3522 switch(Inst.getOpcode()) {
3527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3528 return MCDisassembler::Fail;
3532 // Special case for #-0.
3538 Inst.addOperand(MCOperand::CreateImm(imm));
3543 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3544 uint64_t Address, const void *Decoder) {
3546 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3548 int imm = Val & 0xFF;
3550 if (!(Val & 0x100)) imm *= -1;
3551 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3554 return MCDisassembler::Success;
3557 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3558 uint64_t Address, const void *Decoder) {
3559 DecodeStatus S = MCDisassembler::Success;
3561 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3562 unsigned imm = fieldFromInstruction(Val, 0, 9);
3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3565 return MCDisassembler::Fail;
3566 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3567 return MCDisassembler::Fail;
3572 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3573 uint64_t Address, const void *Decoder) {
3574 DecodeStatus S = MCDisassembler::Success;
3576 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3577 unsigned imm = fieldFromInstruction(Val, 0, 8);
3579 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3580 return MCDisassembler::Fail;
3582 Inst.addOperand(MCOperand::CreateImm(imm));
3587 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3588 uint64_t Address, const void *Decoder) {
3589 int imm = Val & 0xFF;
3592 else if (!(Val & 0x100))
3594 Inst.addOperand(MCOperand::CreateImm(imm));
3596 return MCDisassembler::Success;
3600 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3601 uint64_t Address, const void *Decoder) {
3602 DecodeStatus S = MCDisassembler::Success;
3604 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3605 unsigned imm = fieldFromInstruction(Val, 0, 9);
3607 // Thumb stores cannot use PC as dest register.
3608 switch (Inst.getOpcode()) {
3616 return MCDisassembler::Fail;
3622 // Some instructions always use an additive offset.
3623 switch (Inst.getOpcode()) {
3638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3639 return MCDisassembler::Fail;
3640 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3641 return MCDisassembler::Fail;
3646 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3647 uint64_t Address, const void *Decoder) {
3648 DecodeStatus S = MCDisassembler::Success;
3650 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3651 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3652 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3653 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3655 unsigned load = fieldFromInstruction(Insn, 20, 1);
3658 switch (Inst.getOpcode()) {
3659 case ARM::t2LDR_PRE:
3660 case ARM::t2LDR_POST:
3661 Inst.setOpcode(ARM::t2LDRpci);
3663 case ARM::t2LDRB_PRE:
3664 case ARM::t2LDRB_POST:
3665 Inst.setOpcode(ARM::t2LDRBpci);
3667 case ARM::t2LDRH_PRE:
3668 case ARM::t2LDRH_POST:
3669 Inst.setOpcode(ARM::t2LDRHpci);
3671 case ARM::t2LDRSB_PRE:
3672 case ARM::t2LDRSB_POST:
3674 Inst.setOpcode(ARM::t2PLIpci);
3676 Inst.setOpcode(ARM::t2LDRSBpci);
3678 case ARM::t2LDRSH_PRE:
3679 case ARM::t2LDRSH_POST:
3680 Inst.setOpcode(ARM::t2LDRSHpci);
3683 return MCDisassembler::Fail;
3685 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3690 return MCDisassembler::Fail;
3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3694 return MCDisassembler::Fail;
3697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3698 return MCDisassembler::Fail;
3701 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3702 return MCDisassembler::Fail;
3707 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3708 uint64_t Address, const void *Decoder) {
3709 DecodeStatus S = MCDisassembler::Success;
3711 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3712 unsigned imm = fieldFromInstruction(Val, 0, 12);
3714 // Thumb stores cannot use PC as dest register.
3715 switch (Inst.getOpcode()) {
3717 case ARM::t2STRBi12:
3718 case ARM::t2STRHi12:
3720 return MCDisassembler::Fail;
3725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3726 return MCDisassembler::Fail;
3727 Inst.addOperand(MCOperand::CreateImm(imm));
3733 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3734 uint64_t Address, const void *Decoder) {
3735 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3737 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3738 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3739 Inst.addOperand(MCOperand::CreateImm(imm));
3741 return MCDisassembler::Success;
3744 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3745 uint64_t Address, const void *Decoder) {
3746 DecodeStatus S = MCDisassembler::Success;
3748 if (Inst.getOpcode() == ARM::tADDrSP) {
3749 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3750 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3753 return MCDisassembler::Fail;
3754 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3756 return MCDisassembler::Fail;
3757 } else if (Inst.getOpcode() == ARM::tADDspr) {
3758 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3760 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3761 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3763 return MCDisassembler::Fail;
3769 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3770 uint64_t Address, const void *Decoder) {
3771 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3772 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3774 Inst.addOperand(MCOperand::CreateImm(imod));
3775 Inst.addOperand(MCOperand::CreateImm(flags));
3777 return MCDisassembler::Success;
3780 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3781 uint64_t Address, const void *Decoder) {
3782 DecodeStatus S = MCDisassembler::Success;
3783 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3784 unsigned add = fieldFromInstruction(Insn, 4, 1);
3786 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3787 return MCDisassembler::Fail;
3788 Inst.addOperand(MCOperand::CreateImm(add));
3793 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3794 uint64_t Address, const void *Decoder) {
3795 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3796 // Note only one trailing zero not two. Also the J1 and J2 values are from
3797 // the encoded instruction. So here change to I1 and I2 values via:
3798 // I1 = NOT(J1 EOR S);
3799 // I2 = NOT(J2 EOR S);
3800 // and build the imm32 with two trailing zeros as documented:
3801 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3802 unsigned S = (Val >> 23) & 1;
3803 unsigned J1 = (Val >> 22) & 1;
3804 unsigned J2 = (Val >> 21) & 1;
3805 unsigned I1 = !(J1 ^ S);
3806 unsigned I2 = !(J2 ^ S);
3807 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3808 int imm32 = SignExtend32<25>(tmp << 1);
3810 if (!tryAddingSymbolicOperand(Address,
3811 (Address & ~2u) + imm32 + 4,
3812 true, 4, Inst, Decoder))
3813 Inst.addOperand(MCOperand::CreateImm(imm32));
3814 return MCDisassembler::Success;
3817 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3818 uint64_t Address, const void *Decoder) {
3819 if (Val == 0xA || Val == 0xB)
3820 return MCDisassembler::Fail;
3822 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3824 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3825 return MCDisassembler::Fail;
3827 Inst.addOperand(MCOperand::CreateImm(Val));
3828 return MCDisassembler::Success;
3832 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3833 uint64_t Address, const void *Decoder) {
3834 DecodeStatus S = MCDisassembler::Success;
3836 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3837 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3839 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3841 return MCDisassembler::Fail;
3842 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3843 return MCDisassembler::Fail;
3848 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3849 uint64_t Address, const void *Decoder) {
3850 DecodeStatus S = MCDisassembler::Success;
3852 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3853 if (pred == 0xE || pred == 0xF) {
3854 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3857 return MCDisassembler::Fail;
3859 Inst.setOpcode(ARM::t2DSB);
3862 Inst.setOpcode(ARM::t2DMB);
3865 Inst.setOpcode(ARM::t2ISB);
3869 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3870 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3873 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3874 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3875 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3876 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3877 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3879 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3880 return MCDisassembler::Fail;
3881 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3882 return MCDisassembler::Fail;
3887 // Decode a shifted immediate operand. These basically consist
3888 // of an 8-bit value, and a 4-bit directive that specifies either
3889 // a splat operation or a rotation.
3890 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3891 uint64_t Address, const void *Decoder) {
3892 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3894 unsigned byte = fieldFromInstruction(Val, 8, 2);
3895 unsigned imm = fieldFromInstruction(Val, 0, 8);
3898 Inst.addOperand(MCOperand::CreateImm(imm));
3901 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3904 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3907 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3912 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3913 unsigned rot = fieldFromInstruction(Val, 7, 5);
3914 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3915 Inst.addOperand(MCOperand::CreateImm(imm));
3918 return MCDisassembler::Success;
3922 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3923 uint64_t Address, const void *Decoder){
3924 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3925 true, 2, Inst, Decoder))
3926 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3927 return MCDisassembler::Success;
3930 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3931 uint64_t Address, const void *Decoder){
3932 // Val is passed in as S:J1:J2:imm10:imm11
3933 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3934 // the encoded instruction. So here change to I1 and I2 values via:
3935 // I1 = NOT(J1 EOR S);
3936 // I2 = NOT(J2 EOR S);
3937 // and build the imm32 with one trailing zero as documented:
3938 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3939 unsigned S = (Val >> 23) & 1;
3940 unsigned J1 = (Val >> 22) & 1;
3941 unsigned J2 = (Val >> 21) & 1;
3942 unsigned I1 = !(J1 ^ S);
3943 unsigned I2 = !(J2 ^ S);
3944 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3945 int imm32 = SignExtend32<25>(tmp << 1);
3947 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3948 true, 4, Inst, Decoder))
3949 Inst.addOperand(MCOperand::CreateImm(imm32));
3950 return MCDisassembler::Success;
3953 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3954 uint64_t Address, const void *Decoder) {
3956 return MCDisassembler::Fail;
3958 Inst.addOperand(MCOperand::CreateImm(Val));
3959 return MCDisassembler::Success;
3962 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
3963 uint64_t Address, const void *Decoder) {
3965 return MCDisassembler::Fail;
3967 Inst.addOperand(MCOperand::CreateImm(Val));
3968 return MCDisassembler::Success;
3971 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3972 uint64_t Address, const void *Decoder) {
3973 if (!Val) return MCDisassembler::Fail;
3974 Inst.addOperand(MCOperand::CreateImm(Val));
3975 return MCDisassembler::Success;
3978 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3979 uint64_t Address, const void *Decoder) {
3980 DecodeStatus S = MCDisassembler::Success;
3982 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3983 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3984 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3987 S = MCDisassembler::SoftFail;
3989 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3990 return MCDisassembler::Fail;
3991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3992 return MCDisassembler::Fail;
3993 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3994 return MCDisassembler::Fail;
3999 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4000 uint64_t Address, const void *Decoder){
4001 DecodeStatus S = MCDisassembler::Success;
4003 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4004 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4005 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4006 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4008 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4009 return MCDisassembler::Fail;
4011 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4012 S = MCDisassembler::SoftFail;
4014 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4015 return MCDisassembler::Fail;
4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4017 return MCDisassembler::Fail;
4018 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4019 return MCDisassembler::Fail;
4024 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4025 uint64_t Address, const void *Decoder) {
4026 DecodeStatus S = MCDisassembler::Success;
4028 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4029 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4030 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4031 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4032 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4033 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4035 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4038 return MCDisassembler::Fail;
4039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4040 return MCDisassembler::Fail;
4041 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4042 return MCDisassembler::Fail;
4043 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4044 return MCDisassembler::Fail;
4049 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4050 uint64_t Address, const void *Decoder) {
4051 DecodeStatus S = MCDisassembler::Success;
4053 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4054 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4055 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4056 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4057 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4058 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4059 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4061 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4062 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4065 return MCDisassembler::Fail;
4066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4067 return MCDisassembler::Fail;
4068 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4069 return MCDisassembler::Fail;
4070 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4071 return MCDisassembler::Fail;
4077 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4078 uint64_t Address, const void *Decoder) {
4079 DecodeStatus S = MCDisassembler::Success;
4081 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4082 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4083 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4084 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4085 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4086 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4088 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4091 return MCDisassembler::Fail;
4092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4093 return MCDisassembler::Fail;
4094 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4095 return MCDisassembler::Fail;
4096 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4097 return MCDisassembler::Fail;
4102 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4103 uint64_t Address, const void *Decoder) {
4104 DecodeStatus S = MCDisassembler::Success;
4106 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4107 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4108 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4109 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4110 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4111 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4113 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4116 return MCDisassembler::Fail;
4117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4118 return MCDisassembler::Fail;
4119 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4120 return MCDisassembler::Fail;
4121 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4122 return MCDisassembler::Fail;
4127 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4128 uint64_t Address, const void *Decoder) {
4129 DecodeStatus S = MCDisassembler::Success;
4131 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4132 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4133 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4134 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4135 unsigned size = fieldFromInstruction(Insn, 10, 2);
4141 return MCDisassembler::Fail;
4143 if (fieldFromInstruction(Insn, 4, 1))
4144 return MCDisassembler::Fail; // UNDEFINED
4145 index = fieldFromInstruction(Insn, 5, 3);
4148 if (fieldFromInstruction(Insn, 5, 1))
4149 return MCDisassembler::Fail; // UNDEFINED
4150 index = fieldFromInstruction(Insn, 6, 2);
4151 if (fieldFromInstruction(Insn, 4, 1))
4155 if (fieldFromInstruction(Insn, 6, 1))
4156 return MCDisassembler::Fail; // UNDEFINED
4157 index = fieldFromInstruction(Insn, 7, 1);
4159 switch (fieldFromInstruction(Insn, 4, 2)) {
4165 return MCDisassembler::Fail;
4170 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4171 return MCDisassembler::Fail;
4172 if (Rm != 0xF) { // Writeback
4173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4174 return MCDisassembler::Fail;
4176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4177 return MCDisassembler::Fail;
4178 Inst.addOperand(MCOperand::CreateImm(align));
4181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4182 return MCDisassembler::Fail;
4184 Inst.addOperand(MCOperand::CreateReg(0));
4187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4188 return MCDisassembler::Fail;
4189 Inst.addOperand(MCOperand::CreateImm(index));
4194 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4195 uint64_t Address, const void *Decoder) {
4196 DecodeStatus S = MCDisassembler::Success;
4198 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4199 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4200 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4201 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4202 unsigned size = fieldFromInstruction(Insn, 10, 2);
4208 return MCDisassembler::Fail;
4210 if (fieldFromInstruction(Insn, 4, 1))
4211 return MCDisassembler::Fail; // UNDEFINED
4212 index = fieldFromInstruction(Insn, 5, 3);
4215 if (fieldFromInstruction(Insn, 5, 1))
4216 return MCDisassembler::Fail; // UNDEFINED
4217 index = fieldFromInstruction(Insn, 6, 2);
4218 if (fieldFromInstruction(Insn, 4, 1))
4222 if (fieldFromInstruction(Insn, 6, 1))
4223 return MCDisassembler::Fail; // UNDEFINED
4224 index = fieldFromInstruction(Insn, 7, 1);
4226 switch (fieldFromInstruction(Insn, 4, 2)) {
4232 return MCDisassembler::Fail;
4237 if (Rm != 0xF) { // Writeback
4238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4239 return MCDisassembler::Fail;
4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4242 return MCDisassembler::Fail;
4243 Inst.addOperand(MCOperand::CreateImm(align));
4246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4247 return MCDisassembler::Fail;
4249 Inst.addOperand(MCOperand::CreateReg(0));
4252 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4253 return MCDisassembler::Fail;
4254 Inst.addOperand(MCOperand::CreateImm(index));
4260 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4261 uint64_t Address, const void *Decoder) {
4262 DecodeStatus S = MCDisassembler::Success;
4264 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4265 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4266 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4267 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4268 unsigned size = fieldFromInstruction(Insn, 10, 2);
4275 return MCDisassembler::Fail;
4277 index = fieldFromInstruction(Insn, 5, 3);
4278 if (fieldFromInstruction(Insn, 4, 1))
4282 index = fieldFromInstruction(Insn, 6, 2);
4283 if (fieldFromInstruction(Insn, 4, 1))
4285 if (fieldFromInstruction(Insn, 5, 1))
4289 if (fieldFromInstruction(Insn, 5, 1))
4290 return MCDisassembler::Fail; // UNDEFINED
4291 index = fieldFromInstruction(Insn, 7, 1);
4292 if (fieldFromInstruction(Insn, 4, 1) != 0)
4294 if (fieldFromInstruction(Insn, 6, 1))
4299 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4300 return MCDisassembler::Fail;
4301 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4302 return MCDisassembler::Fail;
4303 if (Rm != 0xF) { // Writeback
4304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4305 return MCDisassembler::Fail;
4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4308 return MCDisassembler::Fail;
4309 Inst.addOperand(MCOperand::CreateImm(align));
4312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4313 return MCDisassembler::Fail;
4315 Inst.addOperand(MCOperand::CreateReg(0));
4318 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4319 return MCDisassembler::Fail;
4320 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4321 return MCDisassembler::Fail;
4322 Inst.addOperand(MCOperand::CreateImm(index));
4327 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4328 uint64_t Address, const void *Decoder) {
4329 DecodeStatus S = MCDisassembler::Success;
4331 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4332 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4333 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4334 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4335 unsigned size = fieldFromInstruction(Insn, 10, 2);
4342 return MCDisassembler::Fail;
4344 index = fieldFromInstruction(Insn, 5, 3);
4345 if (fieldFromInstruction(Insn, 4, 1))
4349 index = fieldFromInstruction(Insn, 6, 2);
4350 if (fieldFromInstruction(Insn, 4, 1))
4352 if (fieldFromInstruction(Insn, 5, 1))
4356 if (fieldFromInstruction(Insn, 5, 1))
4357 return MCDisassembler::Fail; // UNDEFINED
4358 index = fieldFromInstruction(Insn, 7, 1);
4359 if (fieldFromInstruction(Insn, 4, 1) != 0)
4361 if (fieldFromInstruction(Insn, 6, 1))
4366 if (Rm != 0xF) { // Writeback
4367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4368 return MCDisassembler::Fail;
4370 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4371 return MCDisassembler::Fail;
4372 Inst.addOperand(MCOperand::CreateImm(align));
4375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4376 return MCDisassembler::Fail;
4378 Inst.addOperand(MCOperand::CreateReg(0));
4381 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4382 return MCDisassembler::Fail;
4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4384 return MCDisassembler::Fail;
4385 Inst.addOperand(MCOperand::CreateImm(index));
4391 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4392 uint64_t Address, const void *Decoder) {
4393 DecodeStatus S = MCDisassembler::Success;
4395 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4396 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4397 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4398 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4399 unsigned size = fieldFromInstruction(Insn, 10, 2);
4406 return MCDisassembler::Fail;
4408 if (fieldFromInstruction(Insn, 4, 1))
4409 return MCDisassembler::Fail; // UNDEFINED
4410 index = fieldFromInstruction(Insn, 5, 3);
4413 if (fieldFromInstruction(Insn, 4, 1))
4414 return MCDisassembler::Fail; // UNDEFINED
4415 index = fieldFromInstruction(Insn, 6, 2);
4416 if (fieldFromInstruction(Insn, 5, 1))
4420 if (fieldFromInstruction(Insn, 4, 2))
4421 return MCDisassembler::Fail; // UNDEFINED
4422 index = fieldFromInstruction(Insn, 7, 1);
4423 if (fieldFromInstruction(Insn, 6, 1))
4428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4429 return MCDisassembler::Fail;
4430 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4431 return MCDisassembler::Fail;
4432 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4433 return MCDisassembler::Fail;
4435 if (Rm != 0xF) { // Writeback
4436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4437 return MCDisassembler::Fail;
4439 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4440 return MCDisassembler::Fail;
4441 Inst.addOperand(MCOperand::CreateImm(align));
4444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4445 return MCDisassembler::Fail;
4447 Inst.addOperand(MCOperand::CreateReg(0));
4450 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4451 return MCDisassembler::Fail;
4452 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4453 return MCDisassembler::Fail;
4454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4455 return MCDisassembler::Fail;
4456 Inst.addOperand(MCOperand::CreateImm(index));
4461 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4462 uint64_t Address, const void *Decoder) {
4463 DecodeStatus S = MCDisassembler::Success;
4465 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4466 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4467 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4468 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4469 unsigned size = fieldFromInstruction(Insn, 10, 2);
4476 return MCDisassembler::Fail;
4478 if (fieldFromInstruction(Insn, 4, 1))
4479 return MCDisassembler::Fail; // UNDEFINED
4480 index = fieldFromInstruction(Insn, 5, 3);
4483 if (fieldFromInstruction(Insn, 4, 1))
4484 return MCDisassembler::Fail; // UNDEFINED
4485 index = fieldFromInstruction(Insn, 6, 2);
4486 if (fieldFromInstruction(Insn, 5, 1))
4490 if (fieldFromInstruction(Insn, 4, 2))
4491 return MCDisassembler::Fail; // UNDEFINED
4492 index = fieldFromInstruction(Insn, 7, 1);
4493 if (fieldFromInstruction(Insn, 6, 1))
4498 if (Rm != 0xF) { // Writeback
4499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4500 return MCDisassembler::Fail;
4502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4503 return MCDisassembler::Fail;
4504 Inst.addOperand(MCOperand::CreateImm(align));
4507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4508 return MCDisassembler::Fail;
4510 Inst.addOperand(MCOperand::CreateReg(0));
4513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4514 return MCDisassembler::Fail;
4515 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4516 return MCDisassembler::Fail;
4517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4518 return MCDisassembler::Fail;
4519 Inst.addOperand(MCOperand::CreateImm(index));
4525 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4526 uint64_t Address, const void *Decoder) {
4527 DecodeStatus S = MCDisassembler::Success;
4529 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4530 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4531 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4532 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4533 unsigned size = fieldFromInstruction(Insn, 10, 2);
4540 return MCDisassembler::Fail;
4542 if (fieldFromInstruction(Insn, 4, 1))
4544 index = fieldFromInstruction(Insn, 5, 3);
4547 if (fieldFromInstruction(Insn, 4, 1))
4549 index = fieldFromInstruction(Insn, 6, 2);
4550 if (fieldFromInstruction(Insn, 5, 1))
4554 switch (fieldFromInstruction(Insn, 4, 2)) {
4558 return MCDisassembler::Fail;
4560 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4563 index = fieldFromInstruction(Insn, 7, 1);
4564 if (fieldFromInstruction(Insn, 6, 1))
4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4570 return MCDisassembler::Fail;
4571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4572 return MCDisassembler::Fail;
4573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4574 return MCDisassembler::Fail;
4575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4576 return MCDisassembler::Fail;
4578 if (Rm != 0xF) { // Writeback
4579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4580 return MCDisassembler::Fail;
4582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4583 return MCDisassembler::Fail;
4584 Inst.addOperand(MCOperand::CreateImm(align));
4587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4588 return MCDisassembler::Fail;
4590 Inst.addOperand(MCOperand::CreateReg(0));
4593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4594 return MCDisassembler::Fail;
4595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4596 return MCDisassembler::Fail;
4597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4598 return MCDisassembler::Fail;
4599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4600 return MCDisassembler::Fail;
4601 Inst.addOperand(MCOperand::CreateImm(index));
4606 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4607 uint64_t Address, const void *Decoder) {
4608 DecodeStatus S = MCDisassembler::Success;
4610 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4611 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4612 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4613 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4614 unsigned size = fieldFromInstruction(Insn, 10, 2);
4621 return MCDisassembler::Fail;
4623 if (fieldFromInstruction(Insn, 4, 1))
4625 index = fieldFromInstruction(Insn, 5, 3);
4628 if (fieldFromInstruction(Insn, 4, 1))
4630 index = fieldFromInstruction(Insn, 6, 2);
4631 if (fieldFromInstruction(Insn, 5, 1))
4635 switch (fieldFromInstruction(Insn, 4, 2)) {
4639 return MCDisassembler::Fail;
4641 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4644 index = fieldFromInstruction(Insn, 7, 1);
4645 if (fieldFromInstruction(Insn, 6, 1))
4650 if (Rm != 0xF) { // Writeback
4651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4652 return MCDisassembler::Fail;
4654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4655 return MCDisassembler::Fail;
4656 Inst.addOperand(MCOperand::CreateImm(align));
4659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4660 return MCDisassembler::Fail;
4662 Inst.addOperand(MCOperand::CreateReg(0));
4665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4666 return MCDisassembler::Fail;
4667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4668 return MCDisassembler::Fail;
4669 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4670 return MCDisassembler::Fail;
4671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4672 return MCDisassembler::Fail;
4673 Inst.addOperand(MCOperand::CreateImm(index));
4678 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4679 uint64_t Address, const void *Decoder) {
4680 DecodeStatus S = MCDisassembler::Success;
4681 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4682 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4683 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4684 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4685 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4687 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4688 S = MCDisassembler::SoftFail;
4690 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4691 return MCDisassembler::Fail;
4692 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4693 return MCDisassembler::Fail;
4694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4695 return MCDisassembler::Fail;
4696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4697 return MCDisassembler::Fail;
4698 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4699 return MCDisassembler::Fail;
4704 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4705 uint64_t Address, const void *Decoder) {
4706 DecodeStatus S = MCDisassembler::Success;
4707 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4708 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4709 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4710 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4711 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4713 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4714 S = MCDisassembler::SoftFail;
4716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4717 return MCDisassembler::Fail;
4718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4719 return MCDisassembler::Fail;
4720 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4721 return MCDisassembler::Fail;
4722 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4723 return MCDisassembler::Fail;
4724 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4725 return MCDisassembler::Fail;
4730 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4731 uint64_t Address, const void *Decoder) {
4732 DecodeStatus S = MCDisassembler::Success;
4733 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4734 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4738 S = MCDisassembler::SoftFail;
4742 return MCDisassembler::Fail;
4744 Inst.addOperand(MCOperand::CreateImm(pred));
4745 Inst.addOperand(MCOperand::CreateImm(mask));
4750 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4751 uint64_t Address, const void *Decoder) {
4752 DecodeStatus S = MCDisassembler::Success;
4754 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4755 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4756 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4757 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4758 unsigned W = fieldFromInstruction(Insn, 21, 1);
4759 unsigned U = fieldFromInstruction(Insn, 23, 1);
4760 unsigned P = fieldFromInstruction(Insn, 24, 1);
4761 bool writeback = (W == 1) | (P == 0);
4763 addr |= (U << 8) | (Rn << 9);
4765 if (writeback && (Rn == Rt || Rn == Rt2))
4766 Check(S, MCDisassembler::SoftFail);
4768 Check(S, MCDisassembler::SoftFail);
4771 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4772 return MCDisassembler::Fail;
4774 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4775 return MCDisassembler::Fail;
4776 // Writeback operand
4777 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4778 return MCDisassembler::Fail;
4780 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4781 return MCDisassembler::Fail;
4787 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4788 uint64_t Address, const void *Decoder) {
4789 DecodeStatus S = MCDisassembler::Success;
4791 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4792 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4793 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4794 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4795 unsigned W = fieldFromInstruction(Insn, 21, 1);
4796 unsigned U = fieldFromInstruction(Insn, 23, 1);
4797 unsigned P = fieldFromInstruction(Insn, 24, 1);
4798 bool writeback = (W == 1) | (P == 0);
4800 addr |= (U << 8) | (Rn << 9);
4802 if (writeback && (Rn == Rt || Rn == Rt2))
4803 Check(S, MCDisassembler::SoftFail);
4805 // Writeback operand
4806 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4807 return MCDisassembler::Fail;
4809 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4810 return MCDisassembler::Fail;
4812 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4813 return MCDisassembler::Fail;
4815 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4816 return MCDisassembler::Fail;
4821 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4822 uint64_t Address, const void *Decoder) {
4823 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4824 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4825 if (sign1 != sign2) return MCDisassembler::Fail;
4827 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4828 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4829 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4831 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4833 return MCDisassembler::Success;
4836 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4838 const void *Decoder) {
4839 DecodeStatus S = MCDisassembler::Success;
4841 // Shift of "asr #32" is not allowed in Thumb2 mode.
4842 if (Val == 0x20) S = MCDisassembler::SoftFail;
4843 Inst.addOperand(MCOperand::CreateImm(Val));
4847 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4848 uint64_t Address, const void *Decoder) {
4849 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4850 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4851 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4852 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4855 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4857 DecodeStatus S = MCDisassembler::Success;
4859 if (Rt == Rn || Rn == Rt2)
4860 S = MCDisassembler::SoftFail;
4862 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4863 return MCDisassembler::Fail;
4864 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4865 return MCDisassembler::Fail;
4866 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4867 return MCDisassembler::Fail;
4868 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4869 return MCDisassembler::Fail;
4874 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4875 uint64_t Address, const void *Decoder) {
4876 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4877 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4878 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4879 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4880 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4881 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4882 unsigned op = fieldFromInstruction(Insn, 5, 1);
4884 DecodeStatus S = MCDisassembler::Success;
4886 // VMOVv2f32 is ambiguous with these decodings.
4887 if (!(imm & 0x38) && cmode == 0xF) {
4888 if (op == 1) return MCDisassembler::Fail;
4889 Inst.setOpcode(ARM::VMOVv2f32);
4890 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4893 if (!(imm & 0x20)) return MCDisassembler::Fail;
4895 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4896 return MCDisassembler::Fail;
4897 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4898 return MCDisassembler::Fail;
4899 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4904 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4905 uint64_t Address, const void *Decoder) {
4906 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4907 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4908 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4909 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4910 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4911 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4912 unsigned op = fieldFromInstruction(Insn, 5, 1);
4914 DecodeStatus S = MCDisassembler::Success;
4916 // VMOVv4f32 is ambiguous with these decodings.
4917 if (!(imm & 0x38) && cmode == 0xF) {
4918 if (op == 1) return MCDisassembler::Fail;
4919 Inst.setOpcode(ARM::VMOVv4f32);
4920 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4923 if (!(imm & 0x20)) return MCDisassembler::Fail;
4925 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4926 return MCDisassembler::Fail;
4927 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4928 return MCDisassembler::Fail;
4929 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4934 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4935 uint64_t Address, const void *Decoder) {
4936 DecodeStatus S = MCDisassembler::Success;
4938 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4939 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4940 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4941 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4942 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4944 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4945 S = MCDisassembler::SoftFail;
4947 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4948 return MCDisassembler::Fail;
4949 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4950 return MCDisassembler::Fail;
4951 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4952 return MCDisassembler::Fail;
4953 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4954 return MCDisassembler::Fail;
4955 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4956 return MCDisassembler::Fail;
4961 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4962 uint64_t Address, const void *Decoder) {
4964 DecodeStatus S = MCDisassembler::Success;
4966 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4967 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4968 unsigned cop = fieldFromInstruction(Val, 8, 4);
4969 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4970 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4972 if ((cop & ~0x1) == 0xa)
4973 return MCDisassembler::Fail;
4976 S = MCDisassembler::SoftFail;
4978 Inst.addOperand(MCOperand::CreateImm(cop));
4979 Inst.addOperand(MCOperand::CreateImm(opc1));
4980 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4981 return MCDisassembler::Fail;
4982 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4983 return MCDisassembler::Fail;
4984 Inst.addOperand(MCOperand::CreateImm(CRm));