1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
32 // lsr #32 and asr #32 exist, but should be encoded as a 0.
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
40 /// Prints the shift value with an immediate value.
41 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
42 unsigned ShImm, bool UseMarkup) {
43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48 O << getShiftOpcStr(ShOpc);
50 if (ShOpc != ARM_AM::rrx) {
54 O << "#" << translateShiftImm(ShImm);
60 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI,
63 const MCSubtargetInfo &STI) :
64 MCInstPrinter(MAI, MII, MRI) {
65 // Initialize the set of available features.
66 setAvailableFeatures(STI.getFeatureBits());
69 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
71 << getRegisterName(RegNo)
75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
77 unsigned Opcode = MI->getOpcode();
81 // Check for HINT instructions w/ canonical names.
85 switch (MI->getOperand(0).getImm()) {
86 case 0: O << "\tnop"; break;
87 case 1: O << "\tyield"; break;
88 case 2: O << "\twfe"; break;
89 case 3: O << "\twfi"; break;
90 case 4: O << "\tsev"; break;
92 if ((getAvailableFeatures() & ARM::HasV8Ops)) {
95 } // Fallthrough for non-v8
97 // Anything else should just print normally.
98 printInstruction(MI, O);
99 printAnnotation(O, Annot);
102 printPredicateOperand(MI, 1, O);
103 if (Opcode == ARM::t2HINT)
105 printAnnotation(O, Annot);
108 // Check for MOVs and print canonical forms, instead.
110 // FIXME: Thumb variants?
111 const MCOperand &Dst = MI->getOperand(0);
112 const MCOperand &MO1 = MI->getOperand(1);
113 const MCOperand &MO2 = MI->getOperand(2);
114 const MCOperand &MO3 = MI->getOperand(3);
116 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
117 printSBitModifierOperand(MI, 6, O);
118 printPredicateOperand(MI, 4, O);
121 printRegName(O, Dst.getReg());
123 printRegName(O, MO1.getReg());
126 printRegName(O, MO2.getReg());
127 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
128 printAnnotation(O, Annot);
133 // FIXME: Thumb variants?
134 const MCOperand &Dst = MI->getOperand(0);
135 const MCOperand &MO1 = MI->getOperand(1);
136 const MCOperand &MO2 = MI->getOperand(2);
138 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
139 printSBitModifierOperand(MI, 5, O);
140 printPredicateOperand(MI, 3, O);
143 printRegName(O, Dst.getReg());
145 printRegName(O, MO1.getReg());
147 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
148 printAnnotation(O, Annot);
154 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
156 printAnnotation(O, Annot);
162 case ARM::t2STMDB_UPD:
163 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
164 // Should only print PUSH if there are at least two registers in the list.
166 printPredicateOperand(MI, 2, O);
167 if (Opcode == ARM::t2STMDB_UPD)
170 printRegisterList(MI, 4, O);
171 printAnnotation(O, Annot);
176 case ARM::STR_PRE_IMM:
177 if (MI->getOperand(2).getReg() == ARM::SP &&
178 MI->getOperand(3).getImm() == -4) {
180 printPredicateOperand(MI, 4, O);
182 printRegName(O, MI->getOperand(1).getReg());
184 printAnnotation(O, Annot);
191 case ARM::t2LDMIA_UPD:
192 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
193 // Should only print POP if there are at least two registers in the list.
195 printPredicateOperand(MI, 2, O);
196 if (Opcode == ARM::t2LDMIA_UPD)
199 printRegisterList(MI, 4, O);
200 printAnnotation(O, Annot);
205 case ARM::LDR_POST_IMM:
206 if (MI->getOperand(2).getReg() == ARM::SP &&
207 MI->getOperand(4).getImm() == 4) {
209 printPredicateOperand(MI, 5, O);
211 printRegName(O, MI->getOperand(0).getReg());
213 printAnnotation(O, Annot);
219 case ARM::VSTMSDB_UPD:
220 case ARM::VSTMDDB_UPD:
221 if (MI->getOperand(0).getReg() == ARM::SP) {
222 O << '\t' << "vpush";
223 printPredicateOperand(MI, 2, O);
225 printRegisterList(MI, 4, O);
226 printAnnotation(O, Annot);
232 case ARM::VLDMSIA_UPD:
233 case ARM::VLDMDIA_UPD:
234 if (MI->getOperand(0).getReg() == ARM::SP) {
236 printPredicateOperand(MI, 2, O);
238 printRegisterList(MI, 4, O);
239 printAnnotation(O, Annot);
245 bool Writeback = true;
246 unsigned BaseReg = MI->getOperand(0).getReg();
247 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
248 if (MI->getOperand(i).getReg() == BaseReg)
254 printPredicateOperand(MI, 1, O);
256 printRegName(O, BaseReg);
257 if (Writeback) O << "!";
259 printRegisterList(MI, 3, O);
260 printAnnotation(O, Annot);
264 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
265 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
266 // a single GPRPair reg operand is used in the .td file to replace the two
267 // GPRs. However, when decoding them, the two GRPs cannot be automatically
268 // expressed as a GPRPair, so we have to manually merge them.
269 // FIXME: We would really like to be able to tablegen'erate this.
270 case ARM::LDREXD: case ARM::STREXD:
271 case ARM::LDAEXD: case ARM::STLEXD:
272 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
273 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
274 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
275 if (MRC.contains(Reg)) {
278 NewMI.setOpcode(Opcode);
281 NewMI.addOperand(MI->getOperand(0));
282 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
283 &MRI.getRegClass(ARM::GPRPairRegClassID)));
284 NewMI.addOperand(NewReg);
286 // Copy the rest operands into NewMI.
287 for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
288 NewMI.addOperand(MI->getOperand(i));
289 printInstruction(&NewMI, O);
294 printInstruction(MI, O);
295 printAnnotation(O, Annot);
298 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
300 const MCOperand &Op = MI->getOperand(OpNo);
302 unsigned Reg = Op.getReg();
303 printRegName(O, Reg);
304 } else if (Op.isImm()) {
306 << '#' << formatImm(Op.getImm())
309 assert(Op.isExpr() && "unknown operand kind in printOperand");
310 // If a symbolic branch target was added as a constant expression then print
311 // that address in hex. And only print 32 unsigned bits for the address.
312 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
314 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
316 O.write_hex((uint32_t)Address);
319 // Otherwise, just print the expression.
325 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
327 const MCOperand &MO1 = MI->getOperand(OpNum);
333 O << markup("<mem:") << "[pc, ";
335 int32_t OffImm = (int32_t)MO1.getImm();
336 bool isSub = OffImm < 0;
338 // Special value for #-0. All others are normal.
339 if (OffImm == INT32_MIN)
343 << "#-" << formatImm(-OffImm)
347 << "#" << formatImm(OffImm)
350 O << "]" << markup(">");
353 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
354 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
356 // REG REG 0,SH_OPC - e.g. R5, ROR R3
357 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
358 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
360 const MCOperand &MO1 = MI->getOperand(OpNum);
361 const MCOperand &MO2 = MI->getOperand(OpNum+1);
362 const MCOperand &MO3 = MI->getOperand(OpNum+2);
364 printRegName(O, MO1.getReg());
366 // Print the shift opc.
367 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
368 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
369 if (ShOpc == ARM_AM::rrx)
373 printRegName(O, MO2.getReg());
374 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
377 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
379 const MCOperand &MO1 = MI->getOperand(OpNum);
380 const MCOperand &MO2 = MI->getOperand(OpNum+1);
382 printRegName(O, MO1.getReg());
384 // Print the shift opc.
385 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
386 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
390 //===--------------------------------------------------------------------===//
391 // Addressing Mode #2
392 //===--------------------------------------------------------------------===//
394 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
396 const MCOperand &MO1 = MI->getOperand(Op);
397 const MCOperand &MO2 = MI->getOperand(Op+1);
398 const MCOperand &MO3 = MI->getOperand(Op+2);
400 O << markup("<mem:") << "[";
401 printRegName(O, MO1.getReg());
404 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
408 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
409 << ARM_AM::getAM2Offset(MO3.getImm())
412 O << "]" << markup(">");
417 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
418 printRegName(O, MO2.getReg());
420 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
421 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
422 O << "]" << markup(">");
425 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
427 const MCOperand &MO1 = MI->getOperand(Op);
428 const MCOperand &MO2 = MI->getOperand(Op+1);
429 O << markup("<mem:") << "[";
430 printRegName(O, MO1.getReg());
432 printRegName(O, MO2.getReg());
433 O << "]" << markup(">");
436 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
438 const MCOperand &MO1 = MI->getOperand(Op);
439 const MCOperand &MO2 = MI->getOperand(Op+1);
440 O << markup("<mem:") << "[";
441 printRegName(O, MO1.getReg());
443 printRegName(O, MO2.getReg());
444 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
447 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
449 const MCOperand &MO1 = MI->getOperand(Op);
451 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
452 printOperand(MI, Op, O);
457 const MCOperand &MO3 = MI->getOperand(Op+2);
458 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
459 assert(IdxMode != ARMII::IndexModePost &&
460 "Should be pre or offset index op");
463 printAM2PreOrOffsetIndexOp(MI, Op, O);
466 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
469 const MCOperand &MO1 = MI->getOperand(OpNum);
470 const MCOperand &MO2 = MI->getOperand(OpNum+1);
473 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
475 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
481 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
482 printRegName(O, MO1.getReg());
484 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
485 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
488 //===--------------------------------------------------------------------===//
489 // Addressing Mode #3
490 //===--------------------------------------------------------------------===//
492 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
494 const MCOperand &MO1 = MI->getOperand(Op);
495 const MCOperand &MO2 = MI->getOperand(Op+1);
496 const MCOperand &MO3 = MI->getOperand(Op+2);
498 O << markup("<mem:") << "[";
499 printRegName(O, MO1.getReg());
500 O << "], " << markup(">");
503 O << (char)ARM_AM::getAM3Op(MO3.getImm());
504 printRegName(O, MO2.getReg());
508 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
511 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
516 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
518 bool AlwaysPrintImm0) {
519 const MCOperand &MO1 = MI->getOperand(Op);
520 const MCOperand &MO2 = MI->getOperand(Op+1);
521 const MCOperand &MO3 = MI->getOperand(Op+2);
523 O << markup("<mem:") << '[';
524 printRegName(O, MO1.getReg());
527 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
528 printRegName(O, MO2.getReg());
529 O << ']' << markup(">");
533 //If the op is sub we have to print the immediate even if it is 0
534 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
535 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
537 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
541 << ARM_AM::getAddrOpcStr(op)
545 O << ']' << markup(">");
548 template <bool AlwaysPrintImm0>
549 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
551 const MCOperand &MO1 = MI->getOperand(Op);
552 if (!MO1.isReg()) { // For label symbolic references.
553 printOperand(MI, Op, O);
557 const MCOperand &MO3 = MI->getOperand(Op+2);
558 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
560 if (IdxMode == ARMII::IndexModePost) {
561 printAM3PostIndexOp(MI, Op, O);
564 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
567 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
570 const MCOperand &MO1 = MI->getOperand(OpNum);
571 const MCOperand &MO2 = MI->getOperand(OpNum+1);
574 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
575 printRegName(O, MO1.getReg());
579 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
581 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
585 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
588 const MCOperand &MO = MI->getOperand(OpNum);
589 unsigned Imm = MO.getImm();
591 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
595 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
597 const MCOperand &MO1 = MI->getOperand(OpNum);
598 const MCOperand &MO2 = MI->getOperand(OpNum+1);
600 O << (MO2.getImm() ? "" : "-");
601 printRegName(O, MO1.getReg());
604 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
607 const MCOperand &MO = MI->getOperand(OpNum);
608 unsigned Imm = MO.getImm();
610 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
615 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
617 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
619 O << ARM_AM::getAMSubModeStr(Mode);
622 template <bool AlwaysPrintImm0>
623 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
625 const MCOperand &MO1 = MI->getOperand(OpNum);
626 const MCOperand &MO2 = MI->getOperand(OpNum+1);
628 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
629 printOperand(MI, OpNum, O);
633 O << markup("<mem:") << "[";
634 printRegName(O, MO1.getReg());
636 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
637 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
638 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
642 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
646 O << "]" << markup(">");
649 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
651 const MCOperand &MO1 = MI->getOperand(OpNum);
652 const MCOperand &MO2 = MI->getOperand(OpNum+1);
654 O << markup("<mem:") << "[";
655 printRegName(O, MO1.getReg());
657 O << ":" << (MO2.getImm() << 3);
659 O << "]" << markup(">");
662 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
664 const MCOperand &MO1 = MI->getOperand(OpNum);
665 O << markup("<mem:") << "[";
666 printRegName(O, MO1.getReg());
667 O << "]" << markup(">");
670 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
673 const MCOperand &MO = MI->getOperand(OpNum);
674 if (MO.getReg() == 0)
678 printRegName(O, MO.getReg());
682 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
685 const MCOperand &MO = MI->getOperand(OpNum);
686 uint32_t v = ~MO.getImm();
687 int32_t lsb = countTrailingZeros(v);
688 int32_t width = (32 - countLeadingZeros (v)) - lsb;
689 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
690 O << markup("<imm:") << '#' << lsb << markup(">")
692 << markup("<imm:") << '#' << width << markup(">");
695 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
697 unsigned val = MI->getOperand(OpNum).getImm();
698 O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
701 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
703 unsigned val = MI->getOperand(OpNum).getImm();
704 O << ARM_ISB::InstSyncBOptToString(val);
707 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
709 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
710 bool isASR = (ShiftOp & (1 << 5)) != 0;
711 unsigned Amt = ShiftOp & 0x1f;
715 << "#" << (Amt == 0 ? 32 : Amt)
726 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
728 unsigned Imm = MI->getOperand(OpNum).getImm();
731 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
732 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
735 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
737 unsigned Imm = MI->getOperand(OpNum).getImm();
738 // A shift amount of 32 is encoded as 0.
741 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
742 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
745 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
748 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
749 if (i != OpNum) O << ", ";
750 printRegName(O, MI->getOperand(i).getReg());
755 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
757 unsigned Reg = MI->getOperand(OpNum).getReg();
758 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
760 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
764 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
766 const MCOperand &Op = MI->getOperand(OpNum);
773 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
775 const MCOperand &Op = MI->getOperand(OpNum);
776 O << ARM_PROC::IModToString(Op.getImm());
779 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
781 const MCOperand &Op = MI->getOperand(OpNum);
782 unsigned IFlags = Op.getImm();
783 for (int i=2; i >= 0; --i)
784 if (IFlags & (1 << i))
785 O << ARM_PROC::IFlagsToString(1 << i);
791 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
793 const MCOperand &Op = MI->getOperand(OpNum);
794 unsigned SpecRegRBit = Op.getImm() >> 4;
795 unsigned Mask = Op.getImm() & 0xf;
797 if (getAvailableFeatures() & ARM::FeatureMClass) {
798 unsigned SYSm = Op.getImm();
799 unsigned Opcode = MI->getOpcode();
800 // For reads of the special registers ignore the "mask encoding" bits
801 // which are only for writes.
802 if (Opcode == ARM::t2MRS_M)
805 default: llvm_unreachable("Unexpected mask value!");
807 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
808 case 0x400: O << "apsr_g"; return;
809 case 0xc00: O << "apsr_nzcvqg"; return;
811 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
812 case 0x401: O << "iapsr_g"; return;
813 case 0xc01: O << "iapsr_nzcvqg"; return;
815 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
816 case 0x402: O << "eapsr_g"; return;
817 case 0xc02: O << "eapsr_nzcvqg"; return;
819 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
820 case 0x403: O << "xpsr_g"; return;
821 case 0xc03: O << "xpsr_nzcvqg"; return;
823 case 0x805: O << "ipsr"; return;
825 case 0x806: O << "epsr"; return;
827 case 0x807: O << "iepsr"; return;
829 case 0x808: O << "msp"; return;
831 case 0x809: O << "psp"; return;
833 case 0x810: O << "primask"; return;
835 case 0x811: O << "basepri"; return;
837 case 0x812: O << "basepri_max"; return;
839 case 0x813: O << "faultmask"; return;
841 case 0x814: O << "control"; return;
845 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
846 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
847 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
850 default: llvm_unreachable("Unexpected mask value!");
851 case 4: O << "g"; return;
852 case 8: O << "nzcvq"; return;
853 case 12: O << "nzcvqg"; return;
864 if (Mask & 8) O << 'f';
865 if (Mask & 4) O << 's';
866 if (Mask & 2) O << 'x';
867 if (Mask & 1) O << 'c';
871 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
873 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
874 // Handle the undefined 15 CC value here for printing so we don't abort().
875 if ((unsigned)CC == 15)
877 else if (CC != ARMCC::AL)
878 O << ARMCondCodeToString(CC);
881 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
884 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
885 O << ARMCondCodeToString(CC);
888 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
890 if (MI->getOperand(OpNum).getReg()) {
891 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
892 "Expect ARM CPSR register!");
897 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
899 O << MI->getOperand(OpNum).getImm();
902 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
904 O << "p" << MI->getOperand(OpNum).getImm();
907 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
909 O << "c" << MI->getOperand(OpNum).getImm();
912 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
914 O << "{" << MI->getOperand(OpNum).getImm() << "}";
917 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
919 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
922 template<unsigned scale>
923 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
925 const MCOperand &MO = MI->getOperand(OpNum);
932 int32_t OffImm = (int32_t)MO.getImm() << scale;
934 O << markup("<imm:");
935 if (OffImm == INT32_MIN)
938 O << "#-" << -OffImm;
944 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
947 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
951 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
953 unsigned Imm = MI->getOperand(OpNum).getImm();
955 << "#" << formatImm((Imm == 0 ? 32 : Imm))
959 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
961 // (3 - the number of trailing zeros) is the number of then / else.
962 unsigned Mask = MI->getOperand(OpNum).getImm();
963 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
964 unsigned CondBit0 = Firstcond & 1;
965 unsigned NumTZ = countTrailingZeros(Mask);
966 assert(NumTZ <= 3 && "Invalid IT mask!");
967 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
968 bool T = ((Mask >> Pos) & 1) == CondBit0;
976 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
978 const MCOperand &MO1 = MI->getOperand(Op);
979 const MCOperand &MO2 = MI->getOperand(Op + 1);
981 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
982 printOperand(MI, Op, O);
986 O << markup("<mem:") << "[";
987 printRegName(O, MO1.getReg());
988 if (unsigned RegNum = MO2.getReg()) {
990 printRegName(O, RegNum);
992 O << "]" << markup(">");
995 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
999 const MCOperand &MO1 = MI->getOperand(Op);
1000 const MCOperand &MO2 = MI->getOperand(Op + 1);
1002 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1003 printOperand(MI, Op, O);
1007 O << markup("<mem:") << "[";
1008 printRegName(O, MO1.getReg());
1009 if (unsigned ImmOffs = MO2.getImm()) {
1012 << "#" << formatImm(ImmOffs * Scale)
1015 O << "]" << markup(">");
1018 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1021 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1024 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1027 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1030 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1033 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1036 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1038 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1041 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1042 // register with shift forms.
1043 // REG 0 0 - e.g. R5
1044 // REG IMM, SH_OPC - e.g. R5, LSL #3
1045 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1047 const MCOperand &MO1 = MI->getOperand(OpNum);
1048 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1050 unsigned Reg = MO1.getReg();
1051 printRegName(O, Reg);
1053 // Print the shift opc.
1054 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1055 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1056 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1059 template <bool AlwaysPrintImm0>
1060 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1062 const MCOperand &MO1 = MI->getOperand(OpNum);
1063 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1065 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1066 printOperand(MI, OpNum, O);
1070 O << markup("<mem:") << "[";
1071 printRegName(O, MO1.getReg());
1073 int32_t OffImm = (int32_t)MO2.getImm();
1074 bool isSub = OffImm < 0;
1075 // Special value for #-0. All others are normal.
1076 if (OffImm == INT32_MIN)
1084 else if (AlwaysPrintImm0 || OffImm > 0) {
1090 O << "]" << markup(">");
1093 template<bool AlwaysPrintImm0>
1094 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1097 const MCOperand &MO1 = MI->getOperand(OpNum);
1098 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1100 O << markup("<mem:") << "[";
1101 printRegName(O, MO1.getReg());
1103 int32_t OffImm = (int32_t)MO2.getImm();
1104 bool isSub = OffImm < 0;
1106 if (OffImm == INT32_MIN)
1113 } else if (AlwaysPrintImm0 || OffImm > 0) {
1119 O << "]" << markup(">");
1122 template<bool AlwaysPrintImm0>
1123 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1126 const MCOperand &MO1 = MI->getOperand(OpNum);
1127 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1129 if (!MO1.isReg()) { // For label symbolic references.
1130 printOperand(MI, OpNum, O);
1134 O << markup("<mem:") << "[";
1135 printRegName(O, MO1.getReg());
1137 int32_t OffImm = (int32_t)MO2.getImm();
1138 bool isSub = OffImm < 0;
1140 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1143 if (OffImm == INT32_MIN)
1150 } else if (AlwaysPrintImm0 || OffImm > 0) {
1156 O << "]" << markup(">");
1159 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1162 const MCOperand &MO1 = MI->getOperand(OpNum);
1163 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1165 O << markup("<mem:") << "[";
1166 printRegName(O, MO1.getReg());
1170 << "#" << formatImm(MO2.getImm() * 4)
1173 O << "]" << markup(">");
1176 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1179 const MCOperand &MO1 = MI->getOperand(OpNum);
1180 int32_t OffImm = (int32_t)MO1.getImm();
1181 O << ", " << markup("<imm:");
1182 if (OffImm == INT32_MIN)
1184 else if (OffImm < 0)
1185 O << "#-" << -OffImm;
1191 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1194 const MCOperand &MO1 = MI->getOperand(OpNum);
1195 int32_t OffImm = (int32_t)MO1.getImm();
1197 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1199 O << ", " << markup("<imm:");
1200 if (OffImm == INT32_MIN)
1202 else if (OffImm < 0)
1203 O << "#-" << -OffImm;
1209 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1212 const MCOperand &MO1 = MI->getOperand(OpNum);
1213 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1214 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1216 O << markup("<mem:") << "[";
1217 printRegName(O, MO1.getReg());
1219 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1221 printRegName(O, MO2.getReg());
1223 unsigned ShAmt = MO3.getImm();
1225 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1231 O << "]" << markup(">");
1234 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1236 const MCOperand &MO = MI->getOperand(OpNum);
1237 O << markup("<imm:")
1238 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1242 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1244 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1246 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1247 O << markup("<imm:")
1253 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1255 unsigned Imm = MI->getOperand(OpNum).getImm();
1256 O << markup("<imm:")
1257 << "#" << formatImm(Imm + 1)
1261 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1263 unsigned Imm = MI->getOperand(OpNum).getImm();
1270 default: assert (0 && "illegal ror immediate!");
1271 case 1: O << "8"; break;
1272 case 2: O << "16"; break;
1273 case 3: O << "24"; break;
1278 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1280 O << markup("<imm:")
1281 << "#" << 16 - MI->getOperand(OpNum).getImm()
1285 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1287 O << markup("<imm:")
1288 << "#" << 32 - MI->getOperand(OpNum).getImm()
1292 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1294 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1297 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1300 printRegName(O, MI->getOperand(OpNum).getReg());
1304 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1306 unsigned Reg = MI->getOperand(OpNum).getReg();
1307 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1308 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1310 printRegName(O, Reg0);
1312 printRegName(O, Reg1);
1316 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1319 unsigned Reg = MI->getOperand(OpNum).getReg();
1320 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1321 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1323 printRegName(O, Reg0);
1325 printRegName(O, Reg1);
1329 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1331 // Normally, it's not safe to use register enum values directly with
1332 // addition to get the next register, but for VFP registers, the
1333 // sort order is guaranteed because they're all of the form D<n>.
1335 printRegName(O, MI->getOperand(OpNum).getReg());
1337 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1339 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1343 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1345 // Normally, it's not safe to use register enum values directly with
1346 // addition to get the next register, but for VFP registers, the
1347 // sort order is guaranteed because they're all of the form D<n>.
1349 printRegName(O, MI->getOperand(OpNum).getReg());
1351 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1353 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1355 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1359 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1363 printRegName(O, MI->getOperand(OpNum).getReg());
1367 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1370 unsigned Reg = MI->getOperand(OpNum).getReg();
1371 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1372 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1374 printRegName(O, Reg0);
1376 printRegName(O, Reg1);
1380 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1383 // Normally, it's not safe to use register enum values directly with
1384 // addition to get the next register, but for VFP registers, the
1385 // sort order is guaranteed because they're all of the form D<n>.
1387 printRegName(O, MI->getOperand(OpNum).getReg());
1389 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1391 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1395 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1398 // Normally, it's not safe to use register enum values directly with
1399 // addition to get the next register, but for VFP registers, the
1400 // sort order is guaranteed because they're all of the form D<n>.
1402 printRegName(O, MI->getOperand(OpNum).getReg());
1404 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1406 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1408 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1412 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1415 unsigned Reg = MI->getOperand(OpNum).getReg();
1416 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1417 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1419 printRegName(O, Reg0);
1421 printRegName(O, Reg1);
1425 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1428 // Normally, it's not safe to use register enum values directly with
1429 // addition to get the next register, but for VFP registers, the
1430 // sort order is guaranteed because they're all of the form D<n>.
1432 printRegName(O, MI->getOperand(OpNum).getReg());
1434 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1436 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1440 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1443 // Normally, it's not safe to use register enum values directly with
1444 // addition to get the next register, but for VFP registers, the
1445 // sort order is guaranteed because they're all of the form D<n>.
1447 printRegName(O, MI->getOperand(OpNum).getReg());
1449 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1451 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1453 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1457 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1460 // Normally, it's not safe to use register enum values directly with
1461 // addition to get the next register, but for VFP registers, the
1462 // sort order is guaranteed because they're all of the form D<n>.
1464 printRegName(O, MI->getOperand(OpNum).getReg());
1466 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1468 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1472 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1475 // Normally, it's not safe to use register enum values directly with
1476 // addition to get the next register, but for VFP registers, the
1477 // sort order is guaranteed because they're all of the form D<n>.
1479 printRegName(O, MI->getOperand(OpNum).getReg());
1481 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1483 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1485 printRegName(O, MI->getOperand(OpNum).getReg() + 6);