1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/ARMMCTargetDesc.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "MCTargetDesc/ARMFixupKinds.h"
19 #include "MCTargetDesc/ARMMCExpr.h"
20 #include "llvm/ADT/APFloat.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/raw_ostream.h"
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
34 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
37 class ARMMCCodeEmitter : public MCCodeEmitter {
38 ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
39 void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
40 const MCInstrInfo &MCII;
41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
50 ~ARMMCCodeEmitter() {}
52 bool isThumb() const {
53 // FIXME: Can tablegen auto-generate this?
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
56 bool isThumb2() const {
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
59 bool isTargetDarwin() const {
60 Triple TT(STI.getTargetTriple());
61 return TT.isOSDarwin();
64 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
66 // getBinaryCodeForInstr - TableGen'erated function for getting the
67 // binary encoding for an instruction.
68 uint64_t getBinaryCodeForInstr(const MCInst &MI,
69 SmallVectorImpl<MCFixup> &Fixups) const;
71 /// getMachineOpValue - Return binary encoding of operand. If the machine
72 /// operand requires relocation, record the relocation and return zero.
73 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
77 /// the specified operand. This is used for operands with :lower16: and
78 /// :upper16: prefixes.
79 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups) const;
82 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
83 unsigned &Reg, unsigned &Imm,
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
88 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
92 /// BLX branch target.
93 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const;
96 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
97 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 SmallVectorImpl<MCFixup> &Fixups) const;
100 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
101 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
102 SmallVectorImpl<MCFixup> &Fixups) const;
104 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
105 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
106 SmallVectorImpl<MCFixup> &Fixups) const;
108 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
110 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
114 /// immediate Thumb2 direct branch target.
115 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
116 SmallVectorImpl<MCFixup> &Fixups) const;
118 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
120 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
121 SmallVectorImpl<MCFixup> &Fixups) const;
122 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
123 SmallVectorImpl<MCFixup> &Fixups) const;
124 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
127 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
128 /// ADR label target.
129 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
130 SmallVectorImpl<MCFixup> &Fixups) const;
131 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups) const;
133 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
134 SmallVectorImpl<MCFixup> &Fixups) const;
137 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
139 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
140 SmallVectorImpl<MCFixup> &Fixups) const;
142 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
143 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups)const;
146 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
148 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
149 SmallVectorImpl<MCFixup> &Fixups) const;
151 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
153 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
154 SmallVectorImpl<MCFixup> &Fixups) const;
156 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
158 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups) const;
162 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
163 /// operand as needed by load/store instructions.
164 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
165 SmallVectorImpl<MCFixup> &Fixups) const;
167 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
168 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
169 SmallVectorImpl<MCFixup> &Fixups) const {
170 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
172 default: llvm_unreachable("Unknown addressing sub-mode!");
173 case ARM_AM::da: return 0;
174 case ARM_AM::ia: return 1;
175 case ARM_AM::db: return 2;
176 case ARM_AM::ib: return 3;
179 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
181 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
183 case ARM_AM::no_shift:
184 case ARM_AM::lsl: return 0;
185 case ARM_AM::lsr: return 1;
186 case ARM_AM::asr: return 2;
188 case ARM_AM::rrx: return 3;
190 llvm_unreachable("Invalid ShiftOpc!");
193 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
194 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
195 SmallVectorImpl<MCFixup> &Fixups) const;
197 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
198 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
199 SmallVectorImpl<MCFixup> &Fixups) const;
201 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
202 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
203 SmallVectorImpl<MCFixup> &Fixups) const;
205 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
206 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
207 SmallVectorImpl<MCFixup> &Fixups) const;
209 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
210 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
211 SmallVectorImpl<MCFixup> &Fixups) const;
213 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
215 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
216 SmallVectorImpl<MCFixup> &Fixups) const;
218 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
219 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
220 SmallVectorImpl<MCFixup> &Fixups) const;
222 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
223 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
224 SmallVectorImpl<MCFixup> &Fixups) const;
226 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
227 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
228 SmallVectorImpl<MCFixup> &Fixups) const;
230 /// getCCOutOpValue - Return encoding of the 's' bit.
231 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
232 SmallVectorImpl<MCFixup> &Fixups) const {
233 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
235 return MI.getOperand(Op).getReg() == ARM::CPSR;
238 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
239 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
240 SmallVectorImpl<MCFixup> &Fixups) const {
241 unsigned SoImm = MI.getOperand(Op).getImm();
242 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
243 assert(SoImmVal != -1 && "Not a valid so_imm value!");
245 // Encode rotate_imm.
246 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
247 << ARMII::SoRotImmShift;
250 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
254 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
255 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
256 SmallVectorImpl<MCFixup> &Fixups) const {
257 unsigned SoImm = MI.getOperand(Op).getImm();
258 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
259 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
263 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
264 SmallVectorImpl<MCFixup> &Fixups) const;
265 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
266 SmallVectorImpl<MCFixup> &Fixups) const;
267 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
268 SmallVectorImpl<MCFixup> &Fixups) const;
269 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
270 SmallVectorImpl<MCFixup> &Fixups) const;
272 /// getSORegOpValue - Return an encoded so_reg shifted register value.
273 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
274 SmallVectorImpl<MCFixup> &Fixups) const;
275 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
276 SmallVectorImpl<MCFixup> &Fixups) const;
277 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
278 SmallVectorImpl<MCFixup> &Fixups) const;
280 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
281 SmallVectorImpl<MCFixup> &Fixups) const {
282 return 64 - MI.getOperand(Op).getImm();
285 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
286 SmallVectorImpl<MCFixup> &Fixups) const;
288 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
289 SmallVectorImpl<MCFixup> &Fixups) const;
290 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
291 SmallVectorImpl<MCFixup> &Fixups) const;
292 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
293 SmallVectorImpl<MCFixup> &Fixups) const;
294 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
295 SmallVectorImpl<MCFixup> &Fixups) const;
296 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
297 SmallVectorImpl<MCFixup> &Fixups) const;
299 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
300 SmallVectorImpl<MCFixup> &Fixups) const;
301 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
302 SmallVectorImpl<MCFixup> &Fixups) const;
303 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
304 SmallVectorImpl<MCFixup> &Fixups) const;
305 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
306 SmallVectorImpl<MCFixup> &Fixups) const;
308 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
309 SmallVectorImpl<MCFixup> &Fixups) const;
311 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
312 unsigned EncodedValue) const;
313 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
314 unsigned EncodedValue) const;
315 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
316 unsigned EncodedValue) const;
317 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
318 unsigned EncodedValue) const;
320 unsigned VFPThumb2PostEncoder(const MCInst &MI,
321 unsigned EncodedValue) const;
323 void EmitByte(unsigned char C, raw_ostream &OS) const {
327 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
328 // Output the constant in little endian byte order.
329 for (unsigned i = 0; i != Size; ++i) {
330 EmitByte(Val & 255, OS);
335 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
336 SmallVectorImpl<MCFixup> &Fixups) const;
339 } // end anonymous namespace
341 MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
342 const MCRegisterInfo &MRI,
343 const MCSubtargetInfo &STI,
345 return new ARMMCCodeEmitter(MCII, STI, Ctx);
348 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
349 /// instructions, and rewrite them to their Thumb2 form if we are currently in
351 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
352 unsigned EncodedValue) const {
354 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
355 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
357 unsigned Bit24 = EncodedValue & 0x01000000;
358 unsigned Bit28 = Bit24 << 4;
359 EncodedValue &= 0xEFFFFFFF;
360 EncodedValue |= Bit28;
361 EncodedValue |= 0x0F000000;
367 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
368 /// instructions, and rewrite them to their Thumb2 form if we are currently in
370 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
371 unsigned EncodedValue) const {
373 EncodedValue &= 0xF0FFFFFF;
374 EncodedValue |= 0x09000000;
380 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
381 /// instructions, and rewrite them to their Thumb2 form if we are currently in
383 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
384 unsigned EncodedValue) const {
386 EncodedValue &= 0x00FFFFFF;
387 EncodedValue |= 0xEE000000;
393 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
394 /// if we are in Thumb2.
395 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
396 unsigned EncodedValue) const {
398 EncodedValue |= 0xC000000; // Set bits 27-26
404 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
405 /// them to their Thumb2 form if we are currently in Thumb2 mode.
406 unsigned ARMMCCodeEmitter::
407 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
409 EncodedValue &= 0x0FFFFFFF;
410 EncodedValue |= 0xE0000000;
415 /// getMachineOpValue - Return binary encoding of operand. If the machine
416 /// operand requires relocation, record the relocation and return zero.
417 unsigned ARMMCCodeEmitter::
418 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
419 SmallVectorImpl<MCFixup> &Fixups) const {
421 unsigned Reg = MO.getReg();
422 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
424 // Q registers are encoded as 2x their register number.
428 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
429 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
430 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
431 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
434 } else if (MO.isImm()) {
435 return static_cast<unsigned>(MO.getImm());
436 } else if (MO.isFPImm()) {
437 return static_cast<unsigned>(APFloat(MO.getFPImm())
438 .bitcastToAPInt().getHiBits(32).getLimitedValue());
441 llvm_unreachable("Unable to encode MCOperand!");
444 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
445 bool ARMMCCodeEmitter::
446 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
447 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
448 const MCOperand &MO = MI.getOperand(OpIdx);
449 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
451 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
453 int32_t SImm = MO1.getImm();
456 // Special value for #-0
457 if (SImm == INT32_MIN) {
462 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
472 /// getBranchTargetOpValue - Helper function to get the branch target operand,
473 /// which is either an immediate or requires a fixup.
474 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
476 SmallVectorImpl<MCFixup> &Fixups) {
477 const MCOperand &MO = MI.getOperand(OpIdx);
479 // If the destination is an immediate, we have nothing to do.
480 if (MO.isImm()) return MO.getImm();
481 assert(MO.isExpr() && "Unexpected branch target type!");
482 const MCExpr *Expr = MO.getExpr();
483 MCFixupKind Kind = MCFixupKind(FixupKind);
484 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
486 // All of the information is in the fixup.
490 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
491 // determined by negating them and XOR'ing them with bit 23.
492 static int32_t encodeThumbBLOffset(int32_t offset) {
494 uint32_t S = (offset & 0x800000) >> 23;
495 uint32_t J1 = (offset & 0x400000) >> 22;
496 uint32_t J2 = (offset & 0x200000) >> 21;
509 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
510 uint32_t ARMMCCodeEmitter::
511 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
512 SmallVectorImpl<MCFixup> &Fixups) const {
513 const MCOperand MO = MI.getOperand(OpIdx);
515 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
517 return encodeThumbBLOffset(MO.getImm());
520 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
521 /// BLX branch target.
522 uint32_t ARMMCCodeEmitter::
523 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
524 SmallVectorImpl<MCFixup> &Fixups) const {
525 const MCOperand MO = MI.getOperand(OpIdx);
527 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
529 return encodeThumbBLOffset(MO.getImm());
532 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
533 uint32_t ARMMCCodeEmitter::
534 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
535 SmallVectorImpl<MCFixup> &Fixups) const {
536 const MCOperand MO = MI.getOperand(OpIdx);
538 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
540 return (MO.getImm() >> 1);
543 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
544 uint32_t ARMMCCodeEmitter::
545 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
546 SmallVectorImpl<MCFixup> &Fixups) const {
547 const MCOperand MO = MI.getOperand(OpIdx);
549 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
551 return (MO.getImm() >> 1);
554 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
555 uint32_t ARMMCCodeEmitter::
556 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
557 SmallVectorImpl<MCFixup> &Fixups) const {
558 const MCOperand MO = MI.getOperand(OpIdx);
560 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
561 return (MO.getImm() >> 1);
564 /// Return true if this branch has a non-always predication
565 static bool HasConditionalBranch(const MCInst &MI) {
566 int NumOp = MI.getNumOperands();
568 for (int i = 0; i < NumOp-1; ++i) {
569 const MCOperand &MCOp1 = MI.getOperand(i);
570 const MCOperand &MCOp2 = MI.getOperand(i + 1);
571 if (MCOp1.isImm() && MCOp2.isReg() &&
572 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
573 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
581 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
583 uint32_t ARMMCCodeEmitter::
584 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
585 SmallVectorImpl<MCFixup> &Fixups) const {
586 // FIXME: This really, really shouldn't use TargetMachine. We don't want
587 // coupling between MC and TM anywhere we can help it.
590 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
591 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
594 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
596 uint32_t ARMMCCodeEmitter::
597 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
598 SmallVectorImpl<MCFixup> &Fixups) const {
599 const MCOperand MO = MI.getOperand(OpIdx);
601 if (HasConditionalBranch(MI))
602 return ::getBranchTargetOpValue(MI, OpIdx,
603 ARM::fixup_arm_condbranch, Fixups);
604 return ::getBranchTargetOpValue(MI, OpIdx,
605 ARM::fixup_arm_uncondbranch, Fixups);
608 return MO.getImm() >> 2;
611 uint32_t ARMMCCodeEmitter::
612 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
613 SmallVectorImpl<MCFixup> &Fixups) const {
614 const MCOperand MO = MI.getOperand(OpIdx);
616 if (HasConditionalBranch(MI))
617 return ::getBranchTargetOpValue(MI, OpIdx,
618 ARM::fixup_arm_condbl, Fixups);
619 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
622 return MO.getImm() >> 2;
625 uint32_t ARMMCCodeEmitter::
626 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
627 SmallVectorImpl<MCFixup> &Fixups) const {
628 const MCOperand MO = MI.getOperand(OpIdx);
630 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
632 return MO.getImm() >> 1;
635 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
636 /// immediate branch target.
637 uint32_t ARMMCCodeEmitter::
638 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
639 SmallVectorImpl<MCFixup> &Fixups) const {
641 const MCOperand MO = MI.getOperand(OpIdx);
644 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
646 Val = MO.getImm() >> 1;
648 bool I = (Val & 0x800000);
649 bool J1 = (Val & 0x400000);
650 bool J2 = (Val & 0x200000);
664 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
665 /// ADR label target.
666 uint32_t ARMMCCodeEmitter::
667 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
668 SmallVectorImpl<MCFixup> &Fixups) const {
669 const MCOperand MO = MI.getOperand(OpIdx);
671 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
673 int64_t offset = MO.getImm();
674 uint32_t Val = 0x2000;
677 if (offset == INT32_MIN) {
680 } else if (offset < 0) {
683 SoImmVal = ARM_AM::getSOImmVal(offset);
687 SoImmVal = ARM_AM::getSOImmVal(offset);
690 SoImmVal = ARM_AM::getSOImmVal(offset);
694 SoImmVal = ARM_AM::getSOImmVal(offset);
698 assert(SoImmVal != -1 && "Not a valid so_imm value!");
704 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
706 uint32_t ARMMCCodeEmitter::
707 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
708 SmallVectorImpl<MCFixup> &Fixups) const {
709 const MCOperand MO = MI.getOperand(OpIdx);
711 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
713 int32_t Val = MO.getImm();
714 if (Val == INT32_MIN)
723 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
725 uint32_t ARMMCCodeEmitter::
726 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
727 SmallVectorImpl<MCFixup> &Fixups) const {
728 const MCOperand MO = MI.getOperand(OpIdx);
730 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
735 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
737 uint32_t ARMMCCodeEmitter::
738 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
739 SmallVectorImpl<MCFixup> &) const {
743 const MCOperand &MO1 = MI.getOperand(OpIdx);
744 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
745 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
746 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
747 return (Rm << 3) | Rn;
750 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
751 uint32_t ARMMCCodeEmitter::
752 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
753 SmallVectorImpl<MCFixup> &Fixups) const {
755 // {12} = (U)nsigned (add == '1', sub == '0')
759 // If The first operand isn't a register, we have a label reference.
760 const MCOperand &MO = MI.getOperand(OpIdx);
762 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
766 const MCExpr *Expr = MO.getExpr();
767 isAdd = false ; // 'U' bit is set as part of the fixup.
771 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
773 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
774 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
776 ++MCNumCPRelocations;
779 int32_t Offset = MO.getImm();
780 if (Offset == INT32_MIN) {
783 } else if (Offset < 0) {
790 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
792 uint32_t Binary = Imm12 & 0xfff;
793 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
796 Binary |= (Reg << 13);
800 /// getT2Imm8s4OpValue - Return encoding info for
801 /// '+/- imm8<<2' operand.
802 uint32_t ARMMCCodeEmitter::
803 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
804 SmallVectorImpl<MCFixup> &Fixups) const {
805 // FIXME: The immediate operand should have already been encoded like this
806 // before ever getting here. The encoder method should just need to combine
807 // the MI operands for the register and the offset into a single
808 // representation for the complex operand in the .td file. This isn't just
809 // style, unfortunately. As-is, we can't represent the distinct encoding
812 // {8} = (U)nsigned (add == '1', sub == '0')
814 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
815 bool isAdd = Imm8 >= 0;
817 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
819 Imm8 = -(uint32_t)Imm8;
824 uint32_t Binary = Imm8 & 0xff;
825 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
831 /// getT2AddrModeImm8s4OpValue - Return encoding info for
832 /// 'reg +/- imm8<<2' operand.
833 uint32_t ARMMCCodeEmitter::
834 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
835 SmallVectorImpl<MCFixup> &Fixups) const {
837 // {8} = (U)nsigned (add == '1', sub == '0')
841 // If The first operand isn't a register, we have a label reference.
842 const MCOperand &MO = MI.getOperand(OpIdx);
844 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
846 isAdd = false ; // 'U' bit is set as part of the fixup.
848 assert(MO.isExpr() && "Unexpected machine operand type!");
849 const MCExpr *Expr = MO.getExpr();
850 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
851 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
853 ++MCNumCPRelocations;
855 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
857 // FIXME: The immediate operand should have already been encoded like this
858 // before ever getting here. The encoder method should just need to combine
859 // the MI operands for the register and the offset into a single
860 // representation for the complex operand in the .td file. This isn't just
861 // style, unfortunately. As-is, we can't represent the distinct encoding
863 uint32_t Binary = (Imm8 >> 2) & 0xff;
864 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
867 Binary |= (Reg << 9);
871 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
872 /// 'reg + imm8<<2' operand.
873 uint32_t ARMMCCodeEmitter::
874 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
875 SmallVectorImpl<MCFixup> &Fixups) const {
878 const MCOperand &MO = MI.getOperand(OpIdx);
879 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
880 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
881 unsigned Imm8 = MO1.getImm();
882 return (Reg << 8) | Imm8;
885 // FIXME: This routine assumes that a binary
886 // expression will always result in a PCRel expression
887 // In reality, its only true if one or more subexpressions
888 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
889 // but this is good enough for now.
890 static bool EvaluateAsPCRel(const MCExpr *Expr) {
891 switch (Expr->getKind()) {
892 default: llvm_unreachable("Unexpected expression type");
893 case MCExpr::SymbolRef: return false;
894 case MCExpr::Binary: return true;
899 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
900 SmallVectorImpl<MCFixup> &Fixups) const {
901 // {20-16} = imm{15-12}
902 // {11-0} = imm{11-0}
903 const MCOperand &MO = MI.getOperand(OpIdx);
905 // Hi / lo 16 bits already extracted during earlier passes.
906 return static_cast<unsigned>(MO.getImm());
908 // Handle :upper16: and :lower16: assembly prefixes.
909 const MCExpr *E = MO.getExpr();
911 if (E->getKind() == MCExpr::Target) {
912 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
913 E = ARM16Expr->getSubExpr();
915 switch (ARM16Expr->getKind()) {
916 default: llvm_unreachable("Unsupported ARMFixup");
917 case ARMMCExpr::VK_ARM_HI16:
918 if (!isTargetDarwin() && EvaluateAsPCRel(E))
919 Kind = MCFixupKind(isThumb2()
920 ? ARM::fixup_t2_movt_hi16_pcrel
921 : ARM::fixup_arm_movt_hi16_pcrel);
923 Kind = MCFixupKind(isThumb2()
924 ? ARM::fixup_t2_movt_hi16
925 : ARM::fixup_arm_movt_hi16);
927 case ARMMCExpr::VK_ARM_LO16:
928 if (!isTargetDarwin() && EvaluateAsPCRel(E))
929 Kind = MCFixupKind(isThumb2()
930 ? ARM::fixup_t2_movw_lo16_pcrel
931 : ARM::fixup_arm_movw_lo16_pcrel);
933 Kind = MCFixupKind(isThumb2()
934 ? ARM::fixup_t2_movw_lo16
935 : ARM::fixup_arm_movw_lo16);
938 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
941 // If the expression doesn't have :upper16: or :lower16: on it,
942 // it's just a plain immediate expression, and those evaluate to
943 // the lower 16 bits of the expression regardless of whether
944 // we have a movt or a movw.
945 if (!isTargetDarwin() && EvaluateAsPCRel(E))
946 Kind = MCFixupKind(isThumb2()
947 ? ARM::fixup_t2_movw_lo16_pcrel
948 : ARM::fixup_arm_movw_lo16_pcrel);
950 Kind = MCFixupKind(isThumb2()
951 ? ARM::fixup_t2_movw_lo16
952 : ARM::fixup_arm_movw_lo16);
953 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
957 uint32_t ARMMCCodeEmitter::
958 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
959 SmallVectorImpl<MCFixup> &Fixups) const {
960 const MCOperand &MO = MI.getOperand(OpIdx);
961 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
962 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
963 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
964 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
965 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
966 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
967 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
968 unsigned SBits = getShiftOp(ShOp);
970 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
971 // amount. However, it would be an easy mistake to make so check here.
972 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
981 uint32_t Binary = Rm;
983 Binary |= SBits << 5;
984 Binary |= ShImm << 7;
990 uint32_t ARMMCCodeEmitter::
991 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
992 SmallVectorImpl<MCFixup> &Fixups) const {
994 // {13} 1 == imm12, 0 == Rm
997 const MCOperand &MO = MI.getOperand(OpIdx);
998 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
999 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
1004 uint32_t ARMMCCodeEmitter::
1005 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1006 SmallVectorImpl<MCFixup> &Fixups) const {
1007 // {13} 1 == imm12, 0 == Rm
1010 const MCOperand &MO = MI.getOperand(OpIdx);
1011 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1012 unsigned Imm = MO1.getImm();
1013 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1014 bool isReg = MO.getReg() != 0;
1015 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1016 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1018 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1019 Binary <<= 7; // Shift amount is bits [11:7]
1020 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1021 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1023 return Binary | (isAdd << 12) | (isReg << 13);
1026 uint32_t ARMMCCodeEmitter::
1027 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1028 SmallVectorImpl<MCFixup> &Fixups) const {
1031 const MCOperand &MO = MI.getOperand(OpIdx);
1032 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1033 bool isAdd = MO1.getImm() != 0;
1034 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1037 uint32_t ARMMCCodeEmitter::
1038 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1039 SmallVectorImpl<MCFixup> &Fixups) const {
1040 // {9} 1 == imm8, 0 == Rm
1042 // {7-4} imm7_4/zero
1044 const MCOperand &MO = MI.getOperand(OpIdx);
1045 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1046 unsigned Imm = MO1.getImm();
1047 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1048 bool isImm = MO.getReg() == 0;
1049 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1050 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1052 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1053 return Imm8 | (isAdd << 8) | (isImm << 9);
1056 uint32_t ARMMCCodeEmitter::
1057 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1058 SmallVectorImpl<MCFixup> &Fixups) const {
1059 // {13} 1 == imm8, 0 == Rm
1062 // {7-4} imm7_4/zero
1064 const MCOperand &MO = MI.getOperand(OpIdx);
1065 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1066 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1068 // If The first operand isn't a register, we have a label reference.
1070 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1072 assert(MO.isExpr() && "Unexpected machine operand type!");
1073 const MCExpr *Expr = MO.getExpr();
1074 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1075 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1077 ++MCNumCPRelocations;
1078 return (Rn << 9) | (1 << 13);
1080 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1081 unsigned Imm = MO2.getImm();
1082 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1083 bool isImm = MO1.getReg() == 0;
1084 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1085 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1087 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1088 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1091 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1092 uint32_t ARMMCCodeEmitter::
1093 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1094 SmallVectorImpl<MCFixup> &Fixups) const {
1097 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1098 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1099 "Unexpected base register!");
1101 // The immediate is already shifted for the implicit zeroes, so no change
1103 return MO1.getImm() & 0xff;
1106 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1107 uint32_t ARMMCCodeEmitter::
1108 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1109 SmallVectorImpl<MCFixup> &Fixups) const {
1113 const MCOperand &MO = MI.getOperand(OpIdx);
1114 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1115 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1116 unsigned Imm5 = MO1.getImm();
1117 return ((Imm5 & 0x1f) << 3) | Rn;
1120 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1121 uint32_t ARMMCCodeEmitter::
1122 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1123 SmallVectorImpl<MCFixup> &Fixups) const {
1124 const MCOperand MO = MI.getOperand(OpIdx);
1126 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1127 return (MO.getImm() >> 2);
1130 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1131 uint32_t ARMMCCodeEmitter::
1132 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1133 SmallVectorImpl<MCFixup> &Fixups) const {
1135 // {8} = (U)nsigned (add == '1', sub == '0')
1139 // If The first operand isn't a register, we have a label reference.
1140 const MCOperand &MO = MI.getOperand(OpIdx);
1142 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1144 isAdd = false; // 'U' bit is handled as part of the fixup.
1146 assert(MO.isExpr() && "Unexpected machine operand type!");
1147 const MCExpr *Expr = MO.getExpr();
1150 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1152 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1153 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1155 ++MCNumCPRelocations;
1157 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1158 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1161 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1162 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1165 Binary |= (Reg << 9);
1169 unsigned ARMMCCodeEmitter::
1170 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1171 SmallVectorImpl<MCFixup> &Fixups) const {
1172 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1173 // shifted. The second is Rs, the amount to shift by, and the third specifies
1174 // the type of the shift.
1182 const MCOperand &MO = MI.getOperand(OpIdx);
1183 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1184 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1185 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1188 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1190 // Encode the shift opcode.
1192 unsigned Rs = MO1.getReg();
1194 // Set shift operand (bit[7:4]).
1200 default: llvm_unreachable("Unknown shift opc!");
1201 case ARM_AM::lsl: SBits = 0x1; break;
1202 case ARM_AM::lsr: SBits = 0x3; break;
1203 case ARM_AM::asr: SBits = 0x5; break;
1204 case ARM_AM::ror: SBits = 0x7; break;
1208 Binary |= SBits << 4;
1210 // Encode the shift operation Rs.
1211 // Encode Rs bit[11:8].
1212 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1213 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1216 unsigned ARMMCCodeEmitter::
1217 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1218 SmallVectorImpl<MCFixup> &Fixups) const {
1219 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1220 // shifted. The second is the amount to shift by.
1227 const MCOperand &MO = MI.getOperand(OpIdx);
1228 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1229 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1232 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1234 // Encode the shift opcode.
1237 // Set shift operand (bit[6:4]).
1242 // RRX - 110 and bit[11:8] clear.
1244 default: llvm_unreachable("Unknown shift opc!");
1245 case ARM_AM::lsl: SBits = 0x0; break;
1246 case ARM_AM::lsr: SBits = 0x2; break;
1247 case ARM_AM::asr: SBits = 0x4; break;
1248 case ARM_AM::ror: SBits = 0x6; break;
1254 // Encode shift_imm bit[11:7].
1255 Binary |= SBits << 4;
1256 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1257 assert(Offset < 32 && "Offset must be in range 0-31!");
1258 return Binary | (Offset << 7);
1262 unsigned ARMMCCodeEmitter::
1263 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1264 SmallVectorImpl<MCFixup> &Fixups) const {
1265 const MCOperand &MO1 = MI.getOperand(OpNum);
1266 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1267 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1269 // Encoded as [Rn, Rm, imm].
1270 // FIXME: Needs fixup support.
1271 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1273 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1275 Value |= MO3.getImm();
1280 unsigned ARMMCCodeEmitter::
1281 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1282 SmallVectorImpl<MCFixup> &Fixups) const {
1283 const MCOperand &MO1 = MI.getOperand(OpNum);
1284 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1286 // FIXME: Needs fixup support.
1287 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1289 // Even though the immediate is 8 bits long, we need 9 bits in order
1290 // to represent the (inverse of the) sign bit.
1292 int32_t tmp = (int32_t)MO2.getImm();
1296 Value |= 256; // Set the ADD bit
1301 unsigned ARMMCCodeEmitter::
1302 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1303 SmallVectorImpl<MCFixup> &Fixups) const {
1304 const MCOperand &MO1 = MI.getOperand(OpNum);
1306 // FIXME: Needs fixup support.
1308 int32_t tmp = (int32_t)MO1.getImm();
1312 Value |= 256; // Set the ADD bit
1317 unsigned ARMMCCodeEmitter::
1318 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1319 SmallVectorImpl<MCFixup> &Fixups) const {
1320 const MCOperand &MO1 = MI.getOperand(OpNum);
1322 // FIXME: Needs fixup support.
1324 int32_t tmp = (int32_t)MO1.getImm();
1328 Value |= 4096; // Set the ADD bit
1329 Value |= tmp & 4095;
1333 unsigned ARMMCCodeEmitter::
1334 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1335 SmallVectorImpl<MCFixup> &Fixups) const {
1336 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1337 // shifted. The second is the amount to shift by.
1344 const MCOperand &MO = MI.getOperand(OpIdx);
1345 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1346 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1349 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1351 // Encode the shift opcode.
1353 // Set shift operand (bit[6:4]).
1359 default: llvm_unreachable("Unknown shift opc!");
1360 case ARM_AM::lsl: SBits = 0x0; break;
1361 case ARM_AM::lsr: SBits = 0x2; break;
1362 case ARM_AM::asr: SBits = 0x4; break;
1363 case ARM_AM::rrx: // FALLTHROUGH
1364 case ARM_AM::ror: SBits = 0x6; break;
1367 Binary |= SBits << 4;
1368 if (SOpc == ARM_AM::rrx)
1371 // Encode shift_imm bit[11:7].
1372 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1375 unsigned ARMMCCodeEmitter::
1376 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1377 SmallVectorImpl<MCFixup> &Fixups) const {
1378 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1380 const MCOperand &MO = MI.getOperand(Op);
1381 uint32_t v = ~MO.getImm();
1382 uint32_t lsb = countTrailingZeros(v);
1383 uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1384 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1385 return lsb | (msb << 5);
1388 unsigned ARMMCCodeEmitter::
1389 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1390 SmallVectorImpl<MCFixup> &Fixups) const {
1393 // {7-0} = Number of registers
1396 // {15-0} = Bitfield of GPRs.
1397 unsigned Reg = MI.getOperand(Op).getReg();
1398 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1399 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1401 unsigned Binary = 0;
1403 if (SPRRegs || DPRRegs) {
1405 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1406 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1407 Binary |= (RegNo & 0x1f) << 8;
1411 Binary |= NumRegs * 2;
1413 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1414 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1415 Binary |= 1 << RegNo;
1422 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1423 /// with the alignment operand.
1424 unsigned ARMMCCodeEmitter::
1425 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1426 SmallVectorImpl<MCFixup> &Fixups) const {
1427 const MCOperand &Reg = MI.getOperand(Op);
1428 const MCOperand &Imm = MI.getOperand(Op + 1);
1430 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1433 switch (Imm.getImm()) {
1437 case 8: Align = 0x01; break;
1438 case 16: Align = 0x02; break;
1439 case 32: Align = 0x03; break;
1442 return RegNo | (Align << 4);
1445 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1446 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1447 unsigned ARMMCCodeEmitter::
1448 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1449 SmallVectorImpl<MCFixup> &Fixups) const {
1450 const MCOperand &Reg = MI.getOperand(Op);
1451 const MCOperand &Imm = MI.getOperand(Op + 1);
1453 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1456 switch (Imm.getImm()) {
1460 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1461 case 2: Align = 0x00; break;
1462 case 4: Align = 0x03; break;
1465 return RegNo | (Align << 4);
1469 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1470 /// alignment operand for use in VLD-dup instructions. This is the same as
1471 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1472 /// different for VLD4-dup.
1473 unsigned ARMMCCodeEmitter::
1474 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1475 SmallVectorImpl<MCFixup> &Fixups) const {
1476 const MCOperand &Reg = MI.getOperand(Op);
1477 const MCOperand &Imm = MI.getOperand(Op + 1);
1479 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1482 switch (Imm.getImm()) {
1486 case 8: Align = 0x01; break;
1487 case 16: Align = 0x03; break;
1490 return RegNo | (Align << 4);
1493 unsigned ARMMCCodeEmitter::
1494 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1495 SmallVectorImpl<MCFixup> &Fixups) const {
1496 const MCOperand &MO = MI.getOperand(Op);
1497 if (MO.getReg() == 0) return 0x0D;
1498 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1501 unsigned ARMMCCodeEmitter::
1502 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1503 SmallVectorImpl<MCFixup> &Fixups) const {
1504 return 8 - MI.getOperand(Op).getImm();
1507 unsigned ARMMCCodeEmitter::
1508 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1509 SmallVectorImpl<MCFixup> &Fixups) const {
1510 return 16 - MI.getOperand(Op).getImm();
1513 unsigned ARMMCCodeEmitter::
1514 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1515 SmallVectorImpl<MCFixup> &Fixups) const {
1516 return 32 - MI.getOperand(Op).getImm();
1519 unsigned ARMMCCodeEmitter::
1520 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1521 SmallVectorImpl<MCFixup> &Fixups) const {
1522 return 64 - MI.getOperand(Op).getImm();
1525 void ARMMCCodeEmitter::
1526 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1527 SmallVectorImpl<MCFixup> &Fixups) const {
1528 // Pseudo instructions don't get encoded.
1529 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1530 uint64_t TSFlags = Desc.TSFlags;
1531 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1535 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1536 Size = Desc.getSize();
1538 llvm_unreachable("Unexpected instruction size!");
1540 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1541 // Thumb 32-bit wide instructions need to emit the high order halfword
1543 if (isThumb() && Size == 4) {
1544 EmitConstant(Binary >> 16, 2, OS);
1545 EmitConstant(Binary & 0xffff, 2, OS);
1547 EmitConstant(Binary, Size, OS);
1548 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1551 #include "ARMGenMCCodeEmitter.inc"