1 //===- BlackfinInstrInfo.cpp - Blackfin Instruction Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Blackfin implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "BlackfinInstrInfo.h"
15 #include "BlackfinSubtarget.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
24 #define GET_INSTRINFO_CTOR
25 #include "BlackfinGenInstrInfo.inc"
29 BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
30 : BlackfinGenInstrInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
34 /// isLoadFromStackSlot - If the specified machine instruction is a direct
35 /// load from a stack slot, return the virtual or physical register number of
36 /// the destination along with the FrameIndex of the loaded stack slot. If
37 /// not, return 0. This predicate must return 0 if the instruction has
38 /// any side effects other than loading from the stack slot.
39 unsigned BlackfinInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const {
41 switch (MI->getOpcode()) {
45 if (MI->getOperand(1).isFI() &&
46 MI->getOperand(2).isImm() &&
47 MI->getOperand(2).getImm() == 0) {
48 FrameIndex = MI->getOperand(1).getIndex();
49 return MI->getOperand(0).getReg();
56 /// isStoreToStackSlot - If the specified machine instruction is a direct
57 /// store to a stack slot, return the virtual or physical register number of
58 /// the source reg along with the FrameIndex of the loaded stack slot. If
59 /// not, return 0. This predicate must return 0 if the instruction has
60 /// any side effects other than storing to the stack slot.
61 unsigned BlackfinInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
62 int &FrameIndex) const {
63 switch (MI->getOpcode()) {
67 if (MI->getOperand(1).isFI() &&
68 MI->getOperand(2).isImm() &&
69 MI->getOperand(2).getImm() == 0) {
70 FrameIndex = MI->getOperand(1).getIndex();
71 return MI->getOperand(0).getReg();
78 unsigned BlackfinInstrInfo::
79 InsertBranch(MachineBasicBlock &MBB,
80 MachineBasicBlock *TBB,
81 MachineBasicBlock *FBB,
82 const SmallVectorImpl<MachineOperand> &Cond,
84 // Shouldn't be a fall through.
85 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
86 assert((Cond.size() == 1 || Cond.size() == 0) &&
87 "Branch conditions have one component!");
90 // Unconditional branch?
91 assert(!FBB && "Unconditional branch with multiple successors!");
92 BuildMI(&MBB, DL, get(BF::JUMPa)).addMBB(TBB);
96 // Conditional branch.
97 llvm_unreachable("Implement conditional branches!");
100 void BlackfinInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator I, DebugLoc DL,
102 unsigned DestReg, unsigned SrcReg,
103 bool KillSrc) const {
104 if (BF::ALLRegClass.contains(DestReg, SrcReg)) {
105 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg)
106 .addReg(SrcReg, getKillRegState(KillSrc));
110 if (BF::D16RegClass.contains(DestReg, SrcReg)) {
111 BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg)
112 .addReg(SrcReg, getKillRegState(KillSrc))
117 if (BF::DRegClass.contains(DestReg)) {
118 if (SrcReg == BF::NCC) {
119 BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg)
120 .addReg(SrcReg, getKillRegState(KillSrc));
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
124 if (SrcReg == BF::CC) {
125 BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg)
126 .addReg(SrcReg, getKillRegState(KillSrc));
131 if (BF::DRegClass.contains(SrcReg)) {
132 if (DestReg == BF::NCC) {
133 BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg)
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
137 if (DestReg == BF::CC) {
138 BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg)
139 .addReg(SrcReg, getKillRegState(KillSrc));
145 if (DestReg == BF::NCC && SrcReg == BF::CC) {
146 BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg)
147 .addReg(SrcReg, getKillRegState(KillSrc));
151 if (DestReg == BF::CC && SrcReg == BF::NCC) {
152 BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg)
153 .addReg(SrcReg, getKillRegState(KillSrc));
157 llvm_unreachable("Bad reg-to-reg copy");
160 static bool inClass(const TargetRegisterClass &Test,
162 const TargetRegisterClass *RC) {
163 if (TargetRegisterInfo::isPhysicalRegister(Reg))
164 return Test.contains(Reg);
166 return Test.hasSubClassEq(RC);
170 BlackfinInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
171 MachineBasicBlock::iterator I,
175 const TargetRegisterClass *RC,
176 const TargetRegisterInfo *TRI) const {
177 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
179 if (inClass(BF::DPRegClass, SrcReg, RC)) {
180 BuildMI(MBB, I, DL, get(BF::STORE32fi))
181 .addReg(SrcReg, getKillRegState(isKill))
187 if (inClass(BF::D16RegClass, SrcReg, RC)) {
188 BuildMI(MBB, I, DL, get(BF::STORE16fi))
189 .addReg(SrcReg, getKillRegState(isKill))
195 if (inClass(BF::AnyCCRegClass, SrcReg, RC)) {
196 BuildMI(MBB, I, DL, get(BF::STORE8fi))
197 .addReg(SrcReg, getKillRegState(isKill))
203 llvm_unreachable((std::string("Cannot store regclass to stack slot: ")+
204 RC->getName()).c_str());
207 void BlackfinInstrInfo::
208 storeRegToAddr(MachineFunction &MF,
211 SmallVectorImpl<MachineOperand> &Addr,
212 const TargetRegisterClass *RC,
213 SmallVectorImpl<MachineInstr*> &NewMIs) const {
214 llvm_unreachable("storeRegToAddr not implemented");
218 BlackfinInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator I,
222 const TargetRegisterClass *RC,
223 const TargetRegisterInfo *TRI) const {
224 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
225 if (inClass(BF::DPRegClass, DestReg, RC)) {
226 BuildMI(MBB, I, DL, get(BF::LOAD32fi), DestReg)
232 if (inClass(BF::D16RegClass, DestReg, RC)) {
233 BuildMI(MBB, I, DL, get(BF::LOAD16fi), DestReg)
239 if (inClass(BF::AnyCCRegClass, DestReg, RC)) {
240 BuildMI(MBB, I, DL, get(BF::LOAD8fi), DestReg)
246 llvm_unreachable("Cannot load regclass from stack slot");
249 void BlackfinInstrInfo::
250 loadRegFromAddr(MachineFunction &MF,
252 SmallVectorImpl<MachineOperand> &Addr,
253 const TargetRegisterClass *RC,
254 SmallVectorImpl<MachineInstr*> &NewMIs) const {
255 llvm_unreachable("loadRegFromAddr not implemented");