contrib/llvm/lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
  24 def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
  25 def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>;
  26
  27 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  28   SDNode<!strconcat("MipsISD::", Opc), Prof,
  29          [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
  30
  31 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  32   SDNode<!strconcat("MipsISD::", Opc), Prof,
  33          [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>;
  34
  35 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  36 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  37 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  38 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  39 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  40 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  41
  42 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  43 def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>;
  44
  45 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  46 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  47 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  48 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  49 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  50
  51 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  52 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  53 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  54 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  55 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  56 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  57 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  58 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  59
  60 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  61 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  62 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  63 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  64 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  65 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  66 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  69
  70 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  71 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  72 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  73 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  74 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  75 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  76
  77 // Flags.
  78 class IsCommutable {
  79   bit isCommutable = 1;
  80 }
  81
  82 class UseAC {
  83   list<Register> Uses = [AC0];
  84 }
  85
  86 class UseDSPCtrl {
  87   list<Register> Uses = [DSPCtrl];
  88 }
  89
  90 class ClearDefs {
  91   list<Register> Defs = [];
  92 }
  93
  94 // Instruction encoding.
  95 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  96 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  97 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  98 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  99 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 100 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 101 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 102 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 103 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 104 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 105 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 106 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 107 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 108 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 109 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 110 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 111 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 112 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 113 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 114 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 115 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 116 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 117 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 118 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 119 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 120 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 121 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 122 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 123 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 124 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 125 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 126 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 127 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 128 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 129 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 130 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 131 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 132 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 133 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 134 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 135 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 136 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 137 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 138 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 139 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 140 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 141 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 142 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 143 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 144 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 145 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 146 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 147 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 148 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 149 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 150 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 151 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 152 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 153 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 154 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 155 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 156 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 157 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 158 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 159 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 160 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 161 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 162 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 163 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 164 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 165 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 166 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 167 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 168 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 169 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 170 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 171 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 172 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 173 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 174 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 175 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 176 class REPL_QB_ENC : REPL_FMT<0b00010>;
 177 class REPL_PH_ENC : REPL_FMT<0b01010>;
 178 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 179 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 180 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 181 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 182 class LWX_ENC : LX_FMT<0b00000>;
 183 class LHX_ENC : LX_FMT<0b00100>;
 184 class LBUX_ENC : LX_FMT<0b00110>;
 185 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 186 class INSV_ENC : INSV_FMT<0b001100>;
 187
 188 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 189 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 190 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 191 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 192 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 193 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 194 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 195 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 196 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 197 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 198 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 199 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 200 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 201 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 202 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 203
 204 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 205 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 206 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 207 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 208 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 209 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 210 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 211 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 212 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 213 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 214 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 215 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 216 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 217 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 218 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 219 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 220 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 221 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 222 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 223 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 224 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 225 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 226 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 227 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 228 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 229 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 230 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 231 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 232 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 233 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 234 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 235 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 236 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 237 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 238 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 239 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 240 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 241 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 242 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 243 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 244 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 245 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 246 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 247 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 248 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 249 class APPEND_ENC : APPEND_FMT<0b00000>;
 250 class BALIGN_ENC : APPEND_FMT<0b10000>;
 251 class PREPEND_ENC : APPEND_FMT<0b00001>;
 252
 253 // Instruction desc.
 254 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 255                         InstrItinClass itin, RegisterClass RCD,
 256                         RegisterClass RCS,  RegisterClass RCT = RCS> {
 257   dag OutOperandList = (outs RCD:$rd);
 258   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 259   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 260   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 261   InstrItinClass Itinerary = itin;
 262   list<Register> Defs = [DSPCtrl];
 263 }
 264
 265 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 266                            InstrItinClass itin, RegisterClass RCD,
 267                            RegisterClass RCS = RCD> {
 268   dag OutOperandList = (outs RCD:$rd);
 269   dag InOperandList = (ins RCS:$rs);
 270   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 271   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
 272   InstrItinClass Itinerary = itin;
 273   list<Register> Defs = [DSPCtrl];
 274 }
 275
 276 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 277                              InstrItinClass itin, RegisterClass RCS,
 278                              RegisterClass RCT = RCS> {
 279   dag OutOperandList = (outs);
 280   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 281   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 282   list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
 283   InstrItinClass Itinerary = itin;
 284   list<Register> Defs = [DSPCtrl];
 285 }
 286
 287 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 288                              InstrItinClass itin, RegisterClass RCD,
 289                              RegisterClass RCS,  RegisterClass RCT = RCS> {
 290   dag OutOperandList = (outs RCD:$rd);
 291   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 292   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 293   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 294   InstrItinClass Itinerary = itin;
 295   list<Register> Defs = [DSPCtrl];
 296 }
 297
 298 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 299                                InstrItinClass itin, RegisterClass RCT,
 300                                RegisterClass RCS = RCT> {
 301   dag OutOperandList = (outs RCT:$rt);
 302   dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
 303   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 304   list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
 305   InstrItinClass Itinerary = itin;
 306   list<Register> Defs = [DSPCtrl];
 307   string Constraints = "$src = $rt";
 308 }
 309
 310 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 311                              InstrItinClass itin, RegisterClass RCD,
 312                              RegisterClass RCT = RCD> {
 313   dag OutOperandList = (outs RCD:$rd);
 314   dag InOperandList = (ins RCT:$rt);
 315   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 316   list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
 317   InstrItinClass Itinerary = itin;
 318   list<Register> Defs = [DSPCtrl];
 319 }
 320
 321 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 322                      ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
 323   dag OutOperandList = (outs RC:$rd);
 324   dag InOperandList = (ins uimm16:$imm);
 325   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 326   list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
 327   InstrItinClass Itinerary = itin;
 328   list<Register> Defs = [DSPCtrl];
 329 }
 330
 331 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 332                            InstrItinClass itin, RegisterClass RC> {
 333   dag OutOperandList = (outs RC:$rd);
 334   dag InOperandList =  (ins RC:$rt, CPURegs:$rs_sa);
 335   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 336   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))];
 337   InstrItinClass Itinerary = itin;
 338   list<Register> Defs = [DSPCtrl];
 339 }
 340
 341 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 342                            SDPatternOperator ImmPat, InstrItinClass itin,
 343                            RegisterClass RC> {
 344   dag OutOperandList = (outs RC:$rd);
 345   dag InOperandList = (ins RC:$rt, uimm16:$rs_sa);
 346   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 347   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
 348   InstrItinClass Itinerary = itin;
 349   list<Register> Defs = [DSPCtrl];
 350 }
 351
 352 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 353                    InstrItinClass itin> {
 354   dag OutOperandList = (outs CPURegs:$rd);
 355   dag InOperandList = (ins CPURegs:$base, CPURegs:$index);
 356   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 357   list<dag> Pattern = [(set CPURegs:$rd,
 358                        (OpNode CPURegs:$base, CPURegs:$index))];
 359   InstrItinClass Itinerary = itin;
 360   list<Register> Defs = [DSPCtrl];
 361   bit mayLoad = 1;
 362 }
 363
 364 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 365                          InstrItinClass itin, RegisterClass RCD,
 366                          RegisterClass RCS = RCD,  RegisterClass RCT = RCD> {
 367   dag OutOperandList = (outs RCD:$rd);
 368   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 369   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 370   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 371   InstrItinClass Itinerary = itin;
 372   list<Register> Defs = [DSPCtrl];
 373 }
 374
 375 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 376                        SDPatternOperator ImmOp, InstrItinClass itin> {
 377   dag OutOperandList = (outs CPURegs:$rt);
 378   dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src);
 379   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 380   list<dag> Pattern =  [(set CPURegs:$rt,
 381                         (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))];
 382   InstrItinClass Itinerary = itin;
 383   list<Register> Defs = [DSPCtrl];
 384   string Constraints = "$src = $rt";
 385 }
 386
 387 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 388                               InstrItinClass itin> {
 389   dag OutOperandList = (outs CPURegs:$rt);
 390   dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs);
 391   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 392   InstrItinClass Itinerary = itin;
 393   list<Register> Defs = [DSPCtrl];
 394 }
 395
 396 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 397                               InstrItinClass itin> {
 398   dag OutOperandList = (outs CPURegs:$rt);
 399   dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs);
 400   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 401   InstrItinClass Itinerary = itin;
 402   list<Register> Defs = [DSPCtrl];
 403 }
 404
 405 class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 406                            Instruction realinst> :
 407   PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>,
 408   PseudoInstExpansion<(realinst AC0, simm16:$shift)> {
 409   list<Register> Defs = [DSPCtrl, AC0];
 410   list<Register> Uses = [AC0];
 411   InstrItinClass Itinerary = itin;
 412 }
 413
 414 class SHILO_R1_DESC_BASE<string instr_asm> {
 415   dag OutOperandList = (outs ACRegs:$ac);
 416   dag InOperandList = (ins simm16:$shift);
 417   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 418 }
 419
 420 class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 421                            Instruction realinst> :
 422   PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>,
 423   PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> {
 424   list<Register> Defs = [DSPCtrl, AC0];
 425   list<Register> Uses = [AC0];
 426   InstrItinClass Itinerary = itin;
 427 }
 428
 429 class SHILO_R2_DESC_BASE<string instr_asm> {
 430   dag OutOperandList = (outs ACRegs:$ac);
 431   dag InOperandList = (ins CPURegs:$rs);
 432   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 433 }
 434
 435 class MTHLIP_DESC_BASE<string instr_asm> {
 436   dag OutOperandList = (outs ACRegs:$ac);
 437   dag InOperandList = (ins CPURegs:$rs);
 438   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 439 }
 440
 441 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 442                       InstrItinClass itin> {
 443   dag OutOperandList = (outs CPURegs:$rd);
 444   dag InOperandList = (ins uimm16:$mask);
 445   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 446   list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
 447   InstrItinClass Itinerary = itin;
 448   list<Register> Uses = [DSPCtrl];
 449 }
 450
 451 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 452                       InstrItinClass itin> {
 453   dag OutOperandList = (outs);
 454   dag InOperandList = (ins CPURegs:$rs, uimm16:$mask);
 455   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 456   list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)];
 457   InstrItinClass Itinerary = itin;
 458   list<Register> Defs = [DSPCtrl];
 459 }
 460
 461 class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 462                            Instruction realinst> :
 463   PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
 464             [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
 465   PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
 466   list<Register> Defs = [DSPCtrl, AC0];
 467   list<Register> Uses = [AC0];
 468   InstrItinClass Itinerary = itin;
 469 }
 470
 471 class DPA_W_PH_DESC_BASE<string instr_asm> {
 472   dag OutOperandList = (outs ACRegs:$ac);
 473   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 474   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 475 }
 476
 477 class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
 478                        Instruction realinst> :
 479   PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
 480             [(OpNode CPURegs:$rs, CPURegs:$rt)]>,
 481   PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> {
 482   list<Register> Defs = [DSPCtrl, AC0];
 483   InstrItinClass Itinerary = itin;
 484 }
 485
 486 class MULT_DESC_BASE<string instr_asm> {
 487   dag OutOperandList = (outs ACRegs:$ac);
 488   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 489   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 490 }
 491
 492 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 493   MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> {
 494   list<Register> Uses = [DSPCtrl];
 495   bit usesCustomInserter = 1;
 496 }
 497
 498 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 499   dag OutOperandList = (outs);
 500   dag InOperandList = (ins brtarget:$offset);
 501   string AsmString = !strconcat(instr_asm, "\t$offset");
 502   InstrItinClass Itinerary = itin;
 503   list<Register> Uses = [DSPCtrl];
 504   bit isBranch = 1;
 505   bit isTerminator = 1;
 506   bit hasDelaySlot = 1;
 507 }
 508
 509 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 510                      InstrItinClass itin> {
 511   dag OutOperandList = (outs CPURegs:$rt);
 512   dag InOperandList = (ins CPURegs:$src, CPURegs:$rs);
 513   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 514   list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))];
 515   InstrItinClass Itinerary = itin;
 516   list<Register> Uses = [DSPCtrl];
 517   string Constraints = "$src = $rt";
 518 }
 519
 520 //===----------------------------------------------------------------------===//
 521 // MIPS DSP Rev 1
 522 //===----------------------------------------------------------------------===//
 523
 524 // Addition/subtraction
 525 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary,
 526                                        DSPRegs, DSPRegs>, IsCommutable;
 527
 528 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 529                                          NoItinerary, DSPRegs, DSPRegs>,
 530                        IsCommutable;
 531
 532 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary,
 533                                        DSPRegs, DSPRegs>;
 534
 535 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 536                                          NoItinerary, DSPRegs, DSPRegs>;
 537
 538 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary,
 539                                        DSPRegs, DSPRegs>, IsCommutable;
 540
 541 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 542                                          NoItinerary, DSPRegs, DSPRegs>,
 543                        IsCommutable;
 544
 545 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary,
 546                                        DSPRegs, DSPRegs>;
 547
 548 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 549                                          NoItinerary, DSPRegs, DSPRegs>;
 550
 551 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 552                                         NoItinerary, CPURegs, CPURegs>,
 553                       IsCommutable;
 554
 555 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 556                                         NoItinerary, CPURegs, CPURegs>;
 557
 558 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary,
 559                                      CPURegs, CPURegs>, IsCommutable;
 560
 561 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary,
 562                                      CPURegs, CPURegs>,
 563                    IsCommutable, UseDSPCtrl;
 564
 565 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 566                                       CPURegs, CPURegs>, ClearDefs;
 567
 568 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 569                                              NoItinerary, CPURegs, DSPRegs>,
 570                         ClearDefs;
 571
 572 // Absolute value
 573 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 574                                               NoItinerary, DSPRegs>;
 575
 576 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 577                                              NoItinerary, CPURegs>;
 578
 579 // Precision reduce/expand
 580 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 581                                                  int_mips_precrq_qb_ph,
 582                                                  NoItinerary, DSPRegs, DSPRegs>,
 583                           ClearDefs;
 584
 585 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 586                                                 int_mips_precrq_ph_w,
 587                                                 NoItinerary, DSPRegs, CPURegs>,
 588                          ClearDefs;
 589
 590 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 591                                                    int_mips_precrq_rs_ph_w,
 592                                                    NoItinerary, DSPRegs,
 593                                                    CPURegs>;
 594
 595 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 596                                                     int_mips_precrqu_s_qb_ph,
 597                                                     NoItinerary, DSPRegs,
 598                                                     DSPRegs>;
 599
 600 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 601                                                  int_mips_preceq_w_phl,
 602                                                  NoItinerary, CPURegs, DSPRegs>,
 603                           ClearDefs;
 604
 605 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 606                                                  int_mips_preceq_w_phr,
 607                                                  NoItinerary, CPURegs, DSPRegs>,
 608                           ClearDefs;
 609
 610 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 611                                                    int_mips_precequ_ph_qbl,
 612                                                    NoItinerary, DSPRegs>,
 613                             ClearDefs;
 614
 615 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 616                                                    int_mips_precequ_ph_qbr,
 617                                                    NoItinerary, DSPRegs>,
 618                             ClearDefs;
 619
 620 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 621                                                     int_mips_precequ_ph_qbla,
 622                                                     NoItinerary, DSPRegs>,
 623                              ClearDefs;
 624
 625 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 626                                                     int_mips_precequ_ph_qbra,
 627                                                     NoItinerary, DSPRegs>,
 628                              ClearDefs;
 629
 630 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 631                                                   int_mips_preceu_ph_qbl,
 632                                                   NoItinerary, DSPRegs>,
 633                            ClearDefs;
 634
 635 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 636                                                   int_mips_preceu_ph_qbr,
 637                                                   NoItinerary, DSPRegs>,
 638                            ClearDefs;
 639
 640 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 641                                                    int_mips_preceu_ph_qbla,
 642                                                    NoItinerary, DSPRegs>,
 643                             ClearDefs;
 644
 645 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 646                                                    int_mips_preceu_ph_qbra,
 647                                                    NoItinerary, DSPRegs>,
 648                             ClearDefs;
 649
 650 // Shift
 651 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3,
 652                                           NoItinerary, DSPRegs>;
 653
 654 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 655                                            NoItinerary, DSPRegs>;
 656
 657 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3,
 658                                           NoItinerary, DSPRegs>, ClearDefs;
 659
 660 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 661                                            NoItinerary, DSPRegs>, ClearDefs;
 662
 663 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4,
 664                                           NoItinerary, DSPRegs>;
 665
 666 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 667                                            NoItinerary, DSPRegs>;
 668
 669 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 670                                             immZExt4, NoItinerary, DSPRegs>;
 671
 672 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 673                                              NoItinerary, DSPRegs>;
 674
 675 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4,
 676                                           NoItinerary, DSPRegs>, ClearDefs;
 677
 678 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 679                                            NoItinerary, DSPRegs>, ClearDefs;
 680
 681 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 682                                             immZExt4, NoItinerary, DSPRegs>,
 683                        ClearDefs;
 684
 685 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 686                                              NoItinerary, DSPRegs>, ClearDefs;
 687
 688 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 689                                            immZExt5, NoItinerary, CPURegs>;
 690
 691 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 692                                             NoItinerary, CPURegs>;
 693
 694 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 695                                            immZExt5, NoItinerary, CPURegs>,
 696                       ClearDefs;
 697
 698 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 699                                             NoItinerary, CPURegs>;
 700
 701 // Multiplication
 702 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 703                                               int_mips_muleu_s_ph_qbl,
 704                                               NoItinerary, DSPRegs, DSPRegs>;
 705
 706 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 707                                               int_mips_muleu_s_ph_qbr,
 708                                               NoItinerary, DSPRegs, DSPRegs>;
 709
 710 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 711                                              int_mips_muleq_s_w_phl,
 712                                              NoItinerary, CPURegs, DSPRegs>,
 713                            IsCommutable;
 714
 715 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 716                                              int_mips_muleq_s_w_phr,
 717                                              NoItinerary, CPURegs, DSPRegs>,
 718                            IsCommutable;
 719
 720 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 721                                           NoItinerary, DSPRegs, DSPRegs>,
 722                         IsCommutable;
 723
 724 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">;
 725
 726 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">;
 727
 728 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">;
 729
 730 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">;
 731
 732 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">;
 733
 734 // Dot product with accumulate/subtract
 735 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">;
 736
 737 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">;
 738
 739 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">;
 740
 741 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">;
 742
 743 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">;
 744
 745 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">;
 746
 747 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">;
 748
 749 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">;
 750
 751 class MULT_DSP_DESC : MULT_DESC_BASE<"mult">;
 752
 753 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">;
 754
 755 class MADD_DSP_DESC : MULT_DESC_BASE<"madd">;
 756
 757 class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">;
 758
 759 class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">;
 760
 761 class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">;
 762
 763 // Comparison
 764 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 765                                                int_mips_cmpu_eq_qb, NoItinerary,
 766                                                DSPRegs>, IsCommutable;
 767
 768 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 769                                                int_mips_cmpu_lt_qb, NoItinerary,
 770                                                DSPRegs>, IsCommutable;
 771
 772 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 773                                                int_mips_cmpu_le_qb, NoItinerary,
 774                                                DSPRegs>, IsCommutable;
 775
 776 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 777                                                 int_mips_cmpgu_eq_qb,
 778                                                 NoItinerary, CPURegs, DSPRegs>,
 779                          IsCommutable;
 780
 781 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 782                                                 int_mips_cmpgu_lt_qb,
 783                                                 NoItinerary, CPURegs, DSPRegs>,
 784                          IsCommutable;
 785
 786 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 787                                                 int_mips_cmpgu_le_qb,
 788                                                 NoItinerary, CPURegs, DSPRegs>,
 789                          IsCommutable;
 790
 791 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 792                                               NoItinerary, DSPRegs>,
 793                        IsCommutable;
 794
 795 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 796                                               NoItinerary, DSPRegs>,
 797                        IsCommutable;
 798
 799 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 800                                               NoItinerary, DSPRegs>,
 801                        IsCommutable;
 802
 803 // Misc
 804 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 805                                            NoItinerary, CPURegs>, ClearDefs;
 806
 807 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 808                                               NoItinerary, DSPRegs, DSPRegs>,
 809                        ClearDefs;
 810
 811 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 812                                     NoItinerary, DSPRegs>, ClearDefs;
 813
 814 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 815                                     NoItinerary, DSPRegs>, ClearDefs;
 816
 817 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 818                                              NoItinerary, DSPRegs, CPURegs>,
 819                       ClearDefs;
 820
 821 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 822                                              NoItinerary, DSPRegs, CPURegs>,
 823                       ClearDefs;
 824
 825 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 826                                             NoItinerary, DSPRegs, DSPRegs>,
 827                      ClearDefs, UseDSPCtrl;
 828
 829 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 830                                             NoItinerary, DSPRegs, DSPRegs>,
 831                      ClearDefs, UseDSPCtrl;
 832
 833 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs;
 834
 835 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs;
 836
 837 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs;
 838
 839 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 840
 841 // Extr
 842 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
 843
 844 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
 845
 846 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
 847
 848 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 849                                              NoItinerary>;
 850
 851 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
 852
 853 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 854                                              NoItinerary>;
 855
 856 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 857                                               NoItinerary>;
 858
 859 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 860                                                NoItinerary>;
 861
 862 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 863                                                NoItinerary>;
 864
 865 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 866                                                 NoItinerary>;
 867
 868 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 869                                               NoItinerary>;
 870
 871 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 872                                                NoItinerary>;
 873
 874 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">;
 875
 876 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">;
 877
 878 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
 879
 880 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 881
 882 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 883
 884 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>;
 885
 886 //===----------------------------------------------------------------------===//
 887 // MIPS DSP Rev 2
 888 // Addition/subtraction
 889 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 890                                        DSPRegs, DSPRegs>, IsCommutable;
 891
 892 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 893                                          NoItinerary, DSPRegs, DSPRegs>,
 894                        IsCommutable;
 895
 896 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 897                                        DSPRegs, DSPRegs>;
 898
 899 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 900                                          NoItinerary, DSPRegs, DSPRegs>;
 901
 902 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 903                                          NoItinerary, DSPRegs>,
 904                       ClearDefs, IsCommutable;
 905
 906 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 907                                            NoItinerary, DSPRegs>,
 908                         ClearDefs, IsCommutable;
 909
 910 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 911                                          NoItinerary, DSPRegs>, ClearDefs;
 912
 913 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 914                                            NoItinerary, DSPRegs>, ClearDefs;
 915
 916 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 917                                          NoItinerary, DSPRegs>,
 918                       ClearDefs, IsCommutable;
 919
 920 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 921                                            NoItinerary, DSPRegs>,
 922                         ClearDefs, IsCommutable;
 923
 924 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 925                                          NoItinerary, DSPRegs>, ClearDefs;
 926
 927 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 928                                            NoItinerary, DSPRegs>, ClearDefs;
 929
 930 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 931                                         NoItinerary, CPURegs>,
 932                      ClearDefs, IsCommutable;
 933
 934 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 935                                           NoItinerary, CPURegs>,
 936                        ClearDefs, IsCommutable;
 937
 938 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 939                                         NoItinerary, CPURegs>, ClearDefs;
 940
 941 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 942                                           NoItinerary, CPURegs>, ClearDefs;
 943
 944 // Comparison
 945 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 946                                                  int_mips_cmpgdu_eq_qb,
 947                                                  NoItinerary, CPURegs, DSPRegs>,
 948                           IsCommutable;
 949
 950 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 951                                                  int_mips_cmpgdu_lt_qb,
 952                                                  NoItinerary, CPURegs, DSPRegs>,
 953                           IsCommutable;
 954
 955 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 956                                                  int_mips_cmpgdu_le_qb,
 957                                                  NoItinerary, CPURegs, DSPRegs>,
 958                           IsCommutable;
 959
 960 // Absolute
 961 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 962                                               NoItinerary, DSPRegs>;
 963
 964 // Multiplication
 965 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", int_mips_mul_ph, NoItinerary,
 966                                        DSPRegs>, IsCommutable;
 967
 968 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 969                                          NoItinerary, DSPRegs>, IsCommutable;
 970
 971 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 972                                          NoItinerary, CPURegs>, IsCommutable;
 973
 974 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 975                                           NoItinerary, CPURegs>, IsCommutable;
 976
 977 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
 978                                          NoItinerary, DSPRegs, DSPRegs>,
 979                        IsCommutable;
 980
 981 // Dot product with accumulate/subtract
 982 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">;
 983
 984 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">;
 985
 986 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">;
 987
 988 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">;
 989
 990 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">;
 991
 992 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">;
 993
 994 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">;
 995
 996 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">;
 997
 998 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">;
 999
1000 // Precision reduce/expand
1001 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1002                                                 int_mips_precr_qb_ph,
1003                                                 NoItinerary, DSPRegs, DSPRegs>;
1004
1005 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1006                                                      int_mips_precr_sra_ph_w,
1007                                                      NoItinerary, DSPRegs,
1008                                                      CPURegs>, ClearDefs;
1009
1010 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1011                                                       int_mips_precr_sra_r_ph_w,
1012                                                        NoItinerary, DSPRegs,
1013                                                        CPURegs>, ClearDefs;
1014
1015 // Shift
1016 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3,
1017                                           NoItinerary, DSPRegs>, ClearDefs;
1018
1019 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1020                                            NoItinerary, DSPRegs>, ClearDefs;
1021
1022 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1023                                             immZExt3, NoItinerary, DSPRegs>,
1024                        ClearDefs;
1025
1026 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1027                                              NoItinerary, DSPRegs>, ClearDefs;
1028
1029 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4,
1030                                           NoItinerary, DSPRegs>, ClearDefs;
1031
1032 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1033                                            NoItinerary, DSPRegs>, ClearDefs;
1034
1035 // Misc
1036 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1037                                      NoItinerary>, ClearDefs;
1038
1039 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1040                                      NoItinerary>, ClearDefs;
1041
1042 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1043                                       NoItinerary>, ClearDefs;
1044
1045 // Pseudos.
1046 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
1047
1048 // Instruction defs.
1049 // MIPS DSP Rev 1
1050 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
1051 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1052 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1053 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1054 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1055 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1056 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1057 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1058 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1059 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1060 def ADDSC : ADDSC_ENC, ADDSC_DESC;
1061 def ADDWC : ADDWC_ENC, ADDWC_DESC;
1062 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1063 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1064 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1065 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1066 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1067 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1068 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1069 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1070 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1071 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1072 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1073 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1074 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1075 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1076 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1077 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1078 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1079 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1080 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1081 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1082 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1083 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1084 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1085 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1086 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1087 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1088 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1089 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1090 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1091 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1092 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1093 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1094 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1095 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1096 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1097 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1098 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1099 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1100 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1101 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1102 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1103 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1104 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1105 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1106 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1107 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1108 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1109 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1110 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1111 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1112 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1113 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1114 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1115 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1116 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1117 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1118 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1119 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1120 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1121 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1122 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1123 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1124 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1125 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1126 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1127 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1128 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1129 def BITREV : BITREV_ENC, BITREV_DESC;
1130 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1131 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1132 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1133 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1134 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1135 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1136 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1137 def LWX : LWX_ENC, LWX_DESC;
1138 def LHX : LHX_ENC, LHX_DESC;
1139 def LBUX : LBUX_ENC, LBUX_DESC;
1140 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1141 def INSV : INSV_ENC, INSV_DESC;
1142 def EXTP : EXTP_ENC, EXTP_DESC;
1143 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1144 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1145 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1146 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1147 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1148 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1149 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1150 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1151 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1152 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1153 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1154 def SHILO : SHILO_ENC, SHILO_DESC;
1155 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1156 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1157 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1158 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1159
1160 // MIPS DSP Rev 2
1161 let Predicates = [HasDSPR2] in {
1162
1163 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1164 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1165 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1166 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1167 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1168 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1169 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1170 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1171 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1172 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1173 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1174 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1175 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1176 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1177 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1178 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1179 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1180 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1181 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1182 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1183 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1184 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1185 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1186 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1187 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1188 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
1189 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1190 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1191 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1192 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1193 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1194 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1195 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1196 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1197 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1198 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1199 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1200 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1201 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1202 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1203 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1204 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1205 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1206 def APPEND : APPEND_ENC, APPEND_DESC;
1207 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1208 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1209
1210 }
1211
1212 // Pseudos.
1213 def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary,
1214                                                 MULSAQ_S_W_PH>;
1215 def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary,
1216                                               MAQ_S_W_PHL>;
1217 def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary,
1218                                               MAQ_S_W_PHR>;
1219 def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary,
1220                                                MAQ_SA_W_PHL>;
1221 def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary,
1222                                                MAQ_SA_W_PHR>;
1223 def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary,
1224                                              DPAU_H_QBL>;
1225 def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary,
1226                                              DPAU_H_QBR>;
1227 def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary,
1228                                              DPSU_H_QBL>;
1229 def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary,
1230                                              DPSU_H_QBR>;
1231 def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary,
1232                                               DPAQ_S_W_PH>;
1233 def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary,
1234                                               DPSQ_S_W_PH>;
1235 def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary,
1236                                               DPAQ_SA_L_W>;
1237 def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary,
1238                                               DPSQ_SA_L_W>;
1239
1240 def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>,
1241                       IsCommutable;
1242 def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>,
1243                        IsCommutable;
1244 def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>,
1245                       IsCommutable, UseAC;
1246 def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>,
1247                        IsCommutable, UseAC;
1248 def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>,
1249                       UseAC;
1250 def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>,
1251                        UseAC;
1252
1253 def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>;
1254 def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>;
1255 def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>;
1256
1257 let Predicates = [HasDSPR2] in {
1258
1259 def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>;
1260 def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>;
1261 def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary,
1262                                                DPAQX_S_W_PH>;
1263 def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary,
1264                                                 DPAQX_SA_W_PH>;
1265 def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary,
1266                                             DPAX_W_PH>;
1267 def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary,
1268                                             DPSX_W_PH>;
1269 def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary,
1270                                                DPSQX_S_W_PH>;
1271 def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary,
1272                                                 DPSQX_SA_W_PH>;
1273 def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary,
1274                                              MULSA_W_PH>;
1275
1276 }
1277
1278 // Patterns.
1279 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1280   Pat<pattern, result>, Requires<[pred]>;
1281
1282 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1283                     RegisterClass SrcRC> :
1284    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1285           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1286
1287 def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
1288 def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
1289 def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
1290 def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
1291
1292 def : DSPPat<(v2i16 (load addr:$a)),
1293              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1294 def : DSPPat<(v4i8 (load addr:$a)),
1295              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1296 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
1297              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1298 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
1299              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1300
1301 // Extr patterns.
1302 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1303   DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>;
1304
1305 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1306   DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>;
1307
1308 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1309 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1310 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1311 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1312 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1313 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1314 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1315 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1316 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1317 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1318 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1319 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;