1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "llvm/MC/MCTargetAsmParser.h"
12 #include "llvm/MC/MCStreamer.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/MC/MCParser/MCAsmLexer.h"
18 #include "llvm/MC/MCParser/MCAsmParser.h"
19 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/Support/SourceMgr.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/raw_ostream.h"
32 static unsigned RRegs[32] = {
33 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
34 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
35 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
36 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
37 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
38 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
39 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
40 PPC::R28, PPC::R29, PPC::R30, PPC::R31
42 static unsigned RRegsNoR0[32] = {
44 PPC::R1, PPC::R2, PPC::R3,
45 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
46 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
47 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
48 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
49 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
50 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
51 PPC::R28, PPC::R29, PPC::R30, PPC::R31
53 static unsigned XRegs[32] = {
54 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
55 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
56 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
57 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
58 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
59 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
60 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
61 PPC::X28, PPC::X29, PPC::X30, PPC::X31
63 static unsigned XRegsNoX0[32] = {
65 PPC::X1, PPC::X2, PPC::X3,
66 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
67 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
68 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
69 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
70 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
71 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
72 PPC::X28, PPC::X29, PPC::X30, PPC::X31
74 static unsigned FRegs[32] = {
75 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
76 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
77 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
78 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
79 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
80 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
81 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
82 PPC::F28, PPC::F29, PPC::F30, PPC::F31
84 static unsigned VRegs[32] = {
85 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
86 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
87 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
88 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
89 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
90 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
91 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
92 PPC::V28, PPC::V29, PPC::V30, PPC::V31
94 static unsigned CRBITRegs[32] = {
95 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
96 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
97 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
98 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
99 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
100 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
101 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
102 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
104 static unsigned CRRegs[8] = {
105 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
106 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
111 class PPCAsmParser : public MCTargetAsmParser {
112 MCSubtargetInfo &STI;
116 MCAsmParser &getParser() const { return Parser; }
117 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
119 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
120 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
122 bool isPPC64() const { return IsPPC64; }
124 bool MatchRegisterName(const AsmToken &Tok,
125 unsigned &RegNo, int64_t &IntVal);
127 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
129 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
131 bool ParseDirectiveWord(unsigned Size, SMLoc L);
132 bool ParseDirectiveTC(unsigned Size, SMLoc L);
134 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
135 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
136 MCStreamer &Out, unsigned &ErrorInfo,
137 bool MatchingInlineAsm);
139 void ProcessInstruction(MCInst &Inst,
140 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
142 /// @name Auto-generated Match Functions
145 #define GET_ASSEMBLER_HEADER
146 #include "PPCGenAsmMatcher.inc"
152 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
153 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
154 // Check for 64-bit vs. 32-bit pointer mode.
155 Triple TheTriple(STI.getTargetTriple());
156 IsPPC64 = TheTriple.getArch() == Triple::ppc64;
157 // Initialize the set of available features.
158 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
161 virtual bool ParseInstruction(ParseInstructionInfo &Info,
162 StringRef Name, SMLoc NameLoc,
163 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
165 virtual bool ParseDirective(AsmToken DirectiveID);
168 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
170 struct PPCOperand : public MCParsedAsmOperand {
177 SMLoc StartLoc, EndLoc;
199 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
201 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
203 StartLoc = o.StartLoc;
219 /// getStartLoc - Get the location of the first token of this operand.
220 SMLoc getStartLoc() const { return StartLoc; }
222 /// getEndLoc - Get the location of the last token of this operand.
223 SMLoc getEndLoc() const { return EndLoc; }
225 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
226 bool isPPC64() const { return IsPPC64; }
228 int64_t getImm() const {
229 assert(Kind == Immediate && "Invalid access!");
233 const MCExpr *getExpr() const {
234 assert(Kind == Expression && "Invalid access!");
238 unsigned getReg() const {
239 assert(isRegNumber() && "Invalid access!");
240 return (unsigned) Imm.Val;
243 unsigned getCCReg() const {
244 assert(isCCRegNumber() && "Invalid access!");
245 return (unsigned) Imm.Val;
248 unsigned getCRBitMask() const {
249 assert(isCRBitMask() && "Invalid access!");
250 return 7 - CountTrailingZeros_32(Imm.Val);
253 bool isToken() const { return Kind == Token; }
254 bool isImm() const { return Kind == Immediate || Kind == Expression; }
255 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
256 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
257 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
258 bool isU16Imm() const { return Kind == Expression ||
259 (Kind == Immediate && isUInt<16>(getImm())); }
260 bool isS16Imm() const { return Kind == Expression ||
261 (Kind == Immediate && isInt<16>(getImm())); }
262 bool isS16ImmX4() const { return Kind == Expression ||
263 (Kind == Immediate && isInt<16>(getImm()) &&
264 (getImm() & 3) == 0); }
265 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
266 bool isCCRegNumber() const { return Kind == Immediate &&
267 isUInt<3>(getImm()); }
268 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
269 isPowerOf2_32(getImm()); }
270 bool isMem() const { return false; }
271 bool isReg() const { return false; }
273 void addRegOperands(MCInst &Inst, unsigned N) const {
274 llvm_unreachable("addRegOperands");
277 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
278 assert(N == 1 && "Invalid number of operands!");
279 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
282 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
287 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 1 && "Invalid number of operands!");
289 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
292 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
293 assert(N == 1 && "Invalid number of operands!");
294 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
297 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
299 addRegG8RCOperands(Inst, N);
301 addRegGPRCOperands(Inst, N);
304 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
306 addRegG8RCNoX0Operands(Inst, N);
308 addRegGPRCNoR0Operands(Inst, N);
311 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
312 assert(N == 1 && "Invalid number of operands!");
313 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
316 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
317 assert(N == 1 && "Invalid number of operands!");
318 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
321 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
322 assert(N == 1 && "Invalid number of operands!");
323 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
326 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
327 assert(N == 1 && "Invalid number of operands!");
328 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getReg()]));
331 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
332 assert(N == 1 && "Invalid number of operands!");
333 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
336 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
337 assert(N == 1 && "Invalid number of operands!");
338 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
341 void addImmOperands(MCInst &Inst, unsigned N) const {
342 assert(N == 1 && "Invalid number of operands!");
343 if (Kind == Immediate)
344 Inst.addOperand(MCOperand::CreateImm(getImm()));
346 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
349 void addDispRIOperands(MCInst &Inst, unsigned N) const {
350 assert(N == 1 && "Invalid number of operands!");
351 if (Kind == Immediate)
352 Inst.addOperand(MCOperand::CreateImm(getImm()));
354 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
357 void addDispRIXOperands(MCInst &Inst, unsigned N) const {
358 assert(N == 1 && "Invalid number of operands!");
359 if (Kind == Immediate)
360 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
362 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
365 StringRef getToken() const {
366 assert(Kind == Token && "Invalid access!");
367 return StringRef(Tok.Data, Tok.Length);
370 virtual void print(raw_ostream &OS) const;
372 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
373 PPCOperand *Op = new PPCOperand(Token);
374 Op->Tok.Data = Str.data();
375 Op->Tok.Length = Str.size();
378 Op->IsPPC64 = IsPPC64;
382 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
383 PPCOperand *Op = new PPCOperand(Immediate);
387 Op->IsPPC64 = IsPPC64;
391 static PPCOperand *CreateExpr(const MCExpr *Val,
392 SMLoc S, SMLoc E, bool IsPPC64) {
393 PPCOperand *Op = new PPCOperand(Expression);
397 Op->IsPPC64 = IsPPC64;
402 } // end anonymous namespace.
404 void PPCOperand::print(raw_ostream &OS) const {
407 OS << "'" << getToken() << "'";
413 getExpr()->print(OS);
420 ProcessInstruction(MCInst &Inst,
421 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
422 switch (Inst.getOpcode()) {
425 int64_t N = Inst.getOperand(2).getImm();
426 TmpInst.setOpcode(PPC::RLWINM);
427 TmpInst.addOperand(Inst.getOperand(0));
428 TmpInst.addOperand(Inst.getOperand(1));
429 TmpInst.addOperand(MCOperand::CreateImm(N));
430 TmpInst.addOperand(MCOperand::CreateImm(0));
431 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
437 int64_t N = Inst.getOperand(2).getImm();
438 TmpInst.setOpcode(PPC::RLWINM);
439 TmpInst.addOperand(Inst.getOperand(0));
440 TmpInst.addOperand(Inst.getOperand(1));
441 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
442 TmpInst.addOperand(MCOperand::CreateImm(N));
443 TmpInst.addOperand(MCOperand::CreateImm(31));
449 int64_t N = Inst.getOperand(2).getImm();
450 TmpInst.setOpcode(PPC::RLDICR);
451 TmpInst.addOperand(Inst.getOperand(0));
452 TmpInst.addOperand(Inst.getOperand(1));
453 TmpInst.addOperand(MCOperand::CreateImm(N));
454 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
460 int64_t N = Inst.getOperand(2).getImm();
461 TmpInst.setOpcode(PPC::RLDICL);
462 TmpInst.addOperand(Inst.getOperand(0));
463 TmpInst.addOperand(Inst.getOperand(1));
464 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
465 TmpInst.addOperand(MCOperand::CreateImm(N));
473 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
474 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
475 MCStreamer &Out, unsigned &ErrorInfo,
476 bool MatchingInlineAsm) {
479 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
482 // Post-process instructions (typically extended mnemonics)
483 ProcessInstruction(Inst, Operands);
485 Out.EmitInstruction(Inst);
487 case Match_MissingFeature:
488 return Error(IDLoc, "instruction use requires an option to be enabled");
489 case Match_MnemonicFail:
490 return Error(IDLoc, "unrecognized instruction mnemonic");
491 case Match_InvalidOperand: {
492 SMLoc ErrorLoc = IDLoc;
493 if (ErrorInfo != ~0U) {
494 if (ErrorInfo >= Operands.size())
495 return Error(IDLoc, "too few operands for instruction");
497 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
498 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
501 return Error(ErrorLoc, "invalid operand for instruction");
505 llvm_unreachable("Implement any new match types added!");
509 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
510 if (Tok.is(AsmToken::Identifier)) {
511 StringRef Name = Tok.getString();
513 if (Name.equals_lower("lr")) {
514 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
517 } else if (Name.equals_lower("ctr")) {
518 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
521 } else if (Name.substr(0, 1).equals_lower("r") &&
522 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
523 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
525 } else if (Name.substr(0, 1).equals_lower("f") &&
526 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
527 RegNo = FRegs[IntVal];
529 } else if (Name.substr(0, 1).equals_lower("v") &&
530 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
531 RegNo = VRegs[IntVal];
533 } else if (Name.substr(0, 2).equals_lower("cr") &&
534 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
535 RegNo = CRRegs[IntVal];
544 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
545 const AsmToken &Tok = Parser.getTok();
546 StartLoc = Tok.getLoc();
547 EndLoc = Tok.getEndLoc();
551 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
552 Parser.Lex(); // Eat identifier token.
556 return Error(StartLoc, "invalid register name");
560 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
561 SMLoc S = Parser.getTok().getLoc();
562 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
566 // Attempt to parse the next token as an immediate
567 switch (getLexer().getKind()) {
568 // Special handling for register names. These are interpreted
569 // as immediates corresponding to the register number.
570 case AsmToken::Percent:
571 Parser.Lex(); // Eat the '%'.
574 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
575 Parser.Lex(); // Eat the identifier token.
576 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
577 Operands.push_back(Op);
580 return Error(S, "invalid register name");
582 // All other expressions
583 case AsmToken::LParen:
585 case AsmToken::Minus:
586 case AsmToken::Integer:
587 case AsmToken::Identifier:
589 case AsmToken::Dollar:
590 if (!getParser().parseExpression(EVal))
594 return Error(S, "unknown operand");
597 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(EVal))
598 Op = PPCOperand::CreateImm(CE->getValue(), S, E, isPPC64());
600 Op = PPCOperand::CreateExpr(EVal, S, E, isPPC64());
602 // Push the parsed operand into the list of operands
603 Operands.push_back(Op);
605 // Check for D-form memory operands
606 if (getLexer().is(AsmToken::LParen)) {
607 Parser.Lex(); // Eat the '('.
608 S = Parser.getTok().getLoc();
611 switch (getLexer().getKind()) {
612 case AsmToken::Percent:
613 Parser.Lex(); // Eat the '%'.
615 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
616 return Error(S, "invalid register name");
617 Parser.Lex(); // Eat the identifier token.
620 case AsmToken::Integer:
621 if (getParser().parseAbsoluteExpression(IntVal) ||
622 IntVal < 0 || IntVal > 31)
623 return Error(S, "invalid register number");
627 return Error(S, "invalid memory operand");
630 if (getLexer().isNot(AsmToken::RParen))
631 return Error(Parser.getTok().getLoc(), "missing ')'");
632 E = Parser.getTok().getLoc();
633 Parser.Lex(); // Eat the ')'.
635 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
636 Operands.push_back(Op);
642 /// Parse an instruction mnemonic followed by its operands.
644 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
645 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
646 // The first operand is the token for the instruction name.
647 // If the instruction ends in a '.', we need to create a separate
648 // token for it, to match what TableGen is doing.
649 size_t Dot = Name.find('.');
650 StringRef Mnemonic = Name.slice(0, Dot);
651 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
652 if (Dot != StringRef::npos) {
653 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
654 StringRef DotStr = Name.slice(Dot, StringRef::npos);
655 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
658 // If there are no more operands then finish
659 if (getLexer().is(AsmToken::EndOfStatement))
662 // Parse the first operand
663 if (ParseOperand(Operands))
666 while (getLexer().isNot(AsmToken::EndOfStatement) &&
667 getLexer().is(AsmToken::Comma)) {
668 // Consume the comma token
671 // Parse the next operand
672 if (ParseOperand(Operands))
679 /// ParseDirective parses the PPC specific directives
680 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
681 StringRef IDVal = DirectiveID.getIdentifier();
682 if (IDVal == ".word")
683 return ParseDirectiveWord(4, DirectiveID.getLoc());
685 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
689 /// ParseDirectiveWord
690 /// ::= .word [ expression (, expression)* ]
691 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
692 if (getLexer().isNot(AsmToken::EndOfStatement)) {
695 if (getParser().parseExpression(Value))
698 getParser().getStreamer().EmitValue(Value, Size);
700 if (getLexer().is(AsmToken::EndOfStatement))
703 if (getLexer().isNot(AsmToken::Comma))
704 return Error(L, "unexpected token in directive");
714 /// ::= .tc [ symbol (, expression)* ]
715 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
716 // Skip TC symbol, which is only used with XCOFF.
717 while (getLexer().isNot(AsmToken::EndOfStatement)
718 && getLexer().isNot(AsmToken::Comma))
720 if (getLexer().isNot(AsmToken::Comma))
721 return Error(L, "unexpected token in directive");
724 // Align to word size.
725 getParser().getStreamer().EmitValueToAlignment(Size);
728 return ParseDirectiveWord(Size, L);
731 /// Force static initialization.
732 extern "C" void LLVMInitializePowerPCAsmParser() {
733 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
734 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
737 #define GET_REGISTER_MATCHER
738 #define GET_MATCHER_IMPLEMENTATION
739 #include "PPCGenAsmMatcher.inc"