1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
166 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
173 [SDNPHasChain, SDNPOptInGlue]>;
175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
176 [SDNPHasChain, SDNPMayLoad]>;
177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
178 [SDNPHasChain, SDNPMayStore]>;
180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
186 // Instructions to support atomic operations
187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to support medium and large code model
193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
198 // Instructions to support dynamic alloca.
199 def SDTDynOp : SDTypeProfile<1, 2, []>;
200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
202 //===----------------------------------------------------------------------===//
203 // PowerPC specific transformation functions and pattern fragments.
206 def SHL32 : SDNodeXForm<imm, [{
207 // Transformation function: 31 - imm
208 return getI32Imm(31 - N->getZExtValue());
211 def SRL32 : SDNodeXForm<imm, [{
212 // Transformation function: 32 - imm
213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
216 def LO16 : SDNodeXForm<imm, [{
217 // Transformation function: get the low 16 bits.
218 return getI32Imm((unsigned short)N->getZExtValue());
221 def HI16 : SDNodeXForm<imm, [{
222 // Transformation function: shift the immediate value down into the low bits.
223 return getI32Imm((unsigned)N->getZExtValue() >> 16);
226 def HA16 : SDNodeXForm<imm, [{
227 // Transformation function: shift the immediate value down into the low bits.
228 signed int Val = N->getZExtValue();
229 return getI32Imm((Val - (signed short)Val) >> 16);
231 def MB : SDNodeXForm<imm, [{
232 // Transformation function: get the start bit of a mask
234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
235 return getI32Imm(mb);
238 def ME : SDNodeXForm<imm, [{
239 // Transformation function: get the end bit of a mask
241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
242 return getI32Imm(me);
244 def maskimm32 : PatLeaf<(imm), [{
245 // maskImm predicate - True if immediate is a run of ones.
247 if (N->getValueType(0) == MVT::i32)
248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
253 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
254 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
255 // sign extended field. Used by instructions like 'addi'.
256 return (int32_t)Imm == (short)Imm;
258 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
259 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
260 // sign extended field. Used by instructions like 'addi'.
261 return (int64_t)Imm == (short)Imm;
263 def immZExt16 : PatLeaf<(imm), [{
264 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
265 // field. Used by instructions like 'ori'.
266 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
269 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
270 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
271 // identical in 32-bit mode, but in 64-bit mode, they return true if the
272 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
274 def imm16ShiftedZExt : PatLeaf<(imm), [{
275 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'xoris'.
277 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
280 def imm16ShiftedSExt : PatLeaf<(imm), [{
281 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
282 // immediate are set. Used by instructions like 'addis'. Identical to
283 // imm16ShiftedZExt in 32-bit mode.
284 if (N->getZExtValue() & 0xFFFF) return false;
285 if (N->getValueType(0) == MVT::i32)
287 // For 64-bit, make sure it is sext right.
288 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
291 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
292 // restricted memrix (4-aligned) constants are alignment sensitive. If these
293 // offsets are hidden behind TOC entries than the values of the lower-order
294 // bits cannot be checked directly. As a result, we need to also incorporate
295 // an alignment check into the relevant patterns.
297 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
298 return cast<LoadSDNode>(N)->getAlignment() >= 4;
300 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
301 (store node:$val, node:$ptr), [{
302 return cast<StoreSDNode>(N)->getAlignment() >= 4;
304 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
305 return cast<LoadSDNode>(N)->getAlignment() >= 4;
307 def aligned4pre_store : PatFrag<
308 (ops node:$val, node:$base, node:$offset),
309 (pre_store node:$val, node:$base, node:$offset), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
313 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
314 return cast<LoadSDNode>(N)->getAlignment() < 4;
316 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
317 (store node:$val, node:$ptr), [{
318 return cast<StoreSDNode>(N)->getAlignment() < 4;
320 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
321 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 //===----------------------------------------------------------------------===//
325 // PowerPC Flag Definitions.
327 class isPPC64 { bit PPC64 = 1; }
328 class isDOT { bit RC = 1; }
330 class RegConstraint<string C> {
331 string Constraints = C;
333 class NoEncode<string E> {
334 string DisableEncoding = E;
338 //===----------------------------------------------------------------------===//
339 // PowerPC Operand Definitions.
341 // In the default PowerPC assembler syntax, registers are specified simply
342 // by number, so they cannot be distinguished from immediate values (without
343 // looking at the opcode). This means that the default operand matching logic
344 // for the asm parser does not work, and we need to specify custom matchers.
345 // Since those can only be specified with RegisterOperand classes and not
346 // directly on the RegisterClass, all instructions patterns used by the asm
347 // parser need to use a RegisterOperand (instead of a RegisterClass) for
348 // all their register operands.
349 // For this purpose, we define one RegisterOperand for each RegisterClass,
350 // using the same name as the class, just in lower case.
352 def PPCRegGPRCAsmOperand : AsmOperandClass {
353 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
355 def gprc : RegisterOperand<GPRC> {
356 let ParserMatchClass = PPCRegGPRCAsmOperand;
358 def PPCRegG8RCAsmOperand : AsmOperandClass {
359 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
361 def g8rc : RegisterOperand<G8RC> {
362 let ParserMatchClass = PPCRegG8RCAsmOperand;
364 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
365 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
367 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
368 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
370 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
371 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
373 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
374 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
376 def PPCRegF8RCAsmOperand : AsmOperandClass {
377 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
379 def f8rc : RegisterOperand<F8RC> {
380 let ParserMatchClass = PPCRegF8RCAsmOperand;
382 def PPCRegF4RCAsmOperand : AsmOperandClass {
383 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
385 def f4rc : RegisterOperand<F4RC> {
386 let ParserMatchClass = PPCRegF4RCAsmOperand;
388 def PPCRegVRRCAsmOperand : AsmOperandClass {
389 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
391 def vrrc : RegisterOperand<VRRC> {
392 let ParserMatchClass = PPCRegVRRCAsmOperand;
394 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
395 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
397 def crbitrc : RegisterOperand<CRBITRC> {
398 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
400 def PPCRegCRRCAsmOperand : AsmOperandClass {
401 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
403 def crrc : RegisterOperand<CRRC> {
404 let ParserMatchClass = PPCRegCRRCAsmOperand;
407 def PPCS5ImmAsmOperand : AsmOperandClass {
408 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
409 let RenderMethod = "addImmOperands";
411 def s5imm : Operand<i32> {
412 let PrintMethod = "printS5ImmOperand";
413 let ParserMatchClass = PPCS5ImmAsmOperand;
415 def PPCU5ImmAsmOperand : AsmOperandClass {
416 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
417 let RenderMethod = "addImmOperands";
419 def u5imm : Operand<i32> {
420 let PrintMethod = "printU5ImmOperand";
421 let ParserMatchClass = PPCU5ImmAsmOperand;
423 def PPCU6ImmAsmOperand : AsmOperandClass {
424 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
425 let RenderMethod = "addImmOperands";
427 def u6imm : Operand<i32> {
428 let PrintMethod = "printU6ImmOperand";
429 let ParserMatchClass = PPCU6ImmAsmOperand;
431 def PPCS16ImmAsmOperand : AsmOperandClass {
432 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
433 let RenderMethod = "addImmOperands";
435 def s16imm : Operand<i32> {
436 let PrintMethod = "printS16ImmOperand";
437 let EncoderMethod = "getImm16Encoding";
438 let ParserMatchClass = PPCS16ImmAsmOperand;
440 def PPCU16ImmAsmOperand : AsmOperandClass {
441 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
442 let RenderMethod = "addImmOperands";
444 def u16imm : Operand<i32> {
445 let PrintMethod = "printU16ImmOperand";
446 let EncoderMethod = "getImm16Encoding";
447 let ParserMatchClass = PPCU16ImmAsmOperand;
449 def PPCS17ImmAsmOperand : AsmOperandClass {
450 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
451 let RenderMethod = "addImmOperands";
453 def s17imm : Operand<i32> {
454 // This operand type is used for addis/lis to allow the assembler parser
455 // to accept immediates in the range -65536..65535 for compatibility with
456 // the GNU assembler. The operand is treated as 16-bit otherwise.
457 let PrintMethod = "printS16ImmOperand";
458 let EncoderMethod = "getImm16Encoding";
459 let ParserMatchClass = PPCS17ImmAsmOperand;
461 def PPCDirectBrAsmOperand : AsmOperandClass {
462 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
463 let RenderMethod = "addBranchTargetOperands";
465 def directbrtarget : Operand<OtherVT> {
466 let PrintMethod = "printBranchOperand";
467 let EncoderMethod = "getDirectBrEncoding";
468 let ParserMatchClass = PPCDirectBrAsmOperand;
470 def absdirectbrtarget : Operand<OtherVT> {
471 let PrintMethod = "printAbsBranchOperand";
472 let EncoderMethod = "getAbsDirectBrEncoding";
473 let ParserMatchClass = PPCDirectBrAsmOperand;
475 def PPCCondBrAsmOperand : AsmOperandClass {
476 let Name = "CondBr"; let PredicateMethod = "isCondBr";
477 let RenderMethod = "addBranchTargetOperands";
479 def condbrtarget : Operand<OtherVT> {
480 let PrintMethod = "printBranchOperand";
481 let EncoderMethod = "getCondBrEncoding";
482 let ParserMatchClass = PPCCondBrAsmOperand;
484 def abscondbrtarget : Operand<OtherVT> {
485 let PrintMethod = "printAbsBranchOperand";
486 let EncoderMethod = "getAbsCondBrEncoding";
487 let ParserMatchClass = PPCCondBrAsmOperand;
489 def calltarget : Operand<iPTR> {
490 let PrintMethod = "printBranchOperand";
491 let EncoderMethod = "getDirectBrEncoding";
492 let ParserMatchClass = PPCDirectBrAsmOperand;
494 def abscalltarget : Operand<iPTR> {
495 let PrintMethod = "printAbsBranchOperand";
496 let EncoderMethod = "getAbsDirectBrEncoding";
497 let ParserMatchClass = PPCDirectBrAsmOperand;
499 def PPCCRBitMaskOperand : AsmOperandClass {
500 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
502 def crbitm: Operand<i8> {
503 let PrintMethod = "printcrbitm";
504 let EncoderMethod = "get_crbitm_encoding";
505 let ParserMatchClass = PPCCRBitMaskOperand;
508 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
509 def PPCRegGxRCNoR0Operand : AsmOperandClass {
510 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
512 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
513 let ParserMatchClass = PPCRegGxRCNoR0Operand;
515 // A version of ptr_rc usable with the asm parser.
516 def PPCRegGxRCOperand : AsmOperandClass {
517 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
519 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
520 let ParserMatchClass = PPCRegGxRCOperand;
523 def PPCDispRIOperand : AsmOperandClass {
524 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
525 let RenderMethod = "addImmOperands";
527 def dispRI : Operand<iPTR> {
528 let ParserMatchClass = PPCDispRIOperand;
530 def PPCDispRIXOperand : AsmOperandClass {
531 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
532 let RenderMethod = "addImmOperands";
534 def dispRIX : Operand<iPTR> {
535 let ParserMatchClass = PPCDispRIXOperand;
538 def memri : Operand<iPTR> {
539 let PrintMethod = "printMemRegImm";
540 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
541 let EncoderMethod = "getMemRIEncoding";
543 def memrr : Operand<iPTR> {
544 let PrintMethod = "printMemRegReg";
545 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
547 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
548 let PrintMethod = "printMemRegImm";
549 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
550 let EncoderMethod = "getMemRIXEncoding";
553 // A single-register address. This is used with the SjLj
554 // pseudo-instructions.
555 def memr : Operand<iPTR> {
556 let MIOperandInfo = (ops ptr_rc:$ptrreg);
559 // PowerPC Predicate operand.
560 def pred : Operand<OtherVT> {
561 let PrintMethod = "printPredicateOperand";
562 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
565 // Define PowerPC specific addressing mode.
566 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
567 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
568 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
569 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
571 // The address in a single register. This is used with the SjLj
572 // pseudo-instructions.
573 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
575 /// This is just the offset part of iaddr, used for preinc.
576 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
578 //===----------------------------------------------------------------------===//
579 // PowerPC Instruction Predicate Definitions.
580 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
581 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
582 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
583 def IsNotBookE : Predicate<"!PPCSubTarget.isBookE()">;
585 //===----------------------------------------------------------------------===//
586 // PowerPC Multiclass Definitions.
588 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
589 string asmbase, string asmstr, InstrItinClass itin,
591 let BaseName = asmbase in {
592 def NAME : XForm_6<opcode, xo, OOL, IOL,
593 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
594 pattern>, RecFormRel;
596 def o : XForm_6<opcode, xo, OOL, IOL,
597 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
598 []>, isDOT, RecFormRel;
602 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
603 string asmbase, string asmstr, InstrItinClass itin,
605 let BaseName = asmbase in {
606 let Defs = [CARRY] in
607 def NAME : XForm_6<opcode, xo, OOL, IOL,
608 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
609 pattern>, RecFormRel;
610 let Defs = [CARRY, CR0] in
611 def o : XForm_6<opcode, xo, OOL, IOL,
612 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
613 []>, isDOT, RecFormRel;
617 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
618 string asmbase, string asmstr, InstrItinClass itin,
620 let BaseName = asmbase in {
621 def NAME : XForm_10<opcode, xo, OOL, IOL,
622 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
623 pattern>, RecFormRel;
625 def o : XForm_10<opcode, xo, OOL, IOL,
626 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
627 []>, isDOT, RecFormRel;
631 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
632 string asmbase, string asmstr, InstrItinClass itin,
634 let BaseName = asmbase in {
635 let Defs = [CARRY] in
636 def NAME : XForm_10<opcode, xo, OOL, IOL,
637 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
638 pattern>, RecFormRel;
639 let Defs = [CARRY, CR0] in
640 def o : XForm_10<opcode, xo, OOL, IOL,
641 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
642 []>, isDOT, RecFormRel;
646 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
647 string asmbase, string asmstr, InstrItinClass itin,
649 let BaseName = asmbase in {
650 def NAME : XForm_11<opcode, xo, OOL, IOL,
651 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
652 pattern>, RecFormRel;
654 def o : XForm_11<opcode, xo, OOL, IOL,
655 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
656 []>, isDOT, RecFormRel;
660 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
661 string asmbase, string asmstr, InstrItinClass itin,
663 let BaseName = asmbase in {
664 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
665 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
666 pattern>, RecFormRel;
668 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
669 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
670 []>, isDOT, RecFormRel;
674 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
675 string asmbase, string asmstr, InstrItinClass itin,
677 let BaseName = asmbase in {
678 let Defs = [CARRY] in
679 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
680 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
681 pattern>, RecFormRel;
682 let Defs = [CARRY, CR0] in
683 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
684 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
685 []>, isDOT, RecFormRel;
689 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
690 string asmbase, string asmstr, InstrItinClass itin,
692 let BaseName = asmbase in {
693 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
694 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
695 pattern>, RecFormRel;
697 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
698 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
699 []>, isDOT, RecFormRel;
703 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
704 string asmbase, string asmstr, InstrItinClass itin,
706 let BaseName = asmbase in {
707 let Defs = [CARRY] in
708 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
709 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
710 pattern>, RecFormRel;
711 let Defs = [CARRY, CR0] in
712 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
713 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
714 []>, isDOT, RecFormRel;
718 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
719 string asmbase, string asmstr, InstrItinClass itin,
721 let BaseName = asmbase in {
722 def NAME : MForm_2<opcode, OOL, IOL,
723 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
724 pattern>, RecFormRel;
726 def o : MForm_2<opcode, OOL, IOL,
727 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
728 []>, isDOT, RecFormRel;
732 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
733 string asmbase, string asmstr, InstrItinClass itin,
735 let BaseName = asmbase in {
736 def NAME : MDForm_1<opcode, xo, OOL, IOL,
737 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
738 pattern>, RecFormRel;
740 def o : MDForm_1<opcode, xo, OOL, IOL,
741 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
742 []>, isDOT, RecFormRel;
746 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
747 string asmbase, string asmstr, InstrItinClass itin,
749 let BaseName = asmbase in {
750 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
751 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
752 pattern>, RecFormRel;
754 def o : MDSForm_1<opcode, xo, OOL, IOL,
755 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
756 []>, isDOT, RecFormRel;
760 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
761 string asmbase, string asmstr, InstrItinClass itin,
763 let BaseName = asmbase in {
764 let Defs = [CARRY] in
765 def NAME : XSForm_1<opcode, xo, OOL, IOL,
766 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
767 pattern>, RecFormRel;
768 let Defs = [CARRY, CR0] in
769 def o : XSForm_1<opcode, xo, OOL, IOL,
770 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
771 []>, isDOT, RecFormRel;
775 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
776 string asmbase, string asmstr, InstrItinClass itin,
778 let BaseName = asmbase in {
779 def NAME : XForm_26<opcode, xo, OOL, IOL,
780 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
781 pattern>, RecFormRel;
783 def o : XForm_26<opcode, xo, OOL, IOL,
784 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
785 []>, isDOT, RecFormRel;
789 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
790 string asmbase, string asmstr, InstrItinClass itin,
792 let BaseName = asmbase in {
793 def NAME : XForm_28<opcode, xo, OOL, IOL,
794 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
795 pattern>, RecFormRel;
797 def o : XForm_28<opcode, xo, OOL, IOL,
798 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
799 []>, isDOT, RecFormRel;
803 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
804 string asmbase, string asmstr, InstrItinClass itin,
806 let BaseName = asmbase in {
807 def NAME : AForm_1<opcode, xo, OOL, IOL,
808 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
809 pattern>, RecFormRel;
811 def o : AForm_1<opcode, xo, OOL, IOL,
812 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
813 []>, isDOT, RecFormRel;
817 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
818 string asmbase, string asmstr, InstrItinClass itin,
820 let BaseName = asmbase in {
821 def NAME : AForm_2<opcode, xo, OOL, IOL,
822 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
823 pattern>, RecFormRel;
825 def o : AForm_2<opcode, xo, OOL, IOL,
826 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
827 []>, isDOT, RecFormRel;
831 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
832 string asmbase, string asmstr, InstrItinClass itin,
834 let BaseName = asmbase in {
835 def NAME : AForm_3<opcode, xo, OOL, IOL,
836 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
837 pattern>, RecFormRel;
839 def o : AForm_3<opcode, xo, OOL, IOL,
840 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
841 []>, isDOT, RecFormRel;
845 //===----------------------------------------------------------------------===//
846 // PowerPC Instruction Definitions.
848 // Pseudo-instructions:
850 let hasCtrlDep = 1 in {
851 let Defs = [R1], Uses = [R1] in {
852 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
853 [(callseq_start timm:$amt)]>;
854 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
855 [(callseq_end timm:$amt1, timm:$amt2)]>;
858 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
859 "UPDATE_VRSAVE $rD, $rS", []>;
862 let Defs = [R1], Uses = [R1] in
863 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
865 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
867 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
868 // instruction selection into a branch sequence.
869 let usesCustomInserter = 1, // Expanded after instruction selection.
870 PPC970_Single = 1 in {
871 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
872 // because either operand might become the first operand in an isel, and
873 // that operand cannot be r0.
874 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
875 gprc_nor0:$T, gprc_nor0:$F,
876 i32imm:$BROPC), "#SELECT_CC_I4",
878 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
879 g8rc_nox0:$T, g8rc_nox0:$F,
880 i32imm:$BROPC), "#SELECT_CC_I8",
882 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
883 i32imm:$BROPC), "#SELECT_CC_F4",
885 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
886 i32imm:$BROPC), "#SELECT_CC_F8",
888 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
889 i32imm:$BROPC), "#SELECT_CC_VRRC",
893 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
894 // scavenge a register for it.
896 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
899 // RESTORE_CR - Indicate that we're restoring the CR register (previously
900 // spilled), so we'll need to scavenge a register for it.
902 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
905 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
906 let isReturn = 1, Uses = [LR, RM] in
907 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
909 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
910 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
912 let isCodeGenOnly = 1 in
913 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
914 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>;
919 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
922 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
923 let isBarrier = 1 in {
924 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
927 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
931 // BCC represents an arbitrary conditional branch on a predicate.
932 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
933 // a two-value operand where a dag node expects two operands. :(
934 let isCodeGenOnly = 1 in {
935 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
936 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
937 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
938 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
939 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
941 let isReturn = 1, Uses = [LR, RM] in
942 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
943 "b${cond:cc}lr${cond:pm} ${cond:reg}", BrB, []>;
946 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
947 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
949 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
951 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
953 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
955 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
957 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
961 let Defs = [CTR], Uses = [CTR] in {
962 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
964 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
966 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
968 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
970 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
972 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
974 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
976 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
978 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
980 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
982 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
984 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
989 // The unconditional BCL used by the SjLj setjmp code.
990 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
991 let Defs = [LR], Uses = [RM] in {
992 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
997 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
998 // Convenient aliases for call instructions
1000 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1001 "bl $func", BrB, []>; // See Pat patterns below.
1002 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1003 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
1005 let isCodeGenOnly = 1 in {
1006 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1007 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1008 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1009 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1012 let Uses = [CTR, RM] in {
1013 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1014 "bctrl", BrB, [(PPCbctrl)]>,
1015 Requires<[In32BitMode]>;
1017 let isCodeGenOnly = 1 in
1018 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1019 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>;
1021 let Uses = [LR, RM] in {
1022 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1025 let isCodeGenOnly = 1 in
1026 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1027 "b${cond:cc}lrl${cond:pm} ${cond:reg}", BrB, []>;
1029 let Defs = [CTR], Uses = [CTR, RM] in {
1030 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1032 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1034 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1036 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1038 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1040 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1042 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1044 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1046 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1048 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1050 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1052 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1055 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1056 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1058 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1059 "bdnzlrl", BrB, []>;
1060 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1061 "bdzlrl+", BrB, []>;
1062 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1063 "bdnzlrl+", BrB, []>;
1064 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1065 "bdzlrl-", BrB, []>;
1066 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1067 "bdnzlrl-", BrB, []>;
1071 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1072 def TCRETURNdi :Pseudo< (outs),
1073 (ins calltarget:$dst, i32imm:$offset),
1074 "#TC_RETURNd $dst $offset",
1078 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1079 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1080 "#TC_RETURNa $func $offset",
1081 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1083 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1084 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1085 "#TC_RETURNr $dst $offset",
1089 let isCodeGenOnly = 1 in {
1091 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1092 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1093 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
1094 Requires<[In32BitMode]>;
1096 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1097 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1098 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1102 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1103 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1104 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1110 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1112 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1113 "#EH_SJLJ_SETJMP32",
1114 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1115 Requires<[In32BitMode]>;
1116 let isTerminator = 1 in
1117 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1118 "#EH_SJLJ_LONGJMP32",
1119 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1120 Requires<[In32BitMode]>;
1123 let isBranch = 1, isTerminator = 1 in {
1124 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1125 "#EH_SjLj_Setup\t$dst", []>;
1129 let PPC970_Unit = 7 in {
1130 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1131 "sc $lev", BrB, [(PPCsc (i32 imm:$lev))]>;
1134 // DCB* instructions.
1135 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
1136 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1137 PPC970_DGroup_Single;
1138 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
1139 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1140 PPC970_DGroup_Single;
1141 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
1142 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1143 PPC970_DGroup_Single;
1144 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
1145 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1146 PPC970_DGroup_Single;
1147 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
1148 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1149 PPC970_DGroup_Single;
1150 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
1151 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1152 PPC970_DGroup_Single;
1153 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
1154 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1155 PPC970_DGroup_Single;
1156 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
1157 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1158 PPC970_DGroup_Single;
1160 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1161 (DCBT xoaddr:$dst)>;
1163 // Atomic operations
1164 let usesCustomInserter = 1 in {
1165 let Defs = [CR0] in {
1166 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1167 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1168 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1169 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1170 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1171 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1172 def ATOMIC_LOAD_AND_I8 : Pseudo<
1173 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1174 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1175 def ATOMIC_LOAD_OR_I8 : Pseudo<
1176 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1177 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1178 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1179 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1180 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1181 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1182 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1183 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1184 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1185 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1186 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1187 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1188 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1189 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1190 def ATOMIC_LOAD_AND_I16 : Pseudo<
1191 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1192 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1193 def ATOMIC_LOAD_OR_I16 : Pseudo<
1194 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1195 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1196 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1197 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1198 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1199 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1200 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1201 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1202 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1203 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1204 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1205 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1206 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1207 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1208 def ATOMIC_LOAD_AND_I32 : Pseudo<
1209 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1210 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1211 def ATOMIC_LOAD_OR_I32 : Pseudo<
1212 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1213 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1214 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1215 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1216 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1217 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1218 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1219 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1221 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1222 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1223 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1224 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1225 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1226 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1227 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1228 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1229 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1231 def ATOMIC_SWAP_I8 : Pseudo<
1232 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1233 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1234 def ATOMIC_SWAP_I16 : Pseudo<
1235 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1236 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1237 def ATOMIC_SWAP_I32 : Pseudo<
1238 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1239 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1243 // Instructions to support atomic operations
1244 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1245 "lwarx $rD, $src", LdStLWARX,
1246 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1249 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1250 "stwcx. $rS, $dst", LdStSTWCX,
1251 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1254 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1255 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
1257 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1258 "twi $to, $rA, $imm", IntTrapW, []>;
1259 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1260 "tw $to, $rA, $rB", IntTrapW, []>;
1261 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1262 "tdi $to, $rA, $imm", IntTrapD, []>;
1263 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1264 "td $to, $rA, $rB", IntTrapD, []>;
1266 //===----------------------------------------------------------------------===//
1267 // PPC32 Load Instructions.
1270 // Unindexed (r+i) Loads.
1271 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1272 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1273 "lbz $rD, $src", LdStLoad,
1274 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1275 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1276 "lha $rD, $src", LdStLHA,
1277 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1278 PPC970_DGroup_Cracked;
1279 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1280 "lhz $rD, $src", LdStLoad,
1281 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1282 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1283 "lwz $rD, $src", LdStLoad,
1284 [(set i32:$rD, (load iaddr:$src))]>;
1286 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1287 "lfs $rD, $src", LdStLFD,
1288 [(set f32:$rD, (load iaddr:$src))]>;
1289 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1290 "lfd $rD, $src", LdStLFD,
1291 [(set f64:$rD, (load iaddr:$src))]>;
1294 // Unindexed (r+i) Loads with Update (preinc).
1295 let mayLoad = 1, neverHasSideEffects = 1 in {
1296 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1297 "lbzu $rD, $addr", LdStLoadUpd,
1298 []>, RegConstraint<"$addr.reg = $ea_result">,
1299 NoEncode<"$ea_result">;
1301 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1302 "lhau $rD, $addr", LdStLHAU,
1303 []>, RegConstraint<"$addr.reg = $ea_result">,
1304 NoEncode<"$ea_result">;
1306 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1307 "lhzu $rD, $addr", LdStLoadUpd,
1308 []>, RegConstraint<"$addr.reg = $ea_result">,
1309 NoEncode<"$ea_result">;
1311 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1312 "lwzu $rD, $addr", LdStLoadUpd,
1313 []>, RegConstraint<"$addr.reg = $ea_result">,
1314 NoEncode<"$ea_result">;
1316 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1317 "lfsu $rD, $addr", LdStLFDU,
1318 []>, RegConstraint<"$addr.reg = $ea_result">,
1319 NoEncode<"$ea_result">;
1321 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1322 "lfdu $rD, $addr", LdStLFDU,
1323 []>, RegConstraint<"$addr.reg = $ea_result">,
1324 NoEncode<"$ea_result">;
1327 // Indexed (r+r) Loads with Update (preinc).
1328 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1330 "lbzux $rD, $addr", LdStLoadUpd,
1331 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1332 NoEncode<"$ea_result">;
1334 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1336 "lhaux $rD, $addr", LdStLHAU,
1337 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1338 NoEncode<"$ea_result">;
1340 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1342 "lhzux $rD, $addr", LdStLoadUpd,
1343 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1344 NoEncode<"$ea_result">;
1346 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1348 "lwzux $rD, $addr", LdStLoadUpd,
1349 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1350 NoEncode<"$ea_result">;
1352 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1354 "lfsux $rD, $addr", LdStLFDU,
1355 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1356 NoEncode<"$ea_result">;
1358 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1360 "lfdux $rD, $addr", LdStLFDU,
1361 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1362 NoEncode<"$ea_result">;
1366 // Indexed (r+r) Loads.
1368 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1369 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1370 "lbzx $rD, $src", LdStLoad,
1371 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1372 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1373 "lhax $rD, $src", LdStLHA,
1374 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1375 PPC970_DGroup_Cracked;
1376 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1377 "lhzx $rD, $src", LdStLoad,
1378 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1379 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1380 "lwzx $rD, $src", LdStLoad,
1381 [(set i32:$rD, (load xaddr:$src))]>;
1384 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1385 "lhbrx $rD, $src", LdStLoad,
1386 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1387 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1388 "lwbrx $rD, $src", LdStLoad,
1389 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1391 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1392 "lfsx $frD, $src", LdStLFD,
1393 [(set f32:$frD, (load xaddr:$src))]>;
1394 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1395 "lfdx $frD, $src", LdStLFD,
1396 [(set f64:$frD, (load xaddr:$src))]>;
1398 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1399 "lfiwax $frD, $src", LdStLFD,
1400 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1401 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1402 "lfiwzx $frD, $src", LdStLFD,
1403 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1407 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1408 "lmw $rD, $src", LdStLMW, []>;
1410 //===----------------------------------------------------------------------===//
1411 // PPC32 Store Instructions.
1414 // Unindexed (r+i) Stores.
1415 let PPC970_Unit = 2 in {
1416 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1417 "stb $rS, $src", LdStStore,
1418 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1419 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1420 "sth $rS, $src", LdStStore,
1421 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1422 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1423 "stw $rS, $src", LdStStore,
1424 [(store i32:$rS, iaddr:$src)]>;
1425 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1426 "stfs $rS, $dst", LdStSTFD,
1427 [(store f32:$rS, iaddr:$dst)]>;
1428 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1429 "stfd $rS, $dst", LdStSTFD,
1430 [(store f64:$rS, iaddr:$dst)]>;
1433 // Unindexed (r+i) Stores with Update (preinc).
1434 let PPC970_Unit = 2, mayStore = 1 in {
1435 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1436 "stbu $rS, $dst", LdStStoreUpd, []>,
1437 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1438 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1439 "sthu $rS, $dst", LdStStoreUpd, []>,
1440 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1441 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1442 "stwu $rS, $dst", LdStStoreUpd, []>,
1443 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1444 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1445 "stfsu $rS, $dst", LdStSTFDU, []>,
1446 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1447 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1448 "stfdu $rS, $dst", LdStSTFDU, []>,
1449 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1452 // Patterns to match the pre-inc stores. We can't put the patterns on
1453 // the instruction definitions directly as ISel wants the address base
1454 // and offset to be separate operands, not a single complex operand.
1455 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1456 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1457 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1458 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1459 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1460 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1461 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1462 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1463 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1464 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1466 // Indexed (r+r) Stores.
1467 let PPC970_Unit = 2 in {
1468 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1469 "stbx $rS, $dst", LdStStore,
1470 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1471 PPC970_DGroup_Cracked;
1472 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1473 "sthx $rS, $dst", LdStStore,
1474 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1475 PPC970_DGroup_Cracked;
1476 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1477 "stwx $rS, $dst", LdStStore,
1478 [(store i32:$rS, xaddr:$dst)]>,
1479 PPC970_DGroup_Cracked;
1481 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1482 "sthbrx $rS, $dst", LdStStore,
1483 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1484 PPC970_DGroup_Cracked;
1485 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1486 "stwbrx $rS, $dst", LdStStore,
1487 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1488 PPC970_DGroup_Cracked;
1490 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1491 "stfiwx $frS, $dst", LdStSTFD,
1492 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1494 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1495 "stfsx $frS, $dst", LdStSTFD,
1496 [(store f32:$frS, xaddr:$dst)]>;
1497 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1498 "stfdx $frS, $dst", LdStSTFD,
1499 [(store f64:$frS, xaddr:$dst)]>;
1502 // Indexed (r+r) Stores with Update (preinc).
1503 let PPC970_Unit = 2, mayStore = 1 in {
1504 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1505 "stbux $rS, $dst", LdStStoreUpd, []>,
1506 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1507 PPC970_DGroup_Cracked;
1508 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1509 "sthux $rS, $dst", LdStStoreUpd, []>,
1510 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1511 PPC970_DGroup_Cracked;
1512 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1513 "stwux $rS, $dst", LdStStoreUpd, []>,
1514 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1515 PPC970_DGroup_Cracked;
1516 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1517 "stfsux $rS, $dst", LdStSTFDU, []>,
1518 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1519 PPC970_DGroup_Cracked;
1520 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1521 "stfdux $rS, $dst", LdStSTFDU, []>,
1522 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1523 PPC970_DGroup_Cracked;
1526 // Patterns to match the pre-inc stores. We can't put the patterns on
1527 // the instruction definitions directly as ISel wants the address base
1528 // and offset to be separate operands, not a single complex operand.
1529 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1530 (STBUX $rS, $ptrreg, $ptroff)>;
1531 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1532 (STHUX $rS, $ptrreg, $ptroff)>;
1533 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1534 (STWUX $rS, $ptrreg, $ptroff)>;
1535 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1536 (STFSUX $rS, $ptrreg, $ptroff)>;
1537 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1538 (STFDUX $rS, $ptrreg, $ptroff)>;
1541 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1542 "stmw $rS, $dst", LdStLMW, []>;
1544 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1545 "sync $L", LdStSync, []>, Requires<[IsNotBookE]>;
1547 let isCodeGenOnly = 1 in {
1548 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1549 "msync", LdStSync, []>, Requires<[IsBookE]> {
1554 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1555 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1557 //===----------------------------------------------------------------------===//
1558 // PPC32 Arithmetic Instructions.
1561 let PPC970_Unit = 1 in { // FXU Operations.
1562 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1563 "addi $rD, $rA, $imm", IntSimple,
1564 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1565 let BaseName = "addic" in {
1566 let Defs = [CARRY] in
1567 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1568 "addic $rD, $rA, $imm", IntGeneral,
1569 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1570 RecFormRel, PPC970_DGroup_Cracked;
1571 let Defs = [CARRY, CR0] in
1572 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1573 "addic. $rD, $rA, $imm", IntGeneral,
1574 []>, isDOT, RecFormRel;
1576 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1577 "addis $rD, $rA, $imm", IntSimple,
1578 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1579 let isCodeGenOnly = 1 in
1580 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1581 "la $rD, $sym($rA)", IntGeneral,
1582 [(set i32:$rD, (add i32:$rA,
1583 (PPClo tglobaladdr:$sym, 0)))]>;
1584 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1585 "mulli $rD, $rA, $imm", IntMulLI,
1586 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1587 let Defs = [CARRY] in
1588 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1589 "subfic $rD, $rA, $imm", IntGeneral,
1590 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1592 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1593 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1594 "li $rD, $imm", IntSimple,
1595 [(set i32:$rD, imm32SExt16:$imm)]>;
1596 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1597 "lis $rD, $imm", IntSimple,
1598 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1602 let PPC970_Unit = 1 in { // FXU Operations.
1603 let Defs = [CR0] in {
1604 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1605 "andi. $dst, $src1, $src2", IntGeneral,
1606 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1608 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1609 "andis. $dst, $src1, $src2", IntGeneral,
1610 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1613 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1614 "ori $dst, $src1, $src2", IntSimple,
1615 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1616 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1617 "oris $dst, $src1, $src2", IntSimple,
1618 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1619 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1620 "xori $dst, $src1, $src2", IntSimple,
1621 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1622 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1623 "xoris $dst, $src1, $src2", IntSimple,
1624 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1625 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1627 let isCompare = 1, neverHasSideEffects = 1 in {
1628 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1629 "cmpwi $crD, $rA, $imm", IntCompare>;
1630 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1631 "cmplwi $dst, $src1, $src2", IntCompare>;
1635 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1636 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1637 "nand", "$rA, $rS, $rB", IntSimple,
1638 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1639 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1640 "and", "$rA, $rS, $rB", IntSimple,
1641 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1642 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1643 "andc", "$rA, $rS, $rB", IntSimple,
1644 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1645 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1646 "or", "$rA, $rS, $rB", IntSimple,
1647 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1648 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1649 "nor", "$rA, $rS, $rB", IntSimple,
1650 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1651 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1652 "orc", "$rA, $rS, $rB", IntSimple,
1653 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1654 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1655 "eqv", "$rA, $rS, $rB", IntSimple,
1656 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1657 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1658 "xor", "$rA, $rS, $rB", IntSimple,
1659 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1660 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1661 "slw", "$rA, $rS, $rB", IntGeneral,
1662 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1663 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1664 "srw", "$rA, $rS, $rB", IntGeneral,
1665 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1666 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1667 "sraw", "$rA, $rS, $rB", IntShift,
1668 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1671 let PPC970_Unit = 1 in { // FXU Operations.
1672 let neverHasSideEffects = 1 in {
1673 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1674 "srawi", "$rA, $rS, $SH", IntShift,
1675 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1676 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1677 "cntlzw", "$rA, $rS", IntGeneral,
1678 [(set i32:$rA, (ctlz i32:$rS))]>;
1679 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1680 "extsb", "$rA, $rS", IntSimple,
1681 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1682 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1683 "extsh", "$rA, $rS", IntSimple,
1684 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1686 let isCompare = 1, neverHasSideEffects = 1 in {
1687 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1688 "cmpw $crD, $rA, $rB", IntCompare>;
1689 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1690 "cmplw $crD, $rA, $rB", IntCompare>;
1693 let PPC970_Unit = 3 in { // FPU Operations.
1694 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1695 // "fcmpo $crD, $fA, $fB", FPCompare>;
1696 let isCompare = 1, neverHasSideEffects = 1 in {
1697 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1698 "fcmpu $crD, $fA, $fB", FPCompare>;
1699 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1700 "fcmpu $crD, $fA, $fB", FPCompare>;
1703 let Uses = [RM] in {
1704 let neverHasSideEffects = 1 in {
1705 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1706 "fctiw", "$frD, $frB", FPGeneral,
1708 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1709 "fctiwz", "$frD, $frB", FPGeneral,
1710 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1712 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1713 "frsp", "$frD, $frB", FPGeneral,
1714 [(set f32:$frD, (fround f64:$frB))]>;
1716 let Interpretation64Bit = 1 in
1717 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1718 "frin", "$frD, $frB", FPGeneral,
1719 [(set f64:$frD, (frnd f64:$frB))]>;
1720 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1721 "frin", "$frD, $frB", FPGeneral,
1722 [(set f32:$frD, (frnd f32:$frB))]>;
1725 let neverHasSideEffects = 1 in {
1726 let Interpretation64Bit = 1 in
1727 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1728 "frip", "$frD, $frB", FPGeneral,
1729 [(set f64:$frD, (fceil f64:$frB))]>;
1730 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1731 "frip", "$frD, $frB", FPGeneral,
1732 [(set f32:$frD, (fceil f32:$frB))]>;
1733 let Interpretation64Bit = 1 in
1734 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1735 "friz", "$frD, $frB", FPGeneral,
1736 [(set f64:$frD, (ftrunc f64:$frB))]>;
1737 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1738 "friz", "$frD, $frB", FPGeneral,
1739 [(set f32:$frD, (ftrunc f32:$frB))]>;
1740 let Interpretation64Bit = 1 in
1741 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1742 "frim", "$frD, $frB", FPGeneral,
1743 [(set f64:$frD, (ffloor f64:$frB))]>;
1744 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1745 "frim", "$frD, $frB", FPGeneral,
1746 [(set f32:$frD, (ffloor f32:$frB))]>;
1748 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1749 "fsqrt", "$frD, $frB", FPSqrt,
1750 [(set f64:$frD, (fsqrt f64:$frB))]>;
1751 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1752 "fsqrts", "$frD, $frB", FPSqrt,
1753 [(set f32:$frD, (fsqrt f32:$frB))]>;
1758 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1759 /// often coalesced away and we don't want the dispatch group builder to think
1760 /// that they will fill slots (which could cause the load of a LSU reject to
1761 /// sneak into a d-group with a store).
1762 let neverHasSideEffects = 1 in
1763 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1764 "fmr", "$frD, $frB", FPGeneral,
1765 []>, // (set f32:$frD, f32:$frB)
1768 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1769 // These are artificially split into two different forms, for 4/8 byte FP.
1770 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1771 "fabs", "$frD, $frB", FPGeneral,
1772 [(set f32:$frD, (fabs f32:$frB))]>;
1773 let Interpretation64Bit = 1 in
1774 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1775 "fabs", "$frD, $frB", FPGeneral,
1776 [(set f64:$frD, (fabs f64:$frB))]>;
1777 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1778 "fnabs", "$frD, $frB", FPGeneral,
1779 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1780 let Interpretation64Bit = 1 in
1781 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1782 "fnabs", "$frD, $frB", FPGeneral,
1783 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1784 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1785 "fneg", "$frD, $frB", FPGeneral,
1786 [(set f32:$frD, (fneg f32:$frB))]>;
1787 let Interpretation64Bit = 1 in
1788 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1789 "fneg", "$frD, $frB", FPGeneral,
1790 [(set f64:$frD, (fneg f64:$frB))]>;
1792 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1793 "fcpsgn", "$frD, $frA, $frB", FPGeneral,
1794 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1795 let Interpretation64Bit = 1 in
1796 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1797 "fcpsgn", "$frD, $frA, $frB", FPGeneral,
1798 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1800 // Reciprocal estimates.
1801 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1802 "fre", "$frD, $frB", FPGeneral,
1803 [(set f64:$frD, (PPCfre f64:$frB))]>;
1804 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1805 "fres", "$frD, $frB", FPGeneral,
1806 [(set f32:$frD, (PPCfre f32:$frB))]>;
1807 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1808 "frsqrte", "$frD, $frB", FPGeneral,
1809 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1810 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1811 "frsqrtes", "$frD, $frB", FPGeneral,
1812 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1815 // XL-Form instructions. condition register logical ops.
1817 let neverHasSideEffects = 1 in
1818 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1819 "mcrf $BF, $BFA", BrMCR>,
1820 PPC970_DGroup_First, PPC970_Unit_CRU;
1822 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1823 (ins crbitrc:$CRA, crbitrc:$CRB),
1824 "crand $CRD, $CRA, $CRB", BrCR, []>;
1826 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1827 (ins crbitrc:$CRA, crbitrc:$CRB),
1828 "crnand $CRD, $CRA, $CRB", BrCR, []>;
1830 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1831 (ins crbitrc:$CRA, crbitrc:$CRB),
1832 "cror $CRD, $CRA, $CRB", BrCR, []>;
1834 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1835 (ins crbitrc:$CRA, crbitrc:$CRB),
1836 "crxor $CRD, $CRA, $CRB", BrCR, []>;
1838 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1839 (ins crbitrc:$CRA, crbitrc:$CRB),
1840 "crnor $CRD, $CRA, $CRB", BrCR, []>;
1842 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1843 (ins crbitrc:$CRA, crbitrc:$CRB),
1844 "creqv $CRD, $CRA, $CRB", BrCR, []>;
1846 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1847 (ins crbitrc:$CRA, crbitrc:$CRB),
1848 "crandc $CRD, $CRA, $CRB", BrCR, []>;
1850 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1851 (ins crbitrc:$CRA, crbitrc:$CRB),
1852 "crorc $CRD, $CRA, $CRB", BrCR, []>;
1854 let isCodeGenOnly = 1 in {
1855 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1856 "creqv $dst, $dst, $dst", BrCR,
1859 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1860 "crxor $dst, $dst, $dst", BrCR,
1863 let Defs = [CR1EQ], CRD = 6 in {
1864 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1865 "creqv 6, 6, 6", BrCR,
1868 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1869 "crxor 6, 6, 6", BrCR,
1874 // XFX-Form instructions. Instructions that deal with SPRs.
1877 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
1878 "mfspr $RT, $SPR", SprMFSPR>;
1879 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
1880 "mtspr $SPR, $RT", SprMTSPR>;
1882 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
1883 "mftb $RT, $SPR", SprMFTB>, Deprecated<DeprecatedMFTB>;
1885 let Uses = [CTR] in {
1886 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1887 "mfctr $rT", SprMFSPR>,
1888 PPC970_DGroup_First, PPC970_Unit_FXU;
1890 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1891 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1892 "mtctr $rS", SprMTSPR>,
1893 PPC970_DGroup_First, PPC970_Unit_FXU;
1895 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1896 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1897 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1898 "mtctr $rS", SprMTSPR>,
1899 PPC970_DGroup_First, PPC970_Unit_FXU;
1902 let Defs = [LR] in {
1903 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1904 "mtlr $rS", SprMTSPR>,
1905 PPC970_DGroup_First, PPC970_Unit_FXU;
1907 let Uses = [LR] in {
1908 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1909 "mflr $rT", SprMFSPR>,
1910 PPC970_DGroup_First, PPC970_Unit_FXU;
1913 let isCodeGenOnly = 1 in {
1914 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
1915 // like a GPR on the PPC970. As such, copies in and out have the same
1916 // performance characteristics as an OR instruction.
1917 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1918 "mtspr 256, $rS", IntGeneral>,
1919 PPC970_DGroup_Single, PPC970_Unit_FXU;
1920 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1921 "mfspr $rT, 256", IntGeneral>,
1922 PPC970_DGroup_First, PPC970_Unit_FXU;
1924 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1925 (outs VRSAVERC:$reg), (ins gprc:$rS),
1926 "mtspr 256, $rS", IntGeneral>,
1927 PPC970_DGroup_Single, PPC970_Unit_FXU;
1928 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1929 (ins VRSAVERC:$reg),
1930 "mfspr $rT, 256", IntGeneral>,
1931 PPC970_DGroup_First, PPC970_Unit_FXU;
1934 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1935 // so we'll need to scavenge a register for it.
1937 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1938 "#SPILL_VRSAVE", []>;
1940 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1941 // spilled), so we'll need to scavenge a register for it.
1943 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1944 "#RESTORE_VRSAVE", []>;
1946 let neverHasSideEffects = 1 in {
1947 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
1948 "mtocrf $FXM, $ST", BrMCRX>,
1949 PPC970_DGroup_First, PPC970_Unit_CRU;
1951 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
1952 "mtcrf $FXM, $rS", BrMCRX>,
1953 PPC970_MicroCode, PPC970_Unit_CRU;
1955 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
1956 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1957 "mfocrf $rT, $FXM", SprMFCR>,
1958 PPC970_DGroup_First, PPC970_Unit_CRU;
1960 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1961 "mfcr $rT", SprMFCR>,
1962 PPC970_MicroCode, PPC970_Unit_CRU;
1963 } // neverHasSideEffects = 1
1965 // Pseudo instruction to perform FADD in round-to-zero mode.
1966 let usesCustomInserter = 1, Uses = [RM] in {
1967 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1968 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1971 // The above pseudo gets expanded to make use of the following instructions
1972 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1973 let Uses = [RM], Defs = [RM] in {
1974 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1975 "mtfsb0 $FM", IntMTFSB0, []>,
1976 PPC970_DGroup_Single, PPC970_Unit_FPU;
1977 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1978 "mtfsb1 $FM", IntMTFSB0, []>,
1979 PPC970_DGroup_Single, PPC970_Unit_FPU;
1980 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1981 "mtfsf $FM, $rT", IntMTFSB0, []>,
1982 PPC970_DGroup_Single, PPC970_Unit_FPU;
1984 let Uses = [RM] in {
1985 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1986 "mffs $rT", IntMFFS,
1987 [(set f64:$rT, (PPCmffs))]>,
1988 PPC970_DGroup_Single, PPC970_Unit_FPU;
1992 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1993 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1995 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1996 "add", "$rT, $rA, $rB", IntSimple,
1997 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1998 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1999 "addc", "$rT, $rA, $rB", IntGeneral,
2000 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2001 PPC970_DGroup_Cracked;
2002 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2003 "divw", "$rT, $rA, $rB", IntDivW,
2004 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2005 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2006 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2007 "divwu", "$rT, $rA, $rB", IntDivW,
2008 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2009 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2010 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2011 "mulhw", "$rT, $rA, $rB", IntMulHW,
2012 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2013 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2014 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
2015 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2016 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2017 "mullw", "$rT, $rA, $rB", IntMulHW,
2018 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2019 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2020 "subf", "$rT, $rA, $rB", IntGeneral,
2021 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2022 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2023 "subfc", "$rT, $rA, $rB", IntGeneral,
2024 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2025 PPC970_DGroup_Cracked;
2026 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2027 "neg", "$rT, $rA", IntSimple,
2028 [(set i32:$rT, (ineg i32:$rA))]>;
2029 let Uses = [CARRY] in {
2030 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2031 "adde", "$rT, $rA, $rB", IntGeneral,
2032 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2033 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2034 "addme", "$rT, $rA", IntGeneral,
2035 [(set i32:$rT, (adde i32:$rA, -1))]>;
2036 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2037 "addze", "$rT, $rA", IntGeneral,
2038 [(set i32:$rT, (adde i32:$rA, 0))]>;
2039 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2040 "subfe", "$rT, $rA, $rB", IntGeneral,
2041 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2042 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2043 "subfme", "$rT, $rA", IntGeneral,
2044 [(set i32:$rT, (sube -1, i32:$rA))]>;
2045 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2046 "subfze", "$rT, $rA", IntGeneral,
2047 [(set i32:$rT, (sube 0, i32:$rA))]>;
2051 // A-Form instructions. Most of the instructions executed in the FPU are of
2054 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2055 let Uses = [RM] in {
2056 defm FMADD : AForm_1r<63, 29,
2057 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2058 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
2059 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2060 defm FMADDS : AForm_1r<59, 29,
2061 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2062 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2063 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2064 defm FMSUB : AForm_1r<63, 28,
2065 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2066 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
2068 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2069 defm FMSUBS : AForm_1r<59, 28,
2070 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2071 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2073 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2074 defm FNMADD : AForm_1r<63, 31,
2075 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2076 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
2078 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2079 defm FNMADDS : AForm_1r<59, 31,
2080 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2081 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2083 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2084 defm FNMSUB : AForm_1r<63, 30,
2085 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2086 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
2087 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2088 (fneg f64:$FRB))))]>;
2089 defm FNMSUBS : AForm_1r<59, 30,
2090 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2091 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2092 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2093 (fneg f32:$FRB))))]>;
2095 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2096 // having 4 of these, force the comparison to always be an 8-byte double (code
2097 // should use an FMRSD if the input comparison value really wants to be a float)
2098 // and 4/8 byte forms for the result and operand type..
2099 let Interpretation64Bit = 1 in
2100 defm FSELD : AForm_1r<63, 23,
2101 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2102 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2103 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2104 defm FSELS : AForm_1r<63, 23,
2105 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2106 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2107 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2108 let Uses = [RM] in {
2109 defm FADD : AForm_2r<63, 21,
2110 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2111 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
2112 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2113 defm FADDS : AForm_2r<59, 21,
2114 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2115 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
2116 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2117 defm FDIV : AForm_2r<63, 18,
2118 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2119 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
2120 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2121 defm FDIVS : AForm_2r<59, 18,
2122 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2123 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
2124 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2125 defm FMUL : AForm_3r<63, 25,
2126 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2127 "fmul", "$FRT, $FRA, $FRC", FPFused,
2128 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2129 defm FMULS : AForm_3r<59, 25,
2130 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2131 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
2132 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2133 defm FSUB : AForm_2r<63, 20,
2134 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2135 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
2136 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2137 defm FSUBS : AForm_2r<59, 20,
2138 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2139 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
2140 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2144 let neverHasSideEffects = 1 in {
2145 let PPC970_Unit = 1 in { // FXU Operations.
2147 def ISEL : AForm_4<31, 15,
2148 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2149 "isel $rT, $rA, $rB, $cond", IntGeneral,
2153 let PPC970_Unit = 1 in { // FXU Operations.
2154 // M-Form instructions. rotate and mask instructions.
2156 let isCommutable = 1 in {
2157 // RLWIMI can be commuted if the rotate amount is zero.
2158 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2159 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2160 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
2161 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
2164 let BaseName = "rlwinm" in {
2165 def RLWINM : MForm_2<21,
2166 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2167 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
2170 def RLWINMo : MForm_2<21,
2171 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2172 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
2173 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2175 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2176 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2177 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
2180 } // neverHasSideEffects = 1
2182 //===----------------------------------------------------------------------===//
2183 // PowerPC Instruction Patterns
2186 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2187 def : Pat<(i32 imm:$imm),
2188 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2190 // Implement the 'not' operation with the NOR instruction.
2191 def NOT : Pat<(not i32:$in),
2194 // ADD an arbitrary immediate.
2195 def : Pat<(add i32:$in, imm:$imm),
2196 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2197 // OR an arbitrary immediate.
2198 def : Pat<(or i32:$in, imm:$imm),
2199 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2200 // XOR an arbitrary immediate.
2201 def : Pat<(xor i32:$in, imm:$imm),
2202 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2204 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2205 (SUBFIC $in, imm:$imm)>;
2208 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2209 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2210 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2211 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2214 def : Pat<(rotl i32:$in, i32:$sh),
2215 (RLWNM $in, $sh, 0, 31)>;
2216 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2217 (RLWINM $in, imm:$imm, 0, 31)>;
2220 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2221 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2224 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2225 (BL tglobaladdr:$dst)>;
2226 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2227 (BL texternalsym:$dst)>;
2230 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2231 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2233 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2234 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2236 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2237 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2241 // Hi and Lo for Darwin Global Addresses.
2242 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2243 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2244 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2245 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2246 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2247 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2248 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2249 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2250 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2251 (ADDIS $in, tglobaltlsaddr:$g)>;
2252 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2253 (ADDI $in, tglobaltlsaddr:$g)>;
2254 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2255 (ADDIS $in, tglobaladdr:$g)>;
2256 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2257 (ADDIS $in, tconstpool:$g)>;
2258 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2259 (ADDIS $in, tjumptable:$g)>;
2260 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2261 (ADDIS $in, tblockaddress:$g)>;
2263 // Standard shifts. These are represented separately from the real shifts above
2264 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2266 def : Pat<(sra i32:$rS, i32:$rB),
2268 def : Pat<(srl i32:$rS, i32:$rB),
2270 def : Pat<(shl i32:$rS, i32:$rB),
2273 def : Pat<(zextloadi1 iaddr:$src),
2275 def : Pat<(zextloadi1 xaddr:$src),
2277 def : Pat<(extloadi1 iaddr:$src),
2279 def : Pat<(extloadi1 xaddr:$src),
2281 def : Pat<(extloadi8 iaddr:$src),
2283 def : Pat<(extloadi8 xaddr:$src),
2285 def : Pat<(extloadi16 iaddr:$src),
2287 def : Pat<(extloadi16 xaddr:$src),
2289 def : Pat<(f64 (extloadf32 iaddr:$src)),
2290 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2291 def : Pat<(f64 (extloadf32 xaddr:$src)),
2292 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2294 def : Pat<(f64 (fextend f32:$src)),
2295 (COPY_TO_REGCLASS $src, F8RC)>;
2297 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2298 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2300 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2301 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2302 (FNMSUB $A, $C, $B)>;
2303 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2304 (FNMSUB $A, $C, $B)>;
2305 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2306 (FNMSUBS $A, $C, $B)>;
2307 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2308 (FNMSUBS $A, $C, $B)>;
2310 // FCOPYSIGN's operand types need not agree.
2311 def : Pat<(fcopysign f64:$frB, f32:$frA),
2312 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2313 def : Pat<(fcopysign f32:$frB, f64:$frA),
2314 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2316 include "PPCInstrAltivec.td"
2317 include "PPCInstr64Bit.td"
2320 //===----------------------------------------------------------------------===//
2321 // PowerPC Instructions used for assembler/disassembler only
2324 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2325 "isync", SprISYNC, []>;
2327 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2328 "icbi $src", LdStICBI, []>;
2330 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
2331 "eieio", LdStLoad, []>;
2333 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
2334 "wait $L", LdStLoad, []>;
2336 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
2337 "mtmsr $RS, $L", SprMTMSR>;
2339 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
2340 "mfmsr $RT", SprMFMSR, []>;
2342 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
2343 "mtmsrd $RS, $L", SprMTMSRD>;
2345 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
2346 "slbie $RB", SprSLBIE, []>;
2348 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
2349 "slbmte $RS, $RB", SprSLBMTE, []>;
2351 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
2352 "slbmfee $RT, $RB", SprSLBMFEE, []>;
2354 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", SprSLBIA, []>;
2356 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
2357 "tlbsync", SprTLBSYNC, []>;
2359 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
2360 "tlbiel $RB", SprTLBIEL, []>;
2362 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
2363 "tlbie $RB,$RS", SprTLBIE, []>;
2365 //===----------------------------------------------------------------------===//
2366 // PowerPC Assembler Instruction Aliases
2369 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2370 // These are aliases that require C++ handling to convert to the target
2371 // instruction, while InstAliases can be handled directly by tblgen.
2372 class PPCAsmPseudo<string asm, dag iops>
2374 let Namespace = "PPC";
2375 bit PPC64 = 0; // Default value, override with isPPC64
2377 let OutOperandList = (outs);
2378 let InOperandList = iops;
2380 let AsmString = asm;
2381 let isAsmParserOnly = 1;
2385 def : InstAlias<"sc", (SC 0)>;
2387 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
2388 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
2389 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
2390 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
2392 def : InstAlias<"wait", (WAIT 0)>;
2393 def : InstAlias<"waitrsv", (WAIT 1)>;
2394 def : InstAlias<"waitimpl", (WAIT 2)>;
2396 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2397 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
2398 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2399 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
2401 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
2402 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
2404 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
2405 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
2407 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
2409 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2410 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2412 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2413 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2415 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
2417 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
2419 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
2420 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2421 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
2422 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2423 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
2424 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2425 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
2426 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
2428 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2429 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2430 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2431 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
2433 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
2434 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
2436 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
2437 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
2438 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
2439 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
2441 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
2442 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
2443 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
2444 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
2446 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
2447 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
2448 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
2449 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
2451 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
2452 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
2453 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
2454 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
2456 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
2458 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
2459 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
2461 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
2463 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
2464 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
2466 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
2467 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
2468 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
2469 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
2471 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
2473 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
2474 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2475 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
2476 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2477 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
2478 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2479 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
2480 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2481 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
2482 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2483 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
2484 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2485 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
2486 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2487 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
2488 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
2489 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
2490 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2491 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
2492 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2493 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2494 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2495 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
2496 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2497 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2498 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2499 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
2500 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2501 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
2502 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2503 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
2504 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2505 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
2506 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2507 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
2508 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
2510 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2511 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
2512 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2513 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
2514 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2515 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
2517 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
2518 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2519 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
2520 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2521 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
2522 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2523 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
2524 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2525 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
2526 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2527 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
2528 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
2529 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
2530 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2531 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
2532 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2533 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2534 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2535 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
2536 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2537 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2538 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2539 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
2540 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2541 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
2542 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2543 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
2544 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2545 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
2546 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2547 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
2548 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
2550 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2551 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
2552 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2553 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
2554 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2555 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
2557 // These generic branch instruction forms are used for the assembler parser only.
2558 // Defs and Uses are conservative, since we don't know the BO value.
2559 let PPC970_Unit = 7 in {
2560 let Defs = [CTR], Uses = [CTR, RM] in {
2561 def gBC : BForm_3<16, 0, 0, (outs),
2562 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2563 "bc $bo, $bi, $dst">;
2564 def gBCA : BForm_3<16, 1, 0, (outs),
2565 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2566 "bca $bo, $bi, $dst">;
2568 let Defs = [LR, CTR], Uses = [CTR, RM] in {
2569 def gBCL : BForm_3<16, 0, 1, (outs),
2570 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2571 "bcl $bo, $bi, $dst">;
2572 def gBCLA : BForm_3<16, 1, 1, (outs),
2573 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2574 "bcla $bo, $bi, $dst">;
2576 let Defs = [CTR], Uses = [CTR, LR, RM] in
2577 def gBCLR : XLForm_2<19, 16, 0, (outs),
2578 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2579 "bclr $bo, $bi, $bh", BrB, []>;
2580 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2581 def gBCLRL : XLForm_2<19, 16, 1, (outs),
2582 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2583 "bclrl $bo, $bi, $bh", BrB, []>;
2584 let Defs = [CTR], Uses = [CTR, LR, RM] in
2585 def gBCCTR : XLForm_2<19, 528, 0, (outs),
2586 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2587 "bcctr $bo, $bi, $bh", BrB, []>;
2588 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2589 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
2590 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2591 "bcctrl $bo, $bi, $bh", BrB, []>;
2593 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
2594 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
2595 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
2596 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
2598 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
2599 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
2600 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2601 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
2602 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
2603 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2604 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
2606 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
2607 : BranchSimpleMnemonic1<name, pm, bo> {
2608 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
2609 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
2611 defm : BranchSimpleMnemonic2<"t", "", 12>;
2612 defm : BranchSimpleMnemonic2<"f", "", 4>;
2613 defm : BranchSimpleMnemonic2<"t", "-", 14>;
2614 defm : BranchSimpleMnemonic2<"f", "-", 6>;
2615 defm : BranchSimpleMnemonic2<"t", "+", 15>;
2616 defm : BranchSimpleMnemonic2<"f", "+", 7>;
2617 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
2618 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
2619 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
2620 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
2622 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
2623 def : InstAlias<"b"#name#pm#" $cc, $dst",
2624 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
2625 def : InstAlias<"b"#name#pm#" $dst",
2626 (BCC bibo, CR0, condbrtarget:$dst)>;
2628 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
2629 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2630 def : InstAlias<"b"#name#"a"#pm#" $dst",
2631 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
2633 def : InstAlias<"b"#name#"lr"#pm#" $cc",
2634 (BCLR bibo, crrc:$cc)>;
2635 def : InstAlias<"b"#name#"lr"#pm,
2638 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
2639 (BCCTR bibo, crrc:$cc)>;
2640 def : InstAlias<"b"#name#"ctr"#pm,
2643 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
2644 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
2645 def : InstAlias<"b"#name#"l"#pm#" $dst",
2646 (BCCL bibo, CR0, condbrtarget:$dst)>;
2648 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
2649 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2650 def : InstAlias<"b"#name#"la"#pm#" $dst",
2651 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
2653 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
2654 (BCLRL bibo, crrc:$cc)>;
2655 def : InstAlias<"b"#name#"lrl"#pm,
2658 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
2659 (BCCTRL bibo, crrc:$cc)>;
2660 def : InstAlias<"b"#name#"ctrl"#pm,
2661 (BCCTRL bibo, CR0)>;
2663 multiclass BranchExtendedMnemonic<string name, int bibo> {
2664 defm : BranchExtendedMnemonicPM<name, "", bibo>;
2665 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
2666 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
2668 defm : BranchExtendedMnemonic<"lt", 12>;
2669 defm : BranchExtendedMnemonic<"gt", 44>;
2670 defm : BranchExtendedMnemonic<"eq", 76>;
2671 defm : BranchExtendedMnemonic<"un", 108>;
2672 defm : BranchExtendedMnemonic<"so", 108>;
2673 defm : BranchExtendedMnemonic<"ge", 4>;
2674 defm : BranchExtendedMnemonic<"nl", 4>;
2675 defm : BranchExtendedMnemonic<"le", 36>;
2676 defm : BranchExtendedMnemonic<"ng", 36>;
2677 defm : BranchExtendedMnemonic<"ne", 68>;
2678 defm : BranchExtendedMnemonic<"nu", 100>;
2679 defm : BranchExtendedMnemonic<"ns", 100>;
2681 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
2682 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
2683 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
2684 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
2685 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
2686 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
2687 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
2688 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
2690 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
2691 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
2692 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
2693 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
2694 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm:$imm)>;
2695 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2696 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm:$imm)>;
2697 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
2699 multiclass TrapExtendedMnemonic<string name, int to> {
2700 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
2701 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
2702 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
2703 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
2705 defm : TrapExtendedMnemonic<"lt", 16>;
2706 defm : TrapExtendedMnemonic<"le", 20>;
2707 defm : TrapExtendedMnemonic<"eq", 4>;
2708 defm : TrapExtendedMnemonic<"ge", 12>;
2709 defm : TrapExtendedMnemonic<"gt", 8>;
2710 defm : TrapExtendedMnemonic<"nl", 12>;
2711 defm : TrapExtendedMnemonic<"ne", 24>;
2712 defm : TrapExtendedMnemonic<"ng", 20>;
2713 defm : TrapExtendedMnemonic<"llt", 2>;
2714 defm : TrapExtendedMnemonic<"lle", 6>;
2715 defm : TrapExtendedMnemonic<"lge", 5>;
2716 defm : TrapExtendedMnemonic<"lgt", 1>;
2717 defm : TrapExtendedMnemonic<"lnl", 5>;
2718 defm : TrapExtendedMnemonic<"lng", 6>;
2719 defm : TrapExtendedMnemonic<"u", 31>;