1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32>;
27 def isSI : Predicate<"Subtarget.getGeneration() "
28 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
30 def WAIT_FLAG : InstFlag<"printWaitFlag">;
32 let Predicates = [isSI] in {
34 let neverHasSideEffects = 1 in {
36 let isMoveImm = 1 in {
37 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
38 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
39 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
40 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
41 } // End isMoveImm = 1
43 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
44 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
45 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
46 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
47 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
48 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
49 } // End neverHasSideEffects = 1
51 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
52 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
53 ////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>;
54 ////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>;
55 ////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>;
56 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
57 ////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>;
58 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
59 //def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>;
60 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
61 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
62 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
63 //def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>;
64 //def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>;
65 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
66 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
67 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
68 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
69 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
70 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
71 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
72 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
74 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
76 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
77 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
78 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
79 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
80 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
81 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
82 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
83 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
85 } // End hasSideEffects = 1
87 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
88 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
89 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
90 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
91 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
92 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
93 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
94 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
95 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
96 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
97 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
98 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
101 This instruction is disabled for now until we can figure out how to teach
102 the instruction selector to correctly use the S_CMP* vs V_CMP*
105 When this instruction is enabled the code generator sometimes produces this
108 SCC = S_CMPK_EQ_I32 SGPR0, imm
110 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
112 def S_CMPK_EQ_I32 : SOPK <
113 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
115 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
119 let isCompare = 1 in {
120 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
121 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
122 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
123 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
124 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
125 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
126 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
127 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
128 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
129 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
130 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
131 } // End isCompare = 1
133 let Defs = [SCC], isCommutable = 1 in {
134 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
135 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
138 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
139 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
140 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
141 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
142 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
143 //def EXP : EXP_ <0x00000000, "EXP", []>;
145 let isCompare = 1 in {
147 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
148 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
149 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
150 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
151 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
152 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
153 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
154 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
155 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
156 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
157 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
158 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
159 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
160 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
161 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
162 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
164 let hasSideEffects = 1, Defs = [EXEC] in {
166 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
167 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
168 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
169 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
170 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
171 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
172 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
173 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
174 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
175 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
176 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
177 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
178 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
179 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
180 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
181 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
183 } // End hasSideEffects = 1, Defs = [EXEC]
185 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
186 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
187 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
188 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
189 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
190 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
191 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
192 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
193 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
194 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
195 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
196 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
197 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
198 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
199 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
200 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
202 let hasSideEffects = 1, Defs = [EXEC] in {
204 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
205 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
206 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
207 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
208 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
209 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
210 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
211 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
212 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
213 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
214 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
215 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
216 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
217 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
218 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
219 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
221 } // End hasSideEffects = 1, Defs = [EXEC]
223 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
224 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
225 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
226 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
227 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
228 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
229 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
230 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
231 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
232 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
233 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
234 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
235 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
236 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
237 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
238 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
240 let hasSideEffects = 1, Defs = [EXEC] in {
242 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
243 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
244 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
245 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
246 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
247 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
248 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
249 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
250 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
251 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
252 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
253 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
254 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
255 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
256 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
257 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
259 } // End hasSideEffects = 1, Defs = [EXEC]
261 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
262 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
263 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
264 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
265 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
266 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
267 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
268 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
269 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
270 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
271 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
272 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
273 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
274 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
275 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
276 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
278 let hasSideEffects = 1, Defs = [EXEC] in {
280 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
281 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
282 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
283 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
284 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
285 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
286 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
287 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
288 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
289 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
290 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
291 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
292 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
293 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
294 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
295 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
297 } // End hasSideEffects = 1, Defs = [EXEC]
299 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
300 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
301 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
302 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
303 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
304 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
305 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
306 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
308 let hasSideEffects = 1, Defs = [EXEC] in {
310 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
311 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
312 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
313 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
314 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
315 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
316 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
317 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
319 } // End hasSideEffects = 1, Defs = [EXEC]
321 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
322 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
323 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
324 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
325 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
326 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
327 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
328 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
330 let hasSideEffects = 1, Defs = [EXEC] in {
332 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
333 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
334 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
335 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
336 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
337 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
338 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
339 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
341 } // End hasSideEffects = 1, Defs = [EXEC]
343 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
344 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
345 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
346 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
347 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
348 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
349 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
350 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
352 let hasSideEffects = 1, Defs = [EXEC] in {
354 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
355 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
356 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
357 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
358 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
359 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
360 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
361 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
363 } // End hasSideEffects = 1, Defs = [EXEC]
365 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
366 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
367 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
368 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
369 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
370 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
371 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
372 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
374 let hasSideEffects = 1, Defs = [EXEC] in {
376 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
377 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
378 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
379 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
380 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
381 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
382 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
383 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
385 } // End hasSideEffects = 1, Defs = [EXEC]
387 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
389 let hasSideEffects = 1, Defs = [EXEC] in {
390 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
391 } // End hasSideEffects = 1, Defs = [EXEC]
393 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
395 let hasSideEffects = 1, Defs = [EXEC] in {
396 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
397 } // End hasSideEffects = 1, Defs = [EXEC]
399 } // End isCompare = 1
401 def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
402 def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
403 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
404 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
405 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
406 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
407 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
408 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
409 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
410 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
412 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
413 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
414 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
415 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
416 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
417 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
418 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
419 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
420 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
421 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
422 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
423 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
424 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
425 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
426 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
428 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
429 0x00000018, "BUFFER_STORE_BYTE", VReg_32
432 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
433 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
436 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
437 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
440 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
441 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
444 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
445 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
447 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
448 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
449 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
450 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
451 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
452 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
453 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
454 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
455 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
456 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
457 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
458 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
459 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
460 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
461 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
462 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
463 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
464 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
465 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
466 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
467 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
468 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
469 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
470 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
471 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
472 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
473 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
474 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
475 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
476 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
477 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
478 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
479 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
480 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
481 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
482 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
483 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
484 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
485 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
486 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
487 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
488 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
489 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
490 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
494 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
495 // SMRD instructions, because the SGPR_32 register class does not include M0
496 // and writing to M0 from an SMRD instruction will hang the GPU.
497 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
498 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
499 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
500 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
501 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
503 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
504 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
507 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
508 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
511 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
512 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
515 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
516 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
519 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
520 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
525 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
526 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
527 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
528 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
529 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
530 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
531 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
532 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
533 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
534 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
535 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
536 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
537 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
538 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
539 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
540 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
541 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
542 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
543 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
544 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
545 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
546 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
547 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
548 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
549 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
550 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
551 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
552 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
553 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
554 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
555 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
556 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
557 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
558 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
559 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
560 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
561 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
562 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
563 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
564 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
565 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
566 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
567 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
568 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
569 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
570 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
571 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
572 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
573 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
574 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
575 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
576 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
577 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
578 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
579 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
580 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
581 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
582 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
583 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
584 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
585 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
586 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
587 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
588 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
589 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
590 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
591 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
592 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
593 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
594 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
595 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
596 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
597 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
598 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
599 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
600 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
601 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
602 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
603 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
604 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
605 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
606 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
607 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
608 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
609 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
610 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
611 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
612 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
613 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
614 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
615 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
616 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
617 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
618 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
619 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
620 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
621 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
622 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
625 let neverHasSideEffects = 1, isMoveImm = 1 in {
626 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
627 } // End neverHasSideEffects = 1, isMoveImm = 1
629 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
630 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
631 [(set i32:$dst, (fp_to_sint f64:$src0))]
633 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
634 [(set f64:$dst, (sint_to_fp i32:$src0))]
636 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
637 [(set f32:$dst, (sint_to_fp i32:$src0))]
639 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
640 [(set f32:$dst, (uint_to_fp i32:$src0))]
642 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
643 [(set i32:$dst, (fp_to_uint f32:$src0))]
645 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
646 [(set i32:$dst, (fp_to_sint f32:$src0))]
648 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
649 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
650 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
651 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
652 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
653 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
654 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
655 [(set f32:$dst, (fround f64:$src0))]
657 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
658 [(set f64:$dst, (fextend f32:$src0))]
660 //defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
661 //defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
662 //defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
663 //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>;
664 //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>;
665 //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>;
666 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
667 [(set f32:$dst, (AMDGPUfract f32:$src0))]
669 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
670 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
672 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
673 [(set f32:$dst, (fceil f32:$src0))]
675 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
676 [(set f32:$dst, (frint f32:$src0))]
678 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
679 [(set f32:$dst, (ffloor f32:$src0))]
681 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
682 [(set f32:$dst, (fexp2 f32:$src0))]
684 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
685 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
686 [(set f32:$dst, (flog2 f32:$src0))]
688 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
689 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
690 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
691 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
693 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
694 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
695 defm V_RSQ_LEGACY_F32 : VOP1_32 <
696 0x0000002d, "V_RSQ_LEGACY_F32",
697 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
699 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>;
700 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
701 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
703 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
704 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>;
705 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
706 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
707 [(set f32:$dst, (fsqrt f32:$src0))]
709 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
710 [(set f64:$dst, (fsqrt f64:$src0))]
712 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
713 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
714 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
715 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
716 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
717 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
718 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
719 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
720 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
721 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
722 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
723 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
724 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
725 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
726 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
727 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
729 def V_INTERP_P1_F32 : VINTRP <
732 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
733 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
735 let DisableEncoding = "$m0";
738 def V_INTERP_P2_F32 : VINTRP <
741 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
742 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
745 let Constraints = "$src0 = $dst";
746 let DisableEncoding = "$src0,$m0";
750 def V_INTERP_MOV_F32 : VINTRP <
753 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
754 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
756 let DisableEncoding = "$m0";
759 //def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
761 let isTerminator = 1 in {
763 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
770 let isBranch = 1 in {
771 def S_BRANCH : SOPP <
772 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
777 let DisableEncoding = "$scc" in {
778 def S_CBRANCH_SCC0 : SOPP <
779 0x00000004, (ins brtarget:$target, SCCReg:$scc),
780 "S_CBRANCH_SCC0 $target", []
782 def S_CBRANCH_SCC1 : SOPP <
783 0x00000005, (ins brtarget:$target, SCCReg:$scc),
784 "S_CBRANCH_SCC1 $target",
787 } // End DisableEncoding = "$scc"
789 def S_CBRANCH_VCCZ : SOPP <
790 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
791 "S_CBRANCH_VCCZ $target",
794 def S_CBRANCH_VCCNZ : SOPP <
795 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
796 "S_CBRANCH_VCCNZ $target",
800 let DisableEncoding = "$exec" in {
801 def S_CBRANCH_EXECZ : SOPP <
802 0x00000008, (ins brtarget:$target, EXECReg:$exec),
803 "S_CBRANCH_EXECZ $target",
806 def S_CBRANCH_EXECNZ : SOPP <
807 0x00000009, (ins brtarget:$target, EXECReg:$exec),
808 "S_CBRANCH_EXECNZ $target",
811 } // End DisableEncoding = "$exec"
814 } // End isBranch = 1
815 } // End isTerminator = 1
817 let hasSideEffects = 1 in {
818 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
819 [(int_AMDGPU_barrier_local)]
828 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
831 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
832 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
833 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
835 let Uses = [EXEC] in {
836 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
837 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
839 let DisableEncoding = "$m0";
841 } // End Uses = [EXEC]
843 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
844 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
845 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
846 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
847 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
848 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
849 } // End hasSideEffects
851 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
852 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
853 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
856 let DisableEncoding = "$vcc";
859 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
860 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
861 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
862 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
863 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
866 //f32 pattern for V_CNDMASK_B32_e64
868 (f32 (select i1:$src2, f32:$src1, f32:$src0)),
869 (V_CNDMASK_B32_e64 $src0, $src1, $src2)
873 (i32 (trunc i64:$val)),
874 (EXTRACT_SUBREG $val, sub0)
877 //use two V_CNDMASK_B32_e64 instructions for f64
879 (f64 (select i1:$src2, f64:$src1, f64:$src0)),
880 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
881 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0),
882 (EXTRACT_SUBREG $src1, sub0),
884 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1),
885 (EXTRACT_SUBREG $src1, sub1),
889 defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
890 defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>;
892 let isCommutable = 1 in {
893 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
894 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
897 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
898 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
900 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
901 } // End isCommutable = 1
903 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
905 let isCommutable = 1 in {
907 defm V_MUL_LEGACY_F32 : VOP2_32 <
908 0x00000007, "V_MUL_LEGACY_F32",
909 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
912 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
913 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
917 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
918 [(set i32:$dst, (mul I24:$src0, I24:$src1))]
920 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
921 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
922 [(set i32:$dst, (mul U24:$src0, U24:$src1))]
924 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
927 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
928 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
931 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
932 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
935 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
936 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
937 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
938 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
940 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
941 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
943 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
944 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
946 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
947 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
950 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
951 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
953 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
955 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
956 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
958 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
960 let hasPostISelHook = 1 in {
962 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
963 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
967 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
969 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
970 [(set i32:$dst, (and i32:$src0, i32:$src1))]
972 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
973 [(set i32:$dst, (or i32:$src0, i32:$src1))]
975 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
976 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
979 } // End isCommutable = 1
981 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>;
982 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
983 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
984 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
985 //defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
986 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
987 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
989 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
990 // No patterns so that the scalar instructions are always selected.
991 // The scalar versions will be replaced with vector when needed later.
992 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>;
993 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>;
994 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
997 let Uses = [VCC] in { // Carry-in comes from VCC
998 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>;
999 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>;
1000 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
1002 } // End Uses = [VCC]
1003 } // End isCommutable = 1, Defs = [VCC]
1005 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1006 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1007 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1008 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1009 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1010 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1012 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1013 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1014 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>;
1015 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>;
1016 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>;
1017 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>;
1018 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>;
1019 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>;
1020 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>;
1021 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>;
1022 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>;
1023 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>;
1024 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>;
1025 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>;
1026 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
1027 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
1028 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
1029 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
1030 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
1032 let neverHasSideEffects = 1 in {
1034 def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1035 def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
1036 def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1037 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))]
1039 def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1040 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))]
1043 } // End neverHasSideEffects
1044 def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1045 def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1046 def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1047 def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1048 def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
1049 def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
1050 def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
1051 defm : BFIPatterns <V_BFI_B32>;
1052 def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1053 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1055 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1056 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1058 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1059 def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1060 def : ROTRPattern <V_ALIGNBIT_B32>;
1062 def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1063 def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1064 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1065 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1066 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1067 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1068 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1069 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1070 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1071 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1072 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1073 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1074 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1075 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1076 def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1077 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1078 def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1079 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1081 def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64",
1082 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1084 def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64",
1085 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1087 def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64",
1088 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1091 let isCommutable = 1 in {
1093 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1094 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1095 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1096 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1098 } // isCommutable = 1
1101 (fadd f64:$src0, f64:$src1),
1102 (V_ADD_F64 $src0, $src1, (i64 0))
1106 (fmul f64:$src0, f64:$src1),
1107 (V_MUL_F64 $src0, $src1, (i64 0))
1110 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1112 let isCommutable = 1 in {
1114 def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1115 def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1116 def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1117 def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1119 } // isCommutable = 1
1122 (mul i32:$src0, i32:$src1),
1123 (V_MUL_LO_I32 $src0, $src1, (i32 0))
1127 (mulhu i32:$src0, i32:$src1),
1128 (V_MUL_HI_U32 $src0, $src1, (i32 0))
1132 (mulhs i32:$src0, i32:$src1),
1133 (V_MUL_HI_I32 $src0, $src1, (i32 0))
1136 def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1137 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1138 def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1139 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1140 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1141 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1142 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1143 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1145 let Defs = [SCC] in { // Carry out goes to SCC
1146 let isCommutable = 1 in {
1147 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
1148 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
1149 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
1151 } // End isCommutable = 1
1153 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
1154 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
1155 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
1158 let Uses = [SCC] in { // Carry in comes from SCC
1159 let isCommutable = 1 in {
1160 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
1161 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
1162 } // End isCommutable = 1
1164 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
1165 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
1166 } // End Uses = [SCC]
1167 } // End Defs = [SCC]
1169 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>;
1170 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>;
1171 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>;
1172 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>;
1174 def S_CSELECT_B32 : SOP2 <
1175 0x0000000a, (outs SReg_32:$dst),
1176 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
1180 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
1182 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>;
1184 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
1185 [(set i64:$dst, (and i64:$src0, i64:$src1))]
1189 (i1 (and i1:$src0, i1:$src1)),
1190 (S_AND_B64 $src0, $src1)
1193 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>;
1194 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>;
1196 (i1 (or i1:$src0, i1:$src1)),
1197 (S_OR_B64 $src0, $src1)
1199 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>;
1200 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
1201 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1203 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
1204 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
1205 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
1206 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
1207 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
1208 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
1209 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
1210 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
1211 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
1212 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
1214 // Use added complexity so these patterns are preferred to the VALU patterns.
1215 let AddedComplexity = 1 in {
1217 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
1218 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1220 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
1221 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1223 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
1224 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1226 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
1227 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1229 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
1230 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1232 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
1233 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1236 } // End AddedComplexity = 1
1238 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
1239 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
1240 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
1241 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
1242 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
1243 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
1244 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
1245 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
1246 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
1248 let isCodeGenOnly = 1, isPseudo = 1 in {
1250 def LOAD_CONST : AMDGPUShaderInst <
1253 "LOAD_CONST $dst, $src",
1254 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))]
1257 // SI pseudo instructions. These are used by the CFG structurizer pass
1258 // and should be lowered to ISA instructions prior to codegen.
1260 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1261 Uses = [EXEC], Defs = [EXEC] in {
1263 let isBranch = 1, isTerminator = 1 in {
1265 def SI_IF : InstSI <
1266 (outs SReg_64:$dst),
1267 (ins SReg_64:$vcc, brtarget:$target),
1268 "SI_IF $dst, $vcc, $target",
1269 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1272 def SI_ELSE : InstSI <
1273 (outs SReg_64:$dst),
1274 (ins SReg_64:$src, brtarget:$target),
1275 "SI_ELSE $dst, $src, $target",
1276 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> {
1278 let Constraints = "$src = $dst";
1281 def SI_LOOP : InstSI <
1283 (ins SReg_64:$saved, brtarget:$target),
1284 "SI_LOOP $saved, $target",
1285 [(int_SI_loop i64:$saved, bb:$target)]
1288 } // end isBranch = 1, isTerminator = 1
1290 def SI_BREAK : InstSI <
1291 (outs SReg_64:$dst),
1293 "SI_ELSE $dst, $src",
1294 [(set i64:$dst, (int_SI_break i64:$src))]
1297 def SI_IF_BREAK : InstSI <
1298 (outs SReg_64:$dst),
1299 (ins SReg_64:$vcc, SReg_64:$src),
1300 "SI_IF_BREAK $dst, $vcc, $src",
1301 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1304 def SI_ELSE_BREAK : InstSI <
1305 (outs SReg_64:$dst),
1306 (ins SReg_64:$src0, SReg_64:$src1),
1307 "SI_ELSE_BREAK $dst, $src0, $src1",
1308 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1311 def SI_END_CF : InstSI <
1313 (ins SReg_64:$saved),
1315 [(int_SI_end_cf i64:$saved)]
1318 def SI_KILL : InstSI <
1322 [(int_AMDGPU_kill f32:$src)]
1325 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1326 // Uses = [EXEC], Defs = [EXEC]
1328 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1330 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri64, ADDRIndirect>;
1332 let UseNamedOperandTable = 1 in {
1334 def SI_RegisterLoad : AMDGPUShaderInst <
1335 (outs VReg_32:$dst, SReg_64:$temp),
1336 (ins FRAMEri64:$addr, i32imm:$chan),
1339 let isRegisterLoad = 1;
1343 class SIRegStore<dag outs> : AMDGPUShaderInst <
1345 (ins VReg_32:$val, FRAMEri64:$addr, i32imm:$chan),
1348 let isRegisterStore = 1;
1352 let usesCustomInserter = 1 in {
1353 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1354 } // End usesCustomInserter = 1
1355 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1358 } // End UseNamedOperandTable = 1
1360 def SI_INDIRECT_SRC : InstSI <
1361 (outs VReg_32:$dst, SReg_64:$temp),
1362 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1363 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1367 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1368 (outs rc:$dst, SReg_64:$temp),
1369 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1370 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1373 let Constraints = "$src = $dst";
1376 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1377 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1378 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1379 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1380 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1382 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1384 let usesCustomInserter = 1 in {
1386 // This pseudo instruction takes a pointer as input and outputs a resource
1387 // constant that can be used with the ADDR64 MUBUF instructions.
1388 def SI_ADDR64_RSRC : InstSI <
1389 (outs SReg_128:$srsrc),
1394 def V_SUB_F64 : InstSI <
1395 (outs VReg_64:$dst),
1396 (ins VReg_64:$src0, VReg_64:$src1),
1397 "V_SUB_F64 $dst, $src0, $src1",
1401 } // end usesCustomInserter
1403 } // end IsCodeGenOnly, isPseudo
1406 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1407 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1412 (SI_KILL (V_MOV_B32_e32 0xbf800000))
1415 /* int_SI_vs_load_input */
1417 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
1418 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1423 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1424 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1425 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1426 $src0, $src1, $src2, $src3)
1430 (f64 (fsub f64:$src0, f64:$src1)),
1431 (V_SUB_F64 $src0, $src1)
1434 /********** ======================= **********/
1435 /********** Image sampling patterns **********/
1436 /********** ======================= **********/
1438 /* SIsample for simple 1D texture lookup */
1440 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm),
1441 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1444 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1445 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm),
1446 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1449 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1450 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT),
1451 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1454 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1455 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY),
1456 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1459 class SampleShadowPattern<SDNode name, MIMG opcode,
1460 ValueType vt> : Pat <
1461 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW),
1462 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1465 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1466 ValueType vt> : Pat <
1467 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY),
1468 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1471 /* SIsample* for texture lookups consuming more address parameters */
1472 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1473 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1474 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1475 def : SamplePattern <SIsample, sample, addr_type>;
1476 def : SampleRectPattern <SIsample, sample, addr_type>;
1477 def : SampleArrayPattern <SIsample, sample, addr_type>;
1478 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1479 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1481 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1482 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1483 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1484 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1486 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1487 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1488 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1489 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1491 def : SamplePattern <SIsampled, sample_d, addr_type>;
1492 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1493 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1494 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1497 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1498 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1499 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1500 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1502 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1503 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1504 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1505 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1507 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1508 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1509 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1510 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1512 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1513 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1514 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1515 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1518 /* int_SI_imageload for texture fetches consuming varying address parameters */
1519 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1520 (name addr_type:$addr, v32i8:$rsrc, imm),
1521 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1524 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1525 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1526 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1529 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1530 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1531 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1534 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1535 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1536 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1539 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1540 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1541 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1544 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1545 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1546 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1549 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1550 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1552 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1553 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1555 /* Image resource information */
1557 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1558 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1562 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1563 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1567 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1568 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1571 /********** ============================================ **********/
1572 /********** Extraction, Insertion, Building and Casting **********/
1573 /********** ============================================ **********/
1575 foreach Index = 0-2 in {
1576 def Extract_Element_v2i32_#Index : Extract_Element <
1577 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1579 def Insert_Element_v2i32_#Index : Insert_Element <
1580 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1583 def Extract_Element_v2f32_#Index : Extract_Element <
1584 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1586 def Insert_Element_v2f32_#Index : Insert_Element <
1587 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1591 foreach Index = 0-3 in {
1592 def Extract_Element_v4i32_#Index : Extract_Element <
1593 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1595 def Insert_Element_v4i32_#Index : Insert_Element <
1596 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1599 def Extract_Element_v4f32_#Index : Extract_Element <
1600 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1602 def Insert_Element_v4f32_#Index : Insert_Element <
1603 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1607 foreach Index = 0-7 in {
1608 def Extract_Element_v8i32_#Index : Extract_Element <
1609 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1611 def Insert_Element_v8i32_#Index : Insert_Element <
1612 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1615 def Extract_Element_v8f32_#Index : Extract_Element <
1616 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1618 def Insert_Element_v8f32_#Index : Insert_Element <
1619 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1623 foreach Index = 0-15 in {
1624 def Extract_Element_v16i32_#Index : Extract_Element <
1625 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1627 def Insert_Element_v16i32_#Index : Insert_Element <
1628 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1631 def Extract_Element_v16f32_#Index : Extract_Element <
1632 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1634 def Insert_Element_v16f32_#Index : Insert_Element <
1635 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1639 def : BitConvert <i32, f32, SReg_32>;
1640 def : BitConvert <i32, f32, VReg_32>;
1642 def : BitConvert <f32, i32, SReg_32>;
1643 def : BitConvert <f32, i32, VReg_32>;
1645 def : BitConvert <i64, f64, VReg_64>;
1647 def : BitConvert <f64, i64, VReg_64>;
1649 def : BitConvert <v2f32, v2i32, VReg_64>;
1650 def : BitConvert <v2i32, v2f32, VReg_64>;
1651 def : BitConvert <v2i32, i64, VReg_64>;
1653 def : BitConvert <v4f32, v4i32, VReg_128>;
1654 def : BitConvert <v4i32, v4f32, VReg_128>;
1655 def : BitConvert <v4i32, i128, VReg_128>;
1656 def : BitConvert <i128, v4i32, VReg_128>;
1658 def : BitConvert <v8i32, v32i8, SReg_256>;
1659 def : BitConvert <v32i8, v8i32, SReg_256>;
1660 def : BitConvert <v8i32, v32i8, VReg_256>;
1661 def : BitConvert <v32i8, v8i32, VReg_256>;
1663 /********** =================== **********/
1664 /********** Src & Dst modifiers **********/
1665 /********** =================== **********/
1668 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
1669 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1670 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
1673 /********** ================================ **********/
1674 /********** Floating point absolute/negative **********/
1675 /********** ================================ **********/
1677 // Manipulate the sign bit directly, as e.g. using the source negation modifier
1678 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
1679 // breaking the piglit *s-floatBitsToInt-neg* tests
1681 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
1682 // removing these patterns
1685 (fneg (fabs f32:$src)),
1686 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
1691 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */
1696 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */
1699 /********** ================== **********/
1700 /********** Immediate Patterns **********/
1701 /********** ================== **********/
1704 (SGPRImm<(i32 imm)>:$imm),
1705 (S_MOV_B32 imm:$imm)
1709 (SGPRImm<(f32 fpimm)>:$imm),
1710 (S_MOV_B32 fpimm:$imm)
1715 (V_MOV_B32_e32 imm:$imm)
1720 (V_MOV_B32_e32 fpimm:$imm)
1725 (S_MOV_B64 imm:$imm)
1729 (i64 InlineImm<i64>:$imm),
1730 (S_MOV_B64 InlineImm<i64>:$imm)
1733 // i64 immediates aren't supported in hardware, split it into two 32bit values
1736 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1737 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0),
1738 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1)
1743 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
1744 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0),
1745 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1)
1748 /********** ===================== **********/
1749 /********** Interpolation Paterns **********/
1750 /********** ===================== **********/
1753 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
1754 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
1758 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
1759 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
1760 imm:$attr_chan, imm:$attr, i32:$params),
1761 (EXTRACT_SUBREG $ij, sub1),
1762 imm:$attr_chan, imm:$attr, $params)
1765 /********** ================== **********/
1766 /********** Intrinsic Patterns **********/
1767 /********** ================== **********/
1769 /* llvm.AMDGPU.pow */
1770 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
1773 (int_AMDGPU_div f32:$src0, f32:$src1),
1774 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
1778 (fdiv f32:$src0, f32:$src1),
1779 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
1783 (fdiv f64:$src0, f64:$src1),
1784 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
1789 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1794 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1798 (int_AMDGPU_cube v4f32:$src),
1799 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
1800 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
1801 (EXTRACT_SUBREG $src, sub1),
1802 (EXTRACT_SUBREG $src, sub2)),
1804 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
1805 (EXTRACT_SUBREG $src, sub1),
1806 (EXTRACT_SUBREG $src, sub2)),
1808 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
1809 (EXTRACT_SUBREG $src, sub1),
1810 (EXTRACT_SUBREG $src, sub2)),
1812 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
1813 (EXTRACT_SUBREG $src, sub1),
1814 (EXTRACT_SUBREG $src, sub2)),
1819 (i32 (sext i1:$src0)),
1820 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
1824 (i32 (zext i1:$src0)),
1825 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
1828 // 1. Offset as 8bit DWORD immediate
1830 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset),
1831 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset)
1834 // 2. Offset loaded in an 32bit SGPR
1836 (SIload_constant i128:$sbase, imm:$offset),
1837 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1840 // 3. Offset in an 32Bit VGPR
1842 (SIload_constant i128:$sbase, i32:$voff),
1843 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
1846 // The multiplication scales from [0,1] to the unsigned integer range
1848 (AMDGPUurecip i32:$src0),
1850 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
1851 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
1856 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
1857 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0))
1860 /********** ================== **********/
1861 /********** VOP3 Patterns **********/
1862 /********** ================== **********/
1865 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)),
1866 (V_MAD_F32 $src0, $src1, $src2)
1869 /********** ======================= **********/
1870 /********** Load/Store Patterns **********/
1871 /********** ======================= **********/
1873 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
1875 (vt (inst 0, $src0, $src0, $src0, 0, 0))
1878 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
1879 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
1880 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
1881 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
1882 def : DSReadPat <DS_READ_B32, i32, local_load>;
1884 (local_load i32:$src0),
1885 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0))
1888 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
1889 (frag i32:$src1, i32:$src0),
1890 (inst 0, $src0, $src1, $src1, 0, 0)
1893 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
1894 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
1895 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
1897 def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
1898 (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>;
1900 def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val),
1901 (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>;
1903 /********** ================== **********/
1904 /********** SMRD Patterns **********/
1905 /********** ================== **********/
1907 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1909 // 1. Offset as 8bit DWORD immediate
1911 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)),
1912 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset))
1915 // 2. Offset loaded in an 32bit SGPR
1917 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)),
1918 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset)))
1921 // 3. No offset at all
1923 (constant_load i64:$sbase),
1924 (vt (Instr_IMM $sbase, 0))
1928 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1929 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1930 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1931 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1932 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>;
1933 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1934 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1935 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1936 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1938 //===----------------------------------------------------------------------===//
1940 //===----------------------------------------------------------------------===//
1942 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
1943 PatFrag global_ld, PatFrag constant_ld> {
1945 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
1946 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
1950 (vt (global_ld i64:$ptr)),
1951 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
1955 (vt (global_ld (add i64:$ptr, i64:$offset))),
1956 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
1960 (vt (constant_ld (add i64:$ptr, i64:$offset))),
1961 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
1965 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
1966 sextloadi8_global, sextloadi8_constant>;
1967 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
1968 az_extloadi8_global, az_extloadi8_constant>;
1969 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
1970 sextloadi16_global, sextloadi16_constant>;
1971 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
1972 az_extloadi16_global, az_extloadi16_constant>;
1973 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
1974 global_load, constant_load>;
1975 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
1976 global_load, constant_load>;
1977 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
1978 az_extloadi32_global, az_extloadi32_constant>;
1979 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
1980 global_load, constant_load>;
1981 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
1982 global_load, constant_load>;
1984 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
1987 (st vt:$value, i64:$ptr),
1988 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
1992 (st vt:$value, (add i64:$ptr, i64:$offset)),
1993 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
1997 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
1998 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
1999 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2000 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2001 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2002 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2004 // BUFFER_LOAD_DWORD*, addr64=0
2005 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2009 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
2010 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2012 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2013 (as_i1imm $slc), (as_i1imm $tfe))
2017 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
2018 imm, 1, 0, imm:$glc, imm:$slc,
2020 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2025 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
2026 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2028 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2029 (as_i1imm $slc), (as_i1imm $tfe))
2033 (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset,
2034 imm, 1, 1, imm:$glc, imm:$slc,
2036 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2041 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2042 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2043 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2044 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2045 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2046 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2048 //===----------------------------------------------------------------------===//
2050 //===----------------------------------------------------------------------===//
2052 // TBUFFER_STORE_FORMAT_*, addr64=0
2053 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2054 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2055 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2056 imm:$nfmt, imm:$offen, imm:$idxen,
2057 imm:$glc, imm:$slc, imm:$tfe),
2059 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2060 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2061 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2064 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2065 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2066 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2067 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2069 /********** ====================== **********/
2070 /********** Indirect adressing **********/
2071 /********** ====================== **********/
2073 multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> {
2075 // 1. Extract with offset
2077 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2078 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2081 // 2. Extract without offset
2083 (vector_extract vt:$vec, i32:$idx),
2084 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2087 // 3. Insert with offset
2089 (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)),
2090 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2093 // 4. Insert without offset
2095 (vector_insert vt:$vec, f32:$val, i32:$idx),
2096 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2100 defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>;
2101 defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>;
2102 defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>;
2103 defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>;
2105 /********** =============== **********/
2106 /********** Conditions **********/
2107 /********** =============== **********/
2110 (i1 (setcc f32:$src0, f32:$src1, SETO)),
2111 (V_CMP_O_F32_e64 $src0, $src1)
2115 (i1 (setcc f32:$src0, f32:$src1, SETUO)),
2116 (V_CMP_U_F32_e64 $src0, $src1)
2119 //===----------------------------------------------------------------------===//
2120 // Miscellaneous Patterns
2121 //===----------------------------------------------------------------------===//
2124 (i64 (trunc i128:$x)),
2125 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2126 (i32 (EXTRACT_SUBREG $x, sub0)), sub0),
2127 (i32 (EXTRACT_SUBREG $x, sub1)), sub1)
2131 (i32 (trunc i64:$a)),
2132 (EXTRACT_SUBREG $a, sub0)
2136 (i1 (trunc i32:$a)),
2137 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2140 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2141 // case, the sgpr-copies pass will fix this to use the vector version.
2143 (i32 (addc i32:$src0, i32:$src1)),
2144 (S_ADD_I32 $src0, $src1)
2148 (or i64:$a, i64:$b),
2150 (INSERT_SUBREG (IMPLICIT_DEF),
2151 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0),
2152 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1)
2155 //============================================================================//
2156 // Miscellaneous Optimization Patterns
2157 //============================================================================//
2159 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2161 } // End isSI predicate