1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86MCTARGETDESC_H
15 #define X86MCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
27 class MCSubtargetInfo;
28 class MCRelocationInfo;
33 extern Target TheX86_32Target, TheX86_64Target;
35 /// DWARFFlavour - Flavour of dwarf regnumbers
37 namespace DWARFFlavour {
39 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
43 /// N86 namespace - Native X86 register numbers
47 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
52 std::string ParseX86Triple(StringRef TT);
54 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
55 /// the specified arguments. If we can't run cpuid on the host, return true.
56 bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
57 unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
58 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
59 /// the 4 values in the specified arguments. If we can't run cpuid on the
60 /// host, return true.
61 bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
62 unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
64 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
66 unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
68 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
70 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
71 /// This is exposed so Asm parser, etc. do not need to go through
73 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
77 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
78 const MCRegisterInfo &MRI,
79 const MCSubtargetInfo &STI,
82 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
83 StringRef TT, StringRef CPU);
84 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
85 StringRef TT, StringRef CPU);
87 /// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
88 MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
93 /// createX86ELFObjectWriter - Construct an X86 ELF object writer.
94 MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS,
98 /// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer.
99 MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
101 /// createX86_64MachORelocationInfo - Construct X86-64 Mach-O relocation info.
102 MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx);
104 /// createX86_64ELFORelocationInfo - Construct X86-64 ELF relocation info.
105 MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx);
106 } // End llvm namespace
109 // Defines symbolic names for X86 registers. This defines a mapping from
110 // register name to register number.
112 #define GET_REGINFO_ENUM
113 #include "X86GenRegisterInfo.inc"
115 // Defines symbolic names for the X86 instructions.
117 #define GET_INSTRINFO_ENUM
118 #include "X86GenInstrInfo.inc"
120 #define GET_SUBTARGETINFO_ENUM
121 #include "X86GenSubtargetInfo.inc"