1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
46 def MRM_D4 : Format<47>;
47 def MRM_D8 : Format<48>;
48 def MRM_D9 : Format<49>;
49 def MRM_DA : Format<50>;
50 def MRM_DB : Format<51>;
51 def MRM_DC : Format<52>;
52 def MRM_DD : Format<53>;
53 def MRM_DE : Format<54>;
54 def MRM_DF : Format<55>;
56 // ImmType - This specifies the immediate type used by an instruction. This is
57 // part of the ad-hoc solution used to emit machine instruction encodings by our
58 // machine code emitter.
59 class ImmType<bits<3> val> {
62 def NoImm : ImmType<0>;
63 def Imm8 : ImmType<1>;
64 def Imm8PCRel : ImmType<2>;
65 def Imm16 : ImmType<3>;
66 def Imm16PCRel : ImmType<4>;
67 def Imm32 : ImmType<5>;
68 def Imm32PCRel : ImmType<6>;
69 def Imm64 : ImmType<7>;
71 // FPFormat - This specifies what form this FP instruction has. This is used by
72 // the Floating-Point stackifier pass.
73 class FPFormat<bits<3> val> {
76 def NotFP : FPFormat<0>;
77 def ZeroArgFP : FPFormat<1>;
78 def OneArgFP : FPFormat<2>;
79 def OneArgFPRW : FPFormat<3>;
80 def TwoArgFP : FPFormat<4>;
81 def CompareFP : FPFormat<5>;
82 def CondMovFP : FPFormat<6>;
83 def SpecialFP : FPFormat<7>;
85 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
86 // Keep in sync with tables in X86InstrInfo.cpp.
87 class Domain<bits<2> val> {
90 def GenericDomain : Domain<0>;
91 def SSEPackedSingle : Domain<1>;
92 def SSEPackedDouble : Domain<2>;
93 def SSEPackedInt : Domain<3>;
95 // Prefix byte classes which are used to indicate to the ad-hoc machine code
96 // emitter that various prefix bytes are required.
97 class OpSize { bit hasOpSizePrefix = 1; }
98 class AdSize { bit hasAdSizePrefix = 1; }
99 class REX_W { bit hasREX_WPrefix = 1; }
100 class LOCK { bit hasLockPrefix = 1; }
101 class SegFS { bits<2> SegOvrBits = 1; }
102 class SegGS { bits<2> SegOvrBits = 2; }
103 class TB { bits<5> Prefix = 1; }
104 class REP { bits<5> Prefix = 2; }
105 class D8 { bits<5> Prefix = 3; }
106 class D9 { bits<5> Prefix = 4; }
107 class DA { bits<5> Prefix = 5; }
108 class DB { bits<5> Prefix = 6; }
109 class DC { bits<5> Prefix = 7; }
110 class DD { bits<5> Prefix = 8; }
111 class DE { bits<5> Prefix = 9; }
112 class DF { bits<5> Prefix = 10; }
113 class XD { bits<5> Prefix = 11; }
114 class XS { bits<5> Prefix = 12; }
115 class T8 { bits<5> Prefix = 13; }
116 class TA { bits<5> Prefix = 14; }
117 class A6 { bits<5> Prefix = 15; }
118 class A7 { bits<5> Prefix = 16; }
119 class T8XD { bits<5> Prefix = 17; }
120 class T8XS { bits<5> Prefix = 18; }
121 class TAXD { bits<5> Prefix = 19; }
122 class XOP8 { bits<5> Prefix = 20; }
123 class XOP9 { bits<5> Prefix = 21; }
124 class VEX { bit hasVEXPrefix = 1; }
125 class VEX_W { bit hasVEX_WPrefix = 1; }
126 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
127 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
128 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
129 class VEX_L { bit hasVEX_L = 1; }
130 class VEX_LIG { bit ignoresVEX_L = 1; }
131 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
132 class MemOp4 { bit hasMemOp4Prefix = 1; }
133 class XOP { bit hasXOP_Prefix = 1; }
134 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
137 Domain d = GenericDomain>
139 let Namespace = "X86";
141 bits<8> Opcode = opcod;
143 bits<6> FormBits = Form.Value;
146 dag OutOperandList = outs;
147 dag InOperandList = ins;
148 string AsmString = AsmStr;
150 // If this is a pseudo instruction, mark it isCodeGenOnly.
151 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
153 let Itinerary = itin;
156 // Attributes specific to X86 instructions...
158 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
159 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
161 bits<5> Prefix = 0; // Which prefix byte does this inst have?
162 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
163 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
164 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
165 bits<2> SegOvrBits = 0; // Segment override prefix.
166 Domain ExeDomain = d;
167 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
168 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
169 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
170 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
171 // encode the third operand?
172 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
173 // to be encoded in a immediate field?
174 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
175 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
176 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
177 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
178 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
180 // TSFlags layout should be kept in sync with X86InstrInfo.h.
181 let TSFlags{5-0} = FormBits;
182 let TSFlags{6} = hasOpSizePrefix;
183 let TSFlags{7} = hasAdSizePrefix;
184 let TSFlags{12-8} = Prefix;
185 let TSFlags{13} = hasREX_WPrefix;
186 let TSFlags{16-14} = ImmT.Value;
187 let TSFlags{19-17} = FPForm.Value;
188 let TSFlags{20} = hasLockPrefix;
189 let TSFlags{22-21} = SegOvrBits;
190 let TSFlags{24-23} = ExeDomain.Value;
191 let TSFlags{32-25} = Opcode;
192 let TSFlags{33} = hasVEXPrefix;
193 let TSFlags{34} = hasVEX_WPrefix;
194 let TSFlags{35} = hasVEX_4VPrefix;
195 let TSFlags{36} = hasVEX_4VOp3Prefix;
196 let TSFlags{37} = hasVEX_i8ImmReg;
197 let TSFlags{38} = hasVEX_L;
198 let TSFlags{39} = ignoresVEX_L;
199 let TSFlags{40} = has3DNow0F0FOpcode;
200 let TSFlags{41} = hasMemOp4Prefix;
201 let TSFlags{42} = hasXOP_Prefix;
204 class PseudoI<dag oops, dag iops, list<dag> pattern>
205 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
206 let Pattern = pattern;
209 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
210 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
211 Domain d = GenericDomain>
212 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
213 let Pattern = pattern;
216 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
217 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
218 Domain d = GenericDomain>
219 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
220 let Pattern = pattern;
223 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
224 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
225 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
226 let Pattern = pattern;
229 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
230 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
231 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
232 let Pattern = pattern;
235 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
236 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
237 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
238 let Pattern = pattern;
242 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
243 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
244 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
245 let Pattern = pattern;
249 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
250 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
251 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
252 let Pattern = pattern;
256 // FPStack Instruction Templates:
257 // FPI - Floating Point Instruction template.
258 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
259 : I<o, F, outs, ins, asm, []> {}
261 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
262 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
263 InstrItinClass itin = IIC_DEFAULT>
264 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
266 let Pattern = pattern;
269 // Templates for instructions that use a 16- or 32-bit segmented address as
270 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
272 // Iseg16 - 16-bit segment selector, 16-bit offset
273 // Iseg32 - 16-bit segment selector, 32-bit offset
275 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
276 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
277 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
278 let Pattern = pattern;
282 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
283 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
284 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
285 let Pattern = pattern;
289 // SI - SSE 1 & 2 scalar instructions
290 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
291 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
292 : I<o, F, outs, ins, asm, pattern, itin> {
293 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
294 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
296 // AVX instructions have a 'v' prefix in the mnemonic
297 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
300 // SIi8 - SSE 1 & 2 scalar instructions
301 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
302 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
303 : Ii8<o, F, outs, ins, asm, pattern, itin> {
304 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
305 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
307 // AVX instructions have a 'v' prefix in the mnemonic
308 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
311 // PI - SSE 1 & 2 packed instructions
312 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
313 InstrItinClass itin, Domain d>
314 : I<o, F, outs, ins, asm, pattern, itin, d> {
315 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
316 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
318 // AVX instructions have a 'v' prefix in the mnemonic
319 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
322 // PIi8 - SSE 1 & 2 packed instructions with immediate
323 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
324 list<dag> pattern, InstrItinClass itin, Domain d>
325 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
326 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
327 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
329 // AVX instructions have a 'v' prefix in the mnemonic
330 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
333 // SSE1 Instruction Templates:
335 // SSI - SSE1 instructions with XS prefix.
336 // PSI - SSE1 instructions with TB prefix.
337 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
338 // VSSI - SSE1 instructions with XS prefix in AVX form.
339 // VPSI - SSE1 instructions with TB prefix in AVX form.
341 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
342 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
343 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE1]>;
344 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
345 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
346 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE1]>;
347 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
348 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
349 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
351 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
352 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
353 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
355 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
356 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
357 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
359 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
360 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
361 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
364 // SSE2 Instruction Templates:
366 // SDI - SSE2 instructions with XD prefix.
367 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
368 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
369 // PDI - SSE2 instructions with TB and OpSize prefixes.
370 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
371 // VSDI - SSE2 instructions with XD prefix in AVX form.
372 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
374 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
375 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
376 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
377 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
378 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
379 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
380 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
382 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
383 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
384 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
385 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
387 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
388 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
389 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
391 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
392 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
393 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
395 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
396 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
397 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
398 OpSize, Requires<[HasAVX]>;
400 // SSE3 Instruction Templates:
402 // S3I - SSE3 instructions with TB and OpSize prefixes.
403 // S3SI - SSE3 instructions with XS prefix.
404 // S3DI - SSE3 instructions with XD prefix.
406 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
407 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
408 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
410 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
411 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
412 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
414 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
415 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
416 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
420 // SSSE3 Instruction Templates:
422 // SS38I - SSSE3 instructions with T8 prefix.
423 // SS3AI - SSSE3 instructions with TA prefix.
425 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
426 // uses the MMX registers. The 64-bit versions are grouped with the MMX
427 // classes. They need to be enabled even if AVX is enabled.
429 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
430 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
431 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
432 Requires<[HasSSSE3]>;
433 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
434 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
435 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
436 Requires<[HasSSSE3]>;
438 // SSE4.1 Instruction Templates:
440 // SS48I - SSE 4.1 instructions with T8 prefix.
441 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
443 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
444 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
445 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
446 Requires<[HasSSE41]>;
447 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
448 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
449 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
450 Requires<[HasSSE41]>;
452 // SSE4.2 Instruction Templates:
454 // SS428I - SSE 4.2 instructions with T8 prefix.
455 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
456 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
457 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
458 Requires<[HasSSE42]>;
460 // SS42FI - SSE 4.2 instructions with T8XD prefix.
461 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
462 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
463 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
465 // SS42AI = SSE 4.2 instructions with TA prefix
466 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
467 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
468 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
469 Requires<[HasSSE42]>;
471 // AVX Instruction Templates:
472 // Instructions introduced in AVX (no SSE equivalent forms)
474 // AVX8I - AVX instructions with T8 and OpSize prefix.
475 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
476 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
477 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
478 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
480 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
481 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
482 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
485 // AVX2 Instruction Templates:
486 // Instructions introduced in AVX2 (no SSE equivalent forms)
488 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
489 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
490 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
491 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
492 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
494 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
495 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
496 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
499 // AES Instruction Templates:
502 // These use the same encoding as the SSE4.2 T8 and TA encodings.
503 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
504 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
505 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
506 Requires<[HasSSE2, HasAES]>;
508 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
509 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
510 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
511 Requires<[HasSSE2, HasAES]>;
513 // CLMUL Instruction Templates
514 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
515 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
516 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
517 OpSize, Requires<[HasSSE2, HasCLMUL]>;
519 class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
520 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
521 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
522 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
524 // FMA3 Instruction Templates
525 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
526 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
527 : I<o, F, outs, ins, asm, pattern, itin>, T8,
528 OpSize, VEX_4V, Requires<[HasFMA3]>;
530 // FMA4 Instruction Templates
531 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
532 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
533 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
534 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
536 // XOP 2, 3 and 4 Operand Instruction Template
537 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
538 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
539 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
540 XOP, XOP9, Requires<[HasXOP]>;
542 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
543 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
544 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
545 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
546 XOP, XOP8, Requires<[HasXOP]>;
548 // XOP 5 operand instruction (VEX encoding!)
549 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
550 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
551 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
552 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
554 // X86-64 Instruction templates...
557 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
558 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
559 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
560 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
561 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
562 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
563 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
564 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
565 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
567 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
568 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
569 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
570 let Pattern = pattern;
574 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
575 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
576 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
577 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
578 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
579 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
580 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
581 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
582 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
583 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
584 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
585 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
587 // MMX Instruction templates
590 // MMXI - MMX instructions with TB prefix.
591 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
592 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
593 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
594 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
595 // MMXID - MMX instructions with XD prefix.
596 // MMXIS - MMX instructions with XS prefix.
597 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
598 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
599 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
600 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
601 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
602 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
603 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
604 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
605 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
606 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
607 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
608 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
609 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
610 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
611 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
612 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
613 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
614 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
615 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
616 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
617 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;