1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file is part of the XCore Disassembler.
13 //===----------------------------------------------------------------------===//
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/MemoryObject.h"
22 #include "llvm/Support/TargetRegistry.h"
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
30 /// \brief A disassembler class for XCore.
31 class XCoreDisassembler : public MCDisassembler {
32 OwningPtr<const MCRegisterInfo> RegInfo;
34 XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
35 MCDisassembler(STI), RegInfo(Info) {}
37 /// \brief See MCDisassembler.
38 virtual DecodeStatus getInstruction(MCInst &instr,
40 const MemoryObject ®ion,
43 raw_ostream &cStream) const;
45 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
49 static bool readInstruction16(const MemoryObject ®ion,
55 // We want to read exactly 2 Bytes of data.
56 if (region.readBytes(address, 2, Bytes) == -1) {
60 // Encoded as a little-endian 16-bit word in the stream.
61 insn = (Bytes[0] << 0) | (Bytes[1] << 8);
65 static bool readInstruction32(const MemoryObject ®ion,
71 // We want to read exactly 4 Bytes of data.
72 if (region.readBytes(address, 4, Bytes) == -1) {
76 // Encoded as a little-endian 32-bit word in the stream.
77 insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
83 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
84 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
97 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
98 uint64_t Address, const void *Decoder);
100 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
101 uint64_t Address, const void *Decoder);
103 static DecodeStatus Decode2RInstruction(MCInst &Inst,
106 const void *Decoder);
108 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
111 const void *Decoder);
113 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
116 const void *Decoder);
118 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
121 const void *Decoder);
123 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
126 const void *Decoder);
128 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
131 const void *Decoder);
133 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
136 const void *Decoder);
138 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
141 const void *Decoder);
143 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
146 const void *Decoder);
148 static DecodeStatus Decode3RInstruction(MCInst &Inst,
151 const void *Decoder);
153 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
156 const void *Decoder);
158 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
161 const void *Decoder);
163 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
166 const void *Decoder);
168 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
171 const void *Decoder);
173 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
176 const void *Decoder);
178 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
181 const void *Decoder);
183 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
186 const void *Decoder);
188 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
191 const void *Decoder);
193 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
196 const void *Decoder);
198 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
201 const void *Decoder);
203 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
206 const void *Decoder);
208 #include "XCoreGenDisassemblerTables.inc"
210 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
216 return MCDisassembler::Fail;
217 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
218 Inst.addOperand(MCOperand::CreateReg(Reg));
219 return MCDisassembler::Success;
222 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
228 return MCDisassembler::Fail;
229 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
230 Inst.addOperand(MCOperand::CreateReg(Reg));
231 return MCDisassembler::Success;
234 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder) {
237 return MCDisassembler::Fail;
238 static unsigned Values[] = {
239 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
241 Inst.addOperand(MCOperand::CreateImm(Values[Val]));
242 return MCDisassembler::Success;
245 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder) {
247 Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
248 return MCDisassembler::Success;
252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
253 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
255 return MCDisassembler::Fail;
256 if (fieldFromInstruction(Insn, 5, 1)) {
258 return MCDisassembler::Fail;
262 unsigned Op1High = Combined % 3;
263 unsigned Op2High = Combined / 3;
264 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
265 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
266 return MCDisassembler::Success;
270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
272 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
274 return MCDisassembler::Fail;
276 unsigned Op1High = Combined % 3;
277 unsigned Op2High = (Combined / 3) % 3;
278 unsigned Op3High = Combined / 9;
279 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
280 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
281 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
282 return MCDisassembler::Success;
286 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
287 const void *Decoder) {
288 // Try and decode as a 3R instruction.
289 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
292 Inst.setOpcode(XCore::STW_2rus);
293 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
295 Inst.setOpcode(XCore::LDW_2rus);
296 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
298 Inst.setOpcode(XCore::ADD_3r);
299 return Decode3RInstruction(Inst, Insn, Address, Decoder);
301 Inst.setOpcode(XCore::SUB_3r);
302 return Decode3RInstruction(Inst, Insn, Address, Decoder);
304 Inst.setOpcode(XCore::SHL_3r);
305 return Decode3RInstruction(Inst, Insn, Address, Decoder);
307 Inst.setOpcode(XCore::SHR_3r);
308 return Decode3RInstruction(Inst, Insn, Address, Decoder);
310 Inst.setOpcode(XCore::EQ_3r);
311 return Decode3RInstruction(Inst, Insn, Address, Decoder);
313 Inst.setOpcode(XCore::AND_3r);
314 return Decode3RInstruction(Inst, Insn, Address, Decoder);
316 Inst.setOpcode(XCore::OR_3r);
317 return Decode3RInstruction(Inst, Insn, Address, Decoder);
319 Inst.setOpcode(XCore::LDW_3r);
320 return Decode3RInstruction(Inst, Insn, Address, Decoder);
322 Inst.setOpcode(XCore::LD16S_3r);
323 return Decode3RInstruction(Inst, Insn, Address, Decoder);
325 Inst.setOpcode(XCore::LD8U_3r);
326 return Decode3RInstruction(Inst, Insn, Address, Decoder);
328 Inst.setOpcode(XCore::ADD_2rus);
329 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
331 Inst.setOpcode(XCore::SUB_2rus);
332 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
334 Inst.setOpcode(XCore::SHL_2rus);
335 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
337 Inst.setOpcode(XCore::SHR_2rus);
338 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
340 Inst.setOpcode(XCore::EQ_2rus);
341 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
343 Inst.setOpcode(XCore::TSETR_3r);
344 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
346 Inst.setOpcode(XCore::LSS_3r);
347 return Decode3RInstruction(Inst, Insn, Address, Decoder);
349 Inst.setOpcode(XCore::LSU_3r);
350 return Decode3RInstruction(Inst, Insn, Address, Decoder);
352 return MCDisassembler::Fail;
356 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
357 const void *Decoder) {
359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
360 if (S != MCDisassembler::Success)
361 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
363 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
364 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
369 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
370 const void *Decoder) {
372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
373 if (S != MCDisassembler::Success)
374 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
376 Inst.addOperand(MCOperand::CreateImm(Op1));
377 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
382 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
383 const void *Decoder) {
385 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
386 if (S != MCDisassembler::Success)
387 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
389 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
390 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
395 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
396 const void *Decoder) {
398 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
399 if (S != MCDisassembler::Success)
400 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
402 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
403 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
404 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
409 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
410 const void *Decoder) {
412 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
413 if (S != MCDisassembler::Success)
414 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
416 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
417 Inst.addOperand(MCOperand::CreateImm(Op2));
422 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
423 const void *Decoder) {
425 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
426 if (S != MCDisassembler::Success)
427 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
429 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
430 DecodeBitpOperand(Inst, Op2, Address, Decoder);
435 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
436 const void *Decoder) {
438 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
439 if (S != MCDisassembler::Success)
440 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
442 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
443 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
444 DecodeBitpOperand(Inst, Op2, Address, Decoder);
449 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
450 const void *Decoder) {
451 // Try and decode as a L3R / L2RUS instruction.
452 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
453 fieldFromInstruction(Insn, 27, 5) << 4;
456 Inst.setOpcode(XCore::STW_l3r);
457 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
459 Inst.setOpcode(XCore::XOR_l3r);
460 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
462 Inst.setOpcode(XCore::ASHR_l3r);
463 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
465 Inst.setOpcode(XCore::LDAWF_l3r);
466 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
468 Inst.setOpcode(XCore::LDAWB_l3r);
469 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
471 Inst.setOpcode(XCore::LDA16F_l3r);
472 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
474 Inst.setOpcode(XCore::LDA16B_l3r);
475 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
477 Inst.setOpcode(XCore::MUL_l3r);
478 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
480 Inst.setOpcode(XCore::DIVS_l3r);
481 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
483 Inst.setOpcode(XCore::DIVU_l3r);
484 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
486 Inst.setOpcode(XCore::ST16_l3r);
487 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
489 Inst.setOpcode(XCore::ST8_l3r);
490 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
492 Inst.setOpcode(XCore::ASHR_l2rus);
493 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
495 Inst.setOpcode(XCore::OUTPW_l2rus);
496 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
498 Inst.setOpcode(XCore::INPW_l2rus);
499 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
501 Inst.setOpcode(XCore::LDAWF_l2rus);
502 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
504 Inst.setOpcode(XCore::LDAWB_l2rus);
505 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
507 Inst.setOpcode(XCore::CRC_l3r);
508 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
510 Inst.setOpcode(XCore::REMS_l3r);
511 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
513 Inst.setOpcode(XCore::REMU_l3r);
514 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
516 return MCDisassembler::Fail;
520 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
521 const void *Decoder) {
523 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
525 if (S != MCDisassembler::Success)
526 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
528 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
529 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
534 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
535 const void *Decoder) {
537 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
539 if (S != MCDisassembler::Success)
540 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
542 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
543 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
548 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
549 const void *Decoder) {
550 unsigned Op1, Op2, Op3;
551 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
552 if (S == MCDisassembler::Success) {
553 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
554 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
555 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
561 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
562 const void *Decoder) {
563 unsigned Op1, Op2, Op3;
564 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
565 if (S == MCDisassembler::Success) {
566 Inst.addOperand(MCOperand::CreateImm(Op1));
567 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
568 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
574 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
575 const void *Decoder) {
576 unsigned Op1, Op2, Op3;
577 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
578 if (S == MCDisassembler::Success) {
579 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
580 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
581 Inst.addOperand(MCOperand::CreateImm(Op3));
587 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
588 const void *Decoder) {
589 unsigned Op1, Op2, Op3;
590 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
591 if (S == MCDisassembler::Success) {
592 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
593 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
594 DecodeBitpOperand(Inst, Op3, Address, Decoder);
600 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
601 const void *Decoder) {
602 unsigned Op1, Op2, Op3;
604 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
605 if (S == MCDisassembler::Success) {
606 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
607 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
608 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
614 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
615 const void *Decoder) {
616 unsigned Op1, Op2, Op3;
618 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
619 if (S == MCDisassembler::Success) {
620 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
621 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
622 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
623 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
629 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
630 const void *Decoder) {
631 unsigned Op1, Op2, Op3;
633 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
634 if (S == MCDisassembler::Success) {
635 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
636 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
637 Inst.addOperand(MCOperand::CreateImm(Op3));
643 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
644 const void *Decoder) {
645 unsigned Op1, Op2, Op3;
647 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
648 if (S == MCDisassembler::Success) {
649 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
650 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
651 DecodeBitpOperand(Inst, Op3, Address, Decoder);
657 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
658 const void *Decoder) {
659 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
661 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
662 if (S != MCDisassembler::Success)
664 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
665 if (S != MCDisassembler::Success)
667 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
668 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
669 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
670 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
671 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
672 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
677 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
678 const void *Decoder) {
679 // Try and decode as a L6R instruction.
681 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
684 Inst.setOpcode(XCore::LMUL_l6r);
685 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
687 return MCDisassembler::Fail;
691 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
692 const void *Decoder) {
693 unsigned Op1, Op2, Op3, Op4, Op5;
695 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
696 if (S != MCDisassembler::Success)
697 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
698 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
699 if (S != MCDisassembler::Success)
700 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
702 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
703 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
704 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
705 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
706 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
711 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
712 const void *Decoder) {
713 unsigned Op1, Op2, Op3;
714 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
716 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
717 if (S == MCDisassembler::Success) {
718 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
719 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
721 if (S == MCDisassembler::Success) {
722 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
723 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
724 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
730 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
731 const void *Decoder) {
732 unsigned Op1, Op2, Op3;
733 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
735 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
736 if (S == MCDisassembler::Success) {
737 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
738 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
740 if (S == MCDisassembler::Success) {
741 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
742 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
743 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
744 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
749 MCDisassembler::DecodeStatus
750 XCoreDisassembler::getInstruction(MCInst &instr,
752 const MemoryObject &Region,
754 raw_ostream &vStream,
755 raw_ostream &cStream) const {
758 if (!readInstruction16(Region, Address, Size, insn16)) {
762 // Calling the auto-generated decoder function.
763 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
765 if (Result != Fail) {
772 if (!readInstruction32(Region, Address, Size, insn32)) {
776 // Calling the auto-generated decoder function.
777 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
778 if (Result != Fail) {
787 extern Target TheXCoreTarget;
790 static MCDisassembler *createXCoreDisassembler(const Target &T,
791 const MCSubtargetInfo &STI) {
792 return new XCoreDisassembler(STI, T.createMCRegInfo(""));
795 extern "C" void LLVMInitializeXCoreDisassembler() {
796 // Register the disassembler.
797 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
798 createXCoreDisassembler);