1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreInstrInfo.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
25 #define GET_INSTRINFO_CTOR_DTOR
26 #include "XCoreGenInstrInfo.inc"
31 // XCore Condition Codes
43 // Pin the vtable to this file.
44 void XCoreInstrInfo::anchor() {}
46 XCoreInstrInfo::XCoreInstrInfo()
47 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
51 static bool isZeroImm(const MachineOperand &op) {
52 return op.isImm() && op.getImm() == 0;
55 /// isLoadFromStackSlot - If the specified machine instruction is a direct
56 /// load from a stack slot, return the virtual or physical register number of
57 /// the destination along with the FrameIndex of the loaded stack slot. If
58 /// not, return 0. This predicate must return 0 if the instruction has
59 /// any side effects other than loading from the stack slot.
61 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
62 int Opcode = MI->getOpcode();
63 if (Opcode == XCore::LDWFI)
65 if ((MI->getOperand(1).isFI()) && // is a stack slot
66 (MI->getOperand(2).isImm()) && // the imm is zero
67 (isZeroImm(MI->getOperand(2))))
69 FrameIndex = MI->getOperand(1).getIndex();
70 return MI->getOperand(0).getReg();
76 /// isStoreToStackSlot - If the specified machine instruction is a direct
77 /// store to a stack slot, return the virtual or physical register number of
78 /// the source reg along with the FrameIndex of the loaded stack slot. If
79 /// not, return 0. This predicate must return 0 if the instruction has
80 /// any side effects other than storing to the stack slot.
82 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
83 int &FrameIndex) const {
84 int Opcode = MI->getOpcode();
85 if (Opcode == XCore::STWFI)
87 if ((MI->getOperand(1).isFI()) && // is a stack slot
88 (MI->getOperand(2).isImm()) && // the imm is zero
89 (isZeroImm(MI->getOperand(2))))
91 FrameIndex = MI->getOperand(1).getIndex();
92 return MI->getOperand(0).getReg();
98 //===----------------------------------------------------------------------===//
100 //===----------------------------------------------------------------------===//
102 static inline bool IsBRU(unsigned BrOpc) {
103 return BrOpc == XCore::BRFU_u6
104 || BrOpc == XCore::BRFU_lu6
105 || BrOpc == XCore::BRBU_u6
106 || BrOpc == XCore::BRBU_lu6;
109 static inline bool IsBRT(unsigned BrOpc) {
110 return BrOpc == XCore::BRFT_ru6
111 || BrOpc == XCore::BRFT_lru6
112 || BrOpc == XCore::BRBT_ru6
113 || BrOpc == XCore::BRBT_lru6;
116 static inline bool IsBRF(unsigned BrOpc) {
117 return BrOpc == XCore::BRFF_ru6
118 || BrOpc == XCore::BRFF_lru6
119 || BrOpc == XCore::BRBF_ru6
120 || BrOpc == XCore::BRBF_lru6;
123 static inline bool IsCondBranch(unsigned BrOpc) {
124 return IsBRF(BrOpc) || IsBRT(BrOpc);
127 static inline bool IsBR_JT(unsigned BrOpc) {
128 return BrOpc == XCore::BR_JT
129 || BrOpc == XCore::BR_JT32;
132 /// GetCondFromBranchOpc - Return the XCore CC that matches
133 /// the correspondent Branch instruction opcode.
134 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
137 return XCore::COND_TRUE;
138 } else if (IsBRF(BrOpc)) {
139 return XCore::COND_FALSE;
141 return XCore::COND_INVALID;
145 /// GetCondBranchFromCond - Return the Branch instruction
146 /// opcode that matches the cc.
147 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
150 default: llvm_unreachable("Illegal condition code!");
151 case XCore::COND_TRUE : return XCore::BRFT_lru6;
152 case XCore::COND_FALSE : return XCore::BRFF_lru6;
156 /// GetOppositeBranchCondition - Return the inverse of the specified
157 /// condition, e.g. turning COND_E to COND_NE.
158 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
161 default: llvm_unreachable("Illegal condition code!");
162 case XCore::COND_TRUE : return XCore::COND_FALSE;
163 case XCore::COND_FALSE : return XCore::COND_TRUE;
167 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
168 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
169 /// implemented for a target). Upon success, this returns false and returns
170 /// with the following information in various cases:
172 /// 1. If this block ends with no branches (it just falls through to its succ)
173 /// just return false, leaving TBB/FBB null.
174 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
175 /// the destination block.
176 /// 3. If this block ends with an conditional branch and it falls through to
177 /// an successor block, it sets TBB to be the branch destination block and a
178 /// list of operands that evaluate the condition. These
179 /// operands can be passed to other TargetInstrInfo methods to create new
181 /// 4. If this block ends with an conditional branch and an unconditional
182 /// block, it returns the 'true' destination in TBB, the 'false' destination
183 /// in FBB, and a list of operands that evaluate the condition. These
184 /// operands can be passed to other TargetInstrInfo methods to create new
187 /// Note that RemoveBranch and InsertBranch must be implemented to support
188 /// cases where this method returns success.
191 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
192 MachineBasicBlock *&FBB,
193 SmallVectorImpl<MachineOperand> &Cond,
194 bool AllowModify) const {
195 // If the block has no terminators, it just falls into the block after it.
196 MachineBasicBlock::iterator I = MBB.end();
197 if (I == MBB.begin())
200 while (I->isDebugValue()) {
201 if (I == MBB.begin())
205 if (!isUnpredicatedTerminator(I))
208 // Get the last instruction in the block.
209 MachineInstr *LastInst = I;
211 // If there is only one terminator instruction, process it.
212 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
213 if (IsBRU(LastInst->getOpcode())) {
214 TBB = LastInst->getOperand(0).getMBB();
218 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
219 if (BranchCode == XCore::COND_INVALID)
220 return true; // Can't handle indirect branch.
222 // Conditional branch
223 // Block ends with fall-through condbranch.
225 TBB = LastInst->getOperand(1).getMBB();
226 Cond.push_back(MachineOperand::CreateImm(BranchCode));
227 Cond.push_back(LastInst->getOperand(0));
231 // Get the instruction before it if it's a terminator.
232 MachineInstr *SecondLastInst = I;
234 // If there are three terminators, we don't know what sort of block this is.
235 if (SecondLastInst && I != MBB.begin() &&
236 isUnpredicatedTerminator(--I))
239 unsigned SecondLastOpc = SecondLastInst->getOpcode();
240 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
242 // If the block ends with conditional branch followed by unconditional,
244 if (BranchCode != XCore::COND_INVALID
245 && IsBRU(LastInst->getOpcode())) {
247 TBB = SecondLastInst->getOperand(1).getMBB();
248 Cond.push_back(MachineOperand::CreateImm(BranchCode));
249 Cond.push_back(SecondLastInst->getOperand(0));
251 FBB = LastInst->getOperand(0).getMBB();
255 // If the block ends with two unconditional branches, handle it. The second
256 // one is not executed, so remove it.
257 if (IsBRU(SecondLastInst->getOpcode()) &&
258 IsBRU(LastInst->getOpcode())) {
259 TBB = SecondLastInst->getOperand(0).getMBB();
262 I->eraseFromParent();
266 // Likewise if it ends with a branch table followed by an unconditional branch.
267 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
270 I->eraseFromParent();
274 // Otherwise, can't handle this.
279 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
280 MachineBasicBlock *FBB,
281 const SmallVectorImpl<MachineOperand> &Cond,
283 // Shouldn't be a fall through.
284 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
285 assert((Cond.size() == 2 || Cond.size() == 0) &&
286 "Unexpected number of components!");
288 if (FBB == 0) { // One way branch.
290 // Unconditional branch
291 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
293 // Conditional branch.
294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
295 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
301 // Two-way Conditional branch.
302 assert(Cond.size() == 2 && "Unexpected number of components!");
303 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
304 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
306 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
311 XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
312 MachineBasicBlock::iterator I = MBB.end();
313 if (I == MBB.begin()) return 0;
315 while (I->isDebugValue()) {
316 if (I == MBB.begin())
320 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
323 // Remove the branch.
324 I->eraseFromParent();
328 if (I == MBB.begin()) return 1;
330 if (!IsCondBranch(I->getOpcode()))
333 // Remove the branch.
334 I->eraseFromParent();
338 void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
339 MachineBasicBlock::iterator I, DebugLoc DL,
340 unsigned DestReg, unsigned SrcReg,
341 bool KillSrc) const {
342 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
343 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
345 if (GRDest && GRSrc) {
346 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
347 .addReg(SrcReg, getKillRegState(KillSrc))
352 if (GRDest && SrcReg == XCore::SP) {
353 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
357 if (DestReg == XCore::SP && GRSrc) {
358 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
359 .addReg(SrcReg, getKillRegState(KillSrc));
362 llvm_unreachable("Impossible reg-to-reg copy");
365 void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
366 MachineBasicBlock::iterator I,
367 unsigned SrcReg, bool isKill,
369 const TargetRegisterClass *RC,
370 const TargetRegisterInfo *TRI) const
373 if (I != MBB.end()) DL = I->getDebugLoc();
374 BuildMI(MBB, I, DL, get(XCore::STWFI))
375 .addReg(SrcReg, getKillRegState(isKill))
376 .addFrameIndex(FrameIndex)
380 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator I,
382 unsigned DestReg, int FrameIndex,
383 const TargetRegisterClass *RC,
384 const TargetRegisterInfo *TRI) const
387 if (I != MBB.end()) DL = I->getDebugLoc();
388 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
389 .addFrameIndex(FrameIndex)
393 /// ReverseBranchCondition - Return the inverse opcode of the
394 /// specified Branch instruction.
395 bool XCoreInstrInfo::
396 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
397 assert((Cond.size() == 2) &&
398 "Invalid XCore branch condition!");
399 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));