1 Pull in r198149 from upstream llvm trunk (by Venkatraman Govindaraju):
3 [SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
4 This makes the sparc backend to generate Sparc64 ABI compliant code.
6 Introduced here: http://svn.freebsd.org/changeset/base/262261
8 Index: lib/Target/Sparc/SparcISelLowering.cpp
9 ===================================================================
10 --- lib/Target/Sparc/SparcISelLowering.cpp
11 +++ lib/Target/Sparc/SparcISelLowering.cpp
12 @@ -1252,6 +1252,12 @@ SparcTargetLowering::LowerCall_64(TargetLowering::
13 SmallVector<CCValAssign, 16> RVLocs;
14 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
15 DAG.getTarget(), RVLocs, *DAG.getContext());
17 + // Set inreg flag manually for codegen generated library calls that
19 + if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0)
20 + CLI.Ins[0].Flags.setInReg();
22 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
24 // Copy all of the result registers out of their specified physreg.
25 Index: test/CodeGen/SPARC/64abi.ll
26 ===================================================================
27 --- test/CodeGen/SPARC/64abi.ll
28 +++ test/CodeGen/SPARC/64abi.ll
29 @@ -440,4 +440,25 @@ entry:
33 +; CHECK-LABEL: test_call_libfunc
34 +; CHECK: st %f1, [%fp+[[Offset0:[0-9]+]]]
35 +; CHECK: fmovs %f3, %f1
37 +; CHECK: st %f0, [%fp+[[Offset1:[0-9]+]]]
38 +; CHECK: ld [%fp+[[Offset0]]], %f1
40 +; CHECK: ld [%fp+[[Offset1]]], %f1
41 +; CHECK: fmuls %f1, %f0, %f0
43 +define inreg float @test_call_libfunc(float %arg0, float %arg1) {
45 + %0 = tail call inreg float @cosf(float %arg1)
46 + %1 = tail call inreg float @sinf(float %arg0)
47 + %2 = fmul float %0, %1
51 +declare inreg float @cosf(float %arg) readnone nounwind
52 +declare inreg float @sinf(float %arg) readnone nounwind