1 Pull in r198893 from upstream llvm trunk (by Venkatraman Govindaraju):
3 [Sparc] Multiclass for loads/stores. No functionality change intended.
5 Introduced here: http://svnweb.freebsd.org/changeset/base/262261
7 Index: lib/Target/Sparc/SparcInstr64Bit.td
8 ===================================================================
9 --- lib/Target/Sparc/SparcInstr64Bit.td
10 +++ lib/Target/Sparc/SparcInstr64Bit.td
11 @@ -235,14 +235,8 @@ def UDIVXri : F3_2<2, 0b001101,
12 let Predicates = [Is64Bit] in {
15 -def LDXrr : F3_1<3, 0b001011,
16 - (outs I64Regs:$dst), (ins MEMrr:$addr),
17 - "ldx [$addr], $dst",
18 - [(set i64:$dst, (load ADDRrr:$addr))]>;
19 -def LDXri : F3_2<3, 0b001011,
20 - (outs I64Regs:$dst), (ins MEMri:$addr),
21 - "ldx [$addr], $dst",
22 - [(set i64:$dst, (load ADDRri:$addr))]>;
23 +defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>;
25 let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in
26 def TLS_LDXrr : F3_1<3, 0b001011,
27 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
28 @@ -276,24 +270,10 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr
29 def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
31 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
32 -def LDSWrr : F3_1<3, 0b001000,
33 - (outs I64Regs:$dst), (ins MEMrr:$addr),
34 - "ldsw [$addr], $dst",
35 - [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
36 -def LDSWri : F3_2<3, 0b001000,
37 - (outs I64Regs:$dst), (ins MEMri:$addr),
38 - "ldsw [$addr], $dst",
39 - [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
40 +defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
43 -def STXrr : F3_1<3, 0b001110,
44 - (outs), (ins MEMrr:$addr, I64Regs:$rd),
46 - [(store i64:$rd, ADDRrr:$addr)]>;
47 -def STXri : F3_2<3, 0b001110,
48 - (outs), (ins MEMri:$addr, I64Regs:$rd),
50 - [(store i64:$rd, ADDRri:$addr)]>;
51 +defm STX : Store<"stx", 0b001110, store, I64Regs, i64>;
53 // Truncating stores from i64 are identical to the i32 stores.
54 def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
55 Index: lib/Target/Sparc/SparcInstrInfo.td
56 ===================================================================
57 --- lib/Target/Sparc/SparcInstrInfo.td
58 +++ lib/Target/Sparc/SparcInstrInfo.td
59 @@ -250,6 +250,32 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val>
60 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
63 +// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
64 +multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
65 + RegisterClass RC, ValueType Ty> {
66 + def rr : F3_1<3, Op3Val,
67 + (outs RC:$dst), (ins MEMrr:$addr),
68 + !strconcat(OpcStr, " [$addr], $dst"),
69 + [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
70 + def ri : F3_2<3, Op3Val,
71 + (outs RC:$dst), (ins MEMri:$addr),
72 + !strconcat(OpcStr, " [$addr], $dst"),
73 + [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
76 +// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
77 +multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
78 + RegisterClass RC, ValueType Ty> {
79 + def rr : F3_1<3, Op3Val,
80 + (outs), (ins MEMrr:$addr, RC:$rd),
81 + !strconcat(OpcStr, " $rd, [$addr]"),
82 + [(OpNode Ty:$rd, ADDRrr:$addr)]>;
83 + def ri : F3_2<3, Op3Val,
84 + (outs), (ins MEMri:$addr, RC:$rd),
85 + !strconcat(OpcStr, " $rd, [$addr]"),
86 + [(OpNode Ty:$rd, ADDRri:$addr)]>;
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
92 @@ -350,128 +376,28 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot =
95 // Section B.1 - Load Integer Instructions, p. 90
96 -def LDSBrr : F3_1<3, 0b001001,
97 - (outs IntRegs:$dst), (ins MEMrr:$addr),
98 - "ldsb [$addr], $dst",
99 - [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
100 -def LDSBri : F3_2<3, 0b001001,
101 - (outs IntRegs:$dst), (ins MEMri:$addr),
102 - "ldsb [$addr], $dst",
103 - [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
104 -def LDSHrr : F3_1<3, 0b001010,
105 - (outs IntRegs:$dst), (ins MEMrr:$addr),
106 - "ldsh [$addr], $dst",
107 - [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
108 -def LDSHri : F3_2<3, 0b001010,
109 - (outs IntRegs:$dst), (ins MEMri:$addr),
110 - "ldsh [$addr], $dst",
111 - [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
112 -def LDUBrr : F3_1<3, 0b000001,
113 - (outs IntRegs:$dst), (ins MEMrr:$addr),
114 - "ldub [$addr], $dst",
115 - [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
116 -def LDUBri : F3_2<3, 0b000001,
117 - (outs IntRegs:$dst), (ins MEMri:$addr),
118 - "ldub [$addr], $dst",
119 - [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
120 -def LDUHrr : F3_1<3, 0b000010,
121 - (outs IntRegs:$dst), (ins MEMrr:$addr),
122 - "lduh [$addr], $dst",
123 - [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
124 -def LDUHri : F3_2<3, 0b000010,
125 - (outs IntRegs:$dst), (ins MEMri:$addr),
126 - "lduh [$addr], $dst",
127 - [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
128 -def LDrr : F3_1<3, 0b000000,
129 - (outs IntRegs:$dst), (ins MEMrr:$addr),
130 - "ld [$addr], $dst",
131 - [(set i32:$dst, (load ADDRrr:$addr))]>;
132 -def LDri : F3_2<3, 0b000000,
133 - (outs IntRegs:$dst), (ins MEMri:$addr),
134 - "ld [$addr], $dst",
135 - [(set i32:$dst, (load ADDRri:$addr))]>;
136 +defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
137 +defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
138 +defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>;
139 +defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
140 +defm LD : Load<"ld", 0b000000, load, IntRegs, i32>;
142 // Section B.2 - Load Floating-point Instructions, p. 92
143 -def LDFrr : F3_1<3, 0b100000,
144 - (outs FPRegs:$dst), (ins MEMrr:$addr),
145 - "ld [$addr], $dst",
146 - [(set f32:$dst, (load ADDRrr:$addr))]>;
147 -def LDFri : F3_2<3, 0b100000,
148 - (outs FPRegs:$dst), (ins MEMri:$addr),
149 - "ld [$addr], $dst",
150 - [(set f32:$dst, (load ADDRri:$addr))]>;
151 -def LDDFrr : F3_1<3, 0b100011,
152 - (outs DFPRegs:$dst), (ins MEMrr:$addr),
153 - "ldd [$addr], $dst",
154 - [(set f64:$dst, (load ADDRrr:$addr))]>;
155 -def LDDFri : F3_2<3, 0b100011,
156 - (outs DFPRegs:$dst), (ins MEMri:$addr),
157 - "ldd [$addr], $dst",
158 - [(set f64:$dst, (load ADDRri:$addr))]>;
159 -def LDQFrr : F3_1<3, 0b100010,
160 - (outs QFPRegs:$dst), (ins MEMrr:$addr),
161 - "ldq [$addr], $dst",
162 - [(set f128:$dst, (load ADDRrr:$addr))]>,
163 - Requires<[HasV9, HasHardQuad]>;
164 -def LDQFri : F3_2<3, 0b100010,
165 - (outs QFPRegs:$dst), (ins MEMri:$addr),
166 - "ldq [$addr], $dst",
167 - [(set f128:$dst, (load ADDRri:$addr))]>,
168 - Requires<[HasV9, HasHardQuad]>;
169 +defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
170 +defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
171 +defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
172 + Requires<[HasV9, HasHardQuad]>;
174 // Section B.4 - Store Integer Instructions, p. 95
175 -def STBrr : F3_1<3, 0b000101,
176 - (outs), (ins MEMrr:$addr, IntRegs:$rd),
177 - "stb $rd, [$addr]",
178 - [(truncstorei8 i32:$rd, ADDRrr:$addr)]>;
179 -def STBri : F3_2<3, 0b000101,
180 - (outs), (ins MEMri:$addr, IntRegs:$rd),
181 - "stb $rd, [$addr]",
182 - [(truncstorei8 i32:$rd, ADDRri:$addr)]>;
183 -def STHrr : F3_1<3, 0b000110,
184 - (outs), (ins MEMrr:$addr, IntRegs:$rd),
185 - "sth $rd, [$addr]",
186 - [(truncstorei16 i32:$rd, ADDRrr:$addr)]>;
187 -def STHri : F3_2<3, 0b000110,
188 - (outs), (ins MEMri:$addr, IntRegs:$rd),
189 - "sth $rd, [$addr]",
190 - [(truncstorei16 i32:$rd, ADDRri:$addr)]>;
191 -def STrr : F3_1<3, 0b000100,
192 - (outs), (ins MEMrr:$addr, IntRegs:$rd),
194 - [(store i32:$rd, ADDRrr:$addr)]>;
195 -def STri : F3_2<3, 0b000100,
196 - (outs), (ins MEMri:$addr, IntRegs:$rd),
198 - [(store i32:$rd, ADDRri:$addr)]>;
199 +defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>;
200 +defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
201 +defm ST : Store<"st", 0b000100, store, IntRegs, i32>;
203 // Section B.5 - Store Floating-point Instructions, p. 97
204 -def STFrr : F3_1<3, 0b100100,
205 - (outs), (ins MEMrr:$addr, FPRegs:$rd),
207 - [(store f32:$rd, ADDRrr:$addr)]>;
208 -def STFri : F3_2<3, 0b100100,
209 - (outs), (ins MEMri:$addr, FPRegs:$rd),
211 - [(store f32:$rd, ADDRri:$addr)]>;
212 -def STDFrr : F3_1<3, 0b100111,
213 - (outs), (ins MEMrr:$addr, DFPRegs:$rd),
214 - "std $rd, [$addr]",
215 - [(store f64:$rd, ADDRrr:$addr)]>;
216 -def STDFri : F3_2<3, 0b100111,
217 - (outs), (ins MEMri:$addr, DFPRegs:$rd),
218 - "std $rd, [$addr]",
219 - [(store f64:$rd, ADDRri:$addr)]>;
220 -def STQFrr : F3_1<3, 0b100110,
221 - (outs), (ins MEMrr:$addr, QFPRegs:$rd),
222 - "stq $rd, [$addr]",
223 - [(store f128:$rd, ADDRrr:$addr)]>,
224 - Requires<[HasV9, HasHardQuad]>;
225 -def STQFri : F3_2<3, 0b100110,
226 - (outs), (ins MEMri:$addr, QFPRegs:$rd),
227 - "stq $rd, [$addr]",
228 - [(store f128:$rd, ADDRri:$addr)]>,
229 - Requires<[HasV9, HasHardQuad]>;
230 +defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
231 +defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
232 +defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
233 + Requires<[HasV9, HasHardQuad]>;
235 // Section B.9 - SETHI Instruction, p. 104
236 def SETHIi: F2_1<0b100,