1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
32 using namespace clang;
34 //===----------------------------------------------------------------------===//
35 // Common code shared among targets.
36 //===----------------------------------------------------------------------===//
38 /// DefineStd - Define a macro name and standard variants. For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42 const LangOptions &Opts) {
43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46 // in the user's namespace.
48 Builder.defineMacro(MacroName);
51 Builder.defineMacro("__" + MacroName);
54 Builder.defineMacro("__" + MacroName + "__");
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 Builder.defineMacro("__" + CPUName);
60 Builder.defineMacro("__" + CPUName + "__");
62 Builder.defineMacro("__tune_" + CPUName + "__");
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74 MacroBuilder &Builder) const=0;
76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77 virtual void getTargetDefines(const LangOptions &Opts,
78 MacroBuilder &Builder) const {
79 TgtInfo::getTargetDefines(Opts, Builder);
80 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
84 } // end anonymous namespace
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88 const llvm::Triple &Triple,
89 StringRef &PlatformName,
90 VersionTuple &PlatformMinVersion) {
91 Builder.defineMacro("__APPLE_CC__", "6000");
92 Builder.defineMacro("__APPLE__");
93 Builder.defineMacro("__MACH__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 if (!Opts.ObjCAutoRefCount) {
100 // __weak is always defined, for use in blocks and with objc pointers.
101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 // Darwin defines __strong even in C mode (just to nothing).
104 if (Opts.getGC() != LangOptions::NonGC)
105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107 Builder.defineMacro("__strong", "");
109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110 // allow this in C, since one might have block pointers in structs that
111 // are used in pure C code and in Objective-C ARC.
112 Builder.defineMacro("__unsafe_unretained", "");
116 Builder.defineMacro("__STATIC__");
118 Builder.defineMacro("__DYNAMIC__");
120 if (Opts.POSIXThreads)
121 Builder.defineMacro("_REENTRANT");
123 // Get the platform type and version number from the triple.
124 unsigned Maj, Min, Rev;
125 if (Triple.isMacOSX()) {
126 Triple.getMacOSXVersion(Maj, Min, Rev);
127 PlatformName = "macosx";
129 Triple.getOSVersion(Maj, Min, Rev);
130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
133 // If -target arch-pc-win32-macho option specified, we're
134 // generating code for Win32 ABI. No need to emit
135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136 if (PlatformName == "win32") {
137 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
141 // If there's an environment specified in the triple, that means we're dealing
142 // with an embedded variant of some sort and don't want the platform
143 // version-min defines, so only add them if there's not one.
144 if (Triple.getEnvironmentName().empty()) {
145 // Set the appropriate OS version define.
146 if (Triple.isiOS()) {
147 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
150 Str[1] = '0' + (Min / 10);
151 Str[2] = '0' + (Min % 10);
152 Str[3] = '0' + (Rev / 10);
153 Str[4] = '0' + (Rev % 10);
155 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
158 // Note that the Driver allows versions which aren't representable in the
159 // define (because we only get a single digit for the minor and micro
160 // revision numbers). So, we limit them to the maximum representable
162 assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
165 Str[0] = '0' + (Maj / 10);
166 Str[1] = '0' + (Maj % 10);
167 Str[2] = '0' + std::min(Min, 9U);
168 Str[3] = '0' + std::min(Rev, 9U);
170 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
174 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
178 template<typename Target>
179 class DarwinTargetInfo : public OSTargetInfo<Target> {
181 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
182 MacroBuilder &Builder) const {
183 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
184 this->PlatformMinVersion);
188 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
189 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
190 this->MCountName = "\01mcount";
193 virtual std::string isValidSectionSpecifier(StringRef SR) const {
194 // Let MCSectionMachO validate this.
195 StringRef Segment, Section;
196 unsigned TAA, StubSize;
198 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
199 TAA, HasTAA, StubSize);
202 virtual const char *getStaticInitSectionSpecifier() const {
203 // FIXME: We should return 0 when building kexts.
204 return "__TEXT,__StaticInit,regular,pure_instructions";
207 /// Darwin does not support protected visibility. Darwin's "default"
208 /// is very similar to ELF's "protected"; Darwin requires a "weak"
209 /// attribute on declarations that can be dynamically replaced.
210 virtual bool hasProtectedVisibility() const {
216 // DragonFlyBSD Target
217 template<typename Target>
218 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
220 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
221 MacroBuilder &Builder) const {
222 // DragonFly defines; list based off of gcc output
223 Builder.defineMacro("__DragonFly__");
224 Builder.defineMacro("__DragonFly_cc_version", "100001");
225 Builder.defineMacro("__ELF__");
226 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
227 Builder.defineMacro("__tune_i386__");
228 DefineStd(Builder, "unix", Opts);
231 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
232 : OSTargetInfo<Target>(Triple) {
233 this->UserLabelPrefix = "";
235 switch (Triple.getArch()) {
237 case llvm::Triple::x86:
238 case llvm::Triple::x86_64:
239 this->MCountName = ".mcount";
246 template<typename Target>
247 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
249 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
250 MacroBuilder &Builder) const {
251 // FreeBSD defines; list based off of gcc output
253 unsigned Release = Triple.getOSMajorVersion();
257 Builder.defineMacro("__FreeBSD__", Twine(Release));
258 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
259 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
260 DefineStd(Builder, "unix", Opts);
261 Builder.defineMacro("__ELF__");
263 // On FreeBSD, wchar_t contains the number of the code point as
264 // used by the character set of the locale. These character sets are
265 // not necessarily a superset of ASCII.
266 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
269 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
270 this->UserLabelPrefix = "";
272 switch (Triple.getArch()) {
274 case llvm::Triple::x86:
275 case llvm::Triple::x86_64:
276 this->MCountName = ".mcount";
278 case llvm::Triple::mips:
279 case llvm::Triple::mipsel:
280 case llvm::Triple::ppc:
281 case llvm::Triple::ppc64:
282 case llvm::Triple::ppc64le:
283 this->MCountName = "_mcount";
285 case llvm::Triple::arm:
286 this->MCountName = "__mcount";
292 // GNU/kFreeBSD Target
293 template<typename Target>
294 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
296 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
297 MacroBuilder &Builder) const {
298 // GNU/kFreeBSD defines; list based off of gcc output
300 DefineStd(Builder, "unix", Opts);
301 Builder.defineMacro("__FreeBSD_kernel__");
302 Builder.defineMacro("__GLIBC__");
303 Builder.defineMacro("__ELF__");
304 if (Opts.POSIXThreads)
305 Builder.defineMacro("_REENTRANT");
307 Builder.defineMacro("_GNU_SOURCE");
310 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
311 this->UserLabelPrefix = "";
316 template<typename Target>
317 class MinixTargetInfo : public OSTargetInfo<Target> {
319 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
320 MacroBuilder &Builder) const {
323 Builder.defineMacro("__minix", "3");
324 Builder.defineMacro("_EM_WSIZE", "4");
325 Builder.defineMacro("_EM_PSIZE", "4");
326 Builder.defineMacro("_EM_SSIZE", "2");
327 Builder.defineMacro("_EM_LSIZE", "4");
328 Builder.defineMacro("_EM_FSIZE", "4");
329 Builder.defineMacro("_EM_DSIZE", "8");
330 Builder.defineMacro("__ELF__");
331 DefineStd(Builder, "unix", Opts);
334 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
335 this->UserLabelPrefix = "";
340 template<typename Target>
341 class LinuxTargetInfo : public OSTargetInfo<Target> {
343 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
344 MacroBuilder &Builder) const {
345 // Linux defines; list based off of gcc output
346 DefineStd(Builder, "unix", Opts);
347 DefineStd(Builder, "linux", Opts);
348 Builder.defineMacro("__gnu_linux__");
349 Builder.defineMacro("__ELF__");
350 if (Triple.getEnvironment() == llvm::Triple::Android)
351 Builder.defineMacro("__ANDROID__", "1");
352 if (Opts.POSIXThreads)
353 Builder.defineMacro("_REENTRANT");
355 Builder.defineMacro("_GNU_SOURCE");
358 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
359 this->UserLabelPrefix = "";
360 this->WIntType = TargetInfo::UnsignedInt;
363 virtual const char *getStaticInitSectionSpecifier() const {
364 return ".text.startup";
369 template<typename Target>
370 class NetBSDTargetInfo : public OSTargetInfo<Target> {
372 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
373 MacroBuilder &Builder) const {
374 // NetBSD defines; list based off of gcc output
375 Builder.defineMacro("__NetBSD__");
376 Builder.defineMacro("__unix__");
377 Builder.defineMacro("__ELF__");
378 if (Opts.POSIXThreads)
379 Builder.defineMacro("_POSIX_THREADS");
382 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
383 this->UserLabelPrefix = "";
388 template<typename Target>
389 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
391 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
392 MacroBuilder &Builder) const {
393 // OpenBSD defines; list based off of gcc output
395 Builder.defineMacro("__OpenBSD__");
396 DefineStd(Builder, "unix", Opts);
397 Builder.defineMacro("__ELF__");
398 if (Opts.POSIXThreads)
399 Builder.defineMacro("_REENTRANT");
402 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403 this->UserLabelPrefix = "";
404 this->TLSSupported = false;
406 switch (Triple.getArch()) {
408 case llvm::Triple::x86:
409 case llvm::Triple::x86_64:
410 case llvm::Triple::arm:
411 case llvm::Triple::sparc:
412 this->MCountName = "__mcount";
414 case llvm::Triple::mips64:
415 case llvm::Triple::mips64el:
416 case llvm::Triple::ppc:
417 case llvm::Triple::sparcv9:
418 this->MCountName = "_mcount";
425 template<typename Target>
426 class BitrigTargetInfo : public OSTargetInfo<Target> {
428 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
429 MacroBuilder &Builder) const {
430 // Bitrig defines; list based off of gcc output
432 Builder.defineMacro("__Bitrig__");
433 DefineStd(Builder, "unix", Opts);
434 Builder.defineMacro("__ELF__");
435 if (Opts.POSIXThreads)
436 Builder.defineMacro("_REENTRANT");
439 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
440 this->UserLabelPrefix = "";
441 this->TLSSupported = false;
442 this->MCountName = "__mcount";
447 template<typename Target>
448 class PSPTargetInfo : public OSTargetInfo<Target> {
450 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
451 MacroBuilder &Builder) const {
452 // PSP defines; list based on the output of the pspdev gcc toolchain.
453 Builder.defineMacro("PSP");
454 Builder.defineMacro("_PSP");
455 Builder.defineMacro("__psp__");
456 Builder.defineMacro("__ELF__");
459 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
460 this->UserLabelPrefix = "";
465 template<typename Target>
466 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
468 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
469 MacroBuilder &Builder) const {
471 Builder.defineMacro("__PPC__");
472 Builder.defineMacro("__PPU__");
473 Builder.defineMacro("__CELLOS_LV2__");
474 Builder.defineMacro("__ELF__");
475 Builder.defineMacro("__LP32__");
476 Builder.defineMacro("_ARCH_PPC64");
477 Builder.defineMacro("__powerpc64__");
480 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
481 this->UserLabelPrefix = "";
482 this->LongWidth = this->LongAlign = 32;
483 this->PointerWidth = this->PointerAlign = 32;
484 this->IntMaxType = TargetInfo::SignedLongLong;
485 this->UIntMaxType = TargetInfo::UnsignedLongLong;
486 this->Int64Type = TargetInfo::SignedLongLong;
487 this->SizeType = TargetInfo::UnsignedInt;
488 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
489 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
493 // FIXME: Need a real SPU target.
495 template<typename Target>
496 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
498 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
499 MacroBuilder &Builder) const {
501 Builder.defineMacro("__SPU__");
502 Builder.defineMacro("__ELF__");
505 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
506 this->UserLabelPrefix = "";
511 template<typename Target>
512 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
514 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
515 MacroBuilder &Builder) const {
516 DefineStd(Builder, "sun", Opts);
517 DefineStd(Builder, "unix", Opts);
518 Builder.defineMacro("__ELF__");
519 Builder.defineMacro("__svr4__");
520 Builder.defineMacro("__SVR4");
523 AuroraUXTargetInfo(const llvm::Triple &Triple)
524 : OSTargetInfo<Target>(Triple) {
525 this->UserLabelPrefix = "";
526 this->WCharType = this->SignedLong;
527 // FIXME: WIntType should be SignedLong
532 template<typename Target>
533 class SolarisTargetInfo : public OSTargetInfo<Target> {
535 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
536 MacroBuilder &Builder) const {
537 DefineStd(Builder, "sun", Opts);
538 DefineStd(Builder, "unix", Opts);
539 Builder.defineMacro("__ELF__");
540 Builder.defineMacro("__svr4__");
541 Builder.defineMacro("__SVR4");
542 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
543 // newer, but to 500 for everything else. feature_test.h has a check to
544 // ensure that you are not using C99 with an old version of X/Open or C89
545 // with a new version.
546 if (Opts.C99 || Opts.C11)
547 Builder.defineMacro("_XOPEN_SOURCE", "600");
549 Builder.defineMacro("_XOPEN_SOURCE", "500");
551 Builder.defineMacro("__C99FEATURES__");
552 Builder.defineMacro("_LARGEFILE_SOURCE");
553 Builder.defineMacro("_LARGEFILE64_SOURCE");
554 Builder.defineMacro("__EXTENSIONS__");
555 Builder.defineMacro("_REENTRANT");
558 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
559 this->UserLabelPrefix = "";
560 this->WCharType = this->SignedInt;
561 // FIXME: WIntType should be SignedLong
566 template<typename Target>
567 class WindowsTargetInfo : public OSTargetInfo<Target> {
569 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
570 MacroBuilder &Builder) const {
571 Builder.defineMacro("_WIN32");
573 void getVisualStudioDefines(const LangOptions &Opts,
574 MacroBuilder &Builder) const {
575 if (Opts.CPlusPlus) {
577 Builder.defineMacro("_CPPRTTI");
580 Builder.defineMacro("_CPPUNWIND");
583 if (!Opts.CharIsSigned)
584 Builder.defineMacro("_CHAR_UNSIGNED");
586 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
587 // but it works for now.
588 if (Opts.POSIXThreads)
589 Builder.defineMacro("_MT");
591 if (Opts.MSCVersion != 0)
592 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
594 if (Opts.MicrosoftExt) {
595 Builder.defineMacro("_MSC_EXTENSIONS");
597 if (Opts.CPlusPlus11) {
598 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
599 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
600 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
604 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
608 WindowsTargetInfo(const llvm::Triple &Triple)
609 : OSTargetInfo<Target>(Triple) {}
612 template <typename Target>
613 class NaClTargetInfo : public OSTargetInfo<Target> {
615 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
616 MacroBuilder &Builder) const {
617 if (Opts.POSIXThreads)
618 Builder.defineMacro("_REENTRANT");
620 Builder.defineMacro("_GNU_SOURCE");
622 DefineStd(Builder, "unix", Opts);
623 Builder.defineMacro("__ELF__");
624 Builder.defineMacro("__native_client__");
628 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
629 this->UserLabelPrefix = "";
630 this->LongAlign = 32;
631 this->LongWidth = 32;
632 this->PointerAlign = 32;
633 this->PointerWidth = 32;
634 this->IntMaxType = TargetInfo::SignedLongLong;
635 this->UIntMaxType = TargetInfo::UnsignedLongLong;
636 this->Int64Type = TargetInfo::SignedLongLong;
637 this->DoubleAlign = 64;
638 this->LongDoubleWidth = 64;
639 this->LongDoubleAlign = 64;
640 this->SizeType = TargetInfo::UnsignedInt;
641 this->PtrDiffType = TargetInfo::SignedInt;
642 this->IntPtrType = TargetInfo::SignedInt;
643 // RegParmMax is inherited from the underlying architecture
644 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
645 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
646 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
648 virtual typename Target::CallingConvCheckResult checkCallingConvention(
649 CallingConv CC) const {
650 return CC == CC_PnaclCall ? Target::CCCR_OK :
651 Target::checkCallingConvention(CC);
654 } // end anonymous namespace.
656 //===----------------------------------------------------------------------===//
657 // Specific target implementations.
658 //===----------------------------------------------------------------------===//
661 // PPC abstract base class
662 class PPCTargetInfo : public TargetInfo {
663 static const Builtin::Info BuiltinInfo[];
664 static const char * const GCCRegNames[];
665 static const TargetInfo::GCCRegAlias GCCRegAliases[];
668 // Target cpu features.
672 PPCTargetInfo(const llvm::Triple &Triple)
673 : TargetInfo(Triple), HasVSX(false) {
674 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
675 LongDoubleWidth = LongDoubleAlign = 128;
676 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
679 /// \brief Flags for architecture specific defines.
682 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
683 ArchDefinePpcgr = 1 << 1,
684 ArchDefinePpcsq = 1 << 2,
685 ArchDefine440 = 1 << 3,
686 ArchDefine603 = 1 << 4,
687 ArchDefine604 = 1 << 5,
688 ArchDefinePwr4 = 1 << 6,
689 ArchDefinePwr5 = 1 << 7,
690 ArchDefinePwr5x = 1 << 8,
691 ArchDefinePwr6 = 1 << 9,
692 ArchDefinePwr6x = 1 << 10,
693 ArchDefinePwr7 = 1 << 11,
694 ArchDefineA2 = 1 << 12,
695 ArchDefineA2q = 1 << 13
698 // Note: GCC recognizes the following additional cpus:
699 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
700 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
702 virtual bool setCPU(const std::string &Name) {
703 bool CPUKnown = llvm::StringSwitch<bool>(Name)
704 .Case("generic", true)
726 .Case("e500mc", true)
728 .Case("power3", true)
730 .Case("power4", true)
732 .Case("power5", true)
734 .Case("power5x", true)
736 .Case("power6", true)
738 .Case("power6x", true)
740 .Case("power7", true)
742 .Case("powerpc", true)
744 .Case("powerpc64", true)
746 .Case("powerpc64le", true)
747 .Case("ppc64le", true)
756 virtual void getTargetBuiltins(const Builtin::Info *&Records,
757 unsigned &NumRecords) const {
758 Records = BuiltinInfo;
759 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
762 virtual bool isCLZForZeroUndef() const { return false; }
764 virtual void getTargetDefines(const LangOptions &Opts,
765 MacroBuilder &Builder) const;
767 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
769 virtual bool handleTargetFeatures(std::vector<std::string> &Features,
770 DiagnosticsEngine &Diags);
771 virtual bool hasFeature(StringRef Feature) const;
773 virtual void getGCCRegNames(const char * const *&Names,
774 unsigned &NumNames) const;
775 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
776 unsigned &NumAliases) const;
777 virtual bool validateAsmConstraint(const char *&Name,
778 TargetInfo::ConstraintInfo &Info) const {
780 default: return false;
783 case 'b': // Base register
784 case 'f': // Floating point register
785 Info.setAllowsRegister();
787 // FIXME: The following are added to allow parsing.
788 // I just took a guess at what the actions should be.
789 // Also, is more specific checking needed? I.e. specific registers?
790 case 'd': // Floating point register (containing 64-bit value)
791 case 'v': // Altivec vector register
792 Info.setAllowsRegister();
796 case 'd':// VSX vector register to hold vector double data
797 case 'f':// VSX vector register to hold vector float data
798 case 's':// VSX vector register to hold scalar float data
799 case 'a':// Any VSX register
804 Info.setAllowsRegister();
805 Name++; // Skip over 'w'.
807 case 'h': // `MQ', `CTR', or `LINK' register
808 case 'q': // `MQ' register
809 case 'c': // `CTR' register
810 case 'l': // `LINK' register
811 case 'x': // `CR' register (condition register) number 0
812 case 'y': // `CR' register (condition register)
813 case 'z': // `XER[CA]' carry bit (part of the XER register)
814 Info.setAllowsRegister();
816 case 'I': // Signed 16-bit constant
817 case 'J': // Unsigned 16-bit constant shifted left 16 bits
818 // (use `L' instead for SImode constants)
819 case 'K': // Unsigned 16-bit constant
820 case 'L': // Signed 16-bit constant shifted left 16 bits
821 case 'M': // Constant larger than 31
822 case 'N': // Exact power of 2
823 case 'P': // Constant whose negation is a signed 16-bit constant
824 case 'G': // Floating point constant that can be loaded into a
825 // register with one instruction per word
826 case 'H': // Integer/Floating point constant that can be loaded
827 // into a register using three instructions
829 case 'm': // Memory operand. Note that on PowerPC targets, m can
830 // include addresses that update the base register. It
831 // is therefore only safe to use `m' in an asm statement
832 // if that asm statement accesses the operand exactly once.
833 // The asm statement must also use `%U<opno>' as a
834 // placeholder for the "update" flag in the corresponding
835 // load or store instruction. For example:
836 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
838 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
839 // is not. Use es rather than m if you don't want the base
840 // register to be updated.
844 // es: A "stable" memory operand; that is, one which does not
845 // include any automodification of the base register. Unlike
846 // `m', this constraint can be used in asm statements that
847 // might access the operand several times, or that might not
849 Info.setAllowsMemory();
850 Name++; // Skip over 'e'.
852 case 'Q': // Memory operand that is an offset from a register (it is
853 // usually better to use `m' or `es' in asm statements)
854 case 'Z': // Memory operand that is an indexed or indirect from a
855 // register (it is usually better to use `m' or `es' in
857 Info.setAllowsMemory();
858 Info.setAllowsRegister();
860 case 'R': // AIX TOC entry
861 case 'a': // Address operand that is an indexed or indirect from a
862 // register (`p' is preferable for asm statements)
863 case 'S': // Constant suitable as a 64-bit mask operand
864 case 'T': // Constant suitable as a 32-bit mask operand
865 case 'U': // System V Release 4 small data area reference
866 case 't': // AND masks that can be performed by two rldic{l, r}
868 case 'W': // Vector constant that does not require memory
869 case 'j': // Vector constant that is all zeros.
875 virtual const char *getClobbers() const {
878 int getEHDataRegisterNumber(unsigned RegNo) const {
879 if (RegNo == 0) return 3;
880 if (RegNo == 1) return 4;
885 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
886 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
887 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
889 #include "clang/Basic/BuiltinsPPC.def"
892 /// handleTargetFeatures - Perform initialization based on the user
893 /// configured set of features.
894 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
895 DiagnosticsEngine &Diags) {
896 // Remember the maximum enabled sselevel.
897 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
898 // Ignore disabled features.
899 if (Features[i][0] == '-')
902 StringRef Feature = StringRef(Features[i]).substr(1);
904 if (Feature == "vsx") {
909 // TODO: Finish this list and add an assert that we've handled them
916 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
917 /// #defines that are not tied to a specific subtarget.
918 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
919 MacroBuilder &Builder) const {
920 // Target identification.
921 Builder.defineMacro("__ppc__");
922 Builder.defineMacro("__PPC__");
923 Builder.defineMacro("_ARCH_PPC");
924 Builder.defineMacro("__powerpc__");
925 Builder.defineMacro("__POWERPC__");
926 if (PointerWidth == 64) {
927 Builder.defineMacro("_ARCH_PPC64");
928 Builder.defineMacro("__powerpc64__");
929 Builder.defineMacro("__ppc64__");
930 Builder.defineMacro("__PPC64__");
933 // Target properties.
934 if (getTriple().getArch() == llvm::Triple::ppc64le) {
935 Builder.defineMacro("_LITTLE_ENDIAN");
936 Builder.defineMacro("__LITTLE_ENDIAN__");
938 if (getTriple().getOS() != llvm::Triple::NetBSD &&
939 getTriple().getOS() != llvm::Triple::OpenBSD)
940 Builder.defineMacro("_BIG_ENDIAN");
941 Builder.defineMacro("__BIG_ENDIAN__");
944 // Subtarget options.
945 Builder.defineMacro("__NATURAL_ALIGNMENT__");
946 Builder.defineMacro("__REGISTER_PREFIX__", "");
948 // FIXME: Should be controlled by command line option.
949 if (LongDoubleWidth == 128)
950 Builder.defineMacro("__LONG_DOUBLE_128__");
953 Builder.defineMacro("__VEC__", "10206");
954 Builder.defineMacro("__ALTIVEC__");
957 // CPU identification.
958 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
959 .Case("440", ArchDefineName)
960 .Case("450", ArchDefineName | ArchDefine440)
961 .Case("601", ArchDefineName)
962 .Case("602", ArchDefineName | ArchDefinePpcgr)
963 .Case("603", ArchDefineName | ArchDefinePpcgr)
964 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
965 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
966 .Case("604", ArchDefineName | ArchDefinePpcgr)
967 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
968 .Case("620", ArchDefineName | ArchDefinePpcgr)
969 .Case("630", ArchDefineName | ArchDefinePpcgr)
970 .Case("7400", ArchDefineName | ArchDefinePpcgr)
971 .Case("7450", ArchDefineName | ArchDefinePpcgr)
972 .Case("750", ArchDefineName | ArchDefinePpcgr)
973 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
975 .Case("a2", ArchDefineA2)
976 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
977 .Case("pwr3", ArchDefinePpcgr)
978 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
979 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
981 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
982 | ArchDefinePpcgr | ArchDefinePpcsq)
983 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
984 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
985 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
986 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
988 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
989 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
990 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
991 .Case("power3", ArchDefinePpcgr)
992 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
993 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
995 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
996 | ArchDefinePpcgr | ArchDefinePpcsq)
997 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
998 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
999 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1000 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1002 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1003 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1004 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
1005 .Default(ArchDefineNone);
1007 if (defs & ArchDefineName)
1008 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1009 if (defs & ArchDefinePpcgr)
1010 Builder.defineMacro("_ARCH_PPCGR");
1011 if (defs & ArchDefinePpcsq)
1012 Builder.defineMacro("_ARCH_PPCSQ");
1013 if (defs & ArchDefine440)
1014 Builder.defineMacro("_ARCH_440");
1015 if (defs & ArchDefine603)
1016 Builder.defineMacro("_ARCH_603");
1017 if (defs & ArchDefine604)
1018 Builder.defineMacro("_ARCH_604");
1019 if (defs & ArchDefinePwr4)
1020 Builder.defineMacro("_ARCH_PWR4");
1021 if (defs & ArchDefinePwr5)
1022 Builder.defineMacro("_ARCH_PWR5");
1023 if (defs & ArchDefinePwr5x)
1024 Builder.defineMacro("_ARCH_PWR5X");
1025 if (defs & ArchDefinePwr6)
1026 Builder.defineMacro("_ARCH_PWR6");
1027 if (defs & ArchDefinePwr6x)
1028 Builder.defineMacro("_ARCH_PWR6X");
1029 if (defs & ArchDefinePwr7)
1030 Builder.defineMacro("_ARCH_PWR7");
1031 if (defs & ArchDefineA2)
1032 Builder.defineMacro("_ARCH_A2");
1033 if (defs & ArchDefineA2q) {
1034 Builder.defineMacro("_ARCH_A2Q");
1035 Builder.defineMacro("_ARCH_QP");
1038 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1039 Builder.defineMacro("__bg__");
1040 Builder.defineMacro("__THW_BLUEGENE__");
1041 Builder.defineMacro("__bgq__");
1042 Builder.defineMacro("__TOS_BGQ__");
1046 Builder.defineMacro("__VSX__");
1048 // FIXME: The following are not yet generated here by Clang, but are
1049 // generated by GCC:
1052 // __RECIP_PRECISION__
1053 // __APPLE_ALTIVEC__
1062 // __CMODEL_MEDIUM__
1069 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1070 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1079 .Case("ppc64", true)
1080 .Case("ppc64le", true)
1083 Features["qpx"] = (CPU == "a2q");
1086 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1087 return Feature == "powerpc";
1091 const char * const PPCTargetInfo::GCCRegNames[] = {
1092 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1093 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1094 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1095 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1096 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1097 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1098 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1099 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1100 "mq", "lr", "ctr", "ap",
1101 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1103 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1104 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1105 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1106 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1108 "spe_acc", "spefscr",
1112 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1113 unsigned &NumNames) const {
1114 Names = GCCRegNames;
1115 NumNames = llvm::array_lengthof(GCCRegNames);
1118 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1119 // While some of these aliases do map to different registers
1120 // they still share the same register name.
1131 { { "10" }, "r10" },
1132 { { "11" }, "r11" },
1133 { { "12" }, "r12" },
1134 { { "13" }, "r13" },
1135 { { "14" }, "r14" },
1136 { { "15" }, "r15" },
1137 { { "16" }, "r16" },
1138 { { "17" }, "r17" },
1139 { { "18" }, "r18" },
1140 { { "19" }, "r19" },
1141 { { "20" }, "r20" },
1142 { { "21" }, "r21" },
1143 { { "22" }, "r22" },
1144 { { "23" }, "r23" },
1145 { { "24" }, "r24" },
1146 { { "25" }, "r25" },
1147 { { "26" }, "r26" },
1148 { { "27" }, "r27" },
1149 { { "28" }, "r28" },
1150 { { "29" }, "r29" },
1151 { { "30" }, "r30" },
1152 { { "31" }, "r31" },
1153 { { "fr0" }, "f0" },
1154 { { "fr1" }, "f1" },
1155 { { "fr2" }, "f2" },
1156 { { "fr3" }, "f3" },
1157 { { "fr4" }, "f4" },
1158 { { "fr5" }, "f5" },
1159 { { "fr6" }, "f6" },
1160 { { "fr7" }, "f7" },
1161 { { "fr8" }, "f8" },
1162 { { "fr9" }, "f9" },
1163 { { "fr10" }, "f10" },
1164 { { "fr11" }, "f11" },
1165 { { "fr12" }, "f12" },
1166 { { "fr13" }, "f13" },
1167 { { "fr14" }, "f14" },
1168 { { "fr15" }, "f15" },
1169 { { "fr16" }, "f16" },
1170 { { "fr17" }, "f17" },
1171 { { "fr18" }, "f18" },
1172 { { "fr19" }, "f19" },
1173 { { "fr20" }, "f20" },
1174 { { "fr21" }, "f21" },
1175 { { "fr22" }, "f22" },
1176 { { "fr23" }, "f23" },
1177 { { "fr24" }, "f24" },
1178 { { "fr25" }, "f25" },
1179 { { "fr26" }, "f26" },
1180 { { "fr27" }, "f27" },
1181 { { "fr28" }, "f28" },
1182 { { "fr29" }, "f29" },
1183 { { "fr30" }, "f30" },
1184 { { "fr31" }, "f31" },
1185 { { "cc" }, "cr0" },
1188 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1189 unsigned &NumAliases) const {
1190 Aliases = GCCRegAliases;
1191 NumAliases = llvm::array_lengthof(GCCRegAliases);
1193 } // end anonymous namespace.
1196 class PPC32TargetInfo : public PPCTargetInfo {
1198 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1199 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1200 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1202 switch (getTriple().getOS()) {
1203 case llvm::Triple::Linux:
1204 case llvm::Triple::FreeBSD:
1205 case llvm::Triple::NetBSD:
1206 SizeType = UnsignedInt;
1207 PtrDiffType = SignedInt;
1208 IntPtrType = SignedInt;
1214 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1215 LongDoubleWidth = LongDoubleAlign = 64;
1216 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1219 // PPC32 supports atomics up to 4 bytes.
1220 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1223 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1224 // This is the ELF definition, and is overridden by the Darwin sub-target
1225 return TargetInfo::PowerABIBuiltinVaList;
1228 } // end anonymous namespace.
1230 // Note: ABI differences may eventually require us to have a separate
1231 // TargetInfo for little endian.
1233 class PPC64TargetInfo : public PPCTargetInfo {
1235 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1236 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1237 IntMaxType = SignedLong;
1238 UIntMaxType = UnsignedLong;
1239 Int64Type = SignedLong;
1241 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1242 LongDoubleWidth = LongDoubleAlign = 64;
1243 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1244 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1245 "i64:64:64-f32:32:32-f64:64:64-"
1246 "v128:128:128-n32:64";
1248 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1249 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1250 "v128:128:128-n32:64";
1252 // PPC64 supports atomics up to 8 bytes.
1253 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1255 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1256 return TargetInfo::CharPtrBuiltinVaList;
1259 } // end anonymous namespace.
1263 class DarwinPPC32TargetInfo :
1264 public DarwinTargetInfo<PPC32TargetInfo> {
1266 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1267 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1268 HasAlignMac68kSupport = true;
1269 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1270 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1272 SuitableAlign = 128;
1273 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1274 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1276 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1277 return TargetInfo::CharPtrBuiltinVaList;
1281 class DarwinPPC64TargetInfo :
1282 public DarwinTargetInfo<PPC64TargetInfo> {
1284 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1285 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1286 HasAlignMac68kSupport = true;
1287 SuitableAlign = 128;
1288 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1289 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1292 } // end anonymous namespace.
1295 static const unsigned NVPTXAddrSpaceMap[] = {
1298 4, // opencl_constant
1303 class NVPTXTargetInfo : public TargetInfo {
1304 static const char * const GCCRegNames[];
1305 static const Builtin::Info BuiltinInfo[];
1307 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1309 TLSSupported = false;
1310 LongWidth = LongAlign = 64;
1311 AddrSpaceMap = &NVPTXAddrSpaceMap;
1312 UseAddrSpaceMapMangling = true;
1313 // Define available target features
1314 // These must be defined in sorted order!
1315 NoAsmVariants = true;
1317 virtual void getTargetDefines(const LangOptions &Opts,
1318 MacroBuilder &Builder) const {
1319 Builder.defineMacro("__PTX__");
1320 Builder.defineMacro("__NVPTX__");
1322 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1323 unsigned &NumRecords) const {
1324 Records = BuiltinInfo;
1325 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1327 virtual bool hasFeature(StringRef Feature) const {
1328 return Feature == "ptx" || Feature == "nvptx";
1331 virtual void getGCCRegNames(const char * const *&Names,
1332 unsigned &NumNames) const;
1333 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1334 unsigned &NumAliases) const {
1339 virtual bool validateAsmConstraint(const char *&Name,
1340 TargetInfo::ConstraintInfo &Info) const {
1342 default: return false;
1349 Info.setAllowsRegister();
1353 virtual const char *getClobbers() const {
1354 // FIXME: Is this really right?
1357 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1359 return TargetInfo::CharPtrBuiltinVaList;
1361 virtual bool setCPU(const std::string &Name) {
1362 bool Valid = llvm::StringSwitch<bool>(Name)
1363 .Case("sm_20", true)
1364 .Case("sm_21", true)
1365 .Case("sm_30", true)
1366 .Case("sm_35", true)
1373 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1374 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1375 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1377 #include "clang/Basic/BuiltinsNVPTX.def"
1380 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1384 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1385 unsigned &NumNames) const {
1386 Names = GCCRegNames;
1387 NumNames = llvm::array_lengthof(GCCRegNames);
1390 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1392 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1393 PointerWidth = PointerAlign = 32;
1394 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1396 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1397 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1402 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1404 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1405 PointerWidth = PointerAlign = 64;
1406 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1408 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1409 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1417 static const unsigned R600AddrSpaceMap[] = {
1420 2, // opencl_constant
1426 static const char *DescriptionStringR600 =
1429 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1430 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1431 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1434 static const char *DescriptionStringR600DoubleOps =
1437 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1438 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1439 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1442 static const char *DescriptionStringSI =
1446 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1447 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1448 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1451 class R600TargetInfo : public TargetInfo {
1452 /// \brief The GPU profiles supported by the R600 target.
1460 GK_EVERGREEN_DOUBLE_OPS,
1461 GK_NORTHERN_ISLANDS,
1463 GK_SOUTHERN_ISLANDS,
1468 R600TargetInfo(const llvm::Triple &Triple)
1469 : TargetInfo(Triple), GPU(GK_R600) {
1470 DescriptionString = DescriptionStringR600;
1471 AddrSpaceMap = &R600AddrSpaceMap;
1472 UseAddrSpaceMapMangling = true;
1475 virtual const char * getClobbers() const {
1479 virtual void getGCCRegNames(const char * const *&Names,
1480 unsigned &numNames) const {
1485 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1486 unsigned &NumAliases) const {
1491 virtual bool validateAsmConstraint(const char *&Name,
1492 TargetInfo::ConstraintInfo &info) const {
1496 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1497 unsigned &NumRecords) const {
1503 virtual void getTargetDefines(const LangOptions &Opts,
1504 MacroBuilder &Builder) const {
1505 Builder.defineMacro("__R600__");
1508 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1509 return TargetInfo::CharPtrBuiltinVaList;
1512 virtual bool setCPU(const std::string &Name) {
1513 GPU = llvm::StringSwitch<GPUKind>(Name)
1514 .Case("r600" , GK_R600)
1515 .Case("rv610", GK_R600)
1516 .Case("rv620", GK_R600)
1517 .Case("rv630", GK_R600)
1518 .Case("rv635", GK_R600)
1519 .Case("rs780", GK_R600)
1520 .Case("rs880", GK_R600)
1521 .Case("rv670", GK_R600_DOUBLE_OPS)
1522 .Case("rv710", GK_R700)
1523 .Case("rv730", GK_R700)
1524 .Case("rv740", GK_R700_DOUBLE_OPS)
1525 .Case("rv770", GK_R700_DOUBLE_OPS)
1526 .Case("palm", GK_EVERGREEN)
1527 .Case("cedar", GK_EVERGREEN)
1528 .Case("sumo", GK_EVERGREEN)
1529 .Case("sumo2", GK_EVERGREEN)
1530 .Case("redwood", GK_EVERGREEN)
1531 .Case("juniper", GK_EVERGREEN)
1532 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1533 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1534 .Case("barts", GK_NORTHERN_ISLANDS)
1535 .Case("turks", GK_NORTHERN_ISLANDS)
1536 .Case("caicos", GK_NORTHERN_ISLANDS)
1537 .Case("cayman", GK_CAYMAN)
1538 .Case("aruba", GK_CAYMAN)
1539 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1540 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1541 .Case("verde", GK_SOUTHERN_ISLANDS)
1542 .Case("oland", GK_SOUTHERN_ISLANDS)
1543 .Case("bonaire", GK_SEA_ISLANDS)
1544 .Case("kabini", GK_SEA_ISLANDS)
1545 .Case("kaveri", GK_SEA_ISLANDS)
1546 .Case("hawaii", GK_SEA_ISLANDS)
1549 if (GPU == GK_NONE) {
1553 // Set the correct data layout
1559 case GK_NORTHERN_ISLANDS:
1560 DescriptionString = DescriptionStringR600;
1562 case GK_R600_DOUBLE_OPS:
1563 case GK_R700_DOUBLE_OPS:
1564 case GK_EVERGREEN_DOUBLE_OPS:
1566 DescriptionString = DescriptionStringR600DoubleOps;
1568 case GK_SOUTHERN_ISLANDS:
1569 case GK_SEA_ISLANDS:
1570 DescriptionString = DescriptionStringSI;
1578 } // end anonymous namespace
1581 // Namespace for x86 abstract base class
1582 const Builtin::Info BuiltinInfo[] = {
1583 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1584 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1586 #include "clang/Basic/BuiltinsX86.def"
1589 static const char* const GCCRegNames[] = {
1590 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1591 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1592 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1593 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1594 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1595 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1596 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1597 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1598 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1601 const TargetInfo::AddlRegName AddlRegNames[] = {
1602 { { "al", "ah", "eax", "rax" }, 0 },
1603 { { "bl", "bh", "ebx", "rbx" }, 3 },
1604 { { "cl", "ch", "ecx", "rcx" }, 2 },
1605 { { "dl", "dh", "edx", "rdx" }, 1 },
1606 { { "esi", "rsi" }, 4 },
1607 { { "edi", "rdi" }, 5 },
1608 { { "esp", "rsp" }, 7 },
1609 { { "ebp", "rbp" }, 6 },
1612 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1613 // most of the implementation can be shared.
1614 class X86TargetInfo : public TargetInfo {
1616 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1619 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1641 bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
1645 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1647 /// Each enumeration represents a particular CPU supported by Clang. These
1648 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1653 /// i386-generation processors.
1659 /// i486-generation processors.
1668 /// i586-generation processors, P5 microarchitecture based.
1676 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1686 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1687 /// Clang however has some logic to suport this.
1688 // FIXME: Warn, deprecate, and potentially remove this.
1693 /// Netburst microarchitecture based processors.
1702 /// Core microarchitecture based processors.
1706 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1707 /// codename which GCC no longer accepts as an option to -march, but Clang
1708 /// has some logic for recognizing it.
1709 // FIXME: Warn, deprecate, and potentially remove this.
1721 /// Nehalem microarchitecture based processors.
1729 /// \name Knights Landing
1730 /// Knights Landing processor.
1734 /// K6 architecture processors.
1742 /// K7 architecture processors.
1745 CK_AthlonThunderbird,
1752 /// K8 architecture processors.
1765 /// Bobcat architecture processors.
1772 /// Bulldozer architecture processors.
1779 /// This specification is deprecated and will be removed in the future.
1780 /// Users should prefer \see CK_K8.
1781 // FIXME: Warn on this when the CPU is set to it.
1786 /// Geode processors.
1799 X86TargetInfo(const llvm::Triple &Triple)
1800 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1801 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1802 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1803 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
1804 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
1805 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
1806 FPMath(FP_Default) {
1808 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1810 virtual unsigned getFloatEvalMethod() const {
1811 // X87 evaluates with 80 bits "long double" precision.
1812 return SSELevel == NoSSE ? 2 : 0;
1814 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1815 unsigned &NumRecords) const {
1816 Records = BuiltinInfo;
1817 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1819 virtual void getGCCRegNames(const char * const *&Names,
1820 unsigned &NumNames) const {
1821 Names = GCCRegNames;
1822 NumNames = llvm::array_lengthof(GCCRegNames);
1824 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1825 unsigned &NumAliases) const {
1829 virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1830 unsigned &NumNames) const {
1831 Names = AddlRegNames;
1832 NumNames = llvm::array_lengthof(AddlRegNames);
1834 virtual bool validateAsmConstraint(const char *&Name,
1835 TargetInfo::ConstraintInfo &info) const;
1836 virtual std::string convertConstraint(const char *&Constraint) const;
1837 virtual const char *getClobbers() const {
1838 return "~{dirflag},~{fpsr},~{flags}";
1840 virtual void getTargetDefines(const LangOptions &Opts,
1841 MacroBuilder &Builder) const;
1842 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1844 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1846 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1848 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features,
1849 StringRef Name, bool Enabled) const {
1850 setFeatureEnabledImpl(Features, Name, Enabled);
1852 // This exists purely to cut down on the number of virtual calls in
1853 // getDefaultFeatures which calls this repeatedly.
1854 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1855 StringRef Name, bool Enabled);
1856 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1857 virtual bool hasFeature(StringRef Feature) const;
1858 virtual bool handleTargetFeatures(std::vector<std::string> &Features,
1859 DiagnosticsEngine &Diags);
1860 virtual const char* getABI() const {
1861 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1863 else if (getTriple().getArch() == llvm::Triple::x86 &&
1864 MMX3DNowLevel == NoMMX3DNow)
1868 virtual bool setCPU(const std::string &Name) {
1869 CPU = llvm::StringSwitch<CPUKind>(Name)
1870 .Case("i386", CK_i386)
1871 .Case("i486", CK_i486)
1872 .Case("winchip-c6", CK_WinChipC6)
1873 .Case("winchip2", CK_WinChip2)
1875 .Case("i586", CK_i586)
1876 .Case("pentium", CK_Pentium)
1877 .Case("pentium-mmx", CK_PentiumMMX)
1878 .Case("i686", CK_i686)
1879 .Case("pentiumpro", CK_PentiumPro)
1880 .Case("pentium2", CK_Pentium2)
1881 .Case("pentium3", CK_Pentium3)
1882 .Case("pentium3m", CK_Pentium3M)
1883 .Case("pentium-m", CK_PentiumM)
1884 .Case("c3-2", CK_C3_2)
1885 .Case("yonah", CK_Yonah)
1886 .Case("pentium4", CK_Pentium4)
1887 .Case("pentium4m", CK_Pentium4M)
1888 .Case("prescott", CK_Prescott)
1889 .Case("nocona", CK_Nocona)
1890 .Case("core2", CK_Core2)
1891 .Case("penryn", CK_Penryn)
1892 .Case("atom", CK_Atom)
1893 .Case("slm", CK_Silvermont)
1894 .Case("corei7", CK_Corei7)
1895 .Case("corei7-avx", CK_Corei7AVX)
1896 .Case("core-avx-i", CK_CoreAVXi)
1897 .Case("core-avx2", CK_CoreAVX2)
1898 .Case("knl", CK_KNL)
1900 .Case("k6-2", CK_K6_2)
1901 .Case("k6-3", CK_K6_3)
1902 .Case("athlon", CK_Athlon)
1903 .Case("athlon-tbird", CK_AthlonThunderbird)
1904 .Case("athlon-4", CK_Athlon4)
1905 .Case("athlon-xp", CK_AthlonXP)
1906 .Case("athlon-mp", CK_AthlonMP)
1907 .Case("athlon64", CK_Athlon64)
1908 .Case("athlon64-sse3", CK_Athlon64SSE3)
1909 .Case("athlon-fx", CK_AthlonFX)
1911 .Case("k8-sse3", CK_K8SSE3)
1912 .Case("opteron", CK_Opteron)
1913 .Case("opteron-sse3", CK_OpteronSSE3)
1914 .Case("amdfam10", CK_AMDFAM10)
1915 .Case("btver1", CK_BTVER1)
1916 .Case("btver2", CK_BTVER2)
1917 .Case("bdver1", CK_BDVER1)
1918 .Case("bdver2", CK_BDVER2)
1919 .Case("bdver3", CK_BDVER3)
1920 .Case("x86-64", CK_x86_64)
1921 .Case("geode", CK_Geode)
1922 .Default(CK_Generic);
1924 // Perform any per-CPU checks necessary to determine if this CPU is
1926 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1927 // invalid without explaining *why*.
1930 // No processor selected!
1956 case CK_AthlonThunderbird:
1961 // Only accept certain architectures when compiling in 32-bit mode.
1962 if (getTriple().getArch() != llvm::Triple::x86)
1977 case CK_Athlon64SSE3:
1982 case CK_OpteronSSE3:
1992 llvm_unreachable("Unhandled CPU kind");
1995 virtual bool setFPMath(StringRef Name);
1997 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1998 // We accept all non-ARM calling conventions
1999 return (CC == CC_X86ThisCall ||
2000 CC == CC_X86FastCall ||
2001 CC == CC_X86StdCall ||
2003 CC == CC_X86Pascal ||
2004 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2007 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2008 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2012 bool X86TargetInfo::setFPMath(StringRef Name) {
2013 if (Name == "387") {
2017 if (Name == "sse") {
2024 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2025 // FIXME: This *really* should not be here.
2027 // X86_64 always has SSE2.
2028 if (getTriple().getArch() == llvm::Triple::x86_64)
2029 setFeatureEnabledImpl(Features, "sse2", true);
2042 setFeatureEnabledImpl(Features, "mmx", true);
2046 setFeatureEnabledImpl(Features, "sse", true);
2052 setFeatureEnabledImpl(Features, "sse2", true);
2057 setFeatureEnabledImpl(Features, "sse3", true);
2058 setFeatureEnabledImpl(Features, "cx16", true);
2061 setFeatureEnabledImpl(Features, "ssse3", true);
2062 setFeatureEnabledImpl(Features, "cx16", true);
2065 setFeatureEnabledImpl(Features, "sse4.1", true);
2066 setFeatureEnabledImpl(Features, "cx16", true);
2069 setFeatureEnabledImpl(Features, "ssse3", true);
2070 setFeatureEnabledImpl(Features, "cx16", true);
2073 setFeatureEnabledImpl(Features, "sse4.2", true);
2074 setFeatureEnabledImpl(Features, "aes", true);
2075 setFeatureEnabledImpl(Features, "cx16", true);
2076 setFeatureEnabledImpl(Features, "pclmul", true);
2079 setFeatureEnabledImpl(Features, "sse4.2", true);
2080 setFeatureEnabledImpl(Features, "cx16", true);
2083 setFeatureEnabledImpl(Features, "avx", true);
2084 setFeatureEnabledImpl(Features, "aes", true);
2085 setFeatureEnabledImpl(Features, "cx16", true);
2086 setFeatureEnabledImpl(Features, "pclmul", true);
2089 setFeatureEnabledImpl(Features, "avx", true);
2090 setFeatureEnabledImpl(Features, "aes", true);
2091 setFeatureEnabledImpl(Features, "pclmul", true);
2092 setFeatureEnabledImpl(Features, "rdrnd", true);
2093 setFeatureEnabledImpl(Features, "f16c", true);
2096 setFeatureEnabledImpl(Features, "avx2", true);
2097 setFeatureEnabledImpl(Features, "aes", true);
2098 setFeatureEnabledImpl(Features, "pclmul", true);
2099 setFeatureEnabledImpl(Features, "lzcnt", true);
2100 setFeatureEnabledImpl(Features, "rdrnd", true);
2101 setFeatureEnabledImpl(Features, "f16c", true);
2102 setFeatureEnabledImpl(Features, "bmi", true);
2103 setFeatureEnabledImpl(Features, "bmi2", true);
2104 setFeatureEnabledImpl(Features, "rtm", true);
2105 setFeatureEnabledImpl(Features, "fma", true);
2106 setFeatureEnabledImpl(Features, "cx16", true);
2109 setFeatureEnabledImpl(Features, "avx512f", true);
2110 setFeatureEnabledImpl(Features, "avx512cd", true);
2111 setFeatureEnabledImpl(Features, "avx512er", true);
2112 setFeatureEnabledImpl(Features, "avx512pf", true);
2113 setFeatureEnabledImpl(Features, "aes", true);
2114 setFeatureEnabledImpl(Features, "pclmul", true);
2115 setFeatureEnabledImpl(Features, "lzcnt", true);
2116 setFeatureEnabledImpl(Features, "rdrnd", true);
2117 setFeatureEnabledImpl(Features, "f16c", true);
2118 setFeatureEnabledImpl(Features, "bmi", true);
2119 setFeatureEnabledImpl(Features, "bmi2", true);
2120 setFeatureEnabledImpl(Features, "rtm", true);
2121 setFeatureEnabledImpl(Features, "fma", true);
2125 setFeatureEnabledImpl(Features, "mmx", true);
2131 setFeatureEnabledImpl(Features, "3dnow", true);
2134 case CK_AthlonThunderbird:
2136 setFeatureEnabledImpl(Features, "3dnowa", true);
2141 setFeatureEnabledImpl(Features, "sse", true);
2142 setFeatureEnabledImpl(Features, "3dnowa", true);
2148 setFeatureEnabledImpl(Features, "sse2", true);
2149 setFeatureEnabledImpl(Features, "3dnowa", true);
2152 case CK_OpteronSSE3:
2153 case CK_Athlon64SSE3:
2154 setFeatureEnabledImpl(Features, "sse3", true);
2155 setFeatureEnabledImpl(Features, "3dnowa", true);
2158 setFeatureEnabledImpl(Features, "sse3", true);
2159 setFeatureEnabledImpl(Features, "sse4a", true);
2160 setFeatureEnabledImpl(Features, "3dnowa", true);
2161 setFeatureEnabledImpl(Features, "lzcnt", true);
2162 setFeatureEnabledImpl(Features, "popcnt", true);
2165 setFeatureEnabledImpl(Features, "ssse3", true);
2166 setFeatureEnabledImpl(Features, "sse4a", true);
2167 setFeatureEnabledImpl(Features, "cx16", true);
2168 setFeatureEnabledImpl(Features, "lzcnt", true);
2169 setFeatureEnabledImpl(Features, "popcnt", true);
2170 setFeatureEnabledImpl(Features, "prfchw", true);
2173 setFeatureEnabledImpl(Features, "avx", true);
2174 setFeatureEnabledImpl(Features, "sse4a", true);
2175 setFeatureEnabledImpl(Features, "lzcnt", true);
2176 setFeatureEnabledImpl(Features, "aes", true);
2177 setFeatureEnabledImpl(Features, "pclmul", true);
2178 setFeatureEnabledImpl(Features, "prfchw", true);
2179 setFeatureEnabledImpl(Features, "bmi", true);
2180 setFeatureEnabledImpl(Features, "f16c", true);
2181 setFeatureEnabledImpl(Features, "cx16", true);
2184 setFeatureEnabledImpl(Features, "xop", true);
2185 setFeatureEnabledImpl(Features, "lzcnt", true);
2186 setFeatureEnabledImpl(Features, "aes", true);
2187 setFeatureEnabledImpl(Features, "pclmul", true);
2188 setFeatureEnabledImpl(Features, "prfchw", true);
2189 setFeatureEnabledImpl(Features, "cx16", true);
2193 setFeatureEnabledImpl(Features, "xop", true);
2194 setFeatureEnabledImpl(Features, "lzcnt", true);
2195 setFeatureEnabledImpl(Features, "aes", true);
2196 setFeatureEnabledImpl(Features, "pclmul", true);
2197 setFeatureEnabledImpl(Features, "prfchw", true);
2198 setFeatureEnabledImpl(Features, "bmi", true);
2199 setFeatureEnabledImpl(Features, "fma", true);
2200 setFeatureEnabledImpl(Features, "f16c", true);
2201 setFeatureEnabledImpl(Features, "tbm", true);
2202 setFeatureEnabledImpl(Features, "cx16", true);
2205 setFeatureEnabledImpl(Features, "sse", true);
2210 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2211 X86SSEEnum Level, bool Enabled) {
2215 Features["avx512f"] = true;
2217 Features["avx2"] = true;
2219 Features["avx"] = true;
2221 Features["sse4.2"] = true;
2223 Features["sse4.1"] = true;
2225 Features["ssse3"] = true;
2227 Features["sse3"] = true;
2229 Features["sse2"] = true;
2231 Features["sse"] = true;
2241 Features["sse"] = false;
2243 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2244 Features["sha"] = false;
2246 Features["sse3"] = false;
2247 setXOPLevel(Features, NoXOP, false);
2249 Features["ssse3"] = false;
2251 Features["sse4.1"] = false;
2253 Features["sse4.2"] = false;
2255 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2256 setXOPLevel(Features, FMA4, false);
2258 Features["avx2"] = false;
2260 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2261 Features["avx512pf"] = false;
2265 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2266 MMX3DNowEnum Level, bool Enabled) {
2269 case AMD3DNowAthlon:
2270 Features["3dnowa"] = true;
2272 Features["3dnow"] = true;
2274 Features["mmx"] = true;
2284 Features["mmx"] = false;
2286 Features["3dnow"] = false;
2287 case AMD3DNowAthlon:
2288 Features["3dnowa"] = false;
2292 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2297 Features["xop"] = true;
2299 Features["fma4"] = true;
2300 setSSELevel(Features, AVX, true);
2302 Features["sse4a"] = true;
2303 setSSELevel(Features, SSE3, true);
2313 Features["sse4a"] = false;
2315 Features["fma4"] = false;
2317 Features["xop"] = false;
2321 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2322 StringRef Name, bool Enabled) {
2323 // FIXME: This *really* should not be here. We need some way of translating
2324 // options into llvm subtarget features.
2328 Features[Name] = Enabled;
2330 if (Name == "mmx") {
2331 setMMXLevel(Features, MMX, Enabled);
2332 } else if (Name == "sse") {
2333 setSSELevel(Features, SSE1, Enabled);
2334 } else if (Name == "sse2") {
2335 setSSELevel(Features, SSE2, Enabled);
2336 } else if (Name == "sse3") {
2337 setSSELevel(Features, SSE3, Enabled);
2338 } else if (Name == "ssse3") {
2339 setSSELevel(Features, SSSE3, Enabled);
2340 } else if (Name == "sse4.2") {
2341 setSSELevel(Features, SSE42, Enabled);
2342 } else if (Name == "sse4.1") {
2343 setSSELevel(Features, SSE41, Enabled);
2344 } else if (Name == "3dnow") {
2345 setMMXLevel(Features, AMD3DNow, Enabled);
2346 } else if (Name == "3dnowa") {
2347 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2348 } else if (Name == "aes") {
2350 setSSELevel(Features, SSE2, Enabled);
2351 } else if (Name == "pclmul") {
2353 setSSELevel(Features, SSE2, Enabled);
2354 } else if (Name == "avx") {
2355 setSSELevel(Features, AVX, Enabled);
2356 } else if (Name == "avx2") {
2357 setSSELevel(Features, AVX2, Enabled);
2358 } else if (Name == "avx512f") {
2359 setSSELevel(Features, AVX512F, Enabled);
2360 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
2362 setSSELevel(Features, AVX512F, Enabled);
2363 } else if (Name == "fma") {
2365 setSSELevel(Features, AVX, Enabled);
2366 } else if (Name == "fma4") {
2367 setXOPLevel(Features, FMA4, Enabled);
2368 } else if (Name == "xop") {
2369 setXOPLevel(Features, XOP, Enabled);
2370 } else if (Name == "sse4a") {
2371 setXOPLevel(Features, SSE4A, Enabled);
2372 } else if (Name == "f16c") {
2374 setSSELevel(Features, AVX, Enabled);
2375 } else if (Name == "sha") {
2377 setSSELevel(Features, SSE2, Enabled);
2381 /// handleTargetFeatures - Perform initialization based on the user
2382 /// configured set of features.
2383 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2384 DiagnosticsEngine &Diags) {
2385 // Remember the maximum enabled sselevel.
2386 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2387 // Ignore disabled features.
2388 if (Features[i][0] == '-')
2391 StringRef Feature = StringRef(Features[i]).substr(1);
2393 if (Feature == "aes") {
2398 if (Feature == "pclmul") {
2403 if (Feature == "lzcnt") {
2408 if (Feature == "rdrnd") {
2413 if (Feature == "bmi") {
2418 if (Feature == "bmi2") {
2423 if (Feature == "popcnt") {
2428 if (Feature == "rtm") {
2433 if (Feature == "prfchw") {
2438 if (Feature == "rdseed") {
2443 if (Feature == "tbm") {
2448 if (Feature == "fma") {
2453 if (Feature == "f16c") {
2458 if (Feature == "avx512cd") {
2463 if (Feature == "avx512er") {
2468 if (Feature == "avx512pf") {
2473 if (Feature == "sha") {
2478 if (Feature == "cx16") {
2483 assert(Features[i][0] == '+' && "Invalid target feature!");
2484 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2485 .Case("avx512f", AVX512F)
2488 .Case("sse4.2", SSE42)
2489 .Case("sse4.1", SSE41)
2490 .Case("ssse3", SSSE3)
2495 SSELevel = std::max(SSELevel, Level);
2497 MMX3DNowEnum ThreeDNowLevel =
2498 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2499 .Case("3dnowa", AMD3DNowAthlon)
2500 .Case("3dnow", AMD3DNow)
2502 .Default(NoMMX3DNow);
2503 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2505 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2508 .Case("sse4a", SSE4A)
2510 XOPLevel = std::max(XOPLevel, XLevel);
2513 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2514 // Can't do this earlier because we need to be able to explicitly enable
2515 // popcnt and still disable sse4.2.
2516 if (!HasPOPCNT && SSELevel >= SSE42 &&
2517 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2519 Features.push_back("+popcnt");
2522 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2523 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2524 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2526 Features.push_back("+prfchw");
2529 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2530 // matches the selected sse level.
2531 if (FPMath == FP_SSE && SSELevel < SSE1) {
2532 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2534 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2535 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2539 // Don't tell the backend if we're turning off mmx; it will end up disabling
2540 // SSE, which we don't want.
2541 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2543 std::vector<std::string>::iterator it;
2544 it = std::find(Features.begin(), Features.end(), "-mmx");
2545 if (it != Features.end())
2547 else if (SSELevel > NoSSE)
2548 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2552 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2553 /// definitions for this particular subtarget.
2554 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2555 MacroBuilder &Builder) const {
2556 // Target identification.
2557 if (getTriple().getArch() == llvm::Triple::x86_64) {
2558 Builder.defineMacro("__amd64__");
2559 Builder.defineMacro("__amd64");
2560 Builder.defineMacro("__x86_64");
2561 Builder.defineMacro("__x86_64__");
2563 DefineStd(Builder, "i386", Opts);
2566 // Subtarget options.
2567 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2568 // truly should be based on -mtune options.
2573 // The rest are coming from the i386 define above.
2574 Builder.defineMacro("__tune_i386__");
2580 defineCPUMacros(Builder, "i486");
2583 Builder.defineMacro("__pentium_mmx__");
2584 Builder.defineMacro("__tune_pentium_mmx__");
2588 defineCPUMacros(Builder, "i586");
2589 defineCPUMacros(Builder, "pentium");
2594 Builder.defineMacro("__tune_pentium3__");
2598 Builder.defineMacro("__tune_pentium2__");
2601 Builder.defineMacro("__tune_i686__");
2602 Builder.defineMacro("__tune_pentiumpro__");
2605 Builder.defineMacro("__i686");
2606 Builder.defineMacro("__i686__");
2607 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2608 Builder.defineMacro("__pentiumpro");
2609 Builder.defineMacro("__pentiumpro__");
2613 defineCPUMacros(Builder, "pentium4");
2618 defineCPUMacros(Builder, "nocona");
2622 defineCPUMacros(Builder, "core2");
2625 defineCPUMacros(Builder, "atom");
2628 defineCPUMacros(Builder, "slm");
2634 defineCPUMacros(Builder, "corei7");
2637 defineCPUMacros(Builder, "knl");
2640 Builder.defineMacro("__k6_2__");
2641 Builder.defineMacro("__tune_k6_2__");
2644 if (CPU != CK_K6_2) { // In case of fallthrough
2645 // FIXME: GCC may be enabling these in cases where some other k6
2646 // architecture is specified but -m3dnow is explicitly provided. The
2647 // exact semantics need to be determined and emulated here.
2648 Builder.defineMacro("__k6_3__");
2649 Builder.defineMacro("__tune_k6_3__");
2653 defineCPUMacros(Builder, "k6");
2656 case CK_AthlonThunderbird:
2660 defineCPUMacros(Builder, "athlon");
2661 if (SSELevel != NoSSE) {
2662 Builder.defineMacro("__athlon_sse__");
2663 Builder.defineMacro("__tune_athlon_sse__");
2670 case CK_OpteronSSE3:
2672 case CK_Athlon64SSE3:
2674 defineCPUMacros(Builder, "k8");
2677 defineCPUMacros(Builder, "amdfam10");
2680 defineCPUMacros(Builder, "btver1");
2683 defineCPUMacros(Builder, "btver2");
2686 defineCPUMacros(Builder, "bdver1");
2689 defineCPUMacros(Builder, "bdver2");
2692 defineCPUMacros(Builder, "bdver3");
2695 defineCPUMacros(Builder, "geode");
2699 // Target properties.
2700 Builder.defineMacro("__LITTLE_ENDIAN__");
2701 Builder.defineMacro("__REGISTER_PREFIX__", "");
2703 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2704 // functions in glibc header files that use FP Stack inline asm which the
2705 // backend can't deal with (PR879).
2706 Builder.defineMacro("__NO_MATH_INLINES");
2709 Builder.defineMacro("__AES__");
2712 Builder.defineMacro("__PCLMUL__");
2715 Builder.defineMacro("__LZCNT__");
2718 Builder.defineMacro("__RDRND__");
2721 Builder.defineMacro("__BMI__");
2724 Builder.defineMacro("__BMI2__");
2727 Builder.defineMacro("__POPCNT__");
2730 Builder.defineMacro("__RTM__");
2733 Builder.defineMacro("__PRFCHW__");
2736 Builder.defineMacro("__RDSEED__");
2739 Builder.defineMacro("__TBM__");
2743 Builder.defineMacro("__XOP__");
2745 Builder.defineMacro("__FMA4__");
2747 Builder.defineMacro("__SSE4A__");
2753 Builder.defineMacro("__FMA__");
2756 Builder.defineMacro("__F16C__");
2759 Builder.defineMacro("__AVX512CD__");
2761 Builder.defineMacro("__AVX512ER__");
2763 Builder.defineMacro("__AVX512PF__");
2766 Builder.defineMacro("__SHA__");
2769 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2771 // Each case falls through to the previous one here.
2774 Builder.defineMacro("__AVX512F__");
2776 Builder.defineMacro("__AVX2__");
2778 Builder.defineMacro("__AVX__");
2780 Builder.defineMacro("__SSE4_2__");
2782 Builder.defineMacro("__SSE4_1__");
2784 Builder.defineMacro("__SSSE3__");
2786 Builder.defineMacro("__SSE3__");
2788 Builder.defineMacro("__SSE2__");
2789 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
2791 Builder.defineMacro("__SSE__");
2792 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
2797 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2807 Builder.defineMacro("_M_IX86_FP", Twine(2));
2810 Builder.defineMacro("_M_IX86_FP", Twine(1));
2813 Builder.defineMacro("_M_IX86_FP", Twine(0));
2817 // Each case falls through to the previous one here.
2818 switch (MMX3DNowLevel) {
2819 case AMD3DNowAthlon:
2820 Builder.defineMacro("__3dNOW_A__");
2822 Builder.defineMacro("__3dNOW__");
2824 Builder.defineMacro("__MMX__");
2829 if (CPU >= CK_i486) {
2830 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2835 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2838 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2839 return llvm::StringSwitch<bool>(Feature)
2840 .Case("aes", HasAES)
2841 .Case("avx", SSELevel >= AVX)
2842 .Case("avx2", SSELevel >= AVX2)
2843 .Case("avx512f", SSELevel >= AVX512F)
2844 .Case("avx512cd", HasAVX512CD)
2845 .Case("avx512er", HasAVX512ER)
2846 .Case("avx512pf", HasAVX512PF)
2847 .Case("bmi", HasBMI)
2848 .Case("bmi2", HasBMI2)
2849 .Case("cx16", HasCX16)
2850 .Case("f16c", HasF16C)
2851 .Case("fma", HasFMA)
2852 .Case("fma4", XOPLevel >= FMA4)
2853 .Case("tbm", HasTBM)
2854 .Case("lzcnt", HasLZCNT)
2855 .Case("rdrnd", HasRDRND)
2856 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2857 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2858 .Case("mmx", MMX3DNowLevel >= MMX)
2859 .Case("pclmul", HasPCLMUL)
2860 .Case("popcnt", HasPOPCNT)
2861 .Case("rtm", HasRTM)
2862 .Case("prfchw", HasPRFCHW)
2863 .Case("rdseed", HasRDSEED)
2864 .Case("sha", HasSHA)
2865 .Case("sse", SSELevel >= SSE1)
2866 .Case("sse2", SSELevel >= SSE2)
2867 .Case("sse3", SSELevel >= SSE3)
2868 .Case("ssse3", SSELevel >= SSSE3)
2869 .Case("sse4.1", SSELevel >= SSE41)
2870 .Case("sse4.2", SSELevel >= SSE42)
2871 .Case("sse4a", XOPLevel >= SSE4A)
2873 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2874 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2875 .Case("xop", XOPLevel >= XOP)
2880 X86TargetInfo::validateAsmConstraint(const char *&Name,
2881 TargetInfo::ConstraintInfo &Info) const {
2883 default: return false;
2884 case 'Y': // first letter of a pair:
2885 switch (*(Name+1)) {
2886 default: return false;
2887 case '0': // First SSE register.
2888 case 't': // Any SSE register, when SSE2 is enabled.
2889 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
2890 case 'm': // any MMX register, when inter-unit moves enabled.
2891 break; // falls through to setAllowsRegister.
2899 case 'A': // edx:eax.
2900 case 'f': // any x87 floating point stack register.
2901 case 't': // top of floating point stack.
2902 case 'u': // second from top of floating point stack.
2903 case 'q': // Any register accessible as [r]l: a, b, c, and d.
2904 case 'y': // Any MMX register.
2905 case 'x': // Any SSE register.
2906 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2907 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2908 case 'l': // "Index" registers: any general register that can be used as an
2909 // index in a base+index memory access.
2910 Info.setAllowsRegister();
2912 case 'C': // SSE floating point constant.
2913 case 'G': // x87 floating point constant.
2914 case 'e': // 32-bit signed integer constant for use with zero-extending
2915 // x86_64 instructions.
2916 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2917 // x86_64 instructions.
2924 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2925 switch (*Constraint) {
2926 case 'a': return std::string("{ax}");
2927 case 'b': return std::string("{bx}");
2928 case 'c': return std::string("{cx}");
2929 case 'd': return std::string("{dx}");
2930 case 'S': return std::string("{si}");
2931 case 'D': return std::string("{di}");
2932 case 'p': // address
2933 return std::string("im");
2934 case 't': // top of floating point stack.
2935 return std::string("{st}");
2936 case 'u': // second from top of floating point stack.
2937 return std::string("{st(1)}"); // second from top of floating point stack.
2939 return std::string(1, *Constraint);
2942 } // end anonymous namespace
2945 // X86-32 generic target
2946 class X86_32TargetInfo : public X86TargetInfo {
2948 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2949 DoubleAlign = LongLongAlign = 32;
2950 LongDoubleWidth = 96;
2951 LongDoubleAlign = 32;
2952 SuitableAlign = 128;
2953 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2954 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2955 "a0:0:64-f80:32:32-n8:16:32-S128";
2956 SizeType = UnsignedInt;
2957 PtrDiffType = SignedInt;
2958 IntPtrType = SignedInt;
2961 // Use fpret for all types.
2962 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2963 (1 << TargetInfo::Double) |
2964 (1 << TargetInfo::LongDouble));
2966 // x86-32 has atomics up to 8 bytes
2967 // FIXME: Check that we actually have cmpxchg8b before setting
2968 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2969 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2971 virtual BuiltinVaListKind getBuiltinVaListKind() const {
2972 return TargetInfo::CharPtrBuiltinVaList;
2975 int getEHDataRegisterNumber(unsigned RegNo) const {
2976 if (RegNo == 0) return 0;
2977 if (RegNo == 1) return 2;
2980 virtual bool validateInputSize(StringRef Constraint,
2981 unsigned Size) const {
2982 switch (Constraint[0]) {
2994 } // end anonymous namespace
2997 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2999 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3000 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3002 virtual unsigned getFloatEvalMethod() const {
3003 unsigned Major, Minor, Micro;
3004 getTriple().getOSVersion(Major, Minor, Micro);
3005 // New NetBSD uses the default rounding mode.
3006 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3007 return X86_32TargetInfo::getFloatEvalMethod();
3008 // NetBSD before 6.99.26 defaults to "double" rounding.
3012 } // end anonymous namespace
3015 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3017 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3018 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3019 SizeType = UnsignedLong;
3020 IntPtrType = SignedLong;
3021 PtrDiffType = SignedLong;
3024 } // end anonymous namespace
3027 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3029 BitrigI386TargetInfo(const llvm::Triple &Triple)
3030 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3031 SizeType = UnsignedLong;
3032 IntPtrType = SignedLong;
3033 PtrDiffType = SignedLong;
3036 } // end anonymous namespace
3039 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3041 DarwinI386TargetInfo(const llvm::Triple &Triple)
3042 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3043 LongDoubleWidth = 128;
3044 LongDoubleAlign = 128;
3045 SuitableAlign = 128;
3046 MaxVectorAlign = 256;
3047 SizeType = UnsignedLong;
3048 IntPtrType = SignedLong;
3049 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3050 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
3051 "a0:0:64-f80:128:128-n8:16:32-S128";
3052 HasAlignMac68kSupport = true;
3056 } // end anonymous namespace
3059 // x86-32 Windows target
3060 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3062 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3063 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3064 TLSSupported = false;
3065 WCharType = UnsignedShort;
3066 DoubleAlign = LongLongAlign = 64;
3067 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3068 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
3069 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
3071 virtual void getTargetDefines(const LangOptions &Opts,
3072 MacroBuilder &Builder) const {
3073 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3076 } // end anonymous namespace
3080 // x86-32 Windows Visual Studio target
3081 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
3083 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
3084 : WindowsX86_32TargetInfo(Triple) {
3085 LongDoubleWidth = LongDoubleAlign = 64;
3086 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3088 virtual void getTargetDefines(const LangOptions &Opts,
3089 MacroBuilder &Builder) const {
3090 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3091 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3092 // The value of the following reflects processor type.
3093 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3094 // We lost the original triple, so we use the default.
3095 Builder.defineMacro("_M_IX86", "600");
3098 } // end anonymous namespace
3101 // x86-32 MinGW target
3102 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3104 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3105 : WindowsX86_32TargetInfo(Triple) {}
3106 virtual void getTargetDefines(const LangOptions &Opts,
3107 MacroBuilder &Builder) const {
3108 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3109 DefineStd(Builder, "WIN32", Opts);
3110 DefineStd(Builder, "WINNT", Opts);
3111 Builder.defineMacro("_X86_");
3112 Builder.defineMacro("__MSVCRT__");
3113 Builder.defineMacro("__MINGW32__");
3115 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3116 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3117 if (Opts.MicrosoftExt)
3118 // Provide "as-is" __declspec.
3119 Builder.defineMacro("__declspec", "__declspec");
3121 // Provide alias of __attribute__ like mingw32-gcc.
3122 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3125 } // end anonymous namespace
3128 // x86-32 Cygwin target
3129 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3131 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3132 : X86_32TargetInfo(Triple) {
3133 TLSSupported = false;
3134 WCharType = UnsignedShort;
3135 DoubleAlign = LongLongAlign = 64;
3136 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3137 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3138 "a0:0:64-f80:32:32-n8:16:32-S32";
3140 virtual void getTargetDefines(const LangOptions &Opts,
3141 MacroBuilder &Builder) const {
3142 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3143 Builder.defineMacro("_X86_");
3144 Builder.defineMacro("__CYGWIN__");
3145 Builder.defineMacro("__CYGWIN32__");
3146 DefineStd(Builder, "unix", Opts);
3148 Builder.defineMacro("_GNU_SOURCE");
3151 } // end anonymous namespace
3154 // x86-32 Haiku target
3155 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3157 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3158 SizeType = UnsignedLong;
3159 IntPtrType = SignedLong;
3160 PtrDiffType = SignedLong;
3161 ProcessIDType = SignedLong;
3162 this->UserLabelPrefix = "";
3163 this->TLSSupported = false;
3165 virtual void getTargetDefines(const LangOptions &Opts,
3166 MacroBuilder &Builder) const {
3167 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3168 Builder.defineMacro("__INTEL__");
3169 Builder.defineMacro("__HAIKU__");
3172 } // end anonymous namespace
3175 template<typename Target>
3176 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3178 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3179 MacroBuilder &Builder) const {
3180 // RTEMS defines; list based off of gcc output
3182 Builder.defineMacro("__rtems__");
3183 Builder.defineMacro("__ELF__");
3187 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3188 this->UserLabelPrefix = "";
3190 switch (Triple.getArch()) {
3192 case llvm::Triple::x86:
3193 // this->MCountName = ".mcount";
3195 case llvm::Triple::mips:
3196 case llvm::Triple::mipsel:
3197 case llvm::Triple::ppc:
3198 case llvm::Triple::ppc64:
3199 case llvm::Triple::ppc64le:
3200 // this->MCountName = "_mcount";
3202 case llvm::Triple::arm:
3203 // this->MCountName = "__mcount";
3210 // x86-32 RTEMS target
3211 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3213 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3214 SizeType = UnsignedLong;
3215 IntPtrType = SignedLong;
3216 PtrDiffType = SignedLong;
3217 this->UserLabelPrefix = "";
3219 virtual void getTargetDefines(const LangOptions &Opts,
3220 MacroBuilder &Builder) const {
3221 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3222 Builder.defineMacro("__INTEL__");
3223 Builder.defineMacro("__rtems__");
3226 } // end anonymous namespace
3229 // x86-64 generic target
3230 class X86_64TargetInfo : public X86TargetInfo {
3232 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3233 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3234 LongDoubleWidth = 128;
3235 LongDoubleAlign = 128;
3236 LargeArrayMinWidth = 128;
3237 LargeArrayAlign = 128;
3238 SuitableAlign = 128;
3239 IntMaxType = SignedLong;
3240 UIntMaxType = UnsignedLong;
3241 Int64Type = SignedLong;
3244 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3245 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3246 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3248 // Use fpret only for long double.
3249 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3251 // Use fp2ret for _Complex long double.
3252 ComplexLongDoubleUsesFP2Ret = true;
3254 // x86-64 has atomics up to 16 bytes.
3255 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3256 // on CPUs with cmpxchg16b
3257 MaxAtomicPromoteWidth = 128;
3258 MaxAtomicInlineWidth = 64;
3260 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3261 return TargetInfo::X86_64ABIBuiltinVaList;
3264 int getEHDataRegisterNumber(unsigned RegNo) const {
3265 if (RegNo == 0) return 0;
3266 if (RegNo == 1) return 1;
3270 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3271 return (CC == CC_C ||
3272 CC == CC_IntelOclBicc ||
3273 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3276 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3281 } // end anonymous namespace
3284 // x86-64 Windows target
3285 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3287 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3288 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3289 TLSSupported = false;
3290 WCharType = UnsignedShort;
3291 LongWidth = LongAlign = 32;
3292 DoubleAlign = LongLongAlign = 64;
3293 IntMaxType = SignedLongLong;
3294 UIntMaxType = UnsignedLongLong;
3295 Int64Type = SignedLongLong;
3296 SizeType = UnsignedLongLong;
3297 PtrDiffType = SignedLongLong;
3298 IntPtrType = SignedLongLong;
3299 this->UserLabelPrefix = "";
3301 virtual void getTargetDefines(const LangOptions &Opts,
3302 MacroBuilder &Builder) const {
3303 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3304 Builder.defineMacro("_WIN64");
3306 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3307 return TargetInfo::CharPtrBuiltinVaList;
3309 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3310 return (CC == CC_C ||
3311 CC == CC_IntelOclBicc ||
3312 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3315 } // end anonymous namespace
3318 // x86-64 Windows Visual Studio target
3319 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3321 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
3322 : WindowsX86_64TargetInfo(Triple) {
3323 LongDoubleWidth = LongDoubleAlign = 64;
3324 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3326 virtual void getTargetDefines(const LangOptions &Opts,
3327 MacroBuilder &Builder) const {
3328 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3329 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3330 Builder.defineMacro("_M_X64");
3331 Builder.defineMacro("_M_AMD64");
3334 } // end anonymous namespace
3337 // x86-64 MinGW target
3338 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3340 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3341 : WindowsX86_64TargetInfo(Triple) {}
3342 virtual void getTargetDefines(const LangOptions &Opts,
3343 MacroBuilder &Builder) const {
3344 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3345 DefineStd(Builder, "WIN64", Opts);
3346 Builder.defineMacro("__MSVCRT__");
3347 Builder.defineMacro("__MINGW32__");
3348 Builder.defineMacro("__MINGW64__");
3350 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3351 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3352 if (Opts.MicrosoftExt)
3353 // Provide "as-is" __declspec.
3354 Builder.defineMacro("__declspec", "__declspec");
3356 // Provide alias of __attribute__ like mingw32-gcc.
3357 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3360 } // end anonymous namespace
3363 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3365 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3366 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3367 Int64Type = SignedLongLong;
3368 MaxVectorAlign = 256;
3371 } // end anonymous namespace
3374 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3376 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3377 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3378 IntMaxType = SignedLongLong;
3379 UIntMaxType = UnsignedLongLong;
3380 Int64Type = SignedLongLong;
3383 } // end anonymous namespace
3386 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3388 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3389 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3390 IntMaxType = SignedLongLong;
3391 UIntMaxType = UnsignedLongLong;
3392 Int64Type = SignedLongLong;
3398 class AArch64TargetInfo : public TargetInfo {
3399 static const char * const GCCRegNames[];
3400 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3409 static const Builtin::Info BuiltinInfo[];
3412 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3414 LongWidth = LongAlign = 64;
3415 LongDoubleWidth = LongDoubleAlign = 128;
3416 PointerWidth = PointerAlign = 64;
3417 SuitableAlign = 128;
3418 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3419 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3420 "f128:128:128-n32:64-S128";
3422 WCharType = UnsignedInt;
3423 LongDoubleFormat = &llvm::APFloat::IEEEquad;
3425 // AArch64 backend supports 64-bit operations at the moment. In principle
3426 // 128-bit is possible if register-pairs are used.
3427 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3429 TheCXXABI.set(TargetCXXABI::GenericAArch64);
3431 virtual void getTargetDefines(const LangOptions &Opts,
3432 MacroBuilder &Builder) const {
3433 // GCC defines theses currently
3434 Builder.defineMacro("__aarch64__");
3435 Builder.defineMacro("__AARCH64EL__");
3437 // ACLE predefines. Many can only have one possible value on v8 AArch64.
3438 Builder.defineMacro("__ARM_ACLE", "200");
3439 Builder.defineMacro("__ARM_ARCH", "8");
3440 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3442 Builder.defineMacro("__ARM_64BIT_STATE");
3443 Builder.defineMacro("__ARM_PCS_AAPCS64");
3444 Builder.defineMacro("__ARM_ARCH_ISA_A64");
3446 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3447 Builder.defineMacro("__ARM_FEATURE_CLZ");
3448 Builder.defineMacro("__ARM_FEATURE_FMA");
3449 Builder.defineMacro("__ARM_FEATURE_DIV");
3451 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
3453 // 0xe implies support for half, single and double precision operations.
3454 Builder.defineMacro("__ARM_FP", "0xe");
3456 // PCS specifies this for SysV variants, which is all we support. Other ABIs
3457 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3458 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3460 if (Opts.FastMath || Opts.FiniteMathOnly)
3461 Builder.defineMacro("__ARM_FP_FAST");
3463 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3464 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3466 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3467 Opts.ShortWChar ? "2" : "4");
3469 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3470 Opts.ShortEnums ? "1" : "4");
3473 Builder.defineMacro("__AARCH_BIG_ENDIAN");
3475 if (FPU == NeonMode) {
3476 Builder.defineMacro("__ARM_NEON");
3477 // 64-bit NEON supports half, single and double precision operations.
3478 Builder.defineMacro("__ARM_NEON_FP", "7");
3482 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
3485 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3486 unsigned &NumRecords) const {
3487 Records = BuiltinInfo;
3488 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3490 virtual bool hasFeature(StringRef Feature) const {
3491 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode);
3494 virtual bool setCPU(const std::string &Name) {
3495 return llvm::StringSwitch<bool>(Name)
3496 .Case("generic", true)
3497 .Cases("cortex-a53", "cortex-a57", true)
3501 virtual bool handleTargetFeatures(std::vector<std::string> &Features,
3502 DiagnosticsEngine &Diags) {
3505 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3506 if (Features[i] == "+neon")
3508 if (Features[i] == "+crypto")
3514 virtual void getGCCRegNames(const char *const *&Names,
3515 unsigned &NumNames) const;
3516 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3517 unsigned &NumAliases) const;
3519 virtual bool isCLZForZeroUndef() const { return false; }
3521 virtual bool validateAsmConstraint(const char *&Name,
3522 TargetInfo::ConstraintInfo &Info) const {
3524 default: return false;
3525 case 'w': // An FP/SIMD vector register
3526 Info.setAllowsRegister();
3528 case 'I': // Constant that can be used with an ADD instruction
3529 case 'J': // Constant that can be used with a SUB instruction
3530 case 'K': // Constant that can be used with a 32-bit logical instruction
3531 case 'L': // Constant that can be used with a 64-bit logical instruction
3532 case 'M': // Constant that can be used as a 32-bit MOV immediate
3533 case 'N': // Constant that can be used as a 64-bit MOV immediate
3534 case 'Y': // Floating point constant zero
3535 case 'Z': // Integer constant zero
3537 case 'Q': // A memory reference with base register and no offset
3538 Info.setAllowsMemory();
3540 case 'S': // A symbolic address
3541 Info.setAllowsRegister();
3544 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3545 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3546 // Usa: An absolute symbolic address
3547 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3548 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3552 virtual const char *getClobbers() const {
3553 // There are no AArch64 clobbers shared by all asm statements.
3557 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3558 return TargetInfo::AArch64ABIBuiltinVaList;
3562 const char * const AArch64TargetInfo::GCCRegNames[] = {
3563 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3564 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3565 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3566 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3568 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3569 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3570 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3571 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3573 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3574 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3575 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3576 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3578 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3579 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3580 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3581 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3583 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3584 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3585 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3586 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3588 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3589 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3590 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3591 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3593 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3594 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3595 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3596 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3599 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3600 unsigned &NumNames) const {
3601 Names = GCCRegNames;
3602 NumNames = llvm::array_lengthof(GCCRegNames);
3605 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3606 { { "x16" }, "ip0"},
3607 { { "x17" }, "ip1"},
3608 { { "x29" }, "fp" },
3612 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3613 unsigned &NumAliases) const {
3614 Aliases = GCCRegAliases;
3615 NumAliases = llvm::array_lengthof(GCCRegAliases);
3619 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3620 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3621 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3623 #include "clang/Basic/BuiltinsAArch64.def"
3626 } // end anonymous namespace
3629 class ARMTargetInfo : public TargetInfo {
3630 // Possible FPU choices.
3639 // Possible HWDiv features.
3641 HWDivThumb = (1 << 0),
3645 static bool FPUModeIsVFP(FPUMode Mode) {
3646 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3649 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3650 static const char * const GCCRegNames[];
3652 std::string ABI, CPU;
3662 unsigned IsAAPCS : 1;
3663 unsigned IsThumb : 1;
3666 // Initialized via features.
3667 unsigned SoftFloat : 1;
3668 unsigned SoftFloatABI : 1;
3672 static const Builtin::Info BuiltinInfo[];
3674 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3675 // On linux, binaries targeting old cpus call functions in libgcc to
3676 // perform atomic operations. The implementation in libgcc then calls into
3677 // the kernel which on armv6 and newer uses ldrex and strex. The net result
3678 // is that if we assume the kernel is at least as recent as the hardware,
3679 // it is safe to use atomic instructions on armv6 and newer.
3680 if (!T.isOSLinux() &&
3681 T.getOS() != llvm::Triple::FreeBSD &&
3682 T.getOS() != llvm::Triple::NetBSD &&
3683 T.getOS() != llvm::Triple::Bitrig)
3685 StringRef ArchName = T.getArchName();
3686 if (T.getArch() == llvm::Triple::arm) {
3687 if (!ArchName.startswith("armv"))
3689 StringRef VersionStr = ArchName.substr(4);
3691 if (VersionStr.getAsInteger(10, Version))
3693 return Version >= 6;
3695 assert(T.getArch() == llvm::Triple::thumb);
3696 if (!ArchName.startswith("thumbv"))
3698 StringRef VersionStr = ArchName.substr(6);
3700 if (VersionStr.getAsInteger(10, Version))
3702 return Version >= 7;
3706 ARMTargetInfo(const llvm::Triple &Triple)
3707 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"),
3708 FPMath(FP_Default), IsAAPCS(true) {
3710 switch (getTriple().getOS()) {
3711 case llvm::Triple::NetBSD:
3712 SizeType = UnsignedLong;
3713 PtrDiffType = SignedLong;
3714 WCharType = SignedInt;
3717 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3718 WCharType = UnsignedInt;
3719 SizeType = UnsignedInt;
3720 PtrDiffType = SignedInt;
3724 // {} in inline assembly are neon specifiers, not assembly variant
3726 NoAsmVariants = true;
3728 // FIXME: Should we just treat this as a feature?
3729 IsThumb = getTriple().getArchName().startswith("thumb");
3731 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3732 // so set preferred for small types to 32.
3733 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3734 "i64:64:64-f32:32:32-f64:64:64-"
3735 "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3737 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3738 "i64:64:64-f32:32:32-f64:64:64-"
3739 "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3742 // ARM targets default to using the ARM C++ ABI.
3743 TheCXXABI.set(TargetCXXABI::GenericARM);
3745 // ARM has atomics up to 8 bytes
3746 MaxAtomicPromoteWidth = 64;
3747 if (shouldUseInlineAtomic(getTriple()))
3748 MaxAtomicInlineWidth = 64;
3750 // Do force alignment of members that follow zero length bitfields. If
3751 // the alignment of the zero-length bitfield is greater than the member
3752 // that follows it, `bar', `bar' will be aligned as the type of the
3753 // zero length bitfield.
3754 UseZeroLengthBitfieldAlignment = true;
3756 virtual const char *getABI() const { return ABI.c_str(); }
3757 virtual bool setABI(const std::string &Name) {
3760 // The defaults (above) are for AAPCS, check if we need to change them.
3762 // FIXME: We need support for -meabi... we could just mangle it into the
3764 if (Name == "apcs-gnu") {
3765 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3766 // size_t is unsigned int on FreeBSD.
3767 if (getTriple().getOS() != llvm::Triple::FreeBSD)
3768 SizeType = UnsignedLong;
3770 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3771 WCharType = SignedInt;
3773 // Do not respect the alignment of bit-field types when laying out
3774 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3775 UseBitFieldTypeAlignment = false;
3777 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3778 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3780 ZeroLengthBitfieldBoundary = 32;
3785 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3786 // so set preferred for small types to 32.
3787 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3788 "i64:32:64-f32:32:32-f64:32:64-"
3789 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3791 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3792 "i64:32:64-f32:32:32-f64:32:64-"
3793 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3796 // FIXME: Override "preferred align" for double and long long.
3797 } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3798 // size_t is unsigned long on Darwin.
3799 if (getTriple().isOSDarwin())
3800 SizeType = UnsignedLong;
3802 // FIXME: Enumerated types are variable width in straight AAPCS.
3803 } else if (Name == "aapcs-linux") {
3811 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3812 StringRef ArchName = getTriple().getArchName();
3813 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3814 Features["vfp2"] = true;
3815 else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3816 CPU == "cortex-a9-mp") {
3817 Features["vfp3"] = true;
3818 Features["neon"] = true;
3820 else if (CPU == "cortex-a5") {
3821 Features["vfp4"] = true;
3822 Features["neon"] = true;
3823 } else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a15") {
3824 Features["vfp4"] = true;
3825 Features["neon"] = true;
3826 Features["hwdiv"] = true;
3827 Features["hwdiv-arm"] = true;
3828 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3829 Features["fp-armv8"] = true;
3830 Features["neon"] = true;
3831 Features["hwdiv"] = true;
3832 Features["hwdiv-arm"] = true;
3833 Features["crc"] = true;
3834 } else if (CPU == "cortex-r5" || CPU == "cortex-m3" ||
3835 CPU == "cortex-m4" ||
3836 // Enable the hwdiv extension for all v8a AArch32 cores by
3838 ArchName == "armv8a" || ArchName == "armv8" ||
3839 ArchName == "thumbv8a" || ArchName == "thumbv8") {
3840 Features["hwdiv"] = true;
3841 Features["hwdiv-arm"] = true;
3845 virtual bool handleTargetFeatures(std::vector<std::string> &Features,
3846 DiagnosticsEngine &Diags) {
3849 SoftFloat = SoftFloatABI = false;
3851 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3852 if (Features[i] == "+soft-float")
3854 else if (Features[i] == "+soft-float-abi")
3855 SoftFloatABI = true;
3856 else if (Features[i] == "+vfp2")
3858 else if (Features[i] == "+vfp3")
3860 else if (Features[i] == "+vfp4")
3862 else if (Features[i] == "+fp-armv8")
3864 else if (Features[i] == "+neon")
3866 else if (Features[i] == "+hwdiv")
3867 HWDiv |= HWDivThumb;
3868 else if (Features[i] == "+hwdiv-arm")
3870 else if (Features[i] == "+crc")
3874 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3875 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3879 if (FPMath == FP_Neon)
3880 Features.push_back("+neonfp");
3881 else if (FPMath == FP_VFP)
3882 Features.push_back("-neonfp");
3884 // Remove front-end specific options which the backend handles differently.
3885 std::vector<std::string>::iterator it;
3886 it = std::find(Features.begin(), Features.end(), "+soft-float");
3887 if (it != Features.end())
3889 it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3890 if (it != Features.end())
3895 virtual bool hasFeature(StringRef Feature) const {
3896 return llvm::StringSwitch<bool>(Feature)
3898 .Case("softfloat", SoftFloat)
3899 .Case("thumb", IsThumb)
3900 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3901 .Case("hwdiv", HWDiv & HWDivThumb)
3902 .Case("hwdiv-arm", HWDiv & HWDivARM)
3905 // FIXME: Should we actually have some table instead of these switches?
3906 static const char *getCPUDefineSuffix(StringRef Name) {
3907 return llvm::StringSwitch<const char*>(Name)
3908 .Cases("arm8", "arm810", "4")
3909 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3910 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3911 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3912 .Case("ep9312", "4T")
3913 .Cases("arm10tdmi", "arm1020t", "5T")
3914 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3915 .Case("arm926ej-s", "5TEJ")
3916 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3917 .Cases("xscale", "iwmmxt", "5TE")
3918 .Case("arm1136j-s", "6J")
3919 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3920 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3921 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3922 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3923 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A")
3924 .Cases("cortex-r4", "cortex-r5", "7R")
3925 .Case("cortex-a9-mp", "7F")
3926 .Case("swift", "7S")
3927 .Cases("cortex-m3", "cortex-m4", "7M")
3928 .Case("cortex-m0", "6M")
3929 .Cases("cortex-a53", "cortex-a57", "8A")
3932 static const char *getCPUProfile(StringRef Name) {
3933 return llvm::StringSwitch<const char*>(Name)
3934 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
3935 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A")
3936 .Cases("cortex-a53", "cortex-a57", "A")
3937 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3938 .Cases("cortex-r4", "cortex-r5", "R")
3941 virtual bool setCPU(const std::string &Name) {
3942 if (!getCPUDefineSuffix(Name))
3948 virtual bool setFPMath(StringRef Name);
3949 virtual void getTargetDefines(const LangOptions &Opts,
3950 MacroBuilder &Builder) const {
3951 // Target identification.
3952 Builder.defineMacro("__arm");
3953 Builder.defineMacro("__arm__");
3955 // Target properties.
3956 Builder.defineMacro("__ARMEL__");
3957 Builder.defineMacro("__LITTLE_ENDIAN__");
3958 Builder.defineMacro("__REGISTER_PREFIX__", "");
3960 StringRef CPUArch = getCPUDefineSuffix(CPU);
3961 unsigned int CPUArchVer;
3962 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) {
3963 llvm_unreachable("Invalid char for architecture version number");
3965 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3966 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3967 StringRef CPUProfile = getCPUProfile(CPU);
3968 if (!CPUProfile.empty())
3969 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3971 // Subtarget options.
3973 // FIXME: It's more complicated than this and we don't really support
3975 if (5 <= CPUArchVer && CPUArchVer <= 7)
3976 Builder.defineMacro("__THUMB_INTERWORK__");
3978 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3979 // Embedded targets on Darwin follow AAPCS, but not EABI.
3980 if (!getTriple().isOSDarwin())
3981 Builder.defineMacro("__ARM_EABI__");
3982 Builder.defineMacro("__ARM_PCS", "1");
3984 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3985 Builder.defineMacro("__ARM_PCS_VFP", "1");
3989 Builder.defineMacro("__SOFTFP__");
3991 if (CPU == "xscale")
3992 Builder.defineMacro("__XSCALE__");
3995 Builder.defineMacro("__THUMBEL__");
3996 Builder.defineMacro("__thumb__");
3997 if (CPUArch == "6T2" || CPUArchVer == 7)
3998 Builder.defineMacro("__thumb2__");
4000 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4001 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4003 // Note, this is always on in gcc, even though it doesn't make sense.
4004 Builder.defineMacro("__APCS_32__");
4006 if (FPUModeIsVFP((FPUMode) FPU)) {
4007 Builder.defineMacro("__VFP_FP__");
4009 Builder.defineMacro("__ARM_VFPV2__");
4011 Builder.defineMacro("__ARM_VFPV3__");
4013 Builder.defineMacro("__ARM_VFPV4__");
4016 // This only gets set when Neon instructions are actually available, unlike
4017 // the VFP define, hence the soft float and arch check. This is subtly
4018 // different from gcc, we follow the intent which was that it should be set
4019 // when Neon instructions are actually available.
4020 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7)
4021 Builder.defineMacro("__ARM_NEON__");
4024 Builder.defineMacro("__ARM_FEATURE_CRC32");
4026 if (CPUArchVer >= 6 && CPUArch != "6M") {
4027 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4028 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4029 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4030 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4033 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4034 unsigned &NumRecords) const {
4035 Records = BuiltinInfo;
4036 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4038 virtual bool isCLZForZeroUndef() const { return false; }
4039 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4040 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4042 virtual void getGCCRegNames(const char * const *&Names,
4043 unsigned &NumNames) const;
4044 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4045 unsigned &NumAliases) const;
4046 virtual bool validateAsmConstraint(const char *&Name,
4047 TargetInfo::ConstraintInfo &Info) const {
4052 case 'w': // VFP Floating point register single precision
4053 case 'P': // VFP Floating point register double precision
4054 Info.setAllowsRegister();
4056 case 'Q': // A memory address that is a single base register.
4057 Info.setAllowsMemory();
4059 case 'U': // a memory reference...
4061 case 'q': // ...ARMV4 ldrsb
4062 case 'v': // ...VFP load/store (reg+constant offset)
4063 case 'y': // ...iWMMXt load/store
4064 case 't': // address valid for load/store opaque types wider
4066 case 'n': // valid address for Neon doubleword vector load/store
4067 case 'm': // valid address for Neon element and structure load/store
4068 case 's': // valid address for non-offset loads/stores of quad-word
4069 // values in four ARM registers
4070 Info.setAllowsMemory();
4077 virtual std::string convertConstraint(const char *&Constraint) const {
4079 switch (*Constraint) {
4080 case 'U': // Two-character constraint; add "^" hint for later parsing.
4081 R = std::string("^") + std::string(Constraint, 2);
4084 case 'p': // 'p' should be translated to 'r' by default.
4085 R = std::string("r");
4088 return std::string(1, *Constraint);
4092 virtual bool validateConstraintModifier(StringRef Constraint,
4093 const char Modifier,
4094 unsigned Size) const {
4095 bool isOutput = (Constraint[0] == '=');
4096 bool isInOut = (Constraint[0] == '+');
4098 // Strip off constraint modifiers.
4099 while (Constraint[0] == '=' ||
4100 Constraint[0] == '+' ||
4101 Constraint[0] == '&')
4102 Constraint = Constraint.substr(1);
4104 switch (Constraint[0]) {
4109 return (isInOut || isOutput || Size <= 64);
4111 // A register of size 32 cannot fit a vector type.
4119 virtual const char *getClobbers() const {
4120 // FIXME: Is this really right?
4124 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
4125 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4128 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4129 if (RegNo == 0) return 0;
4130 if (RegNo == 1) return 1;
4135 bool ARMTargetInfo::setFPMath(StringRef Name) {
4136 if (Name == "neon") {
4139 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4147 const char * const ARMTargetInfo::GCCRegNames[] = {
4148 // Integer registers
4149 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4150 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4153 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4154 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4155 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4156 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4159 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4160 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4161 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4162 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4165 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4166 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4169 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4170 unsigned &NumNames) const {
4171 Names = GCCRegNames;
4172 NumNames = llvm::array_lengthof(GCCRegNames);
4175 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4185 { { "v6", "rfp" }, "r9" },
4186 { { "sl" }, "r10" },
4187 { { "fp" }, "r11" },
4188 { { "ip" }, "r12" },
4189 { { "r13" }, "sp" },
4190 { { "r14" }, "lr" },
4191 { { "r15" }, "pc" },
4192 // The S, D and Q registers overlap, but aren't really aliases; we
4193 // don't want to substitute one of these for a different-sized one.
4196 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4197 unsigned &NumAliases) const {
4198 Aliases = GCCRegAliases;
4199 NumAliases = llvm::array_lengthof(GCCRegAliases);
4202 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4203 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4204 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4206 #include "clang/Basic/BuiltinsARM.def"
4208 } // end anonymous namespace.
4211 class DarwinARMTargetInfo :
4212 public DarwinTargetInfo<ARMTargetInfo> {
4214 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4215 MacroBuilder &Builder) const {
4216 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4220 DarwinARMTargetInfo(const llvm::Triple &Triple)
4221 : DarwinTargetInfo<ARMTargetInfo>(Triple) {
4222 HasAlignMac68kSupport = true;
4223 // iOS always has 64-bit atomic instructions.
4224 // FIXME: This should be based off of the target features in ARMTargetInfo.
4225 MaxAtomicInlineWidth = 64;
4227 // Darwin on iOS uses a variant of the ARM C++ ABI.
4228 TheCXXABI.set(TargetCXXABI::iOS);
4231 } // end anonymous namespace.
4235 // Hexagon abstract base class
4236 class HexagonTargetInfo : public TargetInfo {
4237 static const Builtin::Info BuiltinInfo[];
4238 static const char * const GCCRegNames[];
4239 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4242 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4244 DescriptionString = ("e-p:32:32:32-"
4245 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4246 "f64:64:64-f32:32:32-a0:0-n32");
4248 // {} in inline assembly are packet specifiers, not assembly variant
4250 NoAsmVariants = true;
4253 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4254 unsigned &NumRecords) const {
4255 Records = BuiltinInfo;
4256 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4259 virtual bool validateAsmConstraint(const char *&Name,
4260 TargetInfo::ConstraintInfo &Info) const {
4264 virtual void getTargetDefines(const LangOptions &Opts,
4265 MacroBuilder &Builder) const;
4267 virtual bool hasFeature(StringRef Feature) const {
4268 return Feature == "hexagon";
4271 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4272 return TargetInfo::CharPtrBuiltinVaList;
4274 virtual void getGCCRegNames(const char * const *&Names,
4275 unsigned &NumNames) const;
4276 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4277 unsigned &NumAliases) const;
4278 virtual const char *getClobbers() const {
4282 static const char *getHexagonCPUSuffix(StringRef Name) {
4283 return llvm::StringSwitch<const char*>(Name)
4284 .Case("hexagonv4", "4")
4285 .Case("hexagonv5", "5")
4289 virtual bool setCPU(const std::string &Name) {
4290 if (!getHexagonCPUSuffix(Name))
4298 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4299 MacroBuilder &Builder) const {
4300 Builder.defineMacro("qdsp6");
4301 Builder.defineMacro("__qdsp6", "1");
4302 Builder.defineMacro("__qdsp6__", "1");
4304 Builder.defineMacro("hexagon");
4305 Builder.defineMacro("__hexagon", "1");
4306 Builder.defineMacro("__hexagon__", "1");
4308 if(CPU == "hexagonv1") {
4309 Builder.defineMacro("__HEXAGON_V1__");
4310 Builder.defineMacro("__HEXAGON_ARCH__", "1");
4311 if(Opts.HexagonQdsp6Compat) {
4312 Builder.defineMacro("__QDSP6_V1__");
4313 Builder.defineMacro("__QDSP6_ARCH__", "1");
4316 else if(CPU == "hexagonv2") {
4317 Builder.defineMacro("__HEXAGON_V2__");
4318 Builder.defineMacro("__HEXAGON_ARCH__", "2");
4319 if(Opts.HexagonQdsp6Compat) {
4320 Builder.defineMacro("__QDSP6_V2__");
4321 Builder.defineMacro("__QDSP6_ARCH__", "2");
4324 else if(CPU == "hexagonv3") {
4325 Builder.defineMacro("__HEXAGON_V3__");
4326 Builder.defineMacro("__HEXAGON_ARCH__", "3");
4327 if(Opts.HexagonQdsp6Compat) {
4328 Builder.defineMacro("__QDSP6_V3__");
4329 Builder.defineMacro("__QDSP6_ARCH__", "3");
4332 else if(CPU == "hexagonv4") {
4333 Builder.defineMacro("__HEXAGON_V4__");
4334 Builder.defineMacro("__HEXAGON_ARCH__", "4");
4335 if(Opts.HexagonQdsp6Compat) {
4336 Builder.defineMacro("__QDSP6_V4__");
4337 Builder.defineMacro("__QDSP6_ARCH__", "4");
4340 else if(CPU == "hexagonv5") {
4341 Builder.defineMacro("__HEXAGON_V5__");
4342 Builder.defineMacro("__HEXAGON_ARCH__", "5");
4343 if(Opts.HexagonQdsp6Compat) {
4344 Builder.defineMacro("__QDSP6_V5__");
4345 Builder.defineMacro("__QDSP6_ARCH__", "5");
4350 const char * const HexagonTargetInfo::GCCRegNames[] = {
4351 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4352 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4353 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4354 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4355 "p0", "p1", "p2", "p3",
4356 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4359 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4360 unsigned &NumNames) const {
4361 Names = GCCRegNames;
4362 NumNames = llvm::array_lengthof(GCCRegNames);
4366 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4367 { { "sp" }, "r29" },
4368 { { "fp" }, "r30" },
4369 { { "lr" }, "r31" },
4372 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4373 unsigned &NumAliases) const {
4374 Aliases = GCCRegAliases;
4375 NumAliases = llvm::array_lengthof(GCCRegAliases);
4379 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4380 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4381 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4383 #include "clang/Basic/BuiltinsHexagon.def"
4389 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4390 class SparcTargetInfo : public TargetInfo {
4391 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4392 static const char * const GCCRegNames[];
4395 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4397 virtual bool handleTargetFeatures(std::vector<std::string> &Features,
4398 DiagnosticsEngine &Diags) {
4400 for (unsigned i = 0, e = Features.size(); i != e; ++i)
4401 if (Features[i] == "+soft-float")
4405 virtual void getTargetDefines(const LangOptions &Opts,
4406 MacroBuilder &Builder) const {
4407 DefineStd(Builder, "sparc", Opts);
4408 Builder.defineMacro("__REGISTER_PREFIX__", "");
4411 Builder.defineMacro("SOFT_FLOAT", "1");
4414 virtual bool hasFeature(StringRef Feature) const {
4415 return llvm::StringSwitch<bool>(Feature)
4416 .Case("softfloat", SoftFloat)
4417 .Case("sparc", true)
4421 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4422 unsigned &NumRecords) const {
4423 // FIXME: Implement!
4425 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4426 return TargetInfo::VoidPtrBuiltinVaList;
4428 virtual void getGCCRegNames(const char * const *&Names,
4429 unsigned &NumNames) const;
4430 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4431 unsigned &NumAliases) const;
4432 virtual bool validateAsmConstraint(const char *&Name,
4433 TargetInfo::ConstraintInfo &info) const {
4434 // FIXME: Implement!
4437 virtual const char *getClobbers() const {
4438 // FIXME: Implement!
4443 const char * const SparcTargetInfo::GCCRegNames[] = {
4444 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4445 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4446 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4447 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4450 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4451 unsigned &NumNames) const {
4452 Names = GCCRegNames;
4453 NumNames = llvm::array_lengthof(GCCRegNames);
4456 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4467 { { "o2" }, "r10" },
4468 { { "o3" }, "r11" },
4469 { { "o4" }, "r12" },
4470 { { "o5" }, "r13" },
4471 { { "o6", "sp" }, "r14" },
4472 { { "o7" }, "r15" },
4473 { { "l0" }, "r16" },
4474 { { "l1" }, "r17" },
4475 { { "l2" }, "r18" },
4476 { { "l3" }, "r19" },
4477 { { "l4" }, "r20" },
4478 { { "l5" }, "r21" },
4479 { { "l6" }, "r22" },
4480 { { "l7" }, "r23" },
4481 { { "i0" }, "r24" },
4482 { { "i1" }, "r25" },
4483 { { "i2" }, "r26" },
4484 { { "i3" }, "r27" },
4485 { { "i4" }, "r28" },
4486 { { "i5" }, "r29" },
4487 { { "i6", "fp" }, "r30" },
4488 { { "i7" }, "r31" },
4491 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4492 unsigned &NumAliases) const {
4493 Aliases = GCCRegAliases;
4494 NumAliases = llvm::array_lengthof(GCCRegAliases);
4497 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4498 class SparcV8TargetInfo : public SparcTargetInfo {
4500 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4501 // FIXME: Support Sparc quad-precision long double?
4502 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4503 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4506 virtual void getTargetDefines(const LangOptions &Opts,
4507 MacroBuilder &Builder) const {
4508 SparcTargetInfo::getTargetDefines(Opts, Builder);
4509 Builder.defineMacro("__sparcv8");
4513 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4514 class SparcV9TargetInfo : public SparcTargetInfo {
4516 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4517 // FIXME: Support Sparc quad-precision long double?
4518 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4519 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4520 // This is an LP64 platform.
4521 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4523 // OpenBSD uses long long for int64_t and intmax_t.
4524 if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4525 IntMaxType = SignedLongLong;
4526 UIntMaxType = UnsignedLongLong;
4528 IntMaxType = SignedLong;
4529 UIntMaxType = UnsignedLong;
4531 Int64Type = IntMaxType;
4533 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
4534 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
4535 LongDoubleWidth = 128;
4536 LongDoubleAlign = 128;
4537 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4538 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4541 virtual void getTargetDefines(const LangOptions &Opts,
4542 MacroBuilder &Builder) const {
4543 SparcTargetInfo::getTargetDefines(Opts, Builder);
4544 Builder.defineMacro("__sparcv9");
4545 Builder.defineMacro("__arch64__");
4546 // Solaris and its derivative AuroraUX don't need these variants, but the
4548 if (getTriple().getOS() != llvm::Triple::Solaris &&
4549 getTriple().getOS() != llvm::Triple::AuroraUX) {
4550 Builder.defineMacro("__sparc64__");
4551 Builder.defineMacro("__sparc_v9__");
4552 Builder.defineMacro("__sparcv9__");
4556 virtual bool setCPU(const std::string &Name) {
4557 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4559 .Case("ultrasparc", true)
4560 .Case("ultrasparc3", true)
4561 .Case("niagara", true)
4562 .Case("niagara2", true)
4563 .Case("niagara3", true)
4564 .Case("niagara4", true)
4567 // No need to store the CPU yet. There aren't any CPU-specific
4568 // macros to define.
4573 } // end anonymous namespace.
4576 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4578 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4579 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4580 SizeType = UnsignedInt;
4581 PtrDiffType = SignedInt;
4584 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4586 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
4587 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
4588 SizeType = UnsignedInt;
4589 PtrDiffType = SignedInt;
4592 } // end anonymous namespace.
4595 class SystemZTargetInfo : public TargetInfo {
4596 static const char *const GCCRegNames[];
4599 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4600 TLSSupported = true;
4601 IntWidth = IntAlign = 32;
4602 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4603 PointerWidth = PointerAlign = 64;
4604 LongDoubleWidth = 128;
4605 LongDoubleAlign = 64;
4606 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4607 MinGlobalAlign = 16;
4608 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4609 "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4610 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4612 virtual void getTargetDefines(const LangOptions &Opts,
4613 MacroBuilder &Builder) const {
4614 Builder.defineMacro("__s390__");
4615 Builder.defineMacro("__s390x__");
4616 Builder.defineMacro("__zarch__");
4617 Builder.defineMacro("__LONG_DOUBLE_128__");
4619 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4620 unsigned &NumRecords) const {
4621 // FIXME: Implement.
4626 virtual void getGCCRegNames(const char *const *&Names,
4627 unsigned &NumNames) const;
4628 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4629 unsigned &NumAliases) const {
4634 virtual bool validateAsmConstraint(const char *&Name,
4635 TargetInfo::ConstraintInfo &info) const;
4636 virtual const char *getClobbers() const {
4637 // FIXME: Is this really right?
4640 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4641 return TargetInfo::SystemZBuiltinVaList;
4643 virtual bool setCPU(const std::string &Name) {
4644 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4647 .Case("zEC12", true)
4650 // No need to store the CPU yet. There aren't any CPU-specific
4651 // macros to define.
4656 const char *const SystemZTargetInfo::GCCRegNames[] = {
4657 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4658 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4659 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
4660 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
4663 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4664 unsigned &NumNames) const {
4665 Names = GCCRegNames;
4666 NumNames = llvm::array_lengthof(GCCRegNames);
4669 bool SystemZTargetInfo::
4670 validateAsmConstraint(const char *&Name,
4671 TargetInfo::ConstraintInfo &Info) const {
4676 case 'a': // Address register
4677 case 'd': // Data register (equivalent to 'r')
4678 case 'f': // Floating-point register
4679 Info.setAllowsRegister();
4682 case 'I': // Unsigned 8-bit constant
4683 case 'J': // Unsigned 12-bit constant
4684 case 'K': // Signed 16-bit constant
4685 case 'L': // Signed 20-bit displacement (on all targets we support)
4686 case 'M': // 0x7fffffff
4689 case 'Q': // Memory with base and unsigned 12-bit displacement
4690 case 'R': // Likewise, plus an index
4691 case 'S': // Memory with base and signed 20-bit displacement
4692 case 'T': // Likewise, plus an index
4693 Info.setAllowsMemory();
4700 class MSP430TargetInfo : public TargetInfo {
4701 static const char * const GCCRegNames[];
4703 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4705 TLSSupported = false;
4706 IntWidth = 16; IntAlign = 16;
4707 LongWidth = 32; LongLongWidth = 64;
4708 LongAlign = LongLongAlign = 16;
4709 PointerWidth = 16; PointerAlign = 16;
4711 SizeType = UnsignedInt;
4712 IntMaxType = SignedLongLong;
4713 UIntMaxType = UnsignedLongLong;
4714 IntPtrType = SignedInt;
4715 PtrDiffType = SignedInt;
4716 SigAtomicType = SignedLong;
4717 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4719 virtual void getTargetDefines(const LangOptions &Opts,
4720 MacroBuilder &Builder) const {
4721 Builder.defineMacro("MSP430");
4722 Builder.defineMacro("__MSP430__");
4723 // FIXME: defines for different 'flavours' of MCU
4725 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4726 unsigned &NumRecords) const {
4727 // FIXME: Implement.
4731 virtual bool hasFeature(StringRef Feature) const {
4732 return Feature == "msp430";
4734 virtual void getGCCRegNames(const char * const *&Names,
4735 unsigned &NumNames) const;
4736 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4737 unsigned &NumAliases) const {
4742 virtual bool validateAsmConstraint(const char *&Name,
4743 TargetInfo::ConstraintInfo &info) const {
4744 // No target constraints for now.
4747 virtual const char *getClobbers() const {
4748 // FIXME: Is this really right?
4751 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4753 return TargetInfo::CharPtrBuiltinVaList;
4757 const char * const MSP430TargetInfo::GCCRegNames[] = {
4758 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4759 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4762 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4763 unsigned &NumNames) const {
4764 Names = GCCRegNames;
4765 NumNames = llvm::array_lengthof(GCCRegNames);
4771 // LLVM and Clang cannot be used directly to output native binaries for
4772 // target, but is used to compile C code to llvm bitcode with correct
4773 // type and alignment information.
4775 // TCE uses the llvm bitcode as input and uses it for generating customized
4776 // target processor and program binary. TCE co-design environment is
4777 // publicly available in http://tce.cs.tut.fi
4779 static const unsigned TCEOpenCLAddrSpaceMap[] = {
4782 5, // opencl_constant
4788 class TCETargetInfo : public TargetInfo{
4790 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4791 TLSSupported = false;
4793 LongWidth = LongLongWidth = 32;
4796 LongAlign = LongLongAlign = 32;
4799 SizeType = UnsignedInt;
4800 IntMaxType = SignedLong;
4801 UIntMaxType = UnsignedLong;
4802 IntPtrType = SignedInt;
4803 PtrDiffType = SignedInt;
4808 LongDoubleWidth = 32;
4809 LongDoubleAlign = 32;
4810 FloatFormat = &llvm::APFloat::IEEEsingle;
4811 DoubleFormat = &llvm::APFloat::IEEEsingle;
4812 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4813 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4814 "i16:16:32-i32:32:32-i64:32:32-"
4815 "f32:32:32-f64:32:32-v64:32:32-"
4816 "v128:32:32-a0:0:32-n32";
4817 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4818 UseAddrSpaceMapMangling = true;
4821 virtual void getTargetDefines(const LangOptions &Opts,
4822 MacroBuilder &Builder) const {
4823 DefineStd(Builder, "tce", Opts);
4824 Builder.defineMacro("__TCE__");
4825 Builder.defineMacro("__TCE_V1__");
4827 virtual bool hasFeature(StringRef Feature) const {
4828 return Feature == "tce";
4831 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4832 unsigned &NumRecords) const {}
4833 virtual const char *getClobbers() const {
4836 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4837 return TargetInfo::VoidPtrBuiltinVaList;
4839 virtual void getGCCRegNames(const char * const *&Names,
4840 unsigned &NumNames) const {}
4841 virtual bool validateAsmConstraint(const char *&Name,
4842 TargetInfo::ConstraintInfo &info) const {
4845 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4846 unsigned &NumAliases) const {}
4851 class MipsTargetInfoBase : public TargetInfo {
4852 virtual void setDescriptionString() = 0;
4854 static const Builtin::Info BuiltinInfo[];
4861 HardFloat, SoftFloat
4873 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
4874 const std::string &CPUStr)
4875 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
4876 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
4877 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
4879 virtual const char *getABI() const { return ABI.c_str(); }
4880 virtual bool setABI(const std::string &Name) = 0;
4881 virtual bool setCPU(const std::string &Name) {
4885 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4886 Features[ABI] = true;
4887 Features[CPU] = true;
4890 virtual void getTargetDefines(const LangOptions &Opts,
4891 MacroBuilder &Builder) const {
4892 DefineStd(Builder, "mips", Opts);
4893 Builder.defineMacro("_mips");
4894 Builder.defineMacro("__REGISTER_PREFIX__", "");
4898 Builder.defineMacro("__mips_hard_float", Twine(1));
4901 Builder.defineMacro("__mips_soft_float", Twine(1));
4906 Builder.defineMacro("__mips_single_float", Twine(1));
4908 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
4909 Builder.defineMacro("_MIPS_FPSET",
4910 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
4913 Builder.defineMacro("__mips16", Twine(1));
4916 Builder.defineMacro("__mips_micromips", Twine(1));
4919 Builder.defineMacro("__mips_nan2008", Twine(1));
4925 Builder.defineMacro("__mips_dsp_rev", Twine(1));
4926 Builder.defineMacro("__mips_dsp", Twine(1));
4929 Builder.defineMacro("__mips_dsp_rev", Twine(2));
4930 Builder.defineMacro("__mips_dspr2", Twine(1));
4931 Builder.defineMacro("__mips_dsp", Twine(1));
4936 Builder.defineMacro("__mips_msa", Twine(1));
4938 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4939 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4940 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4942 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4943 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4946 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4947 unsigned &NumRecords) const {
4948 Records = BuiltinInfo;
4949 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4951 virtual bool hasFeature(StringRef Feature) const {
4952 return llvm::StringSwitch<bool>(Feature)
4954 .Case("fp64", HasFP64)
4957 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4958 return TargetInfo::VoidPtrBuiltinVaList;
4960 virtual void getGCCRegNames(const char * const *&Names,
4961 unsigned &NumNames) const {
4962 static const char *const GCCRegNames[] = {
4963 // CPU register names
4964 // Must match second column of GCCRegAliases
4965 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
4966 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
4967 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
4968 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
4969 // Floating point register names
4970 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
4971 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4972 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4973 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4974 // Hi/lo and condition register names
4975 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4976 "$fcc5","$fcc6","$fcc7",
4977 // MSA register names
4978 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
4979 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
4980 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
4981 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
4982 // MSA control register names
4983 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
4984 "$msarequest", "$msamap", "$msaunmap"
4986 Names = GCCRegNames;
4987 NumNames = llvm::array_lengthof(GCCRegNames);
4989 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4990 unsigned &NumAliases) const = 0;
4991 virtual bool validateAsmConstraint(const char *&Name,
4992 TargetInfo::ConstraintInfo &Info) const {
4997 case 'r': // CPU registers.
4998 case 'd': // Equivalent to "r" unless generating MIPS16 code.
4999 case 'y': // Equivalent to "r", backwards compatibility only.
5000 case 'f': // floating-point registers.
5001 case 'c': // $25 for indirect jumps
5002 case 'l': // lo register
5003 case 'x': // hilo register pair
5004 Info.setAllowsRegister();
5006 case 'R': // An address that can be used in a non-macro load or store
5007 Info.setAllowsMemory();
5012 virtual const char *getClobbers() const {
5013 // FIXME: Implement!
5017 virtual bool handleTargetFeatures(std::vector<std::string> &Features,
5018 DiagnosticsEngine &Diags) {
5020 IsMicromips = false;
5022 IsSingleFloat = false;
5023 FloatABI = HardFloat;
5025 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64";
5027 for (std::vector<std::string>::iterator it = Features.begin(),
5028 ie = Features.end(); it != ie; ++it) {
5029 if (*it == "+single-float")
5030 IsSingleFloat = true;
5031 else if (*it == "+soft-float")
5032 FloatABI = SoftFloat;
5033 else if (*it == "+mips16")
5035 else if (*it == "+micromips")
5037 else if (*it == "+dsp")
5038 DspRev = std::max(DspRev, DSP1);
5039 else if (*it == "+dspr2")
5040 DspRev = std::max(DspRev, DSP2);
5041 else if (*it == "+msa")
5043 else if (*it == "+fp64")
5045 else if (*it == "-fp64")
5047 else if (*it == "+nan2008")
5051 // Remove front-end specific options.
5052 std::vector<std::string>::iterator it =
5053 std::find(Features.begin(), Features.end(), "+soft-float");
5054 if (it != Features.end())
5056 it = std::find(Features.begin(), Features.end(), "+nan2008");
5057 if (it != Features.end())
5060 setDescriptionString();
5065 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
5066 if (RegNo == 0) return 4;
5067 if (RegNo == 1) return 5;
5072 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5073 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5074 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5076 #include "clang/Basic/BuiltinsMips.def"
5079 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5081 Mips32TargetInfoBase(const llvm::Triple &Triple)
5082 : MipsTargetInfoBase(Triple, "o32", "mips32") {
5083 SizeType = UnsignedInt;
5084 PtrDiffType = SignedInt;
5085 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5087 virtual bool setABI(const std::string &Name) {
5088 if ((Name == "o32") || (Name == "eabi")) {
5091 } else if (Name == "32") {
5097 virtual void getTargetDefines(const LangOptions &Opts,
5098 MacroBuilder &Builder) const {
5099 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5102 Builder.defineMacro("__mips_o32");
5103 Builder.defineMacro("_ABIO32", "1");
5104 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5106 else if (ABI == "eabi")
5107 Builder.defineMacro("__mips_eabi");
5109 llvm_unreachable("Invalid ABI for Mips32.");
5111 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5112 unsigned &NumAliases) const {
5113 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5123 { { "t2" }, "$10" },
5124 { { "t3" }, "$11" },
5125 { { "t4" }, "$12" },
5126 { { "t5" }, "$13" },
5127 { { "t6" }, "$14" },
5128 { { "t7" }, "$15" },
5129 { { "s0" }, "$16" },
5130 { { "s1" }, "$17" },
5131 { { "s2" }, "$18" },
5132 { { "s3" }, "$19" },
5133 { { "s4" }, "$20" },
5134 { { "s5" }, "$21" },
5135 { { "s6" }, "$22" },
5136 { { "s7" }, "$23" },
5137 { { "t8" }, "$24" },
5138 { { "t9" }, "$25" },
5139 { { "k0" }, "$26" },
5140 { { "k1" }, "$27" },
5141 { { "gp" }, "$28" },
5142 { { "sp","$sp" }, "$29" },
5143 { { "fp","$fp" }, "$30" },
5146 Aliases = GCCRegAliases;
5147 NumAliases = llvm::array_lengthof(GCCRegAliases);
5151 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5152 virtual void setDescriptionString() {
5153 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5154 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
5158 Mips32EBTargetInfo(const llvm::Triple &Triple)
5159 : Mips32TargetInfoBase(Triple) {
5161 virtual void getTargetDefines(const LangOptions &Opts,
5162 MacroBuilder &Builder) const {
5163 DefineStd(Builder, "MIPSEB", Opts);
5164 Builder.defineMacro("_MIPSEB");
5165 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5169 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5170 virtual void setDescriptionString() {
5171 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5172 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
5176 Mips32ELTargetInfo(const llvm::Triple &Triple)
5177 : Mips32TargetInfoBase(Triple) {
5180 virtual void getTargetDefines(const LangOptions &Opts,
5181 MacroBuilder &Builder) const {
5182 DefineStd(Builder, "MIPSEL", Opts);
5183 Builder.defineMacro("_MIPSEL");
5184 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5188 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5190 Mips64TargetInfoBase(const llvm::Triple &Triple)
5191 : MipsTargetInfoBase(Triple, "n64", "mips64") {
5192 LongWidth = LongAlign = 64;
5193 PointerWidth = PointerAlign = 64;
5194 LongDoubleWidth = LongDoubleAlign = 128;
5195 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5196 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5197 LongDoubleWidth = LongDoubleAlign = 64;
5198 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5200 SuitableAlign = 128;
5201 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5203 virtual bool setABI(const std::string &Name) {
5204 if (Name == "n32") {
5205 LongWidth = LongAlign = 32;
5206 PointerWidth = PointerAlign = 32;
5209 } else if (Name == "n64") {
5212 } else if (Name == "64") {
5218 virtual void getTargetDefines(const LangOptions &Opts,
5219 MacroBuilder &Builder) const {
5220 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5222 Builder.defineMacro("__mips64");
5223 Builder.defineMacro("__mips64__");
5226 Builder.defineMacro("__mips_n32");
5227 Builder.defineMacro("_ABIN32", "2");
5228 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5230 else if (ABI == "n64") {
5231 Builder.defineMacro("__mips_n64");
5232 Builder.defineMacro("_ABI64", "3");
5233 Builder.defineMacro("_MIPS_SIM", "_ABI64");
5236 llvm_unreachable("Invalid ABI for Mips64.");
5238 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5239 unsigned &NumAliases) const {
5240 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5250 { { "a6" }, "$10" },
5251 { { "a7" }, "$11" },
5252 { { "t0" }, "$12" },
5253 { { "t1" }, "$13" },
5254 { { "t2" }, "$14" },
5255 { { "t3" }, "$15" },
5256 { { "s0" }, "$16" },
5257 { { "s1" }, "$17" },
5258 { { "s2" }, "$18" },
5259 { { "s3" }, "$19" },
5260 { { "s4" }, "$20" },
5261 { { "s5" }, "$21" },
5262 { { "s6" }, "$22" },
5263 { { "s7" }, "$23" },
5264 { { "t8" }, "$24" },
5265 { { "t9" }, "$25" },
5266 { { "k0" }, "$26" },
5267 { { "k1" }, "$27" },
5268 { { "gp" }, "$28" },
5269 { { "sp","$sp" }, "$29" },
5270 { { "fp","$fp" }, "$30" },
5273 Aliases = GCCRegAliases;
5274 NumAliases = llvm::array_lengthof(GCCRegAliases);
5278 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5279 virtual void setDescriptionString() {
5281 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5282 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5283 "v64:64:64-n32:64-S128";
5285 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5286 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5287 "v64:64:64-n32:64-S128";
5292 Mips64EBTargetInfo(const llvm::Triple &Triple)
5293 : Mips64TargetInfoBase(Triple) {}
5294 virtual void getTargetDefines(const LangOptions &Opts,
5295 MacroBuilder &Builder) const {
5296 DefineStd(Builder, "MIPSEB", Opts);
5297 Builder.defineMacro("_MIPSEB");
5298 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5302 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5303 virtual void setDescriptionString() {
5305 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5306 "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5307 "-v64:64:64-n32:64-S128";
5309 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5310 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5311 "v64:64:64-n32:64-S128";
5314 Mips64ELTargetInfo(const llvm::Triple &Triple)
5315 : Mips64TargetInfoBase(Triple) {
5316 // Default ABI is n64.
5319 virtual void getTargetDefines(const LangOptions &Opts,
5320 MacroBuilder &Builder) const {
5321 DefineStd(Builder, "MIPSEL", Opts);
5322 Builder.defineMacro("_MIPSEL");
5323 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5326 } // end anonymous namespace.
5329 class PNaClTargetInfo : public TargetInfo {
5331 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5333 this->UserLabelPrefix = "";
5334 this->LongAlign = 32;
5335 this->LongWidth = 32;
5336 this->PointerAlign = 32;
5337 this->PointerWidth = 32;
5338 this->IntMaxType = TargetInfo::SignedLongLong;
5339 this->UIntMaxType = TargetInfo::UnsignedLongLong;
5340 this->Int64Type = TargetInfo::SignedLongLong;
5341 this->DoubleAlign = 64;
5342 this->LongDoubleWidth = 64;
5343 this->LongDoubleAlign = 64;
5344 this->SizeType = TargetInfo::UnsignedInt;
5345 this->PtrDiffType = TargetInfo::SignedInt;
5346 this->IntPtrType = TargetInfo::SignedInt;
5347 this->RegParmMax = 0; // Disallow regparm
5348 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5349 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5352 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5354 virtual void getArchDefines(const LangOptions &Opts,
5355 MacroBuilder &Builder) const {
5356 Builder.defineMacro("__le32__");
5357 Builder.defineMacro("__pnacl__");
5359 virtual void getTargetDefines(const LangOptions &Opts,
5360 MacroBuilder &Builder) const {
5361 Builder.defineMacro("__LITTLE_ENDIAN__");
5362 getArchDefines(Opts, Builder);
5364 virtual bool hasFeature(StringRef Feature) const {
5365 return Feature == "pnacl";
5367 virtual void getTargetBuiltins(const Builtin::Info *&Records,
5368 unsigned &NumRecords) const {
5370 virtual BuiltinVaListKind getBuiltinVaListKind() const {
5371 return TargetInfo::PNaClABIBuiltinVaList;
5373 virtual void getGCCRegNames(const char * const *&Names,
5374 unsigned &NumNames) const;
5375 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5376 unsigned &NumAliases) const;
5377 virtual bool validateAsmConstraint(const char *&Name,
5378 TargetInfo::ConstraintInfo &Info) const {
5382 virtual const char *getClobbers() const {
5387 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5388 unsigned &NumNames) const {
5393 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5394 unsigned &NumAliases) const {
5398 } // end anonymous namespace.
5401 static const unsigned SPIRAddrSpaceMap[] = {
5404 2, // opencl_constant
5409 class SPIRTargetInfo : public TargetInfo {
5411 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5412 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5413 "SPIR target must use unknown OS");
5414 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5415 "SPIR target must use unknown environment type");
5417 TLSSupported = false;
5418 LongWidth = LongAlign = 64;
5419 AddrSpaceMap = &SPIRAddrSpaceMap;
5420 UseAddrSpaceMapMangling = true;
5421 // Define available target features
5422 // These must be defined in sorted order!
5423 NoAsmVariants = true;
5425 virtual void getTargetDefines(const LangOptions &Opts,
5426 MacroBuilder &Builder) const {
5427 DefineStd(Builder, "SPIR", Opts);
5429 virtual bool hasFeature(StringRef Feature) const {
5430 return Feature == "spir";
5433 virtual void getTargetBuiltins(const Builtin::Info *&Records,
5434 unsigned &NumRecords) const {}
5435 virtual const char *getClobbers() const {
5438 virtual void getGCCRegNames(const char * const *&Names,
5439 unsigned &NumNames) const {}
5440 virtual bool validateAsmConstraint(const char *&Name,
5441 TargetInfo::ConstraintInfo &info) const {
5444 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5445 unsigned &NumAliases) const {}
5446 virtual BuiltinVaListKind getBuiltinVaListKind() const {
5447 return TargetInfo::VoidPtrBuiltinVaList;
5452 class SPIR32TargetInfo : public SPIRTargetInfo {
5454 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5455 PointerWidth = PointerAlign = 32;
5456 SizeType = TargetInfo::UnsignedInt;
5457 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5459 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5460 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5461 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5462 "v512:512:512-v1024:1024:1024";
5464 virtual void getTargetDefines(const LangOptions &Opts,
5465 MacroBuilder &Builder) const {
5466 DefineStd(Builder, "SPIR32", Opts);
5470 class SPIR64TargetInfo : public SPIRTargetInfo {
5472 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5473 PointerWidth = PointerAlign = 64;
5474 SizeType = TargetInfo::UnsignedLong;
5475 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5477 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5478 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5479 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5480 "v512:512:512-v1024:1024:1024";
5482 virtual void getTargetDefines(const LangOptions &Opts,
5483 MacroBuilder &Builder) const {
5484 DefineStd(Builder, "SPIR64", Opts);
5490 class XCoreTargetInfo : public TargetInfo {
5491 static const Builtin::Info BuiltinInfo[];
5493 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5495 NoAsmVariants = true;
5498 DoubleAlign = LongDoubleAlign = 32;
5499 SizeType = UnsignedInt;
5500 PtrDiffType = SignedInt;
5501 IntPtrType = SignedInt;
5502 WCharType = UnsignedChar;
5503 WIntType = UnsignedInt;
5504 UseZeroLengthBitfieldAlignment = true;
5505 DescriptionString = "e-p:32:32:32-a0:0:32-n32"
5506 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32"
5507 "-f16:16:32-f32:32:32-f64:32:32";
5509 virtual void getTargetDefines(const LangOptions &Opts,
5510 MacroBuilder &Builder) const {
5511 Builder.defineMacro("__XS1B__");
5513 virtual void getTargetBuiltins(const Builtin::Info *&Records,
5514 unsigned &NumRecords) const {
5515 Records = BuiltinInfo;
5516 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
5518 virtual BuiltinVaListKind getBuiltinVaListKind() const {
5519 return TargetInfo::VoidPtrBuiltinVaList;
5521 virtual const char *getClobbers() const {
5524 virtual void getGCCRegNames(const char * const *&Names,
5525 unsigned &NumNames) const {
5526 static const char * const GCCRegNames[] = {
5527 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5528 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
5530 Names = GCCRegNames;
5531 NumNames = llvm::array_lengthof(GCCRegNames);
5533 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5534 unsigned &NumAliases) const {
5538 virtual bool validateAsmConstraint(const char *&Name,
5539 TargetInfo::ConstraintInfo &Info) const {
5544 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
5545 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5546 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5548 #include "clang/Basic/BuiltinsXCore.def"
5550 } // end anonymous namespace.
5553 //===----------------------------------------------------------------------===//
5555 //===----------------------------------------------------------------------===//
5557 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
5558 llvm::Triple::OSType os = Triple.getOS();
5560 switch (Triple.getArch()) {
5564 case llvm::Triple::xcore:
5565 return new XCoreTargetInfo(Triple);
5567 case llvm::Triple::hexagon:
5568 return new HexagonTargetInfo(Triple);
5570 case llvm::Triple::aarch64:
5572 case llvm::Triple::Linux:
5573 return new LinuxTargetInfo<AArch64TargetInfo>(Triple);
5575 return new AArch64TargetInfo(Triple);
5578 case llvm::Triple::arm:
5579 case llvm::Triple::thumb:
5580 if (Triple.isOSDarwin())
5581 return new DarwinARMTargetInfo(Triple);
5584 case llvm::Triple::Linux:
5585 return new LinuxTargetInfo<ARMTargetInfo>(Triple);
5586 case llvm::Triple::FreeBSD:
5587 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple);
5588 case llvm::Triple::NetBSD:
5589 return new NetBSDTargetInfo<ARMTargetInfo>(Triple);
5590 case llvm::Triple::OpenBSD:
5591 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple);
5592 case llvm::Triple::Bitrig:
5593 return new BitrigTargetInfo<ARMTargetInfo>(Triple);
5594 case llvm::Triple::RTEMS:
5595 return new RTEMSTargetInfo<ARMTargetInfo>(Triple);
5596 case llvm::Triple::NaCl:
5597 return new NaClTargetInfo<ARMTargetInfo>(Triple);
5599 return new ARMTargetInfo(Triple);
5602 case llvm::Triple::msp430:
5603 return new MSP430TargetInfo(Triple);
5605 case llvm::Triple::mips:
5607 case llvm::Triple::Linux:
5608 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
5609 case llvm::Triple::RTEMS:
5610 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
5611 case llvm::Triple::FreeBSD:
5612 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5613 case llvm::Triple::NetBSD:
5614 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5616 return new Mips32EBTargetInfo(Triple);
5619 case llvm::Triple::mipsel:
5621 case llvm::Triple::Linux:
5622 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
5623 case llvm::Triple::RTEMS:
5624 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
5625 case llvm::Triple::FreeBSD:
5626 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5627 case llvm::Triple::NetBSD:
5628 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5629 case llvm::Triple::NaCl:
5630 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
5632 return new Mips32ELTargetInfo(Triple);
5635 case llvm::Triple::mips64:
5637 case llvm::Triple::Linux:
5638 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
5639 case llvm::Triple::RTEMS:
5640 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
5641 case llvm::Triple::FreeBSD:
5642 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5643 case llvm::Triple::NetBSD:
5644 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5645 case llvm::Triple::OpenBSD:
5646 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5648 return new Mips64EBTargetInfo(Triple);
5651 case llvm::Triple::mips64el:
5653 case llvm::Triple::Linux:
5654 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
5655 case llvm::Triple::RTEMS:
5656 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
5657 case llvm::Triple::FreeBSD:
5658 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5659 case llvm::Triple::NetBSD:
5660 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5661 case llvm::Triple::OpenBSD:
5662 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5664 return new Mips64ELTargetInfo(Triple);
5667 case llvm::Triple::le32:
5669 case llvm::Triple::NaCl:
5670 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
5675 case llvm::Triple::ppc:
5676 if (Triple.isOSDarwin())
5677 return new DarwinPPC32TargetInfo(Triple);
5679 case llvm::Triple::Linux:
5680 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
5681 case llvm::Triple::FreeBSD:
5682 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
5683 case llvm::Triple::NetBSD:
5684 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
5685 case llvm::Triple::OpenBSD:
5686 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
5687 case llvm::Triple::RTEMS:
5688 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
5690 return new PPC32TargetInfo(Triple);
5693 case llvm::Triple::ppc64:
5694 if (Triple.isOSDarwin())
5695 return new DarwinPPC64TargetInfo(Triple);
5697 case llvm::Triple::Linux:
5698 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5699 case llvm::Triple::Lv2:
5700 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
5701 case llvm::Triple::FreeBSD:
5702 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
5703 case llvm::Triple::NetBSD:
5704 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
5706 return new PPC64TargetInfo(Triple);
5709 case llvm::Triple::ppc64le:
5711 case llvm::Triple::Linux:
5712 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5714 return new PPC64TargetInfo(Triple);
5717 case llvm::Triple::nvptx:
5718 return new NVPTX32TargetInfo(Triple);
5719 case llvm::Triple::nvptx64:
5720 return new NVPTX64TargetInfo(Triple);
5722 case llvm::Triple::r600:
5723 return new R600TargetInfo(Triple);
5725 case llvm::Triple::sparc:
5727 case llvm::Triple::Linux:
5728 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
5729 case llvm::Triple::AuroraUX:
5730 return new AuroraUXSparcV8TargetInfo(Triple);
5731 case llvm::Triple::Solaris:
5732 return new SolarisSparcV8TargetInfo(Triple);
5733 case llvm::Triple::NetBSD:
5734 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
5735 case llvm::Triple::OpenBSD:
5736 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
5737 case llvm::Triple::RTEMS:
5738 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
5740 return new SparcV8TargetInfo(Triple);
5743 case llvm::Triple::sparcv9:
5745 case llvm::Triple::Linux:
5746 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
5747 case llvm::Triple::AuroraUX:
5748 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
5749 case llvm::Triple::Solaris:
5750 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
5751 case llvm::Triple::NetBSD:
5752 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
5753 case llvm::Triple::OpenBSD:
5754 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
5755 case llvm::Triple::FreeBSD:
5756 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
5758 return new SparcV9TargetInfo(Triple);
5761 case llvm::Triple::systemz:
5763 case llvm::Triple::Linux:
5764 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
5766 return new SystemZTargetInfo(Triple);
5769 case llvm::Triple::tce:
5770 return new TCETargetInfo(Triple);
5772 case llvm::Triple::x86:
5773 if (Triple.isOSDarwin())
5774 return new DarwinI386TargetInfo(Triple);
5777 case llvm::Triple::AuroraUX:
5778 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
5779 case llvm::Triple::Linux:
5780 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
5781 case llvm::Triple::DragonFly:
5782 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
5783 case llvm::Triple::NetBSD:
5784 return new NetBSDI386TargetInfo(Triple);
5785 case llvm::Triple::OpenBSD:
5786 return new OpenBSDI386TargetInfo(Triple);
5787 case llvm::Triple::Bitrig:
5788 return new BitrigI386TargetInfo(Triple);
5789 case llvm::Triple::FreeBSD:
5790 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5791 case llvm::Triple::KFreeBSD:
5792 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5793 case llvm::Triple::Minix:
5794 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
5795 case llvm::Triple::Solaris:
5796 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
5797 case llvm::Triple::Cygwin:
5798 return new CygwinX86_32TargetInfo(Triple);
5799 case llvm::Triple::MinGW32:
5800 return new MinGWX86_32TargetInfo(Triple);
5801 case llvm::Triple::Win32:
5802 return new VisualStudioWindowsX86_32TargetInfo(Triple);
5803 case llvm::Triple::Haiku:
5804 return new HaikuX86_32TargetInfo(Triple);
5805 case llvm::Triple::RTEMS:
5806 return new RTEMSX86_32TargetInfo(Triple);
5807 case llvm::Triple::NaCl:
5808 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
5810 return new X86_32TargetInfo(Triple);
5813 case llvm::Triple::x86_64:
5814 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5815 return new DarwinX86_64TargetInfo(Triple);
5818 case llvm::Triple::AuroraUX:
5819 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
5820 case llvm::Triple::Linux:
5821 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
5822 case llvm::Triple::DragonFly:
5823 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
5824 case llvm::Triple::NetBSD:
5825 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
5826 case llvm::Triple::OpenBSD:
5827 return new OpenBSDX86_64TargetInfo(Triple);
5828 case llvm::Triple::Bitrig:
5829 return new BitrigX86_64TargetInfo(Triple);
5830 case llvm::Triple::FreeBSD:
5831 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5832 case llvm::Triple::KFreeBSD:
5833 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5834 case llvm::Triple::Solaris:
5835 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
5836 case llvm::Triple::MinGW32:
5837 return new MinGWX86_64TargetInfo(Triple);
5838 case llvm::Triple::Win32: // This is what Triple.h supports now.
5839 return new VisualStudioWindowsX86_64TargetInfo(Triple);
5840 case llvm::Triple::NaCl:
5841 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
5843 return new X86_64TargetInfo(Triple);
5846 case llvm::Triple::spir: {
5847 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5848 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5850 return new SPIR32TargetInfo(Triple);
5852 case llvm::Triple::spir64: {
5853 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5854 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5856 return new SPIR64TargetInfo(Triple);
5861 /// CreateTargetInfo - Return the target info object for the specified target
5863 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5864 TargetOptions *Opts) {
5865 llvm::Triple Triple(Opts->Triple);
5867 // Construct the target
5868 OwningPtr<TargetInfo> Target(AllocateTarget(Triple));
5870 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5873 Target->setTargetOpts(Opts);
5875 // Set the target CPU if specified.
5876 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5877 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5881 // Set the target ABI if specified.
5882 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5883 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5887 // Set the target C++ ABI.
5888 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5889 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5893 // Set the fp math unit.
5894 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
5895 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
5899 // Compute the default target features, we need the target to handle this
5900 // because features may have dependencies on one another.
5901 llvm::StringMap<bool> Features;
5902 Target->getDefaultFeatures(Features);
5904 // Apply the user specified deltas.
5905 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
5907 const char *Name = Opts->FeaturesAsWritten[I].c_str();
5908 // Apply the feature via the target.
5909 bool Enabled = Name[0] == '+';
5910 Target->setFeatureEnabled(Features, Name + 1, Enabled);
5913 // Add the features to the compile options.
5915 // FIXME: If we are completely confident that we have the right set, we only
5916 // need to pass the minuses.
5917 Opts->Features.clear();
5918 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5919 ie = Features.end(); it != ie; ++it)
5920 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5921 if (!Target->handleTargetFeatures(Opts->Features, Diags))
5924 return Target.take();