1 //===-- lldb_EmulateInstructionARM.h ----------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef lldb_EmulateInstructionARM_h_
11 #define lldb_EmulateInstructionARM_h_
13 #include "lldb/Core/EmulateInstruction.h"
14 #include "lldb/Core/ConstString.h"
15 #include "lldb/Core/Error.h"
16 #include "Plugins/Process/Utility/ARMDefines.h"
18 namespace lldb_private {
20 // ITSession - Keep track of the IT Block progression.
24 ITSession() : ITCounter(0), ITState(0) {}
27 // InitIT - Initializes ITCounter/ITState.
28 bool InitIT(uint32_t bits7_0);
30 // ITAdvance - Updates ITCounter/ITState as IT Block progresses.
33 // InITBlock - Returns true if we're inside an IT Block.
36 // LastInITBlock - Returns true if we're the last instruction inside an IT Block.
39 // GetCond - Gets condition bits for the current thumb instruction.
43 uint32_t ITCounter; // Possible values: 0, 1, 2, 3, 4.
44 uint32_t ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially.
47 class EmulateInstructionARM : public EmulateInstruction
71 static lldb_private::ConstString
72 GetPluginNameStatic ();
75 GetPluginDescriptionStatic ();
77 static lldb_private::EmulateInstruction *
78 CreateInstance (const lldb_private::ArchSpec &arch,
79 InstructionType inst_type);
82 SupportsEmulatingInstructionsOfTypeStatic (InstructionType inst_type)
86 case eInstructionTypeAny:
87 case eInstructionTypePrologueEpilogue:
88 case eInstructionTypePCModifying:
91 case eInstructionTypeAll:
97 virtual lldb_private::ConstString
100 return GetPluginNameStatic();
110 SetTargetTriple (const ArchSpec &arch);
119 EmulateInstructionARM (const ArchSpec &arch) :
120 EmulateInstruction (arch),
122 m_opcode_mode (eModeInvalid),
125 m_ignore_conditions (false)
127 SetArchitecture (arch);
130 // EmulateInstructionARM (const ArchSpec &arch,
131 // bool ignore_conditions,
133 // ReadMemory read_mem_callback,
134 // WriteMemory write_mem_callback,
135 // ReadRegister read_reg_callback,
136 // WriteRegister write_reg_callback) :
137 // EmulateInstruction (arch,
138 // ignore_conditions,
140 // read_mem_callback,
141 // write_mem_callback,
142 // read_reg_callback,
143 // write_reg_callback),
145 // m_opcode_mode (eModeInvalid),
146 // m_opcode_cpsr (0),
152 SupportsEmulatingInstructionsOfType (InstructionType inst_type)
154 return SupportsEmulatingInstructionsOfTypeStatic (inst_type);
158 SetArchitecture (const ArchSpec &arch);
164 SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target);
167 EvaluateInstruction (uint32_t evaluate_options);
170 TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data);
173 GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info);
177 CreateFunctionEntryUnwind (UnwindPlan &unwind_plan);
183 ConditionPassed (const uint32_t opcode,
184 bool *is_conditional = NULL); // Filled in with true if the opcode is a conditional opcode
185 // Filled in with false if the opcode is always executed
188 CurrentCond (const uint32_t opcode);
190 // InITBlock - Returns true if we're in Thumb mode and inside an IT Block.
193 // LastInITBlock - Returns true if we're in Thumb mode and the last instruction inside an IT Block.
194 bool LastInITBlock();
197 BadMode (uint32_t mode);
200 CurrentModeIsPrivileged ();
203 CPSRWriteByInstr (uint32_t value, uint32_t bytemask, bool affect_execstate);
206 BranchWritePC(const Context &context, uint32_t addr);
209 BXWritePC(Context &context, uint32_t addr);
212 LoadWritePC(Context &context, uint32_t addr);
215 ALUWritePC(Context &context, uint32_t addr);
221 SelectInstrSet(Mode arm_or_thumb);
224 WriteBits32Unknown (int n);
227 WriteBits32UnknownToMemory (lldb::addr_t address);
237 } AddWithCarryResult;
240 AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in);
242 // Helper method to read the content of an ARM core register.
244 ReadCoreReg (uint32_t regnum, bool *success);
246 // See A8.6.96 MOV (immediate) Operation.
247 // Default arguments are specified for carry and overflow parameters, which means
248 // not to update the respective flags even if setflags is true.
250 WriteCoreRegOptionalFlags (Context &context,
251 const uint32_t result,
254 const uint32_t carry = ~0u,
255 const uint32_t overflow = ~0u);
258 WriteCoreReg (Context &context,
259 const uint32_t result,
262 // Don't set the flags.
263 return WriteCoreRegOptionalFlags(context, result, Rd, false);
266 // See A8.6.35 CMP (immediate) Operation.
267 // Default arguments are specified for carry and overflow parameters, which means
268 // not to update the respective flags.
270 WriteFlags (Context &context,
271 const uint32_t result,
272 const uint32_t carry = ~0u,
273 const uint32_t overflow = ~0u);
276 MemARead (EmulateInstruction::Context &context,
277 lldb::addr_t address,
282 // This is a stub function corresponding to "MemA[]" in the ARM manual pseudocode, for
283 // aligned reads from memory. Since we are not trying to write a full hardware simulator, and since
284 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
285 // system registers we would need in order to fully implement this function, we will just call
286 // ReadMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
287 // the hardware, we can update this function appropriately.
289 return ReadMemoryUnsigned (context, address, size, fail_value, success_ptr);
293 MemAWrite (EmulateInstruction::Context &context,
294 lldb::addr_t address,
299 // This is a stub function corresponding to "MemA[]" in the ARM manual pseudocode, for
300 // aligned writes to memory. Since we are not trying to write a full hardware simulator, and since
301 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
302 // system registers we would need in order to fully implement this function, we will just call
303 // WriteMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
304 // the hardware, we can update this function appropriately.
306 return WriteMemoryUnsigned (context, address, data_val, size);
311 MemURead (EmulateInstruction::Context &context,
312 lldb::addr_t address,
317 // This is a stub function corresponding to "MemU[]" in the ARM manual pseudocode, for
318 // unaligned reads from memory. Since we are not trying to write a full hardware simulator, and since
319 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
320 // system registers we would need in order to fully implement this function, we will just call
321 // ReadMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
322 // the hardware, we can update this function appropriately.
324 return ReadMemoryUnsigned (context, address, size, fail_value, success_ptr);
328 MemUWrite (EmulateInstruction::Context &context,
329 lldb::addr_t address,
334 // This is a stub function corresponding to "MemU[]" in the ARM manual pseudocode, for
335 // unaligned writes to memory. Since we are not trying to write a full hardware simulator, and since
336 // we are running in User mode (rather than Kernel mode) and therefore won't have access to many of the
337 // system registers we would need in order to fully implement this function, we will just call
338 // WriteMemoryUnsigned from here. In the future, if we decide we do need to do more faithful emulation of
339 // the hardware, we can update this function appropriately.
341 return WriteMemoryUnsigned (context, address, data_val, size);
346 // Typedef for the callback function used during the emulation.
347 // Pass along (ARMEncoding)encoding as the callback data.
359 EmulateInstructionARM::ARMEncoding encoding;
360 uint32_t vfp_variants;
362 bool (EmulateInstructionARM::*callback) (const uint32_t opcode, const EmulateInstructionARM::ARMEncoding encoding);
367 GetFramePointerRegisterNumber () const;
370 GetFramePointerDWARFRegisterNumber () const;
373 GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask);
376 GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask);
380 EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding);
384 EmulatePOP (const uint32_t opcode, const ARMEncoding encoding);
386 // A8.6.8 ADD (SP plus immediate)
388 EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding);
390 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp
392 EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding);
394 // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7
396 EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding);
398 // A8.6.59 LDR (literal)
400 EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding);
402 // A8.6.8 ADD (SP plus immediate)
404 EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding);
406 // A8.6.9 ADD (SP plus register)
408 EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding);
410 // A8.6.23 BL, BLX (immediate)
412 EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding);
414 // A8.6.24 BLX (register)
416 EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding);
420 EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding);
424 EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding);
426 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
428 EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding);
430 // A8.6.215 SUB (SP minus immediate) -- Rd == ip
432 EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding);
434 // A8.6.215 SUB (SP minus immediate)
436 EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding);
438 // A8.6.216 SUB (SP minus register)
440 EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding);
442 // A8.6.194 STR (immediate, ARM) -- Rn == sp
444 EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding);
448 EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding);
452 EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding);
454 // A8.6.218 SVC (previously SWI)
456 EmulateSVC (const uint32_t opcode, const ARMEncoding encoding);
460 EmulateIT (const uint32_t opcode, const ARMEncoding encoding);
464 EmulateNop (const uint32_t opcode, const ARMEncoding encoding);
468 EmulateB (const uint32_t opcode, const ARMEncoding encoding);
472 EmulateCB (const uint32_t opcode, const ARMEncoding encoding);
476 EmulateTB (const uint32_t opcode, const ARMEncoding encoding);
478 // A8.6.4 ADD (immediate, Thumb)
480 EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding);
482 // A8.6.5 ADD (immediate, ARM)
484 EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding);
486 // A8.6.6 ADD (register)
488 EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding);
490 // A8.6.7 ADD (register-shifted register)
492 EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding);
494 // A8.6.97 MOV (register)
496 EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding);
498 // A8.6.96 MOV (immediate)
500 EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding);
502 // A8.6.35 CMP (immediate)
504 EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding);
506 // A8.6.36 CMP (register)
508 EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding);
510 // A8.6.14 ASR (immediate)
512 EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding);
514 // A8.6.15 ASR (register)
516 EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding);
518 // A8.6.88 LSL (immediate)
520 EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding);
522 // A8.6.89 LSL (register)
524 EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding);
526 // A8.6.90 LSR (immediate)
528 EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding);
530 // A8.6.91 LSR (register)
532 EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding);
534 // A8.6.139 ROR (immediate)
536 EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding);
538 // A8.6.140 ROR (register)
540 EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding);
544 EmulateRRX (const uint32_t opcode, const ARMEncoding encoding);
546 // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX
548 EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
550 // Helper method for ASR, LSL, LSR, and ROR (register)
552 EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type);
556 // A8.6.53 LDM/LDMIA/LDMFD
558 EmulateLDM (const uint32_t opcode, const ARMEncoding encoding);
560 // A8.6.54 LDMDA/LDMFA
562 EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding);
564 // A8.6.55 LDMDB/LDMEA
566 EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding);
568 // A8.6.56 LDMIB/LDMED
570 EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding);
572 // A8.6.57 LDR (immediate, Thumb) -- Encoding T1
574 EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding);
576 // A8.6.58 LDR (immediate, ARM) - Encoding A1
578 EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding);
580 // A8.6.59 LDR (literal)
582 EmulateLDRLiteral (const uint32_t, const ARMEncoding encoding);
584 // A8.6.60 LDR (register) - Encoding T1, T2, A1
586 EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding);
588 // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3
590 EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding);
592 // A8.6.62 LDRB (immediate, ARM)
594 EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding);
596 // A8.6.63 LDRB (literal) - Encoding T1, A1
598 EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding);
600 // A8.6.64 LDRB (register) - Encoding T1, T2, A1
602 EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding);
606 EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding);
608 // A8.6.66 LDRD (immediate)
610 EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding);
614 EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding);
616 // A8.6.68 LDRD (register)
618 EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding);
622 EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding);
626 EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding);
630 EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding);
634 EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding);
636 // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3
638 EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding);
640 // A8.6.74 LDRS (immediate, ARM)
642 EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding);
644 // A8.6.75 LDRH (literal) - Encoding T1, A1
646 EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding);
648 // A8.6.76 LDRH (register) - Encoding T1, T2, A1
650 EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding);
654 EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding);
656 // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1
658 EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding);
660 // A8.6.79 LDRSB (literal) - Encoding T1, A1
662 EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding);
664 // A8.6.80 LDRSB (register) - Encoding T1, T2, A1
666 EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding);
670 EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding);
672 // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1
674 EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding);
676 // A8.6.83 LDRSH (literal) - Encoding T1, A1
678 EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding);
680 // A8.6.84 LDRSH (register) - Encoding T1, T2, A1
682 EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding);
686 EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding);
690 EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding);
695 // A8.6.189 STM/STMIA/STMEA
697 EmulateSTM (const uint32_t opcode, const ARMEncoding encoding);
699 // A8.6.190 STMDA/STMED
701 EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding);
703 // A8.6.191 STMDB/STMFD
705 EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding);
707 // A8.6.192 STMIB/STMFA
709 EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding);
711 // A8.6.193 STR (immediate, Thumb)
713 EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding);
715 // A8.6.194 STR (immediate, ARM)
717 EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding);
719 // A8.6.195 STR (register)
721 EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding);
723 // A8.6.196 STRB (immediate, Thumb)
725 EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding);
727 // A8.6.197 STRB (immediate, ARM)
729 EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding);
731 // A8.6.198 STRB (register)
733 EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding);
737 EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding);
739 // A8.6.200 STRD (immediate)
741 EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding);
743 // A8.6.201 STRD (register)
745 EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding);
749 EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding);
753 EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding);
757 EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding);
761 EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding);
763 // A8.6.206 STRH (immediate, Thumb)
765 EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding);
767 // A8.6.207 STRH (immediate, ARM)
769 EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding);
771 // A8.6.208 STRH (register)
773 EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding);
777 EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding);
781 EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding);
783 // A8.6.1 ADC (immediate)
785 EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding);
787 // A8.6.2 ADC (Register)
789 EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding);
793 EmulateADR (const uint32_t opcode, const ARMEncoding encoding);
795 // A8.6.11 AND (immediate)
797 EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding);
799 // A8.6.12 AND (register)
801 EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding);
803 // A8.6.19 BIC (immediate)
805 EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding);
807 // A8.6.20 BIC (register)
809 EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding);
813 EmulateBXJ (const uint32_t opcode, const ARMEncoding encoding);
815 // A8.6.32 CMN (immediate)
817 EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding);
819 // A8.6.33 CMN (register)
821 EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding);
823 // A8.6.44 EOR (immediate)
825 EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding);
827 // A8.6.45 EOR (register)
829 EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding);
833 EmulateMUL (const uint32_t opcode, const ARMEncoding encoding);
835 // A8.6.106 MVN (immediate)
837 EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding);
839 // A8.6.107 MVN (register)
841 EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding);
843 // A8.6.113 ORR (immediate)
845 EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding);
847 // A8.6.114 ORR (register)
849 EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding);
851 // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1
853 EmulatePLDImmediate (const uint32_t opcode, const ARMEncoding encoding);
855 // A8.6.119 PLI (immediate,literal) - Encoding T3, A1
857 EmulatePLIImmediate (const uint32_t opcode, const ARMEncoding encoding);
859 // A8.6.120 PLI (register) - Encoding T1, A1
861 EmulatePLIRegister (const uint32_t opcode, const ARMEncoding encoding);
863 // A8.6.141 RSB (immediate)
865 EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding);
867 // A8.6.142 RSB (register)
869 EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding);
871 // A8.6.144 RSC (immediate)
873 EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding);
875 // A8.6.145 RSC (register)
877 EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding);
879 // A8.6.150 SBC (immediate)
881 EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding);
883 // A8.6.151 SBC (register)
885 EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding);
887 // A8.6.211 SUB (immediate, Thumb)
889 EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding);
891 // A8.6.212 SUB (immediate, ARM)
893 EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding);
895 // A8.6.213 SUB (register)
897 EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding);
899 // A8.6.214 SUB (register-shifted register)
901 EmulateSUBRegShift (const uint32_t opcode, const ARMEncoding encoding);
903 // A8.6.222 SXTB - Encoding T1
905 EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding);
907 // A8.6.224 SXTH - EncodingT1
909 EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding);
911 // A8.6.227 TEQ (immediate) - Encoding A1
913 EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding);
915 // A8.6.228 TEQ (register) - Encoding A1
917 EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding);
919 // A8.6.230 TST (immediate) - Encoding A1
921 EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding);
923 // A8.6.231 TST (register) - Encoding T1, A1
925 EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding);
927 // A8.6.262 UXTB - Encoding T1
929 EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding);
931 // A8.6.264 UXTH - Encoding T1
933 EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding);
937 EmulateRFE (const uint32_t opcode, const ARMEncoding encoding);
941 EmulateVLDM (const uint32_t opcode, const ARMEncoding encoding);
945 EmulateVSTM (const uint32_t opcode, const ARMEncoding encoding);
947 // A8.6.307 VLD1 (multiple single elements)
949 EmulateVLD1Multiple (const uint32_t opcode, const ARMEncoding encoding);
951 // A8.6.308 VLD1 (single element to one lane)
953 EmulateVLD1Single (const uint32_t opcode, const ARMEncoding encoding);
955 // A8.6.309 VLD1 (single element to all lanes)
957 EmulateVLD1SingleAll (const uint32_t opcode, const ARMEncoding encoding);
959 // A8.6.391 VST1 (multiple single elements)
961 EmulateVST1Multiple (const uint32_t opcode, const ARMEncoding encoding);
963 // A8.6.392 VST1 (single element from one lane)
965 EmulateVST1Single (const uint32_t opcode, const ARMEncoding encoding);
969 EmulateVLDR (const uint32_t opcode, const ARMEncoding encoding);
974 EmulateVSTR (const uint32_t opcode, const ARMEncoding encoding);
976 // B6.2.13 SUBS PC, LR and related instructions
978 EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncoding encoding);
982 uint32_t m_opcode_cpsr;
983 uint32_t m_new_inst_cpsr; // This can get updated by the opcode.
984 ITSession m_it_session;
985 bool m_ignore_conditions;
988 } // namespace lldb_private
990 #endif // lldb_EmulateInstructionARM_h_