1 //===-- RegisterContextDarwin_i386.cpp --------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 #include <stddef.h> // offsetof
15 // Other libraries and framework includes
16 #include "lldb/Core/DataBufferHeap.h"
17 #include "lldb/Core/DataExtractor.h"
18 #include "lldb/Core/Log.h"
19 #include "lldb/Core/RegisterValue.h"
20 #include "lldb/Core/Scalar.h"
21 #include "lldb/Host/Endian.h"
22 #include "llvm/Support/Compiler.h"
24 // Support building against older versions of LLVM, this macro was added
26 #ifndef LLVM_EXTENSION
27 #define LLVM_EXTENSION
31 #include "RegisterContextDarwin_i386.h"
34 using namespace lldb_private;
168 gdb_fctrl = 24, gdb_fcw = gdb_fctrl,
169 gdb_fstat = 25, gdb_fsw = gdb_fstat,
170 gdb_ftag = 26, gdb_ftw = gdb_ftag,
171 gdb_fiseg = 27, gdb_fpu_cs = gdb_fiseg,
172 gdb_fioff = 28, gdb_ip = gdb_fioff,
173 gdb_foseg = 29, gdb_fpu_ds = gdb_foseg,
174 gdb_fooff = 30, gdb_dp = gdb_fooff,
195 RegisterContextDarwin_i386::RegisterContextDarwin_i386 (Thread &thread, uint32_t concrete_frame_idx) :
196 RegisterContext(thread, concrete_frame_idx),
202 for (i=0; i<kNumErrors; i++)
210 RegisterContextDarwin_i386::~RegisterContextDarwin_i386()
216 #define GPR_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::GPR, reg))
217 #define FPU_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::FPU, reg) + sizeof (RegisterContextDarwin_i386::GPR))
218 #define EXC_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_i386::EXC, reg) + sizeof (RegisterContextDarwin_i386::GPR) + sizeof (RegisterContextDarwin_i386::FPU))
220 // These macros will auto define the register name, alt name, register size,
221 // register offset, encoding, format and native register. This ensures that
222 // the register state structures are defined correctly and have the correct
223 // sizes and offsets.
224 #define DEFINE_GPR(reg, alt) #reg, alt, sizeof(((RegisterContextDarwin_i386::GPR *)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, eFormatHex
225 #define DEFINE_FPU_UINT(reg) #reg, NULL, sizeof(((RegisterContextDarwin_i386::FPU *)NULL)->reg), FPU_OFFSET(reg), eEncodingUint, eFormatHex
226 #define DEFINE_FPU_VECT(reg, i) #reg#i, NULL, sizeof(((RegisterContextDarwin_i386::FPU *)NULL)->reg[i].bytes), FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, { LLDB_INVALID_REGNUM, dwarf_##reg##i, LLDB_INVALID_REGNUM, gdb_##reg##i, fpu_##reg##i }, NULL, NULL
228 #define DEFINE_EXC(reg) #reg, NULL, sizeof(((RegisterContextDarwin_i386::EXC *)NULL)->reg), EXC_OFFSET(reg), eEncodingUint, eFormatHex
229 #define REG_CONTEXT_SIZE (sizeof (RegisterContextDarwin_i386::GPR) + sizeof (RegisterContextDarwin_i386::FPU) + sizeof (RegisterContextDarwin_i386::EXC))
231 static RegisterInfo g_register_infos[] =
233 // Macro auto defines most stuff GCC DWARF GENERIC GDB LLDB VALUE REGS INVALIDATE REGS
234 // =============================== ======================= =================== ========================= ================== ================= ========== ===============
235 { DEFINE_GPR(eax , NULL) , { gcc_eax , dwarf_eax , LLDB_INVALID_REGNUM , gdb_eax , gpr_eax }, NULL, NULL},
236 { DEFINE_GPR(ebx , NULL) , { gcc_ebx , dwarf_ebx , LLDB_INVALID_REGNUM , gdb_ebx , gpr_ebx }, NULL, NULL},
237 { DEFINE_GPR(ecx , NULL) , { gcc_ecx , dwarf_ecx , LLDB_INVALID_REGNUM , gdb_ecx , gpr_ecx }, NULL, NULL},
238 { DEFINE_GPR(edx , NULL) , { gcc_edx , dwarf_edx , LLDB_INVALID_REGNUM , gdb_edx , gpr_edx }, NULL, NULL},
239 { DEFINE_GPR(edi , NULL) , { gcc_edi , dwarf_edi , LLDB_INVALID_REGNUM , gdb_edi , gpr_edi }, NULL, NULL},
240 { DEFINE_GPR(esi , NULL) , { gcc_esi , dwarf_esi , LLDB_INVALID_REGNUM , gdb_esi , gpr_esi }, NULL, NULL},
241 { DEFINE_GPR(ebp , "fp") , { gcc_ebp , dwarf_ebp , LLDB_REGNUM_GENERIC_FP , gdb_ebp , gpr_ebp }, NULL, NULL},
242 { DEFINE_GPR(esp , "sp") , { gcc_esp , dwarf_esp , LLDB_REGNUM_GENERIC_SP , gdb_esp , gpr_esp }, NULL, NULL},
243 { DEFINE_GPR(ss , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ss , gpr_ss }, NULL, NULL},
244 { DEFINE_GPR(eflags , "flags") , { gcc_eflags , dwarf_eflags , LLDB_REGNUM_GENERIC_FLAGS , gdb_eflags , gpr_eflags }, NULL, NULL},
245 { DEFINE_GPR(eip , "pc") , { gcc_eip , dwarf_eip , LLDB_REGNUM_GENERIC_PC , gdb_eip , gpr_eip }, NULL, NULL},
246 { DEFINE_GPR(cs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_cs , gpr_cs }, NULL, NULL},
247 { DEFINE_GPR(ds , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ds , gpr_ds }, NULL, NULL},
248 { DEFINE_GPR(es , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_es , gpr_es }, NULL, NULL},
249 { DEFINE_GPR(fs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fs , gpr_fs }, NULL, NULL},
250 { DEFINE_GPR(gs , NULL) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_gs , gpr_gs }, NULL, NULL},
252 { DEFINE_FPU_UINT(fcw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fcw , fpu_fcw }, NULL, NULL},
253 { DEFINE_FPU_UINT(fsw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fsw , fpu_fsw }, NULL, NULL},
254 { DEFINE_FPU_UINT(ftw) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ftw , fpu_ftw }, NULL, NULL},
255 { DEFINE_FPU_UINT(fop) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fop , fpu_fop }, NULL, NULL},
256 { DEFINE_FPU_UINT(ip) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ip , fpu_ip }, NULL, NULL},
257 { DEFINE_FPU_UINT(cs) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_cs , fpu_cs }, NULL, NULL},
258 { DEFINE_FPU_UINT(dp) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_dp , fpu_dp }, NULL, NULL},
259 { DEFINE_FPU_UINT(ds) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_ds , fpu_ds }, NULL, NULL},
260 { DEFINE_FPU_UINT(mxcsr) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_mxcsr , fpu_mxcsr }, NULL, NULL},
261 { DEFINE_FPU_UINT(mxcsrmask) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_mxcsrmask}, NULL, NULL},
262 { DEFINE_FPU_VECT(stmm,0) },
263 { DEFINE_FPU_VECT(stmm,1) },
264 { DEFINE_FPU_VECT(stmm,2) },
265 { DEFINE_FPU_VECT(stmm,3) },
266 { DEFINE_FPU_VECT(stmm,4) },
267 { DEFINE_FPU_VECT(stmm,5) },
268 { DEFINE_FPU_VECT(stmm,6) },
269 { DEFINE_FPU_VECT(stmm,7) },
270 { DEFINE_FPU_VECT(xmm,0) },
271 { DEFINE_FPU_VECT(xmm,1) },
272 { DEFINE_FPU_VECT(xmm,2) },
273 { DEFINE_FPU_VECT(xmm,3) },
274 { DEFINE_FPU_VECT(xmm,4) },
275 { DEFINE_FPU_VECT(xmm,5) },
276 { DEFINE_FPU_VECT(xmm,6) },
277 { DEFINE_FPU_VECT(xmm,7) },
279 { DEFINE_EXC(trapno) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_trapno }, NULL, NULL},
280 { DEFINE_EXC(err) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_err }, NULL, NULL},
281 { DEFINE_EXC(faultvaddr) , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_faultvaddr }, NULL, NULL}
284 static size_t k_num_register_infos = (sizeof(g_register_infos)/sizeof(RegisterInfo));
287 RegisterContextDarwin_i386::InvalidateAllRegisters ()
289 InvalidateAllRegisterStates();
294 RegisterContextDarwin_i386::GetRegisterCount ()
296 assert(k_num_register_infos == k_num_registers);
297 return k_num_registers;
301 RegisterContextDarwin_i386::GetRegisterInfoAtIndex (size_t reg)
303 assert(k_num_register_infos == k_num_registers);
304 if (reg < k_num_registers)
305 return &g_register_infos[reg];
310 RegisterContextDarwin_i386::GetRegisterInfosCount ()
312 return k_num_register_infos;
316 RegisterContextDarwin_i386::GetRegisterInfos ()
318 return g_register_infos;
322 // General purpose registers
344 // Floating point registers
376 // Exception registers
386 // Number of registers in each register set
387 const size_t k_num_gpr_registers = sizeof(g_gpr_regnums) / sizeof(uint32_t);
388 const size_t k_num_fpu_registers = sizeof(g_fpu_regnums) / sizeof(uint32_t);
389 const size_t k_num_exc_registers = sizeof(g_exc_regnums) / sizeof(uint32_t);
391 //----------------------------------------------------------------------
392 // Register set definitions. The first definitions at register set index
393 // of zero is for all registers, followed by other registers sets. The
394 // register information for the all register set need not be filled in.
395 //----------------------------------------------------------------------
396 static const RegisterSet g_reg_sets[] =
398 { "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, },
399 { "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums },
400 { "Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums }
403 const size_t k_num_regsets = sizeof(g_reg_sets) / sizeof(RegisterSet);
407 RegisterContextDarwin_i386::GetRegisterSetCount ()
409 return k_num_regsets;
413 RegisterContextDarwin_i386::GetRegisterSet (size_t reg_set)
415 if (reg_set < k_num_regsets)
416 return &g_reg_sets[reg_set];
421 //----------------------------------------------------------------------
422 // Register information definitions for 32 bit i386.
423 //----------------------------------------------------------------------
425 RegisterContextDarwin_i386::GetSetForNativeRegNum (int reg_num)
427 if (reg_num < fpu_fcw)
429 else if (reg_num < exc_trapno)
431 else if (reg_num < k_num_registers)
438 RegisterContextDarwin_i386::LogGPR(Log *log, const char *title)
443 log->Printf ("%s", title);
444 for (uint32_t i=0; i<k_num_gpr_registers; i++)
446 uint32_t reg = gpr_eax + i;
447 log->Printf("%12s = 0x%8.8x", g_register_infos[reg].name, (&gpr.eax)[reg]);
455 RegisterContextDarwin_i386::ReadGPR (bool force)
458 if (force || !RegisterSetIsCached(set))
460 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
462 return GetError(set, Read);
466 RegisterContextDarwin_i386::ReadFPU (bool force)
469 if (force || !RegisterSetIsCached(set))
471 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
473 return GetError(set, Read);
477 RegisterContextDarwin_i386::ReadEXC (bool force)
480 if (force || !RegisterSetIsCached(set))
482 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
484 return GetError(set, Read);
488 RegisterContextDarwin_i386::WriteGPR ()
491 if (!RegisterSetIsCached(set))
493 SetError (set, Write, -1);
496 SetError (set, Write, DoWriteGPR(GetThreadID(), set, gpr));
497 SetError (set, Read, -1);
498 return GetError(set, Write);
502 RegisterContextDarwin_i386::WriteFPU ()
505 if (!RegisterSetIsCached(set))
507 SetError (set, Write, -1);
510 SetError (set, Write, DoWriteFPU(GetThreadID(), set, fpu));
511 SetError (set, Read, -1);
512 return GetError(set, Write);
516 RegisterContextDarwin_i386::WriteEXC ()
519 if (!RegisterSetIsCached(set))
521 SetError (set, Write, -1);
524 SetError (set, Write, DoWriteEXC(GetThreadID(), set, exc));
525 SetError (set, Read, -1);
526 return GetError(set, Write);
530 RegisterContextDarwin_i386::ReadRegisterSet (uint32_t set, bool force)
534 case GPRRegSet: return ReadGPR(force);
535 case FPURegSet: return ReadFPU(force);
536 case EXCRegSet: return ReadEXC(force);
543 RegisterContextDarwin_i386::WriteRegisterSet (uint32_t set)
545 // Make sure we have a valid context to set.
546 if (RegisterSetIsCached(set))
550 case GPRRegSet: return WriteGPR();
551 case FPURegSet: return WriteFPU();
552 case EXCRegSet: return WriteEXC();
560 RegisterContextDarwin_i386::ReadRegister (const RegisterInfo *reg_info,
561 RegisterValue &value)
563 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
564 int set = RegisterContextDarwin_i386::GetSetForNativeRegNum (reg);
569 if (ReadRegisterSet(set, false) != 0)
590 value = (&gpr.eax)[reg - gpr_eax];
630 value = fpu.mxcsrmask;
641 // These values don't fit into scalar types,
642 // RegisterContext::ReadRegisterBytes() must be used for these
644 //::memcpy (reg_value.value.vector.uint8, fpu.stmm[reg - fpu_stmm0].bytes, 10);
655 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
656 // must be used for these registers
657 //::memcpy (reg_value.value.vector.uint8, fpu.xmm[reg - fpu_xmm0].bytes, 16);
669 value = exc.faultvaddr;
680 RegisterContextDarwin_i386::WriteRegister (const RegisterInfo *reg_info,
681 const RegisterValue &value)
683 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
684 int set = GetSetForNativeRegNum (reg);
689 if (ReadRegisterSet(set, false) != 0)
710 (&gpr.eax)[reg - gpr_eax] = value.GetAsUInt32();
714 fpu.fcw = value.GetAsUInt16();
718 fpu.fsw = value.GetAsUInt16();
722 fpu.ftw = value.GetAsUInt8();
726 fpu.fop = value.GetAsUInt16();
730 fpu.ip = value.GetAsUInt32();
734 fpu.cs = value.GetAsUInt16();
738 fpu.dp = value.GetAsUInt32();
742 fpu.ds = value.GetAsUInt16();
746 fpu.mxcsr = value.GetAsUInt32();
750 fpu.mxcsrmask = value.GetAsUInt32();
761 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
762 // must be used for these registers
763 ::memcpy (fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(), value.GetByteSize());
774 // These values don't fit into scalar types, RegisterContext::ReadRegisterBytes()
775 // must be used for these registers
776 ::memcpy (fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(), value.GetByteSize());
780 exc.trapno = value.GetAsUInt32();
784 exc.err = value.GetAsUInt32();
788 exc.faultvaddr = value.GetAsUInt32();
794 return WriteRegisterSet(set) == 0;
798 RegisterContextDarwin_i386::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
800 data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
802 ReadGPR (false) == 0 &&
803 ReadFPU (false) == 0 &&
804 ReadEXC (false) == 0)
806 uint8_t *dst = data_sp->GetBytes();
807 ::memcpy (dst, &gpr, sizeof(gpr));
810 ::memcpy (dst, &fpu, sizeof(fpu));
813 ::memcpy (dst, &exc, sizeof(exc));
820 RegisterContextDarwin_i386::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
822 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE)
824 const uint8_t *src = data_sp->GetBytes();
825 ::memcpy (&gpr, src, sizeof(gpr));
828 ::memcpy (&fpu, src, sizeof(fpu));
831 ::memcpy (&exc, src, sizeof(exc));
832 uint32_t success_count = 0;
839 return success_count == 3;
846 RegisterContextDarwin_i386::ConvertRegisterKindToRegisterNumber (uint32_t kind, uint32_t reg)
848 if (kind == eRegisterKindGeneric)
852 case LLDB_REGNUM_GENERIC_PC: return gpr_eip;
853 case LLDB_REGNUM_GENERIC_SP: return gpr_esp;
854 case LLDB_REGNUM_GENERIC_FP: return gpr_ebp;
855 case LLDB_REGNUM_GENERIC_FLAGS: return gpr_eflags;
856 case LLDB_REGNUM_GENERIC_RA:
861 else if (kind == eRegisterKindGCC || kind == eRegisterKindDWARF)
865 case dwarf_eax: return gpr_eax;
866 case dwarf_ecx: return gpr_ecx;
867 case dwarf_edx: return gpr_edx;
868 case dwarf_ebx: return gpr_ebx;
869 case dwarf_esp: return gpr_esp;
870 case dwarf_ebp: return gpr_ebp;
871 case dwarf_esi: return gpr_esi;
872 case dwarf_edi: return gpr_edi;
873 case dwarf_eip: return gpr_eip;
874 case dwarf_eflags: return gpr_eflags;
875 case dwarf_stmm0: return fpu_stmm0;
876 case dwarf_stmm1: return fpu_stmm1;
877 case dwarf_stmm2: return fpu_stmm2;
878 case dwarf_stmm3: return fpu_stmm3;
879 case dwarf_stmm4: return fpu_stmm4;
880 case dwarf_stmm5: return fpu_stmm5;
881 case dwarf_stmm6: return fpu_stmm6;
882 case dwarf_stmm7: return fpu_stmm7;
883 case dwarf_xmm0: return fpu_xmm0;
884 case dwarf_xmm1: return fpu_xmm1;
885 case dwarf_xmm2: return fpu_xmm2;
886 case dwarf_xmm3: return fpu_xmm3;
887 case dwarf_xmm4: return fpu_xmm4;
888 case dwarf_xmm5: return fpu_xmm5;
889 case dwarf_xmm6: return fpu_xmm6;
890 case dwarf_xmm7: return fpu_xmm7;
895 else if (kind == eRegisterKindGDB)
899 case gdb_eax : return gpr_eax;
900 case gdb_ebx : return gpr_ebx;
901 case gdb_ecx : return gpr_ecx;
902 case gdb_edx : return gpr_edx;
903 case gdb_esi : return gpr_esi;
904 case gdb_edi : return gpr_edi;
905 case gdb_ebp : return gpr_ebp;
906 case gdb_esp : return gpr_esp;
907 case gdb_eip : return gpr_eip;
908 case gdb_eflags : return gpr_eflags;
909 case gdb_cs : return gpr_cs;
910 case gdb_ss : return gpr_ss;
911 case gdb_ds : return gpr_ds;
912 case gdb_es : return gpr_es;
913 case gdb_fs : return gpr_fs;
914 case gdb_gs : return gpr_gs;
915 case gdb_stmm0 : return fpu_stmm0;
916 case gdb_stmm1 : return fpu_stmm1;
917 case gdb_stmm2 : return fpu_stmm2;
918 case gdb_stmm3 : return fpu_stmm3;
919 case gdb_stmm4 : return fpu_stmm4;
920 case gdb_stmm5 : return fpu_stmm5;
921 case gdb_stmm6 : return fpu_stmm6;
922 case gdb_stmm7 : return fpu_stmm7;
923 case gdb_fctrl : return fpu_fctrl;
924 case gdb_fstat : return fpu_fstat;
925 case gdb_ftag : return fpu_ftag;
926 case gdb_fiseg : return fpu_fiseg;
927 case gdb_fioff : return fpu_fioff;
928 case gdb_foseg : return fpu_foseg;
929 case gdb_fooff : return fpu_fooff;
930 case gdb_fop : return fpu_fop;
931 case gdb_xmm0 : return fpu_xmm0;
932 case gdb_xmm1 : return fpu_xmm1;
933 case gdb_xmm2 : return fpu_xmm2;
934 case gdb_xmm3 : return fpu_xmm3;
935 case gdb_xmm4 : return fpu_xmm4;
936 case gdb_xmm5 : return fpu_xmm5;
937 case gdb_xmm6 : return fpu_xmm6;
938 case gdb_xmm7 : return fpu_xmm7;
939 case gdb_mxcsr : return fpu_mxcsr;
944 else if (kind == eRegisterKindLLDB)
948 return LLDB_INVALID_REGNUM;
953 RegisterContextDarwin_i386::HardwareSingleStep (bool enable)
955 if (ReadGPR(false) != 0)
958 const uint32_t trace_bit = 0x100u;
961 // If the trace bit is already set, there is nothing to do
962 if (gpr.eflags & trace_bit)
965 gpr.eflags |= trace_bit;
969 // If the trace bit is already cleared, there is nothing to do
970 if (gpr.eflags & trace_bit)
971 gpr.eflags &= ~trace_bit;
976 return WriteGPR() == 0;