2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
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11 * This product includes software developed by the University of
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38 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
39 * $NetBSD: fpu_implode.c,v 1.8 2001/08/26 05:44:46 eeh Exp $
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
46 * FPU subroutines: `implode' internal format numbers into the machine's
47 * `packed binary' format.
50 #include <sys/param.h>
56 #include <machine/frame.h>
57 #include <machine/fp.h>
58 #include <machine/fsr.h>
59 #include <machine/ieee.h>
60 #include <machine/instr.h>
62 #include "fpu_arith.h"
64 #include "fpu_extern.h"
65 #include "__sparc_utrap_private.h"
67 static int fpround(struct fpemu *, struct fpn *);
68 static int toinf(struct fpemu *, int);
71 * Round a number (algorithm from Motorola MC68882 manual, modified for
72 * our internal format). Set inexact exception if rounding is required.
73 * Return true iff we rounded up.
75 * After rounding, we discard the guard and round bits by shifting right
76 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
77 * This saves effort later.
79 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
80 * responsibility to fix this if necessary.
83 fpround(struct fpemu *fe, struct fpn *fp)
96 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
97 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
98 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
101 if ((gr | s) == 0) /* result is exact: no rounding needed */
104 fe->fe_cx |= FSR_NX; /* inexact */
106 /* Go to rounddown to round down; break to round up. */
107 switch (FSR_GET_RD(fe->fe_fsr)) {
111 * Round only if guard is set (gr & 2). If guard is set,
112 * but round & sticky both clear, then we want to round
113 * but have a tie, so round to even, i.e., add 1 iff odd.
117 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
122 /* Round towards zero, i.e., down. */
126 /* Round towards -Inf: up if negative, down if positive. */
132 /* Round towards +Inf: up if positive, down otherwise. */
138 /* Bump low bit of mantissa, with carry. */
140 FPU_ADDCS(m2, m2, 0);
141 FPU_ADDCS(m1, m1, 0);
158 * For overflow: return true if overflow is to go to +/-Inf, according
159 * to the sign of the overflowing result. If false, overflow is to go
160 * to the largest magnitude value instead.
163 toinf(struct fpemu *fe, int sign)
167 /* look at rounding direction */
168 switch (FSR_GET_RD(fe->fe_fsr)) {
170 case FSR_RD_N: /* the nearest value is always Inf */
174 case FSR_RD_Z: /* toward 0 => never towards Inf */
178 case FSR_RD_PINF: /* toward +Inf iff positive */
182 case FSR_RD_NINF: /* toward -Inf iff negative */
190 * fpn -> int (int value returned as return value).
192 * N.B.: this conversion always rounds towards zero (this is a peculiarity
193 * of the SPARC instruction set).
204 switch (fp->fp_class) {
210 * If exp >= 2^32, overflow. Otherwise shift value right
211 * into last mantissa word (this will not exceed 0xffffffff),
212 * shifting any guard and round bits out into the sticky
213 * bit. Then ``round'' towards zero, i.e., just set an
214 * inexact exception if sticky is set (see round()).
215 * If the result is > 0x80000000, or is positive and equals
216 * 0x80000000, overflow; otherwise the last fraction word
219 if ((exp = fp->fp_exp) >= 32)
221 /* NB: the following includes exp < 0 cases */
222 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
225 if (i >= ((u_int)0x80000000 + sign))
227 return (sign ? -i : i);
229 default: /* Inf, qNaN, sNaN */
232 /* overflow: replace any inexact exception with invalid */
233 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
234 return (0x7fffffff + sign);
238 * fpn -> extended int (high bits of int value returned as return value).
240 * N.B.: this conversion always rounds towards zero (this is a peculiarity
241 * of the SPARC instruction set).
244 __fpu_ftox(fe, fp, res)
253 switch (fp->fp_class) {
260 * If exp >= 2^64, overflow. Otherwise shift value
261 * right into last mantissa word (this will not exceed
262 * 0xffffffffffffffff), shifting any guard and round
263 * bits out into the sticky bit. Then ``round'' towards
264 * zero, i.e., just set an inexact exception if sticky
265 * is set (see round()).
266 * If the result is > 0x8000000000000000, or is positive
267 * and equals 0x8000000000000000, overflow; otherwise
268 * the last fraction word is the result.
270 if ((exp = fp->fp_exp) >= 64)
272 /* NB: the following includes exp < 0 cases */
273 if (__fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
275 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
276 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
282 default: /* Inf, qNaN, sNaN */
285 /* overflow: replace any inexact exception with invalid */
286 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
287 i = 0x7fffffffffffffffLL + sign;
289 res[1] = i & 0xffffffff;
294 * fpn -> single (32 bit single returned as return value).
295 * We assume <= 29 bits in a single-precision fraction (1.f part).
302 u_int sign = fp->fp_sign << 31;
305 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
306 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
308 /* Take care of non-numbers first. */
311 * Preserve upper bits of NaN, per SPARC V8 appendix N.
312 * Note that fp->fp_mant[0] has the quiet bit set,
313 * even if it is classified as a signalling NaN.
315 (void) __fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
316 exp = SNG_EXP_INFNAN;
320 return (sign | SNG_EXP(SNG_EXP_INFNAN));
325 * Normals (including subnormals). Drop all the fraction bits
326 * (including the explicit ``implied'' 1 bit) down into the
327 * single-precision range. If the number is subnormal, move
328 * the ``implied'' 1 into the explicit range as well, and shift
329 * right to introduce leading zeroes. Rounding then acts
330 * differently for normals and subnormals: the largest subnormal
331 * may round to the smallest normal (1.0 x 2^minexp), or may
332 * remain subnormal. A number that is subnormal before rounding
333 * will signal an underflow if the result is inexact or if underflow
336 * Rounding a normal, on the other hand, always produces another
337 * normal (although either way the result might be too big for
338 * single precision, and cause an overflow). If rounding a
339 * normal produces 2.0 in the fraction, we need not adjust that
340 * fraction at all, since both 1.0 and 2.0 are zero under the
343 * Note that the guard and round bits vanish from the number after
346 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
347 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
348 (void) __fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
349 if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) {
351 return (sign | SNG_EXP(1) | 0);
353 if ((fe->fe_cx & FSR_NX) ||
354 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
356 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
358 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
359 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
361 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
362 __utrap_panic("fpu_ftos");
364 if (fpround(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
366 if (exp >= SNG_EXP_INFNAN) {
367 /* overflow to inf or to max single */
368 fe->fe_cx |= FSR_OF | FSR_NX;
370 return (sign | SNG_EXP(SNG_EXP_INFNAN));
371 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
375 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
379 * fpn -> double (32 bit high-order result returned; 32-bit low order result
380 * left in res[1]). Assumes <= 61 bits in double precision fraction.
382 * This code mimics fpu_ftos; see it for comments.
385 __fpu_ftod(fe, fp, res)
390 u_int sign = fp->fp_sign << 31;
393 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
394 #define DBL_MASK (DBL_EXP(1) - 1)
397 (void) __fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
398 exp = DBL_EXP_INFNAN;
402 sign |= DBL_EXP(DBL_EXP_INFNAN);
410 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
411 (void) __fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
412 if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
415 return (sign | DBL_EXP(1) | 0);
417 if ((fe->fe_cx & FSR_NX) ||
418 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
423 (void) __fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
424 if (fpround(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
426 if (exp >= DBL_EXP_INFNAN) {
427 fe->fe_cx |= FSR_OF | FSR_NX;
428 if (toinf(fe, sign)) {
430 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
433 return (sign | DBL_EXP(DBL_EXP_INFNAN - 1) | DBL_MASK);
436 res[1] = fp->fp_mant[3];
437 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
441 * fpn -> extended (32 bit high-order result returned; low-order fraction
442 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but
443 * our internal format *is* extended precision, plus 2 bits for guard/round,
444 * so we can avoid a small bit of work.
447 __fpu_ftoq(fe, fp, res)
452 u_int sign = fp->fp_sign << 31;
455 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31))
456 #define EXT_MASK (EXT_EXP(1) - 1)
459 (void) __fpu_shr(fp, 2); /* since we are not rounding */
460 exp = EXT_EXP_INFNAN;
464 sign |= EXT_EXP(EXT_EXP_INFNAN);
468 zero: res[1] = res[2] = res[3] = 0;
472 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) {
473 (void) __fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
474 if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) {
476 res[1] = res[2] = res[3] = 0;
477 return (sign | EXT_EXP(1) | 0);
479 if ((fe->fe_cx & FSR_NX) ||
480 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
485 /* Since internal == extended, no need to shift here. */
486 if (fpround(fe, fp) && fp->fp_mant[0] == EXT_EXP(2))
488 if (exp >= EXT_EXP_INFNAN) {
489 fe->fe_cx |= FSR_OF | FSR_NX;
490 if (toinf(fe, sign)) {
491 res[1] = res[2] = res[3] = 0;
492 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
494 res[1] = res[2] = res[3] = ~0;
495 return (sign | EXT_EXP(EXT_EXP_INFNAN - 1) | EXT_MASK);
498 res[1] = fp->fp_mant[1];
499 res[2] = fp->fp_mant[2];
500 res[3] = fp->fp_mant[3];
501 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK));
505 * Implode an fpn, writing the result into the given space.
508 __fpu_implode(fe, fp, type, space)
517 space[0] = __fpu_ftox(fe, fp, space);
521 space[0] = __fpu_ftoi(fe, fp);
525 space[0] = __fpu_ftos(fe, fp);
529 space[0] = __fpu_ftod(fe, fp, space);
533 /* funky rounding precision options ?? */
534 space[0] = __fpu_ftoq(fe, fp, space);
538 __utrap_panic("fpu_implode");
540 DPRINTF(FPE_REG, ("fpu_implode: %x %x %x %x\n",
541 space[0], space[1], space[2], space[3]));