1 .\" Copyright (c) 2008 Joseph Koshy. All rights reserved.
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31 .Nd measurement events for
42 CPUs contain PMCs conforming to version 3 of the
44 performance measurement architecture.
45 These CPUs contains two classes of PMCs:
46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
50 Programmable counters that may be configured to count one of a defined
51 set of hardware events.
54 The number of PMCs available in each class and their widths need to be
55 determined at run time by calling
58 Intel Atom PMCs are documented in
60 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%T "Volume 3: System Programming Guide"
62 .%N "Order Number 253669-027US"
64 .%Q "Intel Corporation"
66 .Ss ATOM FIXED FUNCTION PMCS
67 These PMCs and their supported events are documented in
69 .Ss ATOM PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
72 .It Em Capability Ta Em Support
73 .It PMC_CAP_CASCADE Ta \&No
74 .It PMC_CAP_EDGE Ta Yes
75 .It PMC_CAP_INTERRUPT Ta Yes
76 .It PMC_CAP_INVERT Ta Yes
77 .It PMC_CAP_READ Ta Yes
78 .It PMC_CAP_PRECISE Ta \&No
79 .It PMC_CAP_SYSTEM Ta Yes
80 .It PMC_CAP_TAGGING Ta \&No
81 .It PMC_CAP_THRESHOLD Ta Yes
82 .It PMC_CAP_USER Ta Yes
83 .It PMC_CAP_WRITE Ta Yes
86 Event specifiers for these PMCs support the following common
88 .Bl -tag -width indent
90 Count matching events seen on any logical processor in a package.
91 .It Li cmask= Ns Ar value
92 Configure the PMC to increment only if the number of configured
93 events measured in a cycle is greater than or equal to
96 Configure the PMC to count the number of deasserted to asserted
97 transitions of the conditions expressed by the other qualifiers.
98 If specified, the counter will increment only once whenever a
99 condition becomes true, irrespective of the number of clocks during
100 which the condition remains true.
102 Invert the sense of comparision when the
104 qualifier is present, making the counter increment when the number of
105 events per cycle is less than the value specified by the
109 Configure the PMC to count events happening at processor privilege
112 Configure the PMC to count events occurring at privilege levels 1, 2
120 qualifiers are specified, the default is to enable both.
122 Events that require core-specificity to be specified use a
124 .Dq Li core= Ns Ar core ,
128 .Bl -tag -width indent
130 Measure event conditions on all cores.
132 Measure event conditions on this core.
138 Events that require an agent qualifier to be specified use an
140 .Dq Li agent= Ns agent ,
144 .Bl -tag -width indent
146 Measure events associated with this bus agent.
148 Measure events caused by any bus agent.
154 Events that require a hardware prefetch qualifier to be specified use an
156 .Dq Li prefetch= Ns Ar prefetch ,
160 .Bl -tag -width "exclude"
162 Include all prefetches.
164 Only count hardware prefetches.
166 Exclude hardware prefetches.
172 Events that require a cache coherence qualifier to be specified use an
174 .Dq Li cachestate= Ns Ar state ,
177 contains one or more of the following letters:
178 .Bl -tag -width indent
180 Count cache lines in the exclusive state.
182 Count cache lines in the invalid state.
184 Count cache lines in the modified state.
186 Count cache lines in the shared state.
192 Events that require a snoop response qualifier to be specified use an
194 .Dq Li snoopresponse= Ns Ar response ,
197 comprises of the following keywords separated by
200 .Bl -tag -width indent
202 Measure CLEAN responses.
204 Measure HIT responses.
206 Measure HITM responses.
209 The default is to measure all the above responses.
211 Events that require a snoop type qualifier use an additional qualifier
212 .Dq Li snooptype= Ns Ar type ,
215 comprises the one of the following keywords:
216 .Bl -tag -width indent
218 Measure CMP2I snoops.
220 Measure CMP2S snoops.
223 The default is to measure both snoops.
224 .Ss Event Specifiers (Programmable PMCs)
225 Core2 programmable PMCs support the following events:
226 .Bl -tag -width indent
228 .Pq Event E6H , Umask 01H
229 The number of times the front end is resteered.
231 .Pq Event E4H , Umask 00H
232 The number of byte sequences mistakenly detected as taken branch
234 .It Li BR_BAC_MISSP_EXEC
235 .Pq Event 8AH , Umask 00H
236 The number of branch instructions that were mispredicted when
238 .It Li BR_CALL_MISSP_EXEC
239 .Pq Event 93H , Umask 00H
240 The number of mispredicted
242 instructions that were executed.
244 .Pq Event 92H , Umask 00H
247 instructions executed.
249 .Pq Event 8BH , Umask 00H
250 The number of conditional branches executed, but not necessarily retired.
251 .It Li BR_CND_MISSP_EXEC
252 .Pq Event 8CH , Umask 00H
253 The number of mispredicted conditional branches executed.
254 .It Li BR_IND_CALL_EXEC
255 .Pq Event 94H , Umask 00H
256 The number of indirect
258 instructions executed.
260 .Pq Event 8DH , Umask 00H
261 The number of indirect branch instructions executed.
262 .It Li BR_IND_MISSP_EXEC
263 .Pq Event 8EH , Umask 00H
264 The number of mispredicted indirect branch instructions executed.
265 .It Li BR_INST_DECODED
266 .Pq Event E0H , Umask 01H
267 The number of branch instructions decoded.
269 .Pq Event 88H , Umask 00H
270 The number of branches executed, but not necessarily retired.
271 .It Li BR_INST_RETIRED.ANY
272 .Pq Event C4H , Umask 00H
273 .Pq Alias Qq "Branch Instruction Retired"
274 The number of branch instructions retired.
275 This is an architectural performance event.
276 .It Li BR_INST_RETIRED.ANY1
277 .Pq Event C4H , Umask 0FH
278 The number of branch instructions retired that were mispredicted.
279 .It Li BR_INST_RETIRED.MISPRED
280 .Pq Event C5H , Umask 00H
281 .Pq Alias Qq "Branch Misses Retired"
282 The number of mispredicted branch instructions retired.
283 This is an architectural performance event.
284 .It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN
285 .Pq Event C4H , Umask 02H
286 The number of not taken branch instructions retired that were
288 .It Li BR_INST_RETIRED.MISPRED_TAKEN
289 .Pq Event C4H , Umask 08H
290 The number taken branch instructions retired that were mispredicted.
291 .It Li BR_INST_RETIRED.PRED_NOT_TAKEN
292 .Pq Event C4H , Umask 01H
293 The number of not taken branch instructions retired that were
295 .It Li BR_INST_RETIRED.PRED_TAKEN
296 .Pq Event C4H , Umask 04H
297 The number of taken branch instructions retired that were correctly
299 .It Li BR_INST_RETIRED.TAKEN
300 .Pq Event C4H , Umask 0CH
301 The number of taken branch instructions retired.
303 .Pq Event 89H , Umask 00H
304 The number of mispredicted branch instructions that were executed.
305 .It Li BR_RET_MISSP_EXEC
306 .Pq Event 90H , Umask 00H
307 The number of mispredicted
309 instructions executed.
310 .It Li BR_RET_BAC_MISSP_EXEC
311 .Pq Event 91H , Umask 00H
314 instructions executed that were mispredicted at decode time.
316 .Pq Event 8FH , Umask 00H
319 instructions executed.
320 .It Li BR_TKN_BUBBLE_1
321 .Pq Event 97H , Umask 00H
322 The number of branch predicted taken with bubble 1.
323 .It Li BR_TKN_BUBBLE_2
324 .Pq Event 98H , Umask 00H
325 The number of branch predicted taken with bubble 2.
326 .It Li BUSQ_EMPTY Op ,core= Ns Ar core
328 The number of cycles during which the core did not have any pending
329 transactions in the bus queue.
330 .It Li BUS_BNR_DRV Op ,agent= Ns Ar agent
332 The number of Bus Not Ready signals asserted on the bus.
333 This event is thread-independent.
334 .It Li BUS_DATA_RCV Op ,core= Ns Ar core
336 The number of bus cycles during which the processor is receiving data.
337 This event is thread-independent.
338 .It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent
340 The number of bus cycles during which the Data Ready signal is asserted
342 This event is thread-independent.
343 .It Li BUS_HIT_DRV Op ,agent= Ns Ar agent
345 The number of bus cycles during which the processor drives the
348 This event is thread-independent.
349 .It Li BUS_HITM_DRV Op ,agent= Ns Ar agent
351 The number of bus cycles during which the processor drives the
354 This event is thread-independent.
355 .It Li BUS_IO_WAIT Op ,core= Ns Ar core
357 The number of core cycles during which I/O requests wait in the bus
359 .It Li BUS_LOCK_CLOCKS Xo
360 .Op ,agent= Ns Ar agent
361 .Op ,core= Ns Ar core
364 The number of bus cycles during which the
366 signal was asserted on the bus.
367 This event is thread independent.
368 .It Li BUS_REQUEST_OUTSTANDING Xo
369 .Op ,agent= Ns Ar agent
370 .Op ,core= Ns Ar core
373 The number of pending full cache line read transactions on the bus
374 occuring in each cycle.
375 This event is thread independent.
376 .It Li BUS_TRANS_P Xo
377 .Op ,agent= Ns Ar agent
378 .Op ,core= Ns Ar core
381 The number of partial bus transactions.
382 .It Li BUS_TRANS_IFETCH Xo
383 .Op ,agent= Ns Ar agent
384 .Op ,core= Ns Ar core
387 The number of instruction fetch full cache line bus transactions.
388 .It Li BUS_TRANS_INVAL Xo
389 .Op ,agent= Ns Ar agent
390 .Op ,core= Ns Ar core
393 The number of invalidate bus transactions.
394 .It Li BUS_TRANS_PWR Xo
395 .Op ,agent= Ns Ar agent
396 .Op ,core= Ns Ar core
399 The number of partial write bus transactions.
400 .It Li BUS_TRANS_DEF Xo
401 .Op ,agent= Ns Ar agent
402 .Op ,core= Ns Ar core
405 The number of deferred bus transactions.
406 .It Li BUS_TRANS_BURST Xo
407 .Op ,agent= Ns Ar agent
408 .Op ,core= Ns Ar core
411 The number of burst transactions.
412 .It Li BUS_TRANS_MEM Xo
413 .Op ,agent= Ns Ar agent
414 .Op ,core= Ns Ar core
417 The number of memory bus transactions.
418 .It Li BUS_TRANS_ANY Xo
419 .Op ,agent= Ns Ar agent
420 .Op ,core= Ns Ar core
423 The number of bus transactions of any kind.
424 .It Li BUS_TRANS_BRD Xo
425 .Op ,agent= Ns Ar agent
426 .Op ,core= Ns Ar core
429 The number of burst read transactions.
430 .It Li BUS_TRANS_IO Xo
431 .Op ,agent= Ns Ar agent
432 .Op ,core= Ns Ar core
435 The number of completed I/O bus transaactions due to
440 .It Li BUS_TRANS_RFO Xo
441 .Op ,agent= Ns Ar agent
442 .Op ,core= Ns Ar core
445 The number of Read For Ownership bus transactions.
446 .It Li BUS_TRANS_WB Xo
447 .Op ,agent= Ns Ar agent
448 .Op ,core= Ns Ar core
451 The number explicit writeback bus transactions due to dirty line
454 .Op ,core= Ns Ar core
455 .Op ,snooptype= Ns Ar snoop
458 The number of times the L1 data cache is snooped by the other core in
460 .It Li CPU_CLK_UNHALTED.BUS
461 .Pq Event 3CH , Umask 01H
462 .Pq Alias Qq "Unhalted Reference Cycles"
463 The number of bus cycles when the core is not in the halt state.
464 This is an architectural performance event.
465 .It Li CPU_CLK_UNHALTED.CORE_P
466 .Pq Event 3CH , Umask 00H
467 .Pq Alias Qq "Unhalted Core Cycles"
468 The number of core cycles while the core is not in a halt state.
469 This is an architectural performance event.
470 .It Li CPU_CLK_UNHALTED.NO_OTHER
471 .Pq Event 3CH , Umask 02H
472 The number of bus cycles during which the core remains unhalted and
473 the other core is halted.
474 .It Li CYCLES_DIV_BUSY
475 .Pq Event 14H , Umask 01H
476 The number of cycles the divider is busy.
477 .It Li CYCLES_INT_MASKED.CYCLES_INT_MASKED
478 .Pq Event C6H , Umask 01H
479 The number of cycles during which interrupts are disabled.
480 .It Li CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED
481 .Pq Event C6H , Umask 02H
482 The number of cycles during which there were pending interrupts while
483 interrupts were disabled.
484 .It Li CYCLES_L1I_MEM_STALLED
485 .Pq Event 86H , Umask 00H
486 The number of cycles for which an instruction fetch stalls.
487 .It Li DATA_TLB_MISSES.DTLB_MISS
488 .Pq Event 08H , Umask 07H
489 The number of memory access that missed the Data TLB
490 .It Li DATA_TLB_MISSES.DTLB_MISS_LD
491 .Pq Event 08H , Umask 05H
492 The number of loads that missed the Data TLB.
493 .It Li DATA_TLB_MISSES.DTLB_MISS_ST
494 .Pq Event 08H , Umask 06H
495 The number of stores that missed the Data TLB.
496 .It Li DATA_TLB_MISSES.UTLB_MISS_LD
497 .Pq Event 08H , Umask 09H
498 The number of loads that missed the UTLB.
499 .It Li DELAYED_BYPASS.FP
500 .Pq Event 19H , Umask 00H
501 The number of floating point operations that used data immediately
502 after the data was generated by a non floating point execution unit.
503 .It Li DELAYED_BYPASS.LOAD
504 .Pq Event 19H , Umask 01H
505 The number of delayed bypass penalty cycles that a load operation incurred.
506 .It Li DELAYED_BYPASS.SIMD
507 .Pq Event 19H , Umask 02H
508 The number of times SIMD operations use data immediately after data,
509 was generated by a non-SIMD execution unit.
511 .Pq Event 13H , Umask 00H
512 The number of divide operations executed.
513 This event is only available on PMC1.
515 .Pq Event 13H , Umask 81H
516 The number of divide operations retired.
518 .Pq Event 13H , Umask 01H
519 The number of divide operations executed.
520 .It Li DTLB_MISSES.ANY
521 .Pq Event 08H , Umask 01H
522 The number of Data TLB misses, including misses that result from
523 speculative accesses.
524 .It Li DTLB_MISSES.L0_MISS_LD
525 .Pq Event 08H , Umask 04H
526 The number of level 0 DTLB misses due to load operations.
527 .It Li DTLB_MISSES.MISS_LD
528 .Pq Event 08H , Umask 02H
529 The number of Data TLB misses due to load operations.
530 .It Li DTLB_MISSES.MISS_ST
531 .Pq Event 08H , Umask 08H
532 The number of Data TLB misses due to store operations.
534 .Pq Event 3AH , Umask 00H
535 The number of Enhanced Intel SpeedStep Technology transitions.
537 .Pq Event ABH , Umask 02H
538 The number of automatic additions to the
542 .Pq Event ABH , Umask 01H
543 The number of times the
545 register was explicitly used in an address expression after
546 it is implicitly used by a
552 .Op ,agent= Ns Ar agent
553 .Op ,snoopresponse= Ns Ar response
556 The number of snoop responses to bus transactions.
558 .Pq Event 11H , Umask 01H
559 The number of floating point operations executed that needed
560 a microcode assist, including speculatively executed instructions.
562 .Pq Event 11H , Umask 81H
563 The number of floating point operations retired that needed
565 .It Li FP_COMP_OPS_EXE
566 .Pq Event 10H , Umask 00H
567 The number of floating point computational micro-ops executed.
568 The event is available only on PMC0.
569 .It Li FP_MMX_TRANS_TO_FP
570 .Pq Event CCH , Umask 02H
571 The number of transitions from MMX instructions to floating point
573 .It Li FP_MMX_TRANS_TO_MMX
574 .Pq Event CCH , Umask 01H
575 The number of transitions from floating point instructions to MMX
578 .Pq Event C8H , Umask 00H
579 The number of hardware interrupts recieved.
580 .It Li ICACHE.ACCESSES
581 .Pq Event 80H , Umask 03H
582 The number of instruction fetches.
584 .Pq Event 80H , Umask 02H
585 The number of instruction fetches that miss the instruction cache.
586 .It Li IDLE_DURING_DIV
587 .Pq Event 18H , Umask 00H
588 The number of cycles the divider is busy and no other execution unit
589 or load operation was in progress.
590 This event is available only on PMC0.
592 .Pq Event 87H , Umask 00H
593 The number of cycles the instruction length decoder stalled due to a
594 length changing prefix.
595 .It Li INST_QUEUE.FULL
596 .Pq Event 83H , Umask 02H
597 The number of cycles during which the instruction queue is full.
598 .It Li INST_RETIRED.ANY_P
599 .Pq Event C0H , Umask 00H
600 .Pq Alias Qq "Instruction Retired"
601 The number of instructions retired.
602 This is an architectural performance event.
603 .It Li INST_RETIRED.LOADS
604 .Pq Event C0H , Umask 01H
605 The number of instructions retired that contained a load operation.
606 .It Li INST_RETIRED.OTHER
607 .Pq Event C0H , Umask 04H
608 The number of instructions retired that did not contain a load or a
610 .It Li INST_RETIRED.STORES
611 .Pq Event C0H , Umask 02H
612 The number of instructions retired that contained a store operation.
614 .Pq Event 82H , Umask 04H
615 The number of ITLB flushes.
616 .It Li ITLB.LARGE_MISS
617 .Pq Event 82H , Umask 10H
618 The number of instruction fetches from large pages that miss the
621 .Pq Event 82H , Umask 02H
622 The number of instruction fetches from both large and small pages that
624 .It Li ITLB.SMALL_MISS
625 .Pq Event 82H , Umask 02H
626 The number of instruction fetches from small pages that miss the ITLB.
627 .It Li ITLB_MISS_RETIRED
628 .Pq Event C9H , Umask 00H
629 The number of retired instructions that missed the ITLB when they were
632 .Pq Event 43H , Umask 01H
633 The number of references to L1 data cache counting loads and stores of
635 .It Li L1D_ALL_CACHE_REF
636 .Pq Event 43H , Umask 02H
637 The number of data reads and writes to cacheable memory.
638 .It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state
640 The number of locked reads from cacheable memory.
641 .It Li L1D_CACHE_LOCK_DURATION
642 .Pq Event 42H , Umask 10H
643 The number of cycles during which any cache line is locked by any
646 .Pq Event 40H , Umask 21H
647 The number of data reads from cacheable memory.
649 .Pq Event 41H , Umask 22H
650 The number of data writes to cacheable memory.
652 .Pq Event 47H , Umask 00H
653 The number of modified cache lines evicted from L1 data cache.
655 .Pq Event 46H , Umask 00H
656 The number of modified lines allocated in L1 data cache.
658 .Pq Event 48H , Umask 00H
659 The total number of outstanding L1 data cache misses at any clock.
660 .It Li L1D_PREFETCH.REQUESTS
661 .Pq Event 4EH , Umask 10H
662 The number of times L1 data cache requested to prefetch a data cache
665 .Pq Event 45H , Umask 0FH
666 The number of lines brought into L1 data cache.
667 .It Li L1D_SPLIT.LOADS
668 .Pq Event 49H , Umask 01H
669 The number of load operations that span two cache lines.
670 .It Li L1D_SPLIT.STORES
671 .Pq Event 49H , Umask 02H
672 The number of store operations that span two cache lines.
674 .Pq Event 81H , Umask 00H
675 The number of instruction fetch unit misses.
677 .Pq Event 80H , Umask 00H
678 The number of instruction fetches.
679 .It Li L2_ADS Op ,core= Ns core
681 The number of cycles that the L2 address bus is in use.
682 .It Li L2_DBUS_BUSY_RD Op ,core= Ns core
684 The number of core cycles during which the L2 data bus is busy
685 transferring data to the core.
687 .Op ,cachestate= Ns Ar state
688 .Op ,core= Ns Ar core
691 The number of instruction cache line requests from the instruction
694 .Op ,cachestate= Ns Ar state
695 .Op ,core= Ns Ar core
696 .Op ,prefech= Ns Ar prefetch
699 The number of L2 cache read requests from L1 cache and L2
701 .It Li L2_LINES_IN Xo
702 .Op ,core= Ns Ar core
703 .Op ,prefetch= Ns Ar prefetch
706 The number of cache lines allocated in L2 cache.
707 .It Li L2_LINES_OUT Xo
708 .Op ,core= Ns Ar core
709 .Op ,prefetch= Ns Ar prefetch
712 The number of L2 cache lines evicted.
714 .Op ,cachestate= Ns Ar state
715 .Op ,core= Ns Ar core
718 The number of locked accesses to cache lines that miss L1 data
720 .It Li L2_M_LINES_IN Op ,core= Ns Ar core
722 The number of L2 cache line modifications.
723 .It Li L2_M_LINES_OUT Xo
724 .Op ,core= Ns Ar core
725 .Op ,prefetch= Ns Ar prefetch
728 The number of modified lines evicted from L2 cache.
729 .It Li L2_NO_REQ Op ,core= Ns Ar core
731 The number of cycles during which no L2 cache requests were pending
733 .It Li L2_REJECT_BUSQ Xo
734 .Op ,cachestate= Ns Ar state
735 .Op ,core= Ns Ar core
736 .Op ,prefetch= Ns Ar prefetch
739 The number of L2 cache requests that were rejected.
741 .Op ,cachestate= Ns Ar state
742 .Op ,core= Ns Ar core
743 .Op ,prefetch= Ns Ar prefetch
746 The number of completed L2 cache requests.
747 .It Li L2_RQSTS.SELF.DEMAND.I_STATE
748 .Pq Event 2EH , Umask 41H
749 .Pq Alias Qq "LLC Misses"
750 The number of completed L2 cache demand requests from this core that
752 This is an architectural performance event.
753 .It Li L2_RQSTS.SELF.DEMAND.MESI
754 .Pq Event 2EH , Umask 4FH
755 .Pq Alias Qq "LLC References"
756 The number of completed L2 cache demand requests from this core.
758 .Op ,cachestate= Ns Ar state
759 .Op ,core= Ns Ar core
762 The number of store operations that miss the L1 cache and request data
764 .It Li LOAD_BLOCK.L1D
765 .Pq Event 03H , Umask 20H
766 The number of loads blocked by the L1 data cache.
767 .It Li LOAD_BLOCK.OVERLAP_STORE
768 .Pq Event 03H , Umask 08H
769 The number of loads that partially overlap an earlier store or are
770 aliased with a previous store.
771 .It Li LOAD_BLOCK.STA
772 .Pq Event 03H , Umask 02H
773 The number of loads blocked by preceding stores whose address is yet
775 .It Li LOAD_BLOCK.STD
776 .Pq Event 03H , Umask 04H
777 The number of loads blocked by preceding stores to the same address
778 whose data value is not known.
779 .It Li LOAD_BLOCK.UNTIL_RETIRE
780 .Pq Event 03H , Umask 10H
781 The numer of load operations that were blocked until retirement.
783 .Pq Event 4CH , Umask 00H
784 The number of load operations that conflicted with an prefetch to the
786 .It Li MACHINE_CLEARS.SMC
787 .Pq Event C3H , Umask 01H
788 The number of times a program writes to a code section.
789 .It Li MACHINE_NUKES.MEM_ORDER
790 .Pq Event C3H , Umask 04H
791 The number of times the execution pipeline was restarted due to a
792 memory ordering conflict or memory disambiguation misprediction.
793 .It Li MACRO_INSTS.ALL_DECODED
794 .Pq Event AAH , Umask 03H
795 The number of instructions decoded.
796 .It Li MACRO_INSTS.CISC_DECODED
797 .Pq Event AAH , Umask 02H
798 The number of complex instructions decoded.
799 .It Li MEMORY_DISAMBIGUATION.RESET
800 .Pq Event 09H , Umask 01H
801 The number of cycles during which memory disambiguation misprediction
803 .It Li MEMORY_DISAMBIGUATION.SUCCESS
804 .Pq Event 09H , Umask 02H
805 The number of load operations that were successfully disambiguated.
806 .It Li MEM_LOAD_RETIRED.DTLB_MISS
807 .Pq Event CBH , Umask 04H
808 The number of retired load operations that missed the DTLB.
809 .It Li MEM_LOAD_RETIRED.L2_MISS
810 .Pq Event CBH , Umask 02H
811 The number of retired load operations that miss L2 cache.
812 .It Li MEM_LOAD_RETIRED.L2_HIT
813 .Pq Event CBH , Umask 01H
814 The number of retired load operations that hit L2 cache.
815 .It Li MEM_LOAD_RETIRED.L2_LINE_MISS
816 .Pq Event CBH , Umask 08H
817 The number of load operations that missed L2 cache and that caused a
820 .Pq Event 12H , Umask 00H
821 The number of multiply operations executed.
822 This event is only available on PMC1.
824 .Pq Event 12H , Umask 81H
825 The number of multiply operations retired.
827 .Pq Event 12H , Umask 01H
828 The number of multiply operations executed.
829 .It Li PAGE_WALKS.WALKS
830 .Pq Event 0CH , Umask 03H
831 The number of page walks executed due to an ITLB or DTLB miss.
832 .It Li PAGE_WALKS.CYCLES
833 .Pq Event 0CH , Umask 03H
834 .\" XXX Clarify. Identical event umask/event numbers.
835 The number of cycles spent in a page walk caused by an ITLB or DTLB
838 .Pq Event F8H , Umask 00H
839 The number of downward prefetches issued from the Data Prefetch Logic
842 .Pq Event F0H , Umask 00H
843 The number of upward prefetches issued from the Data Prefetch Logic
845 .It Li PREFETCH.PREFETCHNTA
846 .Pq Event 07H , Umask 08H
849 instructions executed.
850 .It Li PREFETCH.PREFETCHT0
851 .Pq Event 07H , Umask 01H
854 instructions executed.
855 .It Li PREFETCH.SW_L2
856 .Pq Event 07H , Umask 06H
861 instructions executed.
862 .It Li RAT_STALLS.ANY
863 .Pq Event D2H , Umask 0FH
864 The number of stall cycles due to any of
866 .Li RAT_STALLS.FPSW ,
867 .Li RAT_STALLS.PARTIAL
869 .Li RAT_STALLS.ROB_READ_PORT .
870 .It Li RAT_STALLS.FLAGS
871 .Pq Event D2H , Umask 04H
872 The number of cycles execution stalled due to a flag register induced
874 .It Li RAT_STALLS.FPSW
875 .Pq Event D2H , Umask 08H
876 The number of times the floating point status word was written.
877 .It Li RAT_STALLS.PARTIAL_CYCLES
878 .Pq Event D2H , Umask 02H
879 The number of cycles of added instruction execution latency due to the
880 use of a register that was partially written by previous instructions.
881 .It Li RAT_STALLS.ROB_READ_PORT
882 .Pq Event D2H , Umask 01H
883 The number of cycles when ROB read port stalls occurred.
884 .It Li RESOURCE_STALLS.ANY
885 .Pq Event DCH , Umask 1FH
886 The number of cycles during which any resource related stall
888 .It Li RESOURCE_STALLS.BR_MISS_CLEAR
889 .Pq Event DCH , Umask 10H
890 The number of cycles stalled due to branch misprediction.
891 .It Li RESOURCE_STALLS.FPCW
892 .Pq Event DCH , Umask 08H
893 The number of cycles stalled due to writing the floating point control
895 .It Li RESOURCE_STALLS.LD_ST
896 .Pq Event DCH , Umask 04H
897 The number of cycles during which the number of loads and stores in
898 the pipeline exceeded their limits.
899 .It Li RESOURCE_STALLS.ROB_FULL
900 .Pq Event DCH , Umask 01H
901 The number of cycles when the reorder buffer was full.
902 .It Li RESOURCE_STALLS.RS_FULL
903 .Pq Event DCH , Umask 02H
904 The number of cycles during which the RS was full.
905 .It Li RS_UOPS_DISPATCHED
906 .Pq Event A0H , Umask 00H
907 The number of micro-ops dispatched for execution.
908 .It Li RS_UOPS_DISPATCHED.PORT0
909 .Pq Event A1H , Umask 01H
910 The number of cycles micro-ops were dispatched for execution on port
912 .It Li RS_UOPS_DISPATCHED.PORT1
913 .Pq Event A1H , Umask 02H
914 The number of cycles micro-ops were dispatched for execution on port
916 .It Li RS_UOPS_DISPATCHED.PORT2
917 .Pq Event A1H , Umask 04H
918 The number of cycles micro-ops were dispatched for execution on port
920 .It Li RS_UOPS_DISPATCHED.PORT3
921 .Pq Event A1H , Umask 08H
922 The number of cycles micro-ops were dispatched for execution on port
924 .It Li RS_UOPS_DISPATCHED.PORT4
925 .Pq Event A1H , Umask 10H
926 The number of cycles micro-ops were dispatched for execution on port
928 .It Li RS_UOPS_DISPATCHED.PORT5
929 .Pq Event A1H , Umask 20H
930 The number of cycles micro-ops were dispatched for execution on port
932 .It Li SB_DRAIN_CYCLES
933 .Pq Event 04H , Umask 01H
934 The number of cycles while the store buffer is draining.
935 .It Li SEGMENT_REG_LOADS.ANY
936 .Pq Event 06H , Umask 00H
937 The number of segment register loads.
938 .It Li SEG_REG_RENAMES.ANY
939 .Pq Event D5H , Umask 0FH
940 The number of times the any segment register was renamed.
941 .It Li SEG_REG_RENAMES.DS
942 .Pq Event D5H , Umask 02H
943 The number of times the
946 .It Li SEG_REG_RENAMES.ES
947 .Pq Event D5H , Umask 01H
948 The number of times the
951 .It Li SEG_REG_RENAMES.FS
952 .Pq Event D5H , Umask 04H
953 The number of times the
956 .It Li SEG_REG_RENAMES.GS
957 .Pq Event D5H , Umask 08H
958 The number of times the
961 .It Li SEG_RENAME_STALLS.ANY
962 .Pq Event D4H , Umask 0FH
963 The number of stalls due to lack of resource to rename any segment
965 .It Li SEG_RENAME_STALLS.DS
966 .Pq Event D4H , Umask 02H
967 The number of stalls due to lack of renaming resources for the
970 .It Li SEG_RENAME_STALLS.ES
971 .Pq Event D4H , Umask 01H
972 The number of stalls due to lack of renaming resources for the
975 .It Li SEG_RENAME_STALLS.FS
976 .Pq Event D4H , Umask 04H
977 The number of stalls due to lack of renaming resources for the
980 .It Li SEG_RENAME_STALLS.GS
981 .Pq Event D4H , Umask 08H
982 The number of stalls due to lack of renaming resources for the
986 .Pq Event CDH , Umask 00H
987 The number SIMD assists invoked.
988 .It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
989 .Pq Event CAH , Umask 04H
990 Then number of computational SSE2 packed double precision instructions
992 .It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE
993 .Pq Event CAH , Umask 01H
994 Then number of computational SSE2 packed single precision instructions
996 .It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE
997 .Pq Event CAH , Umask 08H
998 Then number of computational SSE2 scalar double precision instructions
1000 .It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE
1001 .Pq Event CAH , Umask 02H
1002 Then number of computational SSE2 scalar single precision instructions
1004 .It Li SIMD_INSTR_RETIRED
1005 .Pq Event CEH , Umask 00H
1006 The number of retired SIMD instructions that use MMX registers.
1007 .It Li SIMD_INST_RETIRED.ANY
1008 .Pq Event C7H , Umask 1FH
1009 The number of streaming SIMD instructions retired.
1010 .It Li SIMD_INST_RETIRED.PACKED_DOUBLE
1011 .Pq Event C7H , Umask 04H
1012 The number of SSE2 packed double precision instructions retired.
1013 .It Li SIMD_INST_RETIRED.PACKED_SINGLE
1014 .Pq Event C7H , Umask 01H
1015 The number of SSE packed single precision instructions retired.
1016 .It Li SIMD_INST_RETIRED.SCALAR_DOUBLE
1017 .Pq Event C7H , Umask 08H
1018 The number of SSE2 scalar double precision instructions retired.
1019 .It Li SIMD_INST_RETIRED.SCALAR_SINGLE
1020 .Pq Event C7H , Umask 02H
1021 The number of SSE scalar single precision instructions retired.
1022 .It Li SIMD_INST_RETIRED.VECTOR
1023 .Pq Event C7H , Umask 10H
1024 The number of SSE2 vector instructions retired.
1025 .It Li SIMD_SAT_INSTR_RETIRED
1026 .Pq Event CFH , Umask 00H
1027 The number of saturated arithmetic SIMD instructions retired.
1028 .It Li SIMD_SAT_UOP_EXEC.AR
1029 .Pq Event B1H , Umask 80H
1030 The number of SIMD saturated arithmetic micro-ops retired.
1031 .It Li SIMD_SAT_UOP_EXEC.S
1032 .Pq Event B1H , Umask 00H
1033 The number of SIMD saturated arithmetic micro-ops executed.
1034 .It Li SIMD_UOPS_EXEC.AR
1035 .Pq Event B0H , Umask 80H
1036 The number of SIMD micro-ops retired.
1037 .It Li SIMD_UOPS_EXEC.S
1038 .Pq Event B0H , Umask 00H
1039 The number of SIMD micro-ops executed.
1040 .It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR
1041 .Pq Event B3H , Umask A0H
1042 The number of SIMD packed arithmetic micro-ops executed.
1043 .It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.S
1044 .Pq Event B3H , Umask 20H
1045 The number of SIMD packed arithmetic micro-ops executed.
1046 .It Li SIMD_UOP_TYPE_EXEC.LOGICAL.AR
1047 .Pq Event B3H , Umask 90H
1048 The number of SIMD packed logical micro-ops executed.
1049 .It Li SIMD_UOP_TYPE_EXEC.LOGICAL.S
1050 .Pq Event B3H , Umask 10H
1051 The number of SIMD packed logical micro-ops executed.
1052 .It Li SIMD_UOP_TYPE_EXEC.MUL.AR
1053 .Pq Event B3H , Umask 81H
1054 The number of SIMD packed multiply micro-ops retired.
1055 .It Li SIMD_UOP_TYPE_EXEC.MUL.S
1056 .Pq Event B3H , Umask 01H
1057 The number of SIMD packed multiply micro-ops executed.
1058 .It Li SIMD_UOP_TYPE_EXEC.PACK.AR
1059 .Pq Event B3H , Umask 84H
1060 The number of SIMD pack micro-ops retired.
1061 .It Li SIMD_UOP_TYPE_EXEC.PACK.S
1062 .Pq Event B3H , Umask 04H
1063 The number of SIMD pack micro-ops executed.
1064 .It Li SIMD_UOP_TYPE_EXEC.SHIFT.AR
1065 .Pq Event B3H , Umask 82H
1066 The number of SIMD packed shift micro-ops retired.
1067 .It Li SIMD_UOP_TYPE_EXEC.SHIFT.S
1068 .Pq Event B3H , Umask 02H
1069 The number of SIMD packed shift micro-ops executed.
1070 .It Li SIMD_UOP_TYPE_EXEC.UNPACK.AR
1071 .Pq Event B3H , Umask 88H
1072 The number of SIMD unpack micro-ops executed.
1073 .It Li SIMD_UOP_TYPE_EXEC.UNPACK.S
1074 .Pq Event B3H , Umask 08H
1075 The number of SIMD unpack micro-ops executed.
1076 .It Li SNOOP_STALL_DRV Xo
1077 .Op ,agent= Ns Ar agent
1078 .Op ,core= Ns Ar core
1081 The number of times the bus stalled for snoops.
1082 This event is thread-independent.
1083 .It Li SSE_PRE_EXEC.L2
1084 .Pq Event 07H , Umask 02H
1087 instructions executed.
1088 .It Li SSE_PRE_EXEC.STORES
1089 .Pq Event 07H , Umask 03H
1090 The number of times SSE non-temporal store instructions were executed.
1091 .It Li SSE_PRE_MISS.L1
1092 .Pq Event 4BH , Umask 01H
1093 The number of times the
1095 instruction executed and missed all cache levels.
1096 .It Li SSE_PRE_MISS.L2
1097 .Pq Event 4BH , Umask 02H
1098 The number of times the
1100 instruction executed and missed all cache levels.
1101 .It Li SSE_PRE_MISS.NTA
1102 .Pq Event 4BH , Umask 00H
1103 The number of times the
1105 instruction executed and missed all cache levels.
1106 .It Li STORE_BLOCK.ORDER
1107 .Pq Event 04H , Umask 02H
1108 The number of cycles while a store was waiting for another store to be
1110 .It Li STORE_BLOCK.SNOOP
1111 .Pq Event 04H , Umask 08H
1112 The number of cycles while a store was blocked due to a conflict with
1113 an internal or external snoop.
1114 .It Li STORE_FORWARDS.GOOD
1115 .Pq Event 02H , Umask 81H
1116 The number of times stored data was forwarded directly to a load.
1118 .Pq Event 3BH , Umask C0H
1119 The number of thermal trips.
1120 .It Li UOPS_RETIRED.LD_IND_BR
1121 .Pq Event C2H , Umask 01H
1122 The number of micro-ops retired that fused a load with another
1124 .It Li UOPS_RETIRED.STD_STA
1125 .Pq Event C2H , Umask 02H
1126 The number of store address calculations that fused into one micro-op.
1127 .It Li UOPS_RETIRED.MACRO_FUSION
1128 .Pq Event C2H , Umask 04H
1129 The number of times retired instruction pairs were fused into one
1131 .It Li UOPS_RETIRED.FUSED
1132 .Pq Event C2H , Umask 07H
1133 The number of fused micro-ops retired.
1134 .It Li UOPS_RETIRED.NON_FUSED
1135 .Pq Event C2H , Umask 8H
1136 The number of non-fused micro-ops retired.
1137 .It Li UOPS_RETIRED.ANY
1138 .Pq Event C2H , Umask 10H
1139 The number of micro-ops retired.
1140 .It Li X87_COMP_OPS_EXE.ANY.AR
1141 .Pq Event 10H , Umask 81H
1142 The number of x87 floating-point computational micro-ops retired.
1143 .It Li X87_COMP_OPS_EXE.ANY.S
1144 .Pq Event 10H , Umask 01H
1145 The number of x87 floating-point computational micro-ops executed.
1146 .It Li X87_OPS_RETIRED.ANY
1147 .Pq Event C1H , Umask FEH
1148 The number of floating point computational instructions retired.
1149 .It Li X87_OPS_RETIRED.FXCH
1150 .Pq Event C1H , Umask 01H
1153 instructions retired.
1155 .Ss Event Name Aliases
1156 The following table shows the mapping between the PMC-independent
1157 aliases supported by
1159 and the underlying hardware events used on these CPUs.
1160 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
1161 .It Em Alias Ta Em Event Ta Em PMC Class
1162 .It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP
1163 .It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
1164 .It Li ic-misses Ta Li ICACHE.MISSES Ta Li PMC_CLASS_IAP
1165 .It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF
1166 .It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP
1167 .It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF
1186 library first appeared in
1191 library was written by
1193 .Aq jkoshy@FreeBSD.org .