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31 .Nd measurement events for
39 There are two counters per core supported by the hardware and each is 64 bits
41 .Ss Event Specifiers (Programmable PMCs)
42 MIPS programmable PMCs support the following events:
43 .Bl -tag -width indent
46 Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks)
49 Instructions issued but not retired
64 Cycle ifetch issued (but not necessarily commit to pp_mem)
82 Cycles idle due to unaligned_replays
88 Unexpected unaligned loads (REPUN=1)
91 Unexpected unaligned store (REPUN=1)
94 Unaligned loads (REPUN=1 or USEUN=1)
97 Unaligned store (REPUN=1 or USEUN=1)
100 Exec clocks(must set CvmCtl[DISCE] for accurate timing)
103 Mul clocks(must set CvmCtl[DISCE] for accurate timing)
106 Crypto clocks(must set CvmCtl[DISCE] for accurate timing)
109 Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing)
112 Icache committed fetches (demand+prefetch)
115 Icache committed prefetches
127 Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing)
130 Number of write buffer entries created
133 Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts)
136 Number of write buffer entries forced out by loads
139 Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
142 Number of stores that found no available write buffer entries
145 Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
148 Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts)
151 Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
154 Number of Dstream DIDs created
157 Number of Istream DIDs created
160 Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
163 Number of load issues
166 Number of local memory load
169 Number of I/O load issues
172 Number of loads that were not prefetches and missed in the cache
175 Number of store issues
178 Number of local memory store issues
181 Number of I/O store issues
187 Number of dstream TLB refill, invalid, or modified exceptions
190 Number of dstream TLB address errors
193 Number of istream TLB refill, invalid, or address error exceptions
196 Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
199 Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
205 D/eret mispredicts (CN63XX specific)
208 Branch likely mispredicts (CN63XX specific)
211 Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific)
213 .Ss Event Name Aliases
214 The following table shows the mapping between the PMC-independent
217 and the underlying hardware events used.
218 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
219 .It Em Alias Ta Em Event
220 .It Li instructions Ta Li RET
221 .It Li branches Ta Li BR
222 .It Li branch-mispredicts Ta Li BS
243 library first appeared in
248 library was written by
250 .Aq jkoshy@FreeBSD.org .
251 MIPS support was added by
252 .An "George Neville-Neil"
253 .Aq gnn@FreeBSD.org .