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31 .Nd measurement events for
41 CPUs are ARM CPUs based on the ARMv5e core.
43 Second generation cores have 2 counters, while third generation cores
45 Third generation cores also have an increased number of PMC events.
48 PMCs are documented in
50 .%B "3rd Generation Intel XScale Microarchitecture Developer's Manual"
53 .Ss Event Specifiers (Programmable PMCs)
55 programmable PMCs support the following events:
56 .Bl -tag -width indent
58 External memory fetch due to L1 instruction cache miss.
60 Instruction cache or TLB miss.
61 .It Li DATA_DEPENDENCY_STALLED
62 A data dependency stalled
68 Branch instruction retired (executed).
72 Instructions retired (executed).
74 L1 data cache buffer full stall.
75 Event occurs on every cycle the
78 L1 data cache buffer full stall.
79 Event occurs once for each contiguous sequence of this type of stall.
81 L1 data cache access, not including cache operations.
83 L1 data cache miss, not including cache operations.
85 L1 data cache write-back.
86 Occurs for each cache line that's written back from the cache.
88 Software changed the program counter.
89 .It Li BRANCH_RETIRED_ALL
90 Branch instruction retired (executed).
91 This event counts all branch instructions, indirect or direct.
93 Count the number of microarchitecture cycles each instruction requires
96 Coprocessor stalled the instruction pipeline.
98 Software changed the program counter (includes exceptions).
100 Pipeline flushes due to mispredictions or exceptions.
102 Backend stalled the instruction pipeline.
103 .It Li MULTIPLIER_USE
105 .It Li MULTIPLIER_STALLED
106 Multiplier stalled the instruction pipeline.
107 .It Li DATA_CACHE_STALLED
108 Data cache stalled the instruction pipeline.
110 L2 cache request, not including cache operations.
112 L2 cache miss, not including cache operations.
113 .It Li ADDRESS_BUS_TRANS
114 Address bus transaction.
115 .It Li SELF_ADDRESS_BUS_TRANS
116 Self initiated address bus transaction.
117 .It Li DATA_BUS_TRANS
118 Data bus transaction.
120 .Ss Event Name Aliases
121 The following table shows the mapping between the PMC-independent
124 and the underlying hardware events used.
125 .Bl -column "branch-mispredicts" "BRANCH_MISPRED"
126 .It Em Alias Ta Em Event
127 .It Li branches Ta Li BRANCH_RETIRED
128 .It Li branch-mispredicts Ta Li BRANCH_MISPRED
129 .It Li dc-misses Ta Li DC_MISS
130 .It Li ic-misses Ta Li IC_MISS
131 .It Li instructions Ta Li INSTR_RETIRED
142 library first appeared in
144 Intel XScale support first appeared in
149 library was written by
151 .Aq jkoshy@FreeBSD.org .
153 Intel XScale support was added by
155 .Aq rpaulo@FreeBSD.org .
157 The Intel XScale code does not yet support sampling.