2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/_types.h>
35 #define __fenv_static static
38 typedef __uint32_t fenv_t;
39 typedef __uint32_t fexcept_t;
42 #define FE_INEXACT 0x02000000
43 #define FE_DIVBYZERO 0x04000000
44 #define FE_UNDERFLOW 0x08000000
45 #define FE_OVERFLOW 0x10000000
46 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */
49 * The PowerPC architecture has extra invalid flags that indicate the
50 * specific type of invalid operation occurred. These flags may be
51 * tested, set, and cleared---but not masked---separately. All of
52 * these bits are cleared when FE_INVALID is cleared, but only
53 * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
55 #define FE_VXCVI 0x00000100 /* invalid integer convert */
56 #define FE_VXSQRT 0x00000200 /* square root of a negative */
57 #define FE_VXSOFT 0x00000400 /* software-requested exception */
58 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */
59 #define FE_VXIMZ 0x00100000 /* inf * 0 */
60 #define FE_VXZDZ 0x00200000 /* 0 / 0 */
61 #define FE_VXIDI 0x00400000 /* inf / inf */
62 #define FE_VXISI 0x00800000 /* inf - inf */
63 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */
64 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
65 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
66 FE_VXSNAN | FE_INVALID)
67 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
68 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
71 #define FE_TONEAREST 0x0000
72 #define FE_TOWARDZERO 0x0001
73 #define FE_UPWARD 0x0002
74 #define FE_DOWNWARD 0x0003
75 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
76 FE_UPWARD | FE_TOWARDZERO)
80 /* Default floating-point environment */
81 extern const fenv_t __fe_dfl_env;
82 #define FE_DFL_ENV (&__fe_dfl_env)
84 /* We need to be able to map status flag positions to mask flag positions */
85 #define _FPUSW_SHIFT 22
86 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
87 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
90 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env)))
91 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env))
94 #define __mtfsf(__env)
105 __fenv_static inline int
106 feclearexcept(int __excepts)
110 if (__excepts & FE_INVALID)
111 __excepts |= FE_ALL_INVALID;
113 __r.__bits.__reg &= ~__excepts;
118 __fenv_static inline int
119 fegetexceptflag(fexcept_t *__flagp, int __excepts)
124 *__flagp = __r.__bits.__reg & __excepts;
128 __fenv_static inline int
129 fesetexceptflag(const fexcept_t *__flagp, int __excepts)
133 if (__excepts & FE_INVALID)
134 __excepts |= FE_ALL_EXCEPT;
136 __r.__bits.__reg &= ~__excepts;
137 __r.__bits.__reg |= *__flagp & __excepts;
142 __fenv_static inline int
143 feraiseexcept(int __excepts)
147 if (__excepts & FE_INVALID)
148 __excepts |= FE_VXSOFT;
150 __r.__bits.__reg |= __excepts;
155 __fenv_static inline int
156 fetestexcept(int __excepts)
161 return (__r.__bits.__reg & __excepts);
164 __fenv_static inline int
170 return (__r.__bits.__reg & _ROUND_MASK);
173 __fenv_static inline int
174 fesetround(int __round)
178 if (__round & ~_ROUND_MASK)
181 __r.__bits.__reg &= ~_ROUND_MASK;
182 __r.__bits.__reg |= __round;
187 __fenv_static inline int
188 fegetenv(fenv_t *__envp)
193 *__envp = __r.__bits.__reg;
197 __fenv_static inline int
198 feholdexcept(fenv_t *__envp)
204 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
209 __fenv_static inline int
210 fesetenv(const fenv_t *__envp)
214 __r.__bits.__reg = *__envp;
219 __fenv_static inline int
220 feupdateenv(const fenv_t *__envp)
225 __r.__bits.__reg &= FE_ALL_EXCEPT;
226 __r.__bits.__reg |= *__envp;
233 /* We currently provide no external definitions of the functions below. */
236 feenableexcept(int __mask)
242 __oldmask = __r.__bits.__reg;
243 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
245 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
249 fedisableexcept(int __mask)
255 __oldmask = __r.__bits.__reg;
256 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
258 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
267 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
270 #endif /* __BSD_VISIBLE */
274 #endif /* !_FENV_H_ */