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34 .Nd Adaptec VL/EISA/PCI SCSI host adapter driver
36 To compile this driver into the kernel,
37 place the following lines in your
38 kernel configuration file:
39 .Bd -ragged -offset indent
43 For one or more VL/EISA cards:
46 For one or more PCI cards:
49 To allow PCI adapters to use memory mapped I/O if enabled:
50 .Cd options AHC_ALLOW_MEMIO
52 To configure one or more controllers to assume the target role:
53 .Cd options AHC_TMODE_ENABLE <bitmask of units>
56 Alternatively, to load the driver as a
57 module at boot time, place the following lines in
59 .Bd -literal -offset indent
66 This driver provides access to the
68 bus(es) connected to the Adaptec AIC77xx and AIC78xx
71 Driver features include support for twin and wide busses,
72 fast, ultra or ultra2 synchronous transfers depending on controller type,
73 tagged queueing, SCB paging, and target mode.
75 Memory mapped I/O can be enabled for PCI devices with the
76 .Dq Dv AHC_ALLOW_MEMIO
78 Memory mapped I/O is more efficient than the alternative, programmed I/O.
79 Most PCI BIOSes will map devices so that either technique for communicating
80 with the card is available.
82 usually when the PCI device is sitting behind a PCI->PCI bridge,
83 the BIOS may fail to properly initialize the chip for memory mapped I/O.
84 The typical symptom of this problem is a system hang if memory mapped I/O
86 Most modern motherboards perform the initialization correctly and work fine
87 with this option enabled.
89 Individual controllers may be configured to operate in the target role
91 .Dq Dv AHC_TMODE_ENABLE
93 The value assigned to this option should be a bitmap
94 of all units where target mode is desired.
95 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
96 A value of 0x8a enables it for units 1, 3, and 7.
98 Per target configuration performed in the
100 menu, accessible at boot
106 configuration utility for
109 is honored by this driver.
110 This includes synchronous/asynchronous transfers,
111 maximum synchronous negotiation rate,
114 the host adapter's SCSI ID,
118 Twin Channel controllers,
119 the primary channel selection.
120 For systems that store non-volatile settings in a system specific manner
121 rather than a serial eeprom directly connected to the aic7xxx controller,
124 must be enabled for the driver to access this information.
125 This restriction applies to all
127 and many motherboard configurations.
129 Note that I/O addresses are determined automatically by the probe routines,
130 but care should be taken when using a 284x
131 .Pq Tn VESA No local bus controller
135 The jumpers setting the I/O area for the 284x should match the
137 slot into which the card is inserted to prevent conflicts with other
141 Performance and feature sets vary throughout the aic7xxx product line.
142 The following table provides a comparison of the different chips supported
146 Note that wide and twin channel features, although always supported
147 by a particular chip, may be disabled in a particular motherboard or card
149 .Bd -ragged -offset indent
150 .Bl -column "aic7895CX" "MIPSX" "EISA/VLX" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
151 .It Em "Chip" Ta "MIPS" Ta "Bus" Ta "MaxSync" Ta "MaxWidth" Ta "SCBs" Ta "Features"
152 .It "aic7770" Ta "10" Ta "EISA/VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
153 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
154 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
155 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
156 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
157 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
158 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
159 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
160 .It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5"
161 .It "aic7895C" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 8"
162 .It "aic7896" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
163 .It "aic7897" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
164 .It "aic7899" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5 6 7 8"
169 Multiplexed Twin Channel Device - One controller servicing two busses.
171 Multi-function Twin Channel Device - Two controllers on one chip.
173 Command Channel Secondary DMA Engine - Allows scatter gather list and
176 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
178 Block Move Instruction Support - Doubles the speed of certain sequencer
182 style Scatter Gather Engine - Improves S/G prefetch performance.
184 Queuing Registers - Allows queueing of new transactions without pausing the
187 Multiple Target IDs - Allows the controller to respond to selection as a
188 target on multiple SCSI IDs.
194 driver supports the following
196 host adapter chips and
352 NEC PC-9821Xt13 (PC-98)
356 NEC PC-9821X-B02L/B09 (PC-98)
358 NEC SV-98/2-B03 (PC-98)
360 Many motherboards with on-board
364 .Sh SCSI CONTROL BLOCKS (SCBs)
365 Every transaction sent to a device on the SCSI bus is assigned a
366 .Sq SCSI Control Block
368 The SCB contains all of the information required by the
369 controller to process a transaction.
370 The chip feature table lists
371 the number of SCBs that can be stored in on-chip memory.
373 with model numbers greater than or equal to 7870 allow for the on chip
374 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
375 Very few Adaptec controller configurations have external SRAM.
377 If external SRAM is not available, SCBs are a limited resource.
378 Using the SCBs in a straight forward manner would only allow the driver to
379 handle as many concurrent transactions as there are physical SCBs.
380 To fully utilize the SCSI bus and the devices on it,
381 requires much more concurrency.
382 The solution to this problem is
384 a concept similar to memory paging.
385 SCB paging takes advantage of
386 the fact that devices usually disconnect from the SCSI bus for long
387 periods of time without talking to the controller.
388 The SCBs for disconnected transactions are only of use to the controller
389 when the transfer is resumed.
390 When the host queues another transaction
391 for the controller to execute, the controller firmware will use a
392 free SCB if one is available.
393 Otherwise, the state of the most recently
394 disconnected (and therefore most likely to stay disconnected) SCB is
395 saved, via dma, to host memory, and the local SCB reused to start
397 This allows the controller to queue up to
398 255 transactions regardless of the amount of SCB space.
400 local SCB space serves as a cache for disconnected transactions, the
401 more SCB space available, the less host bus traffic consumed saving
402 and restoring SCB data.
420 sequencer-code assembler,
421 and the firmware running on the aic7xxx chips was written by
422 .An Justin T. Gibbs .
424 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
426 Rev B in synchronous mode at 10MHz.
427 Controllers with this problem have a
428 42 MHz clock crystal on them and run slightly above 10MHz.
429 This confuses the drive and hangs the bus.
430 Setting a maximum synchronous negotiation rate of 8MHz in the
432 utility will allow normal operation.
434 Although the Ultra2 and Ultra160 products have sufficient instruction
435 ram space to support both the initiator and target roles concurrently,
436 this configuration is disabled in favor of allowing the target role
437 to respond on multiple target ids.
438 A method for configuring dual role mode should be provided.
440 Tagged Queuing is not supported in target mode.
442 Reselection in target mode fails to function correctly on all high
443 voltage differential boards as shipped by Adaptec.
445 how to modify HVD board to work correctly in target mode is available