2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #include "opt_atpic.h"
38 #include "opt_compat.h"
39 #include "opt_hwpmc_hooks.h"
40 #include "opt_kdtrace.h"
42 #include <machine/asmacros.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/specialreg.h>
51 .globl dtrace_invop_jump_addr
53 .type dtrace_invop_jump_addr,@object
54 .size dtrace_invop_jump_addr,8
55 dtrace_invop_jump_addr:
57 .globl dtrace_invop_calltrap_addr
59 .type dtrace_invop_calltrap_addr,@object
60 .size dtrace_invop_calltrap_addr,8
61 dtrace_invop_calltrap_addr:
66 ENTRY(start_exceptions)
69 /*****************************************************************************/
71 /*****************************************************************************/
73 * Trap and fault vector routines.
75 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
76 * state on the stack but also disables interrupts. This is important for
77 * us for the use of the swapgs instruction. We cannot be interrupted
78 * until the GS.base value is correct. For most traps, we automatically
79 * then enable interrupts if the interrupted context had them enabled.
80 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
82 * The cpu will push a certain amount of state onto the kernel stack for
83 * the current process. See amd64/include/frame.h.
84 * This includes the current RFLAGS (status register, which includes
85 * the interrupt disable state prior to the trap), the code segment register,
86 * and the return instruction pointer are pushed by the cpu. The cpu
87 * will also push an 'error' code for certain traps. We push a dummy
88 * error code for those traps where the cpu doesn't in order to maintain
89 * a consistent frame. We also push a contrived 'trap number'.
91 * The cpu does not push the general registers, we must do that, and we
92 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
93 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
94 * must load them with appropriate values for supervisor mode operation.
100 /* Traps that we leave interrupts disabled for.. */
101 #define TRAP_NOEN(a) \
103 movl $(a),TF_TRAPNO(%rsp) ; \
104 movq $0,TF_ADDR(%rsp) ; \
105 movq $0,TF_ERR(%rsp) ; \
113 TRAP_NOEN(T_DTRACE_RET)
116 /* Regular traps; The cpu does not supply tf_err for these. */
119 movl $(a),TF_TRAPNO(%rsp) ; \
120 movq $0,TF_ADDR(%rsp) ; \
121 movq $0,TF_ERR(%rsp) ; \
144 /* This group of traps have tf_err already pushed by the cpu */
145 #define TRAP_ERR(a) \
147 movl $(a),TF_TRAPNO(%rsp) ; \
148 movq $0,TF_ADDR(%rsp) ; \
154 movl $T_SEGNPFLT,TF_TRAPNO(%rsp)
158 movl $T_STKFLT,TF_TRAPNO(%rsp)
164 * alltraps entry point. Use swapgs if this is the first time in the
165 * kernel from userland. Reenable interrupts if they were enabled
166 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
170 .type alltraps,@function
172 movq %rdi,TF_RDI(%rsp)
173 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
174 jz alltraps_testi /* already running with kernel GS.base */
176 movq PCPU(CURPCB),%rdi
177 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
183 testl $PSL_I,TF_RFLAGS(%rsp)
184 jz alltraps_pushregs_no_rdi
186 alltraps_pushregs_no_rdi:
187 movq %rsi,TF_RSI(%rsp)
188 movq %rdx,TF_RDX(%rsp)
189 movq %rcx,TF_RCX(%rsp)
192 movq %rax,TF_RAX(%rsp)
193 movq %rbx,TF_RBX(%rsp)
194 movq %rbp,TF_RBP(%rsp)
195 movq %r10,TF_R10(%rsp)
196 movq %r11,TF_R11(%rsp)
197 movq %r12,TF_R12(%rsp)
198 movq %r13,TF_R13(%rsp)
199 movq %r14,TF_R14(%rsp)
200 movq %r15,TF_R15(%rsp)
201 movl $TF_HASSEGS,TF_FLAGS(%rsp)
203 FAKE_MCOUNT(TF_RIP(%rsp))
206 * DTrace Function Boundary Trace (fbt) probes are triggered
207 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
208 * interrupt. For all other trap types, just handle them in
211 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
214 /* Check if there is no DTrace hook registered. */
215 cmpq $0,dtrace_invop_jump_addr
219 * Set our jump address for the jump back in the event that
220 * the breakpoint wasn't caused by DTrace at all.
222 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
224 /* Jump to the code hooked in by DTrace. */
225 movq dtrace_invop_jump_addr,%rax
226 jmpq *dtrace_invop_jump_addr
229 .type calltrap,@function
234 jmp doreti /* Handle any pending ASTs */
237 * alltraps_noen entry point. Unlike alltraps above, we want to
238 * leave the interrupts disabled. This corresponds to
239 * SDT_SYS386IGT on the i386 port.
243 .type alltraps_noen,@function
245 movq %rdi,TF_RDI(%rsp)
246 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
247 jz 1f /* already running with kernel GS.base */
249 movq PCPU(CURPCB),%rdi
250 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
251 1: movw %fs,TF_FS(%rsp)
255 jmp alltraps_pushregs_no_rdi
259 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
260 movq $0,TF_ADDR(%rsp)
262 movq %rdi,TF_RDI(%rsp)
263 movq %rsi,TF_RSI(%rsp)
264 movq %rdx,TF_RDX(%rsp)
265 movq %rcx,TF_RCX(%rsp)
268 movq %rax,TF_RAX(%rsp)
269 movq %rbx,TF_RBX(%rsp)
270 movq %rbp,TF_RBP(%rsp)
271 movq %r10,TF_R10(%rsp)
272 movq %r11,TF_R11(%rsp)
273 movq %r12,TF_R12(%rsp)
274 movq %r13,TF_R13(%rsp)
275 movq %r14,TF_R14(%rsp)
276 movq %r15,TF_R15(%rsp)
281 movl $TF_HASSEGS,TF_FLAGS(%rsp)
283 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
284 jz 1f /* already running with kernel GS.base */
288 call dblfault_handler
295 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
296 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
297 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
298 jz 1f /* already running with kernel GS.base */
300 movq PCPU(CURPCB),%rdi
301 andl $~PCB_FULL_IRET,PCB_FLAGS(%rdi)
302 1: movq %cr2,%rdi /* preserve %cr2 before .. */
303 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
308 testl $PSL_I,TF_RFLAGS(%rsp)
309 jz alltraps_pushregs_no_rdi
311 jmp alltraps_pushregs_no_rdi
314 * We have to special-case this one. If we get a trap in doreti() at
315 * the iretq stage, we'll reenter with the wrong gs state. We'll have
316 * to do a special the swapgs in this case even coming from the kernel.
317 * XXX linux has a trap handler for their equivalent of load_gs().
321 movl $T_PROTFLT,TF_TRAPNO(%rsp)
323 movq $0,TF_ADDR(%rsp)
324 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
325 leaq doreti_iret(%rip),%rdi
326 cmpq %rdi,TF_RIP(%rsp)
327 je 1f /* kernel but with user gsbase!! */
328 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
329 jz 2f /* already running with kernel GS.base */
331 2: movq PCPU(CURPCB),%rdi
332 orl $PCB_FULL_IRET,PCB_FLAGS(%rdi) /* always full iret from GPF */
337 testl $PSL_I,TF_RFLAGS(%rsp)
338 jz alltraps_pushregs_no_rdi
340 jmp alltraps_pushregs_no_rdi
343 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
344 * and the new privilige level. We are still running on the old user stack
345 * pointer. We have to juggle a few things around to find our stack etc.
346 * swapgs gives us access to our PCPU space only.
348 * We do not support invoking this from a custom %cs or %ss (e.g. using
349 * entries from an LDT).
353 movq %rsp,PCPU(SCRATCH_RSP)
355 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
357 /* defer TF_RSP till we have a spare register */
358 movq %r11,TF_RFLAGS(%rsp)
359 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
360 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
361 movq %r11,TF_RSP(%rsp) /* user stack pointer */
366 movq PCPU(CURPCB),%r11
367 andl $~PCB_FULL_IRET,PCB_FLAGS(%r11)
369 movq $KUDSEL,TF_SS(%rsp)
370 movq $KUCSEL,TF_CS(%rsp)
372 movq %rdi,TF_RDI(%rsp) /* arg 1 */
373 movq %rsi,TF_RSI(%rsp) /* arg 2 */
374 movq %rdx,TF_RDX(%rsp) /* arg 3 */
375 movq %r10,TF_RCX(%rsp) /* arg 4 */
376 movq %r8,TF_R8(%rsp) /* arg 5 */
377 movq %r9,TF_R9(%rsp) /* arg 6 */
378 movq %rax,TF_RAX(%rsp) /* syscall number */
379 movq %rbx,TF_RBX(%rsp) /* C preserved */
380 movq %rbp,TF_RBP(%rsp) /* C preserved */
381 movq %r12,TF_R12(%rsp) /* C preserved */
382 movq %r13,TF_R13(%rsp) /* C preserved */
383 movq %r14,TF_R14(%rsp) /* C preserved */
384 movq %r15,TF_R15(%rsp) /* C preserved */
385 movl $TF_HASSEGS,TF_FLAGS(%rsp)
387 FAKE_MCOUNT(TF_RIP(%rsp))
388 movq PCPU(CURTHREAD),%rdi
389 movq %rsp,TD_FRAME(%rdi)
390 movl TF_RFLAGS(%rsp),%esi
393 1: movq PCPU(CURPCB),%rax
394 /* Disable interrupts before testing PCB_FULL_IRET. */
396 testl $PCB_FULL_IRET,PCB_FLAGS(%rax)
398 /* Check for and handle AST's on return to userland. */
399 movq PCPU(CURTHREAD),%rax
400 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
402 /* Restore preserved registers. */
404 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */
405 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */
406 movq TF_RDX(%rsp),%rdx /* return value 2 */
407 movq TF_RAX(%rsp),%rax /* return value 1 */
408 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */
409 movq TF_RIP(%rsp),%rcx /* original %rip */
410 movq TF_RSP(%rsp),%rsp /* user stack pointer */
414 2: /* AST scheduled. */
420 3: /* Requested full context restore, use doreti for that. */
425 * Here for CYA insurance, in case a "syscall" instruction gets
426 * issued from 32 bit compatability mode. MSR_CSTAR has to point
427 * to *something* if EFER_SCE is enabled.
429 IDTVEC(fast_syscall32)
433 * NMI handling is special.
435 * First, NMIs do not respect the state of the processor's RFLAGS.IF
436 * bit. The NMI handler may be entered at any time, including when
437 * the processor is in a critical section with RFLAGS.IF == 0.
438 * The processor's GS.base value could be invalid on entry to the
441 * Second, the processor treats NMIs specially, blocking further NMIs
442 * until an 'iretq' instruction is executed. We thus need to execute
443 * the NMI handler with interrupts disabled, to prevent a nested interrupt
444 * from executing an 'iretq' instruction and inadvertently taking the
445 * processor out of NMI mode.
447 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
448 * GS.base value for the processor is stored just above the bottom of its
449 * NMI stack. For NMIs taken from kernel mode, the current value in
450 * the processor's GS.base is saved at entry to C-preserved register %r12,
451 * the canonical value for GS.base is then loaded into the processor, and
452 * the saved value is restored at exit time. For NMIs taken from user mode,
453 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
458 movl $(T_NMI),TF_TRAPNO(%rsp)
459 movq $0,TF_ADDR(%rsp)
461 movq %rdi,TF_RDI(%rsp)
462 movq %rsi,TF_RSI(%rsp)
463 movq %rdx,TF_RDX(%rsp)
464 movq %rcx,TF_RCX(%rsp)
467 movq %rax,TF_RAX(%rsp)
468 movq %rbx,TF_RBX(%rsp)
469 movq %rbp,TF_RBP(%rsp)
470 movq %r10,TF_R10(%rsp)
471 movq %r11,TF_R11(%rsp)
472 movq %r12,TF_R12(%rsp)
473 movq %r13,TF_R13(%rsp)
474 movq %r14,TF_R14(%rsp)
475 movq %r15,TF_R15(%rsp)
480 movl $TF_HASSEGS,TF_FLAGS(%rsp)
483 testb $SEL_RPL_MASK,TF_CS(%rsp)
484 jnz nmi_fromuserspace
486 * We've interrupted the kernel. Preserve GS.base in %r12.
488 movl $MSR_GSBASE,%ecx
493 /* Retrieve and load the canonical value for GS.base. */
494 movq TF_SIZE(%rsp),%rdx
502 /* Note: this label is also used by ddb and gdb: */
504 FAKE_MCOUNT(TF_RIP(%rsp))
510 * Capture a userspace callchain if needed.
512 * - Check if the current trap was from user mode.
513 * - Check if the current thread is valid.
514 * - Check if the thread requires a user call chain to be
517 * We are still in NMI mode at this point.
520 jz nocallchain /* not from userspace */
521 movq PCPU(CURTHREAD),%rax
522 orq %rax,%rax /* curthread present? */
524 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
527 * A user callchain is to be captured, so:
528 * - Move execution to the regular kernel stack, to allow for
529 * nested NMI interrupts.
530 * - Take the processor out of "NMI" mode by faking an "iret".
531 * - Enable interrupts, so that copyin() can work.
533 movq %rsp,%rsi /* source stack pointer */
537 movq %rdx,%rdi /* destination stack pointer */
539 shrq $3,%rcx /* trap frame size in long words */
542 movsq /* copy trapframe */
545 pushq %rax /* tf_ss */
546 pushq %rdx /* tf_rsp (on kernel stack) */
547 pushfq /* tf_rflags */
549 pushq %rax /* tf_cs */
550 pushq $outofnmi /* tf_rip */
554 * At this point the processor has exited NMI mode and is running
555 * with interrupts turned off on the normal kernel stack.
557 * If a pending NMI gets recognized at or after this point, it
558 * will cause a kernel callchain to be traced.
560 * We turn interrupts back on, and call the user callchain capture hook.
565 movq PCPU(CURTHREAD),%rdi /* thread */
566 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
567 movq %rsp,%rdx /* frame */
577 * Put back the preserved MSR_GSBASE value.
579 movl $MSR_GSBASE,%ecx
585 movq TF_RDI(%rsp),%rdi
586 movq TF_RSI(%rsp),%rsi
587 movq TF_RDX(%rsp),%rdx
588 movq TF_RCX(%rsp),%rcx
591 movq TF_RAX(%rsp),%rax
592 movq TF_RBX(%rsp),%rbx
593 movq TF_RBP(%rsp),%rbp
594 movq TF_R10(%rsp),%r10
595 movq TF_R11(%rsp),%r11
596 movq TF_R12(%rsp),%r12
597 movq TF_R13(%rsp),%r13
598 movq TF_R14(%rsp),%r14
599 movq TF_R15(%rsp),%r15
603 ENTRY(fork_trampoline)
604 movq %r12,%rdi /* function */
605 movq %rbx,%rsi /* arg1 */
606 movq %rsp,%rdx /* trapframe pointer */
609 jmp doreti /* Handle any ASTs */
612 * To efficiently implement classification of trap and interrupt handlers
613 * for profiling, there must be only trap handlers between the labels btrap
614 * and bintr, and only interrupt handlers between the labels bintr and
615 * eintr. This is implemented (partly) by including files that contain
616 * some of the handlers. Before including the files, set up a normal asm
617 * environment so that the included files doen't need to know that they are
621 #ifdef COMPAT_FREEBSD32
627 #include <amd64/ia32/ia32_exception.S>
636 #include <amd64/amd64/apic_vector.S>
644 #include <amd64/amd64/atpic_vector.S>
651 * void doreti(struct trapframe)
653 * Handle return from interrupts, traps and syscalls.
657 .type doreti,@function
659 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
661 * Check if ASTs can be handled now.
663 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
664 jz doreti_exit /* can't handle ASTs now if not */
668 * Check for ASTs atomically with returning. Disabling CPU
669 * interrupts provides sufficient locking even in the SMP case,
670 * since we will be informed of any new ASTs by an IPI.
673 movq PCPU(CURTHREAD),%rax
674 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
677 movq %rsp,%rdi /* pass a pointer to the trapframe */
682 * doreti_exit: pop registers, iret.
684 * The segment register pop is a special case, since it may
685 * fault if (for example) a sigreturn specifies bad segment
686 * registers. The fault is handled in trap.c.
690 movq PCPU(CURPCB),%r8
693 * Do not reload segment registers for kernel.
694 * Since we do not reload segments registers with sane
695 * values on kernel entry, descriptors referenced by
696 * segments registers might be not valid. This is fatal
697 * for user mode, but is not a problem for the kernel.
699 testb $SEL_RPL_MASK,TF_CS(%rsp)
701 testl $PCB_FULL_IRET,PCB_FLAGS(%r8)
703 testl $TF_HASSEGS,TF_FLAGS(%rsp)
707 /* Restore %fs and fsbase */
714 movl $MSR_FSBASE,%ecx
715 movl PCB_FSBASE(%r8),%eax
716 movl PCB_FSBASE+4(%r8),%edx
721 /* Restore %gs and gsbase */
725 movl $MSR_GSBASE,%ecx
726 /* Save current kernel %gs base into %r12d:%r13d */
733 /* Save user %gs base into %r14d:%r15d */
737 /* Restore kernel %gs base */
743 * Restore user %gs base, either from PCB if used for TLS, or
744 * from the previously saved msr read.
746 movl $MSR_KGSBASE,%ecx
749 movl PCB_GSBASE(%r8),%eax
750 movl PCB_GSBASE+4(%r8),%edx
757 wrmsr /* May trap if non-canonical, but only for TLS. */
765 movq TF_RDI(%rsp),%rdi
766 movq TF_RSI(%rsp),%rsi
767 movq TF_RDX(%rsp),%rdx
768 movq TF_RCX(%rsp),%rcx
771 movq TF_RAX(%rsp),%rax
772 movq TF_RBX(%rsp),%rbx
773 movq TF_RBP(%rsp),%rbp
774 movq TF_R10(%rsp),%r10
775 movq TF_R11(%rsp),%r11
776 movq TF_R12(%rsp),%r12
777 movq TF_R13(%rsp),%r13
778 movq TF_R14(%rsp),%r14
779 movq TF_R15(%rsp),%r15
780 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
781 jz 1f /* keep running with kernel GS.base */
785 addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */
794 movw $KUF32SEL,TF_FS(%rsp)
795 movw $KUG32SEL,TF_GS(%rsp)
799 * doreti_iret_fault. Alternative return code for
800 * the case where we get a fault in the doreti_exit code
801 * above. trap() (amd64/amd64/trap.c) catches this specific
802 * case, sends the process a signal and continues in the
803 * corresponding place in the code below.
806 .globl doreti_iret_fault
808 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
809 testl $PSL_I,TF_RFLAGS(%rsp)
817 movl $TF_HASSEGS,TF_FLAGS(%rsp)
818 movq %rdi,TF_RDI(%rsp)
819 movq %rsi,TF_RSI(%rsp)
820 movq %rdx,TF_RDX(%rsp)
821 movq %rcx,TF_RCX(%rsp)
824 movq %rax,TF_RAX(%rsp)
825 movq %rbx,TF_RBX(%rsp)
826 movq %rbp,TF_RBP(%rsp)
827 movq %r10,TF_R10(%rsp)
828 movq %r11,TF_R11(%rsp)
829 movq %r12,TF_R12(%rsp)
830 movq %r13,TF_R13(%rsp)
831 movq %r14,TF_R14(%rsp)
832 movq %r15,TF_R15(%rsp)
833 movl $T_PROTFLT,TF_TRAPNO(%rsp)
834 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
835 movq $0,TF_ADDR(%rsp)
836 FAKE_MCOUNT(TF_RIP(%rsp))
842 movl $T_PROTFLT,TF_TRAPNO(%rsp)
843 testl $PSL_I,TF_RFLAGS(%rsp)
849 movw $KUDSEL,TF_DS(%rsp)
855 movl $T_PROTFLT,TF_TRAPNO(%rsp)
856 testl $PSL_I,TF_RFLAGS(%rsp)
862 movw $KUDSEL,TF_ES(%rsp)
868 testl $PSL_I,TF_RFLAGS(%rsp)
872 movl $T_PROTFLT,TF_TRAPNO(%rsp)
875 movw $KUF32SEL,TF_FS(%rsp)
882 movl $T_PROTFLT,TF_TRAPNO(%rsp)
883 testl $PSL_I,TF_RFLAGS(%rsp)
889 movw $KUG32SEL,TF_GS(%rsp)
893 .globl fsbase_load_fault
895 movl $T_PROTFLT,TF_TRAPNO(%rsp)
896 testl $PSL_I,TF_RFLAGS(%rsp)
902 movq PCPU(CURTHREAD),%r8
904 movq $0,PCB_FSBASE(%r8)
908 .globl gsbase_load_fault
910 movl $T_PROTFLT,TF_TRAPNO(%rsp)
911 testl $PSL_I,TF_RFLAGS(%rsp)
917 movq PCPU(CURTHREAD),%r8
919 movq $0,PCB_GSBASE(%r8)
923 ENTRY(end_exceptions)