2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/mutex.h>
46 #include <sys/sysctl.h>
47 #include <machine/bus.h>
49 #include <sys/signalvar.h>
51 #include <machine/cputypes.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/md_var.h>
55 #include <machine/pcb.h>
56 #include <machine/psl.h>
57 #include <machine/resource.h>
58 #include <machine/specialreg.h>
59 #include <machine/segments.h>
60 #include <machine/ucontext.h>
63 * Floating point support.
66 #if defined(__GNUCLIKE_ASM) && !defined(lint)
68 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
69 #define fnclex() __asm __volatile("fnclex")
70 #define fninit() __asm __volatile("fninit")
71 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
72 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
73 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
75 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
76 #define start_emulating() __asm __volatile( \
77 "smsw %%ax; orb %0,%%al; lmsw %%ax" \
78 : : "n" (CR0_TS) : "ax")
79 #define stop_emulating() __asm __volatile("clts")
82 xrstor(char *addr, uint64_t mask)
89 __asm __volatile(".byte 0x0f,0xae,0x2f" : :
90 "a" (low), "d" (hi), "D" (addr));
94 xsave(char *addr, uint64_t mask)
101 __asm __volatile(".byte 0x0f,0xae,0x27" : :
102 "a" (low), "d" (hi), "D" (addr) : "memory");
106 xsetbv(uint32_t reg, uint64_t val)
112 __asm __volatile(".byte 0x0f,0x01,0xd1" : :
113 "c" (reg), "a" (low), "d" (hi));
116 #else /* !(__GNUCLIKE_ASM && !lint) */
118 void fldcw(u_short cw);
121 void fnstcw(caddr_t addr);
122 void fnstsw(caddr_t addr);
123 void fxsave(caddr_t addr);
124 void fxrstor(caddr_t addr);
125 void ldmxcsr(u_int csr);
126 void start_emulating(void);
127 void stop_emulating(void);
128 void xrstor(char *addr, uint64_t mask);
129 void xsave(char *addr, uint64_t mask);
130 void xsetbv(uint32_t reg, uint64_t val);
132 #endif /* __GNUCLIKE_ASM && !lint */
134 #define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save->sv_env.en_cw)
135 #define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save->sv_env.en_sw)
137 typedef u_char bool_t;
139 static void fpu_clean_state(void);
141 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
142 NULL, 1, "Floating point instructions executed in hardware");
144 static struct savefpu fpu_initialstate;
147 * Initialize the floating point unit. On the boot CPU we generate a
148 * clean state that is used to initialize the floating point unit when
149 * it is first used by a process.
159 * It is too early for critical_enter() to work on AP.
161 saveintr = intr_disable();
164 control = __INITIAL_FPUCW__;
166 mxcsr = __INITIAL_MXCSR__;
168 if (PCPU_GET(cpuid) == 0) {
169 fxsave(&fpu_initialstate);
170 if (fpu_initialstate.sv_env.en_mxcsr_mask)
171 cpu_mxcsr_mask = fpu_initialstate.sv_env.en_mxcsr_mask;
173 cpu_mxcsr_mask = 0xFFBF;
174 bzero(fpu_initialstate.sv_fp, sizeof(fpu_initialstate.sv_fp));
175 bzero(fpu_initialstate.sv_xmm, sizeof(fpu_initialstate.sv_xmm));
178 intr_restore(saveintr);
182 * Free coprocessor (if we have it).
185 fpuexit(struct thread *td)
189 if (curthread == PCPU_GET(fpcurthread)) {
191 fxsave(PCPU_GET(curpcb)->pcb_save);
193 PCPU_SET(fpcurthread, 0);
202 return (_MC_FPFMT_XMM);
206 * The following mechanism is used to ensure that the FPE_... value
207 * that is passed as a trapcode to the signal handler of the user
208 * process does not have more than one bit set.
210 * Multiple bits may be set if the user process modifies the control
211 * word while a status word bit is already set. While this is a sign
212 * of bad coding, we have no choise than to narrow them down to one
213 * bit, since we must not send a trapcode that is not exactly one of
216 * The mechanism has a static table with 127 entries. Each combination
217 * of the 7 FPU status word exception bits directly translates to a
218 * position in this table, where a single FPE_... value is stored.
219 * This FPE_... value stored there is considered the "most important"
220 * of the exception bits and will be sent as the signal code. The
221 * precedence of the bits is based upon Intel Document "Numerical
222 * Applications", Chapter "Special Computational Situations".
224 * The macro to choose one of these values does these steps: 1) Throw
225 * away status word bits that cannot be masked. 2) Throw away the bits
226 * currently masked in the control word, assuming the user isn't
227 * interested in them anymore. 3) Reinsert status word bit 7 (stack
228 * fault) if it is set, which cannot be masked but must be presered.
229 * 4) Use the remaining bits to point into the trapcode table.
231 * The 6 maskable bits in order of their preference, as stated in the
232 * above referenced Intel manual:
233 * 1 Invalid operation (FP_X_INV)
236 * 1c Operand of unsupported format
238 * 2 QNaN operand (not an exception, irrelavant here)
239 * 3 Any other invalid-operation not mentioned above or zero divide
240 * (FP_X_INV, FP_X_DZ)
241 * 4 Denormal operand (FP_X_DNML)
242 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
243 * 6 Inexact result (FP_X_IMP)
245 static char fpetable[128] = {
247 FPE_FLTINV, /* 1 - INV */
248 FPE_FLTUND, /* 2 - DNML */
249 FPE_FLTINV, /* 3 - INV | DNML */
250 FPE_FLTDIV, /* 4 - DZ */
251 FPE_FLTINV, /* 5 - INV | DZ */
252 FPE_FLTDIV, /* 6 - DNML | DZ */
253 FPE_FLTINV, /* 7 - INV | DNML | DZ */
254 FPE_FLTOVF, /* 8 - OFL */
255 FPE_FLTINV, /* 9 - INV | OFL */
256 FPE_FLTUND, /* A - DNML | OFL */
257 FPE_FLTINV, /* B - INV | DNML | OFL */
258 FPE_FLTDIV, /* C - DZ | OFL */
259 FPE_FLTINV, /* D - INV | DZ | OFL */
260 FPE_FLTDIV, /* E - DNML | DZ | OFL */
261 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
262 FPE_FLTUND, /* 10 - UFL */
263 FPE_FLTINV, /* 11 - INV | UFL */
264 FPE_FLTUND, /* 12 - DNML | UFL */
265 FPE_FLTINV, /* 13 - INV | DNML | UFL */
266 FPE_FLTDIV, /* 14 - DZ | UFL */
267 FPE_FLTINV, /* 15 - INV | DZ | UFL */
268 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
269 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
270 FPE_FLTOVF, /* 18 - OFL | UFL */
271 FPE_FLTINV, /* 19 - INV | OFL | UFL */
272 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
273 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
274 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
275 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
276 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
277 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
278 FPE_FLTRES, /* 20 - IMP */
279 FPE_FLTINV, /* 21 - INV | IMP */
280 FPE_FLTUND, /* 22 - DNML | IMP */
281 FPE_FLTINV, /* 23 - INV | DNML | IMP */
282 FPE_FLTDIV, /* 24 - DZ | IMP */
283 FPE_FLTINV, /* 25 - INV | DZ | IMP */
284 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
285 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
286 FPE_FLTOVF, /* 28 - OFL | IMP */
287 FPE_FLTINV, /* 29 - INV | OFL | IMP */
288 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
289 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
290 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
291 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
292 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
293 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
294 FPE_FLTUND, /* 30 - UFL | IMP */
295 FPE_FLTINV, /* 31 - INV | UFL | IMP */
296 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
297 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
298 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
299 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
300 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
301 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
302 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
303 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
304 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
305 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
306 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
307 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
308 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
309 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
310 FPE_FLTSUB, /* 40 - STK */
311 FPE_FLTSUB, /* 41 - INV | STK */
312 FPE_FLTUND, /* 42 - DNML | STK */
313 FPE_FLTSUB, /* 43 - INV | DNML | STK */
314 FPE_FLTDIV, /* 44 - DZ | STK */
315 FPE_FLTSUB, /* 45 - INV | DZ | STK */
316 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
317 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
318 FPE_FLTOVF, /* 48 - OFL | STK */
319 FPE_FLTSUB, /* 49 - INV | OFL | STK */
320 FPE_FLTUND, /* 4A - DNML | OFL | STK */
321 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
322 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
323 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
324 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
325 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
326 FPE_FLTUND, /* 50 - UFL | STK */
327 FPE_FLTSUB, /* 51 - INV | UFL | STK */
328 FPE_FLTUND, /* 52 - DNML | UFL | STK */
329 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
330 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
331 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
332 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
333 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
334 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
335 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
336 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
337 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
338 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
339 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
340 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
341 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
342 FPE_FLTRES, /* 60 - IMP | STK */
343 FPE_FLTSUB, /* 61 - INV | IMP | STK */
344 FPE_FLTUND, /* 62 - DNML | IMP | STK */
345 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
346 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
347 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
348 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
349 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
350 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
351 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
352 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
353 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
354 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
355 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
356 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
357 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
358 FPE_FLTUND, /* 70 - UFL | IMP | STK */
359 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
360 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
361 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
362 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
363 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
364 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
365 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
366 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
367 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
368 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
369 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
370 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
371 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
372 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
373 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
377 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
379 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
380 * depend on longjmp() restoring a usable state. Restoring the state
381 * or examining it might fail if we didn't clear exceptions.
383 * The error code chosen will be one of the FPE_... macros. It will be
384 * sent as the second argument to old BSD-style signal handlers and as
385 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
387 * XXX the FP state is not preserved across signal handlers. So signal
388 * handlers cannot afford to do FP unless they preserve the state or
389 * longjmp() out. Both preserving the state and longjmp()ing may be
390 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
391 * solution for signals other than SIGFPE.
396 u_short control, status;
401 * Interrupt handling (for another interrupt) may have pushed the
402 * state to memory. Fetch the relevant parts of the state from
405 if (PCPU_GET(fpcurthread) != curthread) {
406 control = GET_FPU_CW(curthread);
407 status = GET_FPU_SW(curthread);
413 if (PCPU_GET(fpcurthread) == curthread)
416 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
420 * Implement device not available (DNA) exception
422 * It would be better to switch FP context here (if curthread != fpcurthread)
423 * and not necessarily for every context switch, but it is too hard to
424 * access foreign pcb's.
427 static int err_count = 0;
435 if (PCPU_GET(fpcurthread) == curthread) {
436 printf("fpudna: fpcurthread == curthread %d times\n",
442 if (PCPU_GET(fpcurthread) != NULL) {
443 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
444 PCPU_GET(fpcurthread),
445 PCPU_GET(fpcurthread)->td_proc->p_pid,
446 curthread, curthread->td_proc->p_pid);
451 * Record new context early in case frstor causes a trap.
453 PCPU_SET(fpcurthread, curthread);
454 pcb = PCPU_GET(curpcb);
458 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
460 * This is the first time this thread has used the FPU or
461 * the PCB doesn't contain a clean FPU state. Explicitly
462 * load an initial state.
464 fxrstor(&fpu_initialstate);
465 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
466 fldcw(pcb->pcb_initial_fpucw);
467 if (PCB_USER_FPU(pcb))
469 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
471 set_pcb_flags(pcb, PCB_FPUINITDONE);
473 fxrstor(pcb->pcb_save);
482 td = PCPU_GET(fpcurthread);
483 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
485 PCPU_SET(fpcurthread, NULL);
486 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
491 * Get the user state of the FPU into pcb->pcb_user_save without
492 * dropping ownership (if possible). It returns the FPU ownership
496 fpugetregs(struct thread *td)
501 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
502 bcopy(&fpu_initialstate, &pcb->pcb_user_save,
503 sizeof(fpu_initialstate));
504 pcb->pcb_user_save.sv_env.en_cw = pcb->pcb_initial_fpucw;
506 return (_MC_FPOWNED_PCB);
509 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
510 fxsave(&pcb->pcb_user_save);
512 return (_MC_FPOWNED_FPU);
515 return (_MC_FPOWNED_PCB);
520 fpuuserinited(struct thread *td)
525 if (PCB_USER_FPU(pcb))
527 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
529 set_pcb_flags(pcb, PCB_FPUINITDONE);
533 * Set the state of the FPU.
536 fpusetregs(struct thread *td, struct savefpu *addr)
542 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
545 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE);
548 bcopy(addr, &td->td_pcb->pcb_user_save, sizeof(*addr));
554 * On AuthenticAMD processors, the fxrstor instruction does not restore
555 * the x87's stored last instruction pointer, last data pointer, and last
556 * opcode values, except in the rare case in which the exception summary
557 * (ES) bit in the x87 status word is set to 1.
559 * In order to avoid leaking this information across processes, we clean
560 * these values by performing a dummy load before executing fxrstor().
563 fpu_clean_state(void)
565 static float dummy_variable = 0.0;
569 * Clear the ES bit in the x87 status word if it is currently
570 * set, in order to avoid causing a fault in the upcoming load.
577 * Load the dummy variable into the x87 stack. This mangles
578 * the x87 stack, but we don't care since we're about to call
581 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
585 * This really sucks. We want the acpi version only, but it requires
586 * the isa_if.h file in order to get the definitions.
590 #include <isa/isavar.h>
592 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
594 static struct isa_pnp_id fpupnp_ids[] = {
595 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
600 fpupnp_probe(device_t dev)
604 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
611 fpupnp_attach(device_t dev)
617 static device_method_t fpupnp_methods[] = {
618 /* Device interface */
619 DEVMETHOD(device_probe, fpupnp_probe),
620 DEVMETHOD(device_attach, fpupnp_attach),
621 DEVMETHOD(device_detach, bus_generic_detach),
622 DEVMETHOD(device_shutdown, bus_generic_shutdown),
623 DEVMETHOD(device_suspend, bus_generic_suspend),
624 DEVMETHOD(device_resume, bus_generic_resume),
629 static driver_t fpupnp_driver = {
635 static devclass_t fpupnp_devclass;
637 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
641 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
646 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == &pcb->pcb_user_save,
647 ("mangled pcb_save"));
649 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
650 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
652 ctx->prev = pcb->pcb_save;
653 pcb->pcb_save = &ctx->hwstate;
654 set_pcb_flags(pcb, PCB_KERNFPU);
655 clear_pcb_flags(pcb, PCB_FPUINITDONE);
660 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
666 if (curthread == PCPU_GET(fpcurthread))
669 pcb->pcb_save = ctx->prev;
670 if (pcb->pcb_save == &pcb->pcb_user_save) {
671 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
672 set_pcb_flags(pcb, PCB_FPUINITDONE);
673 clear_pcb_flags(pcb, PCB_KERNFPU);
675 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
677 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
678 set_pcb_flags(pcb, PCB_FPUINITDONE);
680 clear_pcb_flags(pcb, PCB_FPUINITDONE);
681 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
687 fpu_kern_thread(u_int flags)
691 pcb = PCPU_GET(curpcb);
692 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
693 ("Only kthread may use fpu_kern_thread"));
694 KASSERT(pcb->pcb_save == &pcb->pcb_user_save, ("mangled pcb_save"));
695 KASSERT(PCB_USER_FPU(pcb), ("recursive call"));
697 set_pcb_flags(pcb, PCB_KERNFPU);
702 is_fpu_kern_thread(u_int flags)
705 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
707 return ((PCPU_GET(curpcb)->pcb_flags & PCB_KERNFPU) != 0);