2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/mutex.h>
46 #include <sys/sysctl.h>
47 #include <machine/bus.h>
49 #include <sys/signalvar.h>
51 #include <machine/cputypes.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/md_var.h>
55 #include <machine/pcb.h>
56 #include <machine/psl.h>
57 #include <machine/resource.h>
58 #include <machine/specialreg.h>
59 #include <machine/segments.h>
60 #include <machine/ucontext.h>
63 * Floating point support.
66 #if defined(__GNUCLIKE_ASM) && !defined(lint)
68 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
69 #define fnclex() __asm __volatile("fnclex")
70 #define fninit() __asm __volatile("fninit")
71 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
72 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
73 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
75 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
78 xrstor(char *addr, uint64_t mask)
84 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
88 xsave(char *addr, uint64_t mask)
94 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
98 #else /* !(__GNUCLIKE_ASM && !lint) */
100 void fldcw(u_short cw);
103 void fnstcw(caddr_t addr);
104 void fnstsw(caddr_t addr);
105 void fxsave(caddr_t addr);
106 void fxrstor(caddr_t addr);
107 void ldmxcsr(u_int csr);
108 void xrstor(char *addr, uint64_t mask);
109 void xsave(char *addr, uint64_t mask);
111 #endif /* __GNUCLIKE_ASM && !lint */
113 #define start_emulating() load_cr0(rcr0() | CR0_TS)
114 #define stop_emulating() clts()
116 #define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save->sv_env.en_cw)
117 #define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save->sv_env.en_sw)
119 CTASSERT(sizeof(struct savefpu) == 512);
120 CTASSERT(sizeof(struct xstate_hdr) == 64);
121 CTASSERT(sizeof(struct savefpu_ymm) == 832);
124 * This requirement is to make it easier for asm code to calculate
125 * offset of the fpu save area from the pcb address. FPU save area
126 * must be 64-byte aligned.
128 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
130 static void fpu_clean_state(void);
132 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
133 NULL, 1, "Floating point instructions executed in hardware");
135 static int use_xsaveopt;
136 int use_xsave; /* non-static for cpu_switch.S */
137 uint64_t xsave_mask; /* the same */
138 static struct savefpu *fpu_initialstate;
140 struct xsave_area_elm_descr {
150 xsave((char *)addr, xsave_mask);
152 fxsave((char *)addr);
156 fpurestore(void *addr)
160 xrstor((char *)addr, xsave_mask);
162 fxrstor((char *)addr);
166 * Enable XSAVE if supported and allowed by user.
167 * Calculate the xsave_mask.
173 uint64_t xsave_mask_user;
175 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
177 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
182 cpuid_count(0xd, 0x0, cp);
183 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
184 if ((cp[0] & xsave_mask) != xsave_mask)
185 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
186 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
187 xsave_mask_user = xsave_mask;
188 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
189 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
190 xsave_mask &= xsave_mask_user;
192 cpuid_count(0xd, 0x1, cp);
193 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
195 * Patch the XSAVE instruction in the cpu_switch code
196 * to XSAVEOPT. We assume that XSAVE encoding used
197 * REX byte, and set the bit 4 of the r/m byte.
199 ctx_switch_xsave[3] |= 0x10;
205 * Calculate the fpu save area size.
213 cpuid_count(0xd, 0x0, cp);
214 cpu_max_ext_state_size = cp[1];
217 * Reload the cpu_feature2, since we enabled OSXSAVE.
220 cpu_feature2 = cp[2];
222 cpu_max_ext_state_size = sizeof(struct savefpu);
226 * Initialize the floating point unit.
239 load_cr4(rcr4() | CR4_XSAVE);
240 load_xcr(XCR0, xsave_mask);
244 * XCR0 shall be set up before CPU can report the save area size.
250 * It is too early for critical_enter() to work on AP.
252 saveintr = intr_disable();
255 control = __INITIAL_FPUCW__;
257 mxcsr = __INITIAL_MXCSR__;
260 intr_restore(saveintr);
264 * On the boot CPU we generate a clean state that is used to
265 * initialize the floating point unit when it is first used by a
269 fpuinitstate(void *arg __unused)
272 int cp[4], i, max_ext_n;
274 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
276 saveintr = intr_disable();
279 fpusave(fpu_initialstate);
280 if (fpu_initialstate->sv_env.en_mxcsr_mask)
281 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
283 cpu_mxcsr_mask = 0xFFBF;
286 * The fninit instruction does not modify XMM registers. The
287 * fpusave call dumped the garbage contained in the registers
288 * after reset to the initial state saved. Clear XMM
289 * registers file image to make the startup program state and
290 * signal handler XMM register content predictable.
292 bzero(&fpu_initialstate->sv_xmm[0], sizeof(struct xmmacc));
295 * Create a table describing the layout of the CPU Extended
299 max_ext_n = flsl(xsave_mask);
300 xsave_area_desc = malloc(max_ext_n * sizeof(struct
301 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
303 xsave_area_desc[0].offset = 0;
304 xsave_area_desc[0].size = 160;
306 xsave_area_desc[1].offset = 160;
307 xsave_area_desc[1].size = 288 - 160;
309 for (i = 2; i < max_ext_n; i++) {
310 cpuid_count(0xd, i, cp);
311 xsave_area_desc[i].offset = cp[1];
312 xsave_area_desc[i].size = cp[0];
317 intr_restore(saveintr);
319 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, fpuinitstate, NULL);
322 * Free coprocessor (if we have it).
325 fpuexit(struct thread *td)
329 if (curthread == PCPU_GET(fpcurthread)) {
331 fpusave(PCPU_GET(curpcb)->pcb_save);
333 PCPU_SET(fpcurthread, 0);
342 return (_MC_FPFMT_XMM);
346 * The following mechanism is used to ensure that the FPE_... value
347 * that is passed as a trapcode to the signal handler of the user
348 * process does not have more than one bit set.
350 * Multiple bits may be set if the user process modifies the control
351 * word while a status word bit is already set. While this is a sign
352 * of bad coding, we have no choise than to narrow them down to one
353 * bit, since we must not send a trapcode that is not exactly one of
356 * The mechanism has a static table with 127 entries. Each combination
357 * of the 7 FPU status word exception bits directly translates to a
358 * position in this table, where a single FPE_... value is stored.
359 * This FPE_... value stored there is considered the "most important"
360 * of the exception bits and will be sent as the signal code. The
361 * precedence of the bits is based upon Intel Document "Numerical
362 * Applications", Chapter "Special Computational Situations".
364 * The macro to choose one of these values does these steps: 1) Throw
365 * away status word bits that cannot be masked. 2) Throw away the bits
366 * currently masked in the control word, assuming the user isn't
367 * interested in them anymore. 3) Reinsert status word bit 7 (stack
368 * fault) if it is set, which cannot be masked but must be presered.
369 * 4) Use the remaining bits to point into the trapcode table.
371 * The 6 maskable bits in order of their preference, as stated in the
372 * above referenced Intel manual:
373 * 1 Invalid operation (FP_X_INV)
376 * 1c Operand of unsupported format
378 * 2 QNaN operand (not an exception, irrelavant here)
379 * 3 Any other invalid-operation not mentioned above or zero divide
380 * (FP_X_INV, FP_X_DZ)
381 * 4 Denormal operand (FP_X_DNML)
382 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
383 * 6 Inexact result (FP_X_IMP)
385 static char fpetable[128] = {
387 FPE_FLTINV, /* 1 - INV */
388 FPE_FLTUND, /* 2 - DNML */
389 FPE_FLTINV, /* 3 - INV | DNML */
390 FPE_FLTDIV, /* 4 - DZ */
391 FPE_FLTINV, /* 5 - INV | DZ */
392 FPE_FLTDIV, /* 6 - DNML | DZ */
393 FPE_FLTINV, /* 7 - INV | DNML | DZ */
394 FPE_FLTOVF, /* 8 - OFL */
395 FPE_FLTINV, /* 9 - INV | OFL */
396 FPE_FLTUND, /* A - DNML | OFL */
397 FPE_FLTINV, /* B - INV | DNML | OFL */
398 FPE_FLTDIV, /* C - DZ | OFL */
399 FPE_FLTINV, /* D - INV | DZ | OFL */
400 FPE_FLTDIV, /* E - DNML | DZ | OFL */
401 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
402 FPE_FLTUND, /* 10 - UFL */
403 FPE_FLTINV, /* 11 - INV | UFL */
404 FPE_FLTUND, /* 12 - DNML | UFL */
405 FPE_FLTINV, /* 13 - INV | DNML | UFL */
406 FPE_FLTDIV, /* 14 - DZ | UFL */
407 FPE_FLTINV, /* 15 - INV | DZ | UFL */
408 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
409 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
410 FPE_FLTOVF, /* 18 - OFL | UFL */
411 FPE_FLTINV, /* 19 - INV | OFL | UFL */
412 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
413 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
414 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
415 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
416 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
417 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
418 FPE_FLTRES, /* 20 - IMP */
419 FPE_FLTINV, /* 21 - INV | IMP */
420 FPE_FLTUND, /* 22 - DNML | IMP */
421 FPE_FLTINV, /* 23 - INV | DNML | IMP */
422 FPE_FLTDIV, /* 24 - DZ | IMP */
423 FPE_FLTINV, /* 25 - INV | DZ | IMP */
424 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
425 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
426 FPE_FLTOVF, /* 28 - OFL | IMP */
427 FPE_FLTINV, /* 29 - INV | OFL | IMP */
428 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
429 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
430 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
431 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
432 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
433 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
434 FPE_FLTUND, /* 30 - UFL | IMP */
435 FPE_FLTINV, /* 31 - INV | UFL | IMP */
436 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
437 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
438 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
439 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
440 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
441 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
442 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
443 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
444 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
445 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
446 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
447 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
448 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
449 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
450 FPE_FLTSUB, /* 40 - STK */
451 FPE_FLTSUB, /* 41 - INV | STK */
452 FPE_FLTUND, /* 42 - DNML | STK */
453 FPE_FLTSUB, /* 43 - INV | DNML | STK */
454 FPE_FLTDIV, /* 44 - DZ | STK */
455 FPE_FLTSUB, /* 45 - INV | DZ | STK */
456 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
457 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
458 FPE_FLTOVF, /* 48 - OFL | STK */
459 FPE_FLTSUB, /* 49 - INV | OFL | STK */
460 FPE_FLTUND, /* 4A - DNML | OFL | STK */
461 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
462 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
463 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
464 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
465 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
466 FPE_FLTUND, /* 50 - UFL | STK */
467 FPE_FLTSUB, /* 51 - INV | UFL | STK */
468 FPE_FLTUND, /* 52 - DNML | UFL | STK */
469 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
470 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
471 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
472 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
473 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
474 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
475 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
476 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
477 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
478 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
479 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
480 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
481 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
482 FPE_FLTRES, /* 60 - IMP | STK */
483 FPE_FLTSUB, /* 61 - INV | IMP | STK */
484 FPE_FLTUND, /* 62 - DNML | IMP | STK */
485 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
486 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
487 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
488 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
489 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
490 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
491 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
492 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
493 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
494 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
495 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
496 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
497 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
498 FPE_FLTUND, /* 70 - UFL | IMP | STK */
499 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
500 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
501 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
502 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
503 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
504 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
505 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
506 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
507 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
508 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
509 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
510 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
511 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
512 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
513 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
517 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
519 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
520 * depend on longjmp() restoring a usable state. Restoring the state
521 * or examining it might fail if we didn't clear exceptions.
523 * The error code chosen will be one of the FPE_... macros. It will be
524 * sent as the second argument to old BSD-style signal handlers and as
525 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
527 * XXX the FP state is not preserved across signal handlers. So signal
528 * handlers cannot afford to do FP unless they preserve the state or
529 * longjmp() out. Both preserving the state and longjmp()ing may be
530 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
531 * solution for signals other than SIGFPE.
536 u_short control, status;
541 * Interrupt handling (for another interrupt) may have pushed the
542 * state to memory. Fetch the relevant parts of the state from
545 if (PCPU_GET(fpcurthread) != curthread) {
546 control = GET_FPU_CW(curthread);
547 status = GET_FPU_SW(curthread);
553 if (PCPU_GET(fpcurthread) == curthread)
556 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
560 * Implement device not available (DNA) exception
562 * It would be better to switch FP context here (if curthread != fpcurthread)
563 * and not necessarily for every context switch, but it is too hard to
564 * access foreign pcb's.
567 static int err_count = 0;
575 if (PCPU_GET(fpcurthread) == curthread) {
576 printf("fpudna: fpcurthread == curthread %d times\n",
582 if (PCPU_GET(fpcurthread) != NULL) {
583 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
584 PCPU_GET(fpcurthread),
585 PCPU_GET(fpcurthread)->td_proc->p_pid,
586 curthread, curthread->td_proc->p_pid);
591 * Record new context early in case frstor causes a trap.
593 PCPU_SET(fpcurthread, curthread);
594 pcb = PCPU_GET(curpcb);
598 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
600 * This is the first time this thread has used the FPU or
601 * the PCB doesn't contain a clean FPU state. Explicitly
602 * load an initial state.
604 * We prefer to restore the state from the actual save
605 * area in PCB instead of directly loading from
606 * fpu_initialstate, to ignite the XSAVEOPT
609 bcopy(fpu_initialstate, pcb->pcb_save, cpu_max_ext_state_size);
610 fpurestore(pcb->pcb_save);
611 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
612 fldcw(pcb->pcb_initial_fpucw);
613 if (PCB_USER_FPU(pcb))
615 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
617 set_pcb_flags(pcb, PCB_FPUINITDONE);
619 fpurestore(pcb->pcb_save);
628 td = PCPU_GET(fpcurthread);
629 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
631 PCPU_SET(fpcurthread, NULL);
632 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
637 * Get the user state of the FPU into pcb->pcb_user_save without
638 * dropping ownership (if possible). It returns the FPU ownership
642 fpugetregs(struct thread *td)
645 uint64_t *xstate_bv, bit;
650 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
651 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
652 cpu_max_ext_state_size);
653 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
654 pcb->pcb_initial_fpucw;
656 return (_MC_FPOWNED_PCB);
659 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
660 fpusave(get_pcb_user_save_pcb(pcb));
662 return (_MC_FPOWNED_FPU);
667 * Handle partially saved state.
669 sa = (char *)get_pcb_user_save_pcb(pcb);
670 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
671 offsetof(struct xstate_hdr, xstate_bv));
672 max_ext_n = flsl(xsave_mask);
673 for (i = 0; i < max_ext_n; i++) {
675 if ((*xstate_bv & bit) != 0)
677 bcopy((char *)fpu_initialstate +
678 xsave_area_desc[i].offset,
679 sa + xsave_area_desc[i].offset,
680 xsave_area_desc[i].size);
684 return (_MC_FPOWNED_PCB);
689 fpuuserinited(struct thread *td)
694 if (PCB_USER_FPU(pcb))
696 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
698 set_pcb_flags(pcb, PCB_FPUINITDONE);
702 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
704 struct xstate_hdr *hdr, *ehdr;
708 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
709 if (xfpustate == NULL)
714 len = xfpustate_size;
715 if (len < sizeof(struct xstate_hdr))
717 max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
721 ehdr = (struct xstate_hdr *)xfpustate;
722 bv = ehdr->xstate_bv;
727 if (bv & ~xsave_mask)
729 if ((bv & (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE)) !=
730 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE))
733 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
736 bcopy(xfpustate + sizeof(struct xstate_hdr),
737 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
743 * Set the state of the FPU.
746 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
747 size_t xfpustate_size)
754 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
755 error = fpusetxstate(td, xfpustate, xfpustate_size);
760 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
761 fpurestore(get_pcb_user_save_td(td));
763 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE);
766 error = fpusetxstate(td, xfpustate, xfpustate_size);
769 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
776 * On AuthenticAMD processors, the fxrstor instruction does not restore
777 * the x87's stored last instruction pointer, last data pointer, and last
778 * opcode values, except in the rare case in which the exception summary
779 * (ES) bit in the x87 status word is set to 1.
781 * In order to avoid leaking this information across processes, we clean
782 * these values by performing a dummy load before executing fxrstor().
785 fpu_clean_state(void)
787 static float dummy_variable = 0.0;
791 * Clear the ES bit in the x87 status word if it is currently
792 * set, in order to avoid causing a fault in the upcoming load.
799 * Load the dummy variable into the x87 stack. This mangles
800 * the x87 stack, but we don't care since we're about to call
803 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
807 * This really sucks. We want the acpi version only, but it requires
808 * the isa_if.h file in order to get the definitions.
812 #include <isa/isavar.h>
814 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
816 static struct isa_pnp_id fpupnp_ids[] = {
817 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
822 fpupnp_probe(device_t dev)
826 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
833 fpupnp_attach(device_t dev)
839 static device_method_t fpupnp_methods[] = {
840 /* Device interface */
841 DEVMETHOD(device_probe, fpupnp_probe),
842 DEVMETHOD(device_attach, fpupnp_attach),
843 DEVMETHOD(device_detach, bus_generic_detach),
844 DEVMETHOD(device_shutdown, bus_generic_shutdown),
845 DEVMETHOD(device_suspend, bus_generic_suspend),
846 DEVMETHOD(device_resume, bus_generic_resume),
851 static driver_t fpupnp_driver = {
857 static devclass_t fpupnp_devclass;
859 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
862 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
863 "Kernel contexts for FPU state");
865 #define FPU_KERN_CTX_FPUINITDONE 0x01
867 struct fpu_kern_ctx {
868 struct savefpu *prev;
873 struct fpu_kern_ctx *
874 fpu_kern_alloc_ctx(u_int flags)
876 struct fpu_kern_ctx *res;
879 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
880 cpu_max_ext_state_size;
881 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
882 M_NOWAIT : M_WAITOK) | M_ZERO);
887 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
890 /* XXXKIB clear the memory ? */
891 free(ctx, M_FPUKERN_CTX);
894 static struct savefpu *
895 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
899 p = (vm_offset_t)&ctx->hwstate1;
900 p = roundup2(p, XSAVE_AREA_ALIGN);
901 return ((struct savefpu *)p);
905 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
910 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
911 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
913 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
914 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
916 ctx->prev = pcb->pcb_save;
917 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
918 set_pcb_flags(pcb, PCB_KERNFPU);
919 clear_pcb_flags(pcb, PCB_FPUINITDONE);
924 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
930 if (curthread == PCPU_GET(fpcurthread))
933 pcb->pcb_save = ctx->prev;
934 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
935 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
936 set_pcb_flags(pcb, PCB_FPUINITDONE);
937 clear_pcb_flags(pcb, PCB_KERNFPU);
939 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
941 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
942 set_pcb_flags(pcb, PCB_FPUINITDONE);
944 clear_pcb_flags(pcb, PCB_FPUINITDONE);
945 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
951 fpu_kern_thread(u_int flags)
955 pcb = PCPU_GET(curpcb);
956 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
957 ("Only kthread may use fpu_kern_thread"));
958 KASSERT(pcb->pcb_save == get_pcb_user_save_pcb(pcb),
959 ("mangled pcb_save"));
960 KASSERT(PCB_USER_FPU(pcb), ("recursive call"));
962 set_pcb_flags(pcb, PCB_KERNFPU);
967 is_fpu_kern_thread(u_int flags)
970 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
972 return ((PCPU_GET(curpcb)->pcb_flags & PCB_KERNFPU) != 0);