2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
49 #include <sys/eventhandler.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/sysctl.h>
53 #include <sys/power.h>
55 #include <machine/asmacros.h>
56 #include <machine/clock.h>
57 #include <machine/cputypes.h>
58 #include <machine/frame.h>
59 #include <machine/intr_machdep.h>
60 #include <machine/segments.h>
61 #include <machine/specialreg.h>
62 #include <machine/md_var.h>
64 #include <amd64/isa/icu.h>
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void identify_cpu(void);
69 void earlysetcpuclass(void);
70 void panicifcpuunsupported(void);
72 static u_int find_cpu_vendor_id(void);
73 static void print_AMD_info(void);
74 static void print_AMD_assoc(int i);
75 static void print_via_padlock_info(void);
78 char machine[] = "amd64";
79 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
80 machine, 0, "Machine class");
82 static char cpu_model[128];
83 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
84 cpu_model, 0, "Machine model");
86 static int hw_clockrate;
87 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
88 &hw_clockrate, 0, "CPU instruction clock rate");
90 static char cpu_brand[48];
96 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
97 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
104 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
105 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
106 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
116 cpu_class = amd64_cpus[cpu].cpu_class;
118 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
120 /* Check for extended CPUID information and a processor name. */
121 if (cpu_exthigh >= 0x80000004) {
123 for (i = 0x80000002; i < 0x80000005; i++) {
125 memcpy(brand, regs, sizeof(regs));
126 brand += sizeof(regs);
130 switch (cpu_vendor_id) {
131 case CPU_VENDOR_INTEL:
132 /* Please make up your mind folks! */
133 strcat(cpu_model, "EM64T");
137 * Values taken from AMD Processor Recognition
138 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
139 * (also describes ``Features'' encodings.
141 strcpy(cpu_model, "AMD ");
142 if ((cpu_id & 0xf00) == 0xf00)
143 strcat(cpu_model, "AMD64 Processor");
145 strcat(cpu_model, "Unknown");
147 case CPU_VENDOR_CENTAUR:
148 strcpy(cpu_model, "VIA ");
149 if ((cpu_id & 0xff0) == 0x6f0)
150 strcat(cpu_model, "Nano Processor");
152 strcat(cpu_model, "Unknown");
155 strcat(cpu_model, "Unknown");
160 * Replace cpu_model with cpu_brand minus leading spaces if
164 while (*brand == ' ')
167 strcpy(cpu_model, brand);
169 printf("%s (", cpu_model);
172 hw_clockrate = (tsc_freq + 5000) / 1000000;
173 printf("%jd.%02d-MHz ",
174 (intmax_t)(tsc_freq + 4999) / 1000000,
175 (u_int)((tsc_freq + 4999) / 10000) % 100);
179 printf("Unknown"); /* will panic below... */
181 printf("-class CPU)\n");
183 printf(" Origin = \"%s\"", cpu_vendor);
185 printf(" Id = 0x%x", cpu_id);
187 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
188 cpu_vendor_id == CPU_VENDOR_AMD ||
189 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
190 printf(" Stepping = %u", cpu_id & 0xf);
194 * Here we should probably set up flags indicating
195 * whether or not various features are available.
196 * The interesting ones are probably VME, PSE, PAE,
197 * and PGE. The code already assumes without bothering
198 * to check that all CPUs >= Pentium have a TSC and
201 printf("\n Features=0x%b", cpu_feature,
203 "\001FPU" /* Integral FPU */
204 "\002VME" /* Extended VM86 mode support */
205 "\003DE" /* Debugging Extensions (CR4.DE) */
206 "\004PSE" /* 4MByte page tables */
207 "\005TSC" /* Timestamp counter */
208 "\006MSR" /* Machine specific registers */
209 "\007PAE" /* Physical address extension */
210 "\010MCE" /* Machine Check support */
211 "\011CX8" /* CMPEXCH8 instruction */
212 "\012APIC" /* SMP local APIC */
213 "\013oldMTRR" /* Previous implementation of MTRR */
214 "\014SEP" /* Fast System Call */
215 "\015MTRR" /* Memory Type Range Registers */
216 "\016PGE" /* PG_G (global bit) support */
217 "\017MCA" /* Machine Check Architecture */
218 "\020CMOV" /* CMOV instruction */
219 "\021PAT" /* Page attributes table */
220 "\022PSE36" /* 36 bit address space support */
221 "\023PN" /* Processor Serial number */
222 "\024CLFLUSH" /* Has the CLFLUSH instruction */
224 "\026DTS" /* Debug Trace Store */
225 "\027ACPI" /* ACPI support */
226 "\030MMX" /* MMX instructions */
227 "\031FXSR" /* FXSAVE/FXRSTOR */
228 "\032SSE" /* Streaming SIMD Extensions */
229 "\033SSE2" /* Streaming SIMD Extensions #2 */
230 "\034SS" /* Self snoop */
231 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
232 "\036TM" /* Thermal Monitor clock slowdown */
233 "\037IA64" /* CPU can execute IA64 instructions */
234 "\040PBE" /* Pending Break Enable */
237 if (cpu_feature2 != 0) {
238 printf("\n Features2=0x%b", cpu_feature2,
240 "\001SSE3" /* SSE3 */
242 "\003DTES64" /* 64-bit Debug Trace */
243 "\004MON" /* MONITOR/MWAIT Instructions */
244 "\005DS_CPL" /* CPL Qualified Debug Store */
245 "\006VMX" /* Virtual Machine Extensions */
246 "\007SMX" /* Safer Mode Extensions */
247 "\010EST" /* Enhanced SpeedStep */
248 "\011TM2" /* Thermal Monitor 2 */
249 "\012SSSE3" /* SSSE3 */
250 "\013CNXT-ID" /* L1 context ID available */
253 "\016CX16" /* CMPXCHG16B Instruction */
254 "\017xTPR" /* Send Task Priority Messages*/
255 "\020PDCM" /* Perf/Debug Capability MSR */
258 "\023DCA" /* Direct Cache Access */
261 "\026x2APIC" /* xAPIC Extensions */
276 * AMD64 Architecture Programmer's Manual Volume 3:
277 * General-Purpose and System Instructions
278 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
280 * IA-32 Intel Architecture Software Developer's Manual,
281 * Volume 2A: Instruction Set Reference, A-M
282 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
284 if (amd_feature != 0) {
285 printf("\n AMD Features=0x%b", amd_feature,
287 "\001<s0>" /* Same */
288 "\002<s1>" /* Same */
289 "\003<s2>" /* Same */
290 "\004<s3>" /* Same */
291 "\005<s4>" /* Same */
292 "\006<s5>" /* Same */
293 "\007<s6>" /* Same */
294 "\010<s7>" /* Same */
295 "\011<s8>" /* Same */
296 "\012<s9>" /* Same */
297 "\013<b10>" /* Undefined */
298 "\014SYSCALL" /* Have SYSCALL/SYSRET */
299 "\015<s12>" /* Same */
300 "\016<s13>" /* Same */
301 "\017<s14>" /* Same */
302 "\020<s15>" /* Same */
303 "\021<s16>" /* Same */
304 "\022<s17>" /* Same */
305 "\023<b18>" /* Reserved, unknown */
306 "\024MP" /* Multiprocessor Capable */
307 "\025NX" /* Has EFER.NXE, NX */
308 "\026<b21>" /* Undefined */
309 "\027MMX+" /* AMD MMX Extensions */
310 "\030<s23>" /* Same */
311 "\031<s24>" /* Same */
312 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
313 "\033Page1GB" /* 1-GB large page support */
314 "\034RDTSCP" /* RDTSCP */
315 "\035<b28>" /* Undefined */
316 "\036LM" /* 64 bit long mode */
317 "\0373DNow!+" /* AMD 3DNow! Extensions */
318 "\0403DNow!" /* AMD 3DNow! */
322 if (amd_feature2 != 0) {
323 printf("\n AMD Features2=0x%b", amd_feature2,
325 "\001LAHF" /* LAHF/SAHF in long mode */
326 "\002CMP" /* CMP legacy */
327 "\003SVM" /* Secure Virtual Mode */
328 "\004ExtAPIC" /* Extended APIC register */
329 "\005CR8" /* CR8 in legacy mode */
330 "\006ABM" /* LZCNT instruction */
331 "\007SSE4A" /* SSE4A */
332 "\010MAS" /* Misaligned SSE mode */
333 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
334 "\012OSVW" /* OS visible workaround */
335 "\013IBS" /* Instruction based sampling */
336 "\014SSE5" /* SSE5 */
337 "\015SKINIT" /* SKINIT/STGI */
338 "\016WDT" /* Watchdog timer */
360 if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
361 print_via_padlock_info();
363 if ((cpu_feature & CPUID_HTT) &&
364 cpu_vendor_id == CPU_VENDOR_AMD)
365 cpu_feature &= ~CPUID_HTT;
368 * If this CPU supports P-state invariant TSC then
369 * mention the capability.
371 switch (cpu_vendor_id) {
373 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
374 AMD64_CPU_FAMILY(cpu_id) >= 0x10 ||
376 tsc_is_invariant = 1;
378 case CPU_VENDOR_INTEL:
379 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
380 (AMD64_CPU_FAMILY(cpu_id) == 0x6 &&
381 AMD64_CPU_MODEL(cpu_id) >= 0xe) ||
382 (AMD64_CPU_FAMILY(cpu_id) == 0xf &&
383 AMD64_CPU_MODEL(cpu_id) >= 0x3))
384 tsc_is_invariant = 1;
386 case CPU_VENDOR_CENTAUR:
387 if (AMD64_CPU_FAMILY(cpu_id) == 0x6 &&
388 AMD64_CPU_MODEL(cpu_id) >= 0xf &&
389 (rdmsr(0x1203) & 0x100000000ULL) == 0)
390 tsc_is_invariant = 1;
393 if (tsc_is_invariant)
394 printf("\n TSC: P-state invariant");
398 /* Avoid ugly blank lines: only print newline when we have to. */
399 if (*cpu_vendor || cpu_id)
405 if (cpu_vendor_id == CPU_VENDOR_AMD)
410 panicifcpuunsupported(void)
414 #error "You need to specify a cpu type"
417 * Now that we have told the user what they have,
418 * let them know if that machine type isn't configured.
425 panic("CPU class not configured");
432 /* Update TSC freq with the value indicated by the caller. */
434 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
437 * If there was an error during the transition or
438 * TSC is P-state invariant, don't do anything.
440 if (status != 0 || tsc_is_invariant)
443 /* Total setting for this level gives the new frequency in MHz. */
444 hw_clockrate = level->total_set.freq;
447 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
448 EVENTHANDLER_PRI_ANY);
451 * Final stage of CPU identification.
460 ((u_int *)&cpu_vendor)[0] = regs[1];
461 ((u_int *)&cpu_vendor)[1] = regs[3];
462 ((u_int *)&cpu_vendor)[2] = regs[2];
463 cpu_vendor[12] = '\0';
464 cpu_vendor_id = find_cpu_vendor_id();
468 cpu_procinfo = regs[1];
469 cpu_feature = regs[3];
470 cpu_feature2 = regs[2];
473 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
474 * function number again if it is set from BIOS. It is necessary
475 * for probing correct CPU topology later.
476 * XXX This is only done on the BSP package.
478 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) {
480 msr = rdmsr(MSR_IA32_MISC_ENABLE);
481 if ((msr & 0x400000ULL) != 0) {
482 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
488 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
489 cpu_vendor_id == CPU_VENDOR_AMD ||
490 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
491 do_cpuid(0x80000000, regs);
492 cpu_exthigh = regs[0];
494 if (cpu_exthigh >= 0x80000001) {
495 do_cpuid(0x80000001, regs);
496 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
497 amd_feature2 = regs[2];
499 if (cpu_exthigh >= 0x80000007) {
500 do_cpuid(0x80000007, regs);
501 amd_pminfo = regs[3];
503 if (cpu_exthigh >= 0x80000008) {
504 do_cpuid(0x80000008, regs);
505 cpu_procinfo2 = regs[2];
509 cpu = CPU_CLAWHAMMER;
513 find_cpu_vendor_id(void)
517 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
518 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
519 return (cpu_vendors[i].vendor_id);
524 print_AMD_assoc(int i)
527 printf(", fully associative\n");
529 printf(", %d-way associative\n", i);
533 print_AMD_l2_assoc(int i)
536 case 0: printf(", disabled/not present\n"); break;
537 case 1: printf(", direct mapped\n"); break;
538 case 2: printf(", 2-way associative\n"); break;
539 case 4: printf(", 4-way associative\n"); break;
540 case 6: printf(", 8-way associative\n"); break;
541 case 8: printf(", 16-way associative\n"); break;
542 case 15: printf(", fully associative\n"); break;
543 default: printf(", reserved configuration\n"); break;
552 if (cpu_exthigh < 0x80000005)
555 do_cpuid(0x80000005, regs);
556 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
557 print_AMD_assoc(regs[0] >> 24);
559 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
560 print_AMD_assoc((regs[0] >> 8) & 0xff);
562 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
563 print_AMD_assoc(regs[1] >> 24);
565 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
566 print_AMD_assoc((regs[1] >> 8) & 0xff);
568 printf("L1 data cache: %d kbytes", regs[2] >> 24);
569 printf(", %d bytes/line", regs[2] & 0xff);
570 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
571 print_AMD_assoc((regs[2] >> 16) & 0xff);
573 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
574 printf(", %d bytes/line", regs[3] & 0xff);
575 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
576 print_AMD_assoc((regs[3] >> 16) & 0xff);
578 if (cpu_exthigh >= 0x80000006) {
579 do_cpuid(0x80000006, regs);
580 if ((regs[0] >> 16) != 0) {
581 printf("L2 2MB data TLB: %d entries",
582 (regs[0] >> 16) & 0xfff);
583 print_AMD_l2_assoc(regs[0] >> 28);
584 printf("L2 2MB instruction TLB: %d entries",
586 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
588 printf("L2 2MB unified TLB: %d entries",
590 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
592 if ((regs[1] >> 16) != 0) {
593 printf("L2 4KB data TLB: %d entries",
594 (regs[1] >> 16) & 0xfff);
595 print_AMD_l2_assoc(regs[1] >> 28);
597 printf("L2 4KB instruction TLB: %d entries",
598 (regs[1] >> 16) & 0xfff);
599 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
601 printf("L2 4KB unified TLB: %d entries",
602 (regs[1] >> 16) & 0xfff);
603 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
605 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
606 printf(", %d bytes/line", regs[2] & 0xff);
607 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
608 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
612 * Opteron Rev E shows a bug as in very rare occasions a read memory
613 * barrier is not performed as expected if it is followed by a
614 * non-atomic read-modify-write instruction.
615 * As long as that bug pops up very rarely (intensive machine usage
616 * on other operating systems generally generates one unexplainable
617 * crash any 2 months) and as long as a model specific fix would be
618 * impratical at this stage, print out a warning string if the broken
619 * model and family are identified.
621 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
622 CPUID_TO_MODEL(cpu_id) <= 0x3f)
623 printf("WARNING: This architecture revision has known SMP "
624 "hardware bugs which may cause random instability\n");
628 print_via_padlock_info(void)
632 /* Check for supported models. */
633 switch (cpu_id & 0xff0) {
635 if ((cpu_id & 0xf) < 3)
645 do_cpuid(0xc0000000, regs);
646 if (regs[0] >= 0xc0000001)
647 do_cpuid(0xc0000001, regs);
651 printf("\n VIA Padlock Features=0x%b", regs[3],
655 "\011AES-CTR" /* ACE2 */
656 "\013SHA1,SHA256" /* PHE */