2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
47 static int hw_instruction_sse;
48 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
49 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
51 * -1: automatic (default)
52 * 0: keep enable CLFLUSH
53 * 1: force disable CLFLUSH
55 static int hw_clflush_disable = -1;
57 int cpu; /* Are we 386, 386sx, 486, etc? */
58 u_int cpu_feature; /* Feature flags */
59 u_int cpu_feature2; /* Feature flags */
60 u_int amd_feature; /* AMD feature flags */
61 u_int amd_feature2; /* AMD feature flags */
62 u_int amd_pminfo; /* AMD advanced power management info */
63 u_int via_feature_rng; /* VIA RNG features */
64 u_int via_feature_xcrypt; /* VIA ACE features */
65 u_int cpu_high; /* Highest arg to CPUID */
66 u_int cpu_exthigh; /* Highest arg to extended CPUID */
67 u_int cpu_id; /* Stepping ID */
68 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
69 u_int cpu_procinfo2; /* Multicore info */
70 char cpu_vendor[20]; /* CPU Origin code */
71 u_int cpu_vendor_id; /* CPU vendor ID */
72 u_int cpu_fxsr; /* SSE enabled */
73 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
74 u_int cpu_clflush_line_size = 32;
76 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
77 &via_feature_rng, 0, "VIA RNG feature available in CPU");
78 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
79 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
82 * Initialize special VIA features
90 * Check extended CPUID for PadLock features.
92 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
94 do_cpuid(0xc0000000, regs);
95 if (regs[0] >= 0xc0000001) {
96 do_cpuid(0xc0000001, regs);
101 /* Enable RNG if present. */
102 if ((val & VIA_CPUID_HAS_RNG) != 0) {
103 via_feature_rng = VIA_HAS_RNG;
104 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
107 /* Enable PadLock if present. */
108 if ((val & VIA_CPUID_HAS_ACE) != 0)
109 via_feature_xcrypt |= VIA_HAS_AES;
110 if ((val & VIA_CPUID_HAS_ACE2) != 0)
111 via_feature_xcrypt |= VIA_HAS_AESCTR;
112 if ((val & VIA_CPUID_HAS_PHE) != 0)
113 via_feature_xcrypt |= VIA_HAS_SHA;
114 if ((val & VIA_CPUID_HAS_PMM) != 0)
115 via_feature_xcrypt |= VIA_HAS_MM;
116 if (via_feature_xcrypt != 0)
117 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
121 * Initialize CPU control registers
128 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
129 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
130 cpu_fxsr = hw_instruction_sse = 1;
132 if ((amd_feature & AMDID_NX) != 0) {
133 msr = rdmsr(MSR_EFER) | EFER_NXE;
134 wrmsr(MSR_EFER, msr);
137 if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
146 * CPUID with %eax = 1, %ebx returns
147 * Bits 15-8: CLFLUSH line size
148 * (Value * 8 = cache line size in bytes)
150 if ((cpu_feature & CPUID_CLFSH) != 0)
151 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
153 * XXXKIB: (temporary) hack to work around traps generated
154 * when CLFLUSHing APIC register window under virtualization
155 * environments. These environments tend to disable the
156 * CPUID_SS feature even though the native CPU supports it.
158 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
159 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
160 cpu_feature &= ~CPUID_CLFSH;
162 * Allow to disable CLFLUSH feature manually by
163 * hw.clflush_disable tunable.
165 if (hw_clflush_disable == 1)
166 cpu_feature &= ~CPUID_CLFSH;