2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * In addition to hardware address maps, this
86 * module is called upon to provide software-use-only
87 * maps which may or may not be stored in the same
88 * form as hardware maps. These pseudo-maps are
89 * used to store intermediate results from copy
90 * operations to and from address spaces.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include "opt_pmap.h"
111 #include <sys/param.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/rwlock.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
129 #include <sys/cpuset.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_reserv.h>
144 #include <machine/intr_machdep.h>
145 #include <machine/apicvar.h>
146 #include <machine/cpu.h>
147 #include <machine/cputypes.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
150 #include <machine/specialreg.h>
152 #include <machine/smp.h>
155 #if !defined(DIAGNOSTIC)
156 #ifdef __GNUC_GNU_INLINE__
157 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
159 #define PMAP_INLINE extern inline
166 #define PV_STAT(x) do { x ; } while (0)
168 #define PV_STAT(x) do { } while (0)
171 #define pa_index(pa) ((pa) >> PDRSHIFT)
172 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
174 #define NPV_LIST_LOCKS MAXCPU
176 #define PHYS_TO_PV_LIST_LOCK(pa) \
177 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
179 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
180 struct rwlock **_lockp = (lockp); \
181 struct rwlock *_new_lock; \
183 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
184 if (_new_lock != *_lockp) { \
185 if (*_lockp != NULL) \
186 rw_wunlock(*_lockp); \
187 *_lockp = _new_lock; \
192 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
193 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
195 #define RELEASE_PV_LIST_LOCK(lockp) do { \
196 struct rwlock **_lockp = (lockp); \
198 if (*_lockp != NULL) { \
199 rw_wunlock(*_lockp); \
204 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
205 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
207 struct pmap kernel_pmap_store;
209 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
210 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
213 vm_paddr_t dmaplimit;
214 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
217 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
219 static int pat_works = 1;
220 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
221 "Is page attribute table fully functional?");
223 static int pg_ps_enabled = 1;
224 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
225 "Are large page mappings enabled?");
227 #define PAT_INDEX_SIZE 8
228 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
231 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
232 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
233 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
235 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
236 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
239 * Isolate the global pv list lock from data and other locks to prevent false
240 * sharing within the cache.
244 char padding[CACHE_LINE_SIZE - sizeof(struct rwlock)];
245 } pvh_global __aligned(CACHE_LINE_SIZE);
247 #define pvh_global_lock pvh_global.lock
250 * Data for the pv entry allocation mechanism
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static struct mtx pv_chunks_mutex;
254 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
255 static struct md_page *pv_table;
258 * All those kernel PT submaps that BSD is so fond of
260 pt_entry_t *CMAP1 = 0;
266 static caddr_t crashdumpmap;
268 static void free_pv_chunk(struct pv_chunk *pc);
269 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
270 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
271 static int popcnt_pc_map_elem(uint64_t elem);
272 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
273 static void reserve_pv_entries(pmap_t pmap, int needed,
274 struct rwlock **lockp);
275 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
276 struct rwlock **lockp);
277 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
278 struct rwlock **lockp);
279 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
280 struct rwlock **lockp);
281 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
282 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
284 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
286 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
287 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
288 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
289 vm_offset_t va, struct rwlock **lockp);
290 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
292 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
293 vm_prot_t prot, struct rwlock **lockp);
294 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
295 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
296 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
297 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
298 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
299 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
300 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
301 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
302 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
303 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
304 struct rwlock **lockp);
305 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
307 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
308 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
309 vm_page_t *free, struct rwlock **lockp);
310 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq,
311 vm_offset_t sva, pd_entry_t ptepde, vm_page_t *free,
312 struct rwlock **lockp);
313 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
314 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
316 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
317 vm_page_t m, struct rwlock **lockp);
318 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
320 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
322 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
323 struct rwlock **lockp);
324 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
325 struct rwlock **lockp);
326 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
327 struct rwlock **lockp);
329 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
331 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, vm_page_t *);
332 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
334 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
335 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
338 * Move the kernel virtual free pointer to the next
339 * 2MB. This is used to help improve performance
340 * by using a large (2MB) page for much of the kernel
341 * (.text, .data, .bss)
344 pmap_kmem_choose(vm_offset_t addr)
346 vm_offset_t newaddr = addr;
348 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
352 /********************/
353 /* Inline functions */
354 /********************/
356 /* Return a non-clipped PD index for a given VA */
357 static __inline vm_pindex_t
358 pmap_pde_pindex(vm_offset_t va)
360 return (va >> PDRSHIFT);
364 /* Return various clipped indexes for a given VA */
365 static __inline vm_pindex_t
366 pmap_pte_index(vm_offset_t va)
369 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
372 static __inline vm_pindex_t
373 pmap_pde_index(vm_offset_t va)
376 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
379 static __inline vm_pindex_t
380 pmap_pdpe_index(vm_offset_t va)
383 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
386 static __inline vm_pindex_t
387 pmap_pml4e_index(vm_offset_t va)
390 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
393 /* Return a pointer to the PML4 slot that corresponds to a VA */
394 static __inline pml4_entry_t *
395 pmap_pml4e(pmap_t pmap, vm_offset_t va)
398 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
401 /* Return a pointer to the PDP slot that corresponds to a VA */
402 static __inline pdp_entry_t *
403 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
407 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
408 return (&pdpe[pmap_pdpe_index(va)]);
411 /* Return a pointer to the PDP slot that corresponds to a VA */
412 static __inline pdp_entry_t *
413 pmap_pdpe(pmap_t pmap, vm_offset_t va)
417 pml4e = pmap_pml4e(pmap, va);
418 if ((*pml4e & PG_V) == 0)
420 return (pmap_pml4e_to_pdpe(pml4e, va));
423 /* Return a pointer to the PD slot that corresponds to a VA */
424 static __inline pd_entry_t *
425 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
429 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
430 return (&pde[pmap_pde_index(va)]);
433 /* Return a pointer to the PD slot that corresponds to a VA */
434 static __inline pd_entry_t *
435 pmap_pde(pmap_t pmap, vm_offset_t va)
439 pdpe = pmap_pdpe(pmap, va);
440 if (pdpe == NULL || (*pdpe & PG_V) == 0)
442 return (pmap_pdpe_to_pde(pdpe, va));
445 /* Return a pointer to the PT slot that corresponds to a VA */
446 static __inline pt_entry_t *
447 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
451 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
452 return (&pte[pmap_pte_index(va)]);
455 /* Return a pointer to the PT slot that corresponds to a VA */
456 static __inline pt_entry_t *
457 pmap_pte(pmap_t pmap, vm_offset_t va)
461 pde = pmap_pde(pmap, va);
462 if (pde == NULL || (*pde & PG_V) == 0)
464 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
465 return ((pt_entry_t *)pde);
466 return (pmap_pde_to_pte(pde, va));
470 pmap_resident_count_inc(pmap_t pmap, int count)
473 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
474 pmap->pm_stats.resident_count += count;
478 pmap_resident_count_dec(pmap_t pmap, int count)
481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
482 KASSERT(pmap->pm_stats.resident_count >= count,
483 ("pmap %p resident count underflow %ld %d", pmap,
484 pmap->pm_stats.resident_count, count));
485 pmap->pm_stats.resident_count -= count;
488 PMAP_INLINE pt_entry_t *
489 vtopte(vm_offset_t va)
491 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
493 return (PTmap + ((va >> PAGE_SHIFT) & mask));
496 static __inline pd_entry_t *
497 vtopde(vm_offset_t va)
499 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
501 return (PDmap + ((va >> PDRSHIFT) & mask));
505 allocpages(vm_paddr_t *firstaddr, int n)
510 bzero((void *)ret, n * PAGE_SIZE);
511 *firstaddr += n * PAGE_SIZE;
515 CTASSERT(powerof2(NDMPML4E));
518 create_pagetables(vm_paddr_t *firstaddr)
523 KPTphys = allocpages(firstaddr, NKPT);
524 KPML4phys = allocpages(firstaddr, 1);
525 KPDPphys = allocpages(firstaddr, NKPML4E);
526 KPDphys = allocpages(firstaddr, NKPDPE);
528 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
529 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
531 DMPDPphys = allocpages(firstaddr, NDMPML4E);
533 if ((amd_feature & AMDID_PAGE1GB) != 0)
534 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
536 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
537 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
539 /* Fill in the underlying page table pages */
540 /* Read-only from zero to physfree */
541 /* XXX not fully used, underneath 2M pages */
542 for (i = 0; (i << PAGE_SHIFT) < *firstaddr; i++) {
543 ((pt_entry_t *)KPTphys)[i] = i << PAGE_SHIFT;
544 ((pt_entry_t *)KPTphys)[i] |= PG_RW | PG_V | PG_G;
547 /* Now map the page tables at their location within PTmap */
548 for (i = 0; i < NKPT; i++) {
549 ((pd_entry_t *)KPDphys)[i] = KPTphys + (i << PAGE_SHIFT);
550 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V;
553 /* Map from zero to end of allocations under 2M pages */
554 /* This replaces some of the KPTphys entries above */
555 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++) {
556 ((pd_entry_t *)KPDphys)[i] = i << PDRSHIFT;
557 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V | PG_PS | PG_G;
560 /* And connect up the PD to the PDP */
561 for (i = 0; i < NKPDPE; i++) {
562 ((pdp_entry_t *)KPDPphys)[i + KPDPI] = KPDphys +
564 ((pdp_entry_t *)KPDPphys)[i + KPDPI] |= PG_RW | PG_V | PG_U;
568 * Now, set up the direct map region using 2MB and/or 1GB pages. If
569 * the end of physical memory is not aligned to a 1GB page boundary,
570 * then the residual physical memory is mapped with 2MB pages. Later,
571 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
572 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
573 * that are partially used.
575 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
576 ((pd_entry_t *)DMPDphys)[j] = (vm_paddr_t)i << PDRSHIFT;
577 /* Preset PG_M and PG_A because demotion expects it. */
578 ((pd_entry_t *)DMPDphys)[j] |= PG_RW | PG_V | PG_PS | PG_G |
581 for (i = 0; i < ndm1g; i++) {
582 ((pdp_entry_t *)DMPDPphys)[i] = (vm_paddr_t)i << PDPSHIFT;
583 /* Preset PG_M and PG_A because demotion expects it. */
584 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_PS | PG_G |
587 for (j = 0; i < ndmpdp; i++, j++) {
588 ((pdp_entry_t *)DMPDPphys)[i] = DMPDphys + (j << PAGE_SHIFT);
589 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_U;
592 /* And recursively map PML4 to itself in order to get PTmap */
593 ((pdp_entry_t *)KPML4phys)[PML4PML4I] = KPML4phys;
594 ((pdp_entry_t *)KPML4phys)[PML4PML4I] |= PG_RW | PG_V | PG_U;
596 /* Connect the Direct Map slot(s) up to the PML4. */
597 for (i = 0; i < NDMPML4E; i++) {
598 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] = DMPDPphys +
600 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] |= PG_RW | PG_V | PG_U;
603 /* Connect the KVA slot up to the PML4 */
604 ((pdp_entry_t *)KPML4phys)[KPML4I] = KPDPphys;
605 ((pdp_entry_t *)KPML4phys)[KPML4I] |= PG_RW | PG_V | PG_U;
609 * Bootstrap the system enough to run with virtual memory.
611 * On amd64 this is called after mapping has already been enabled
612 * and just syncs the pmap module with what has already been done.
613 * [We can't call it easily with mapping off since the kernel is not
614 * mapped with PA == VA, hence we would have to relocate every address
615 * from the linked base (virtual) address "KERNBASE" to the actual
616 * (physical) address starting relative to 0]
619 pmap_bootstrap(vm_paddr_t *firstaddr)
622 pt_entry_t *pte, *unused;
625 * Create an initial set of page tables to run the kernel in.
627 create_pagetables(firstaddr);
629 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
630 virtual_avail = pmap_kmem_choose(virtual_avail);
632 virtual_end = VM_MAX_KERNEL_ADDRESS;
635 /* XXX do %cr0 as well */
636 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
638 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
639 load_cr4(rcr4() | CR4_SMEP);
642 * Initialize the kernel pmap (which is statically allocated).
644 PMAP_LOCK_INIT(kernel_pmap);
645 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
646 kernel_pmap->pm_root = NULL;
647 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
648 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
651 * Initialize the global pv list lock.
653 rw_init(&pvh_global_lock, "pmap pv global");
656 * Reserve some special page table entries/VA space for temporary
659 #define SYSMAP(c, p, v, n) \
660 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
666 * CMAP1 is only used for the memory test.
668 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
673 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
677 /* Initialize the PAT MSR. */
687 int pat_table[PAT_INDEX_SIZE];
692 /* Bail if this CPU doesn't implement PAT. */
693 if ((cpu_feature & CPUID_PAT) == 0)
696 /* Set default PAT index table. */
697 for (i = 0; i < PAT_INDEX_SIZE; i++)
699 pat_table[PAT_WRITE_BACK] = 0;
700 pat_table[PAT_WRITE_THROUGH] = 1;
701 pat_table[PAT_UNCACHEABLE] = 3;
702 pat_table[PAT_WRITE_COMBINING] = 3;
703 pat_table[PAT_WRITE_PROTECTED] = 3;
704 pat_table[PAT_UNCACHED] = 3;
706 /* Initialize default PAT entries. */
707 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
708 PAT_VALUE(1, PAT_WRITE_THROUGH) |
709 PAT_VALUE(2, PAT_UNCACHED) |
710 PAT_VALUE(3, PAT_UNCACHEABLE) |
711 PAT_VALUE(4, PAT_WRITE_BACK) |
712 PAT_VALUE(5, PAT_WRITE_THROUGH) |
713 PAT_VALUE(6, PAT_UNCACHED) |
714 PAT_VALUE(7, PAT_UNCACHEABLE);
718 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
719 * Program 5 and 6 as WP and WC.
720 * Leave 4 and 7 as WB and UC.
722 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
723 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
724 PAT_VALUE(6, PAT_WRITE_COMBINING);
725 pat_table[PAT_UNCACHED] = 2;
726 pat_table[PAT_WRITE_PROTECTED] = 5;
727 pat_table[PAT_WRITE_COMBINING] = 6;
730 * Just replace PAT Index 2 with WC instead of UC-.
732 pat_msr &= ~PAT_MASK(2);
733 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
734 pat_table[PAT_WRITE_COMBINING] = 2;
739 load_cr4(cr4 & ~CR4_PGE);
741 /* Disable caches (CD = 1, NW = 0). */
743 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
745 /* Flushes caches and TLBs. */
749 /* Update PAT and index table. */
750 wrmsr(MSR_PAT, pat_msr);
751 for (i = 0; i < PAT_INDEX_SIZE; i++)
752 pat_index[i] = pat_table[i];
754 /* Flush caches and TLBs again. */
758 /* Restore caches and PGE. */
764 * Initialize a vm_page's machine-dependent fields.
767 pmap_page_init(vm_page_t m)
770 TAILQ_INIT(&m->md.pv_list);
771 m->md.pat_mode = PAT_WRITE_BACK;
775 * Initialize the pmap module.
776 * Called by vm_init, to initialize any structures that the pmap
777 * system needs to map virtual memory.
787 * Initialize the vm page array entries for the kernel pmap's
790 for (i = 0; i < NKPT; i++) {
791 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
792 KASSERT(mpte >= vm_page_array &&
793 mpte < &vm_page_array[vm_page_array_size],
794 ("pmap_init: page table page is out of range"));
795 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
796 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
800 * If the kernel is running in a virtual machine on an AMD Family 10h
801 * processor, then it must assume that MCA is enabled by the virtual
804 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
805 CPUID_TO_FAMILY(cpu_id) == 0x10)
806 workaround_erratum383 = 1;
809 * Are large page mappings enabled?
811 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
813 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
814 ("pmap_init: can't assign to pagesizes[1]"));
815 pagesizes[1] = NBPDR;
819 * Initialize the pv chunk list mutex.
821 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
824 * Initialize the pool of pv list locks.
826 for (i = 0; i < NPV_LIST_LOCKS; i++)
827 rw_init(&pv_list_locks[i], "pmap pv list");
830 * Calculate the size of the pv head table for superpages.
832 for (i = 0; phys_avail[i + 1]; i += 2);
833 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
836 * Allocate memory for the pv head table for superpages.
838 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
840 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
841 for (i = 0; i < pv_npg; i++)
842 TAILQ_INIT(&pv_table[i].pv_list);
845 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
846 "2MB page mapping counters");
848 static u_long pmap_pde_demotions;
849 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
850 &pmap_pde_demotions, 0, "2MB page demotions");
852 static u_long pmap_pde_mappings;
853 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
854 &pmap_pde_mappings, 0, "2MB page mappings");
856 static u_long pmap_pde_p_failures;
857 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
858 &pmap_pde_p_failures, 0, "2MB page promotion failures");
860 static u_long pmap_pde_promotions;
861 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
862 &pmap_pde_promotions, 0, "2MB page promotions");
864 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
865 "1GB page mapping counters");
867 static u_long pmap_pdpe_demotions;
868 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
869 &pmap_pdpe_demotions, 0, "1GB page demotions");
871 /***************************************************
872 * Low level helper routines.....
873 ***************************************************/
876 * Determine the appropriate bits to set in a PTE or PDE for a specified
880 pmap_cache_bits(int mode, boolean_t is_pde)
882 int cache_bits, pat_flag, pat_idx;
884 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
885 panic("Unknown caching mode %d\n", mode);
887 /* The PAT bit is different for PTE's and PDE's. */
888 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
890 /* Map the caching mode to a PAT index. */
891 pat_idx = pat_index[mode];
893 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
896 cache_bits |= pat_flag;
898 cache_bits |= PG_NC_PCD;
900 cache_bits |= PG_NC_PWT;
905 * After changing the page size for the specified virtual address in the page
906 * table, flush the corresponding entries from the processor's TLB. Only the
907 * calling processor's TLB is affected.
909 * The calling thread must be pinned to a processor.
912 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
916 if ((newpde & PG_PS) == 0)
917 /* Demotion: flush a specific 2MB page mapping. */
919 else if ((newpde & PG_G) == 0)
921 * Promotion: flush every 4KB page mapping from the TLB
922 * because there are too many to flush individually.
927 * Promotion: flush every 4KB page mapping from the TLB,
928 * including any global (PG_G) mappings.
931 load_cr4(cr4 & ~CR4_PGE);
933 * Although preemption at this point could be detrimental to
934 * performance, it would not lead to an error. PG_G is simply
935 * ignored if CR4.PGE is clear. Moreover, in case this block
936 * is re-entered, the load_cr4() either above or below will
937 * modify CR4.PGE flushing the TLB.
939 load_cr4(cr4 | CR4_PGE);
944 * For SMP, these functions have to use the IPI mechanism for coherence.
946 * N.B.: Before calling any of the following TLB invalidation functions,
947 * the calling processor must ensure that all stores updating a non-
948 * kernel page table are globally performed. Otherwise, another
949 * processor could cache an old, pre-update entry without being
950 * invalidated. This can happen one of two ways: (1) The pmap becomes
951 * active on another processor after its pm_active field is checked by
952 * one of the following functions but before a store updating the page
953 * table is globally performed. (2) The pmap becomes active on another
954 * processor before its pm_active field is checked but due to
955 * speculative loads one of the following functions stills reads the
956 * pmap as inactive on the other processor.
958 * The kernel page table is exempt because its pm_active field is
959 * immutable. The kernel page table is always active on every
963 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
969 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
973 cpuid = PCPU_GET(cpuid);
974 other_cpus = all_cpus;
975 CPU_CLR(cpuid, &other_cpus);
976 if (CPU_ISSET(cpuid, &pmap->pm_active))
978 CPU_AND(&other_cpus, &pmap->pm_active);
979 if (!CPU_EMPTY(&other_cpus))
980 smp_masked_invlpg(other_cpus, va);
986 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
993 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
994 for (addr = sva; addr < eva; addr += PAGE_SIZE)
996 smp_invlpg_range(sva, eva);
998 cpuid = PCPU_GET(cpuid);
999 other_cpus = all_cpus;
1000 CPU_CLR(cpuid, &other_cpus);
1001 if (CPU_ISSET(cpuid, &pmap->pm_active))
1002 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1004 CPU_AND(&other_cpus, &pmap->pm_active);
1005 if (!CPU_EMPTY(&other_cpus))
1006 smp_masked_invlpg_range(other_cpus, sva, eva);
1012 pmap_invalidate_all(pmap_t pmap)
1014 cpuset_t other_cpus;
1018 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1022 cpuid = PCPU_GET(cpuid);
1023 other_cpus = all_cpus;
1024 CPU_CLR(cpuid, &other_cpus);
1025 if (CPU_ISSET(cpuid, &pmap->pm_active))
1027 CPU_AND(&other_cpus, &pmap->pm_active);
1028 if (!CPU_EMPTY(&other_cpus))
1029 smp_masked_invltlb(other_cpus);
1035 pmap_invalidate_cache(void)
1045 cpuset_t invalidate; /* processors that invalidate their TLB */
1049 u_int store; /* processor that updates the PDE */
1053 pmap_update_pde_action(void *arg)
1055 struct pde_action *act = arg;
1057 if (act->store == PCPU_GET(cpuid))
1058 pde_store(act->pde, act->newpde);
1062 pmap_update_pde_teardown(void *arg)
1064 struct pde_action *act = arg;
1066 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1067 pmap_update_pde_invalidate(act->va, act->newpde);
1071 * Change the page size for the specified virtual address in a way that
1072 * prevents any possibility of the TLB ever having two entries that map the
1073 * same virtual address using different page sizes. This is the recommended
1074 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1075 * machine check exception for a TLB state that is improperly diagnosed as a
1079 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1081 struct pde_action act;
1082 cpuset_t active, other_cpus;
1086 cpuid = PCPU_GET(cpuid);
1087 other_cpus = all_cpus;
1088 CPU_CLR(cpuid, &other_cpus);
1089 if (pmap == kernel_pmap)
1092 active = pmap->pm_active;
1093 if (CPU_OVERLAP(&active, &other_cpus)) {
1095 act.invalidate = active;
1098 act.newpde = newpde;
1099 CPU_SET(cpuid, &active);
1100 smp_rendezvous_cpus(active,
1101 smp_no_rendevous_barrier, pmap_update_pde_action,
1102 pmap_update_pde_teardown, &act);
1104 pde_store(pde, newpde);
1105 if (CPU_ISSET(cpuid, &active))
1106 pmap_update_pde_invalidate(va, newpde);
1112 * Normal, non-SMP, invalidation functions.
1113 * We inline these within pmap.c for speed.
1116 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1119 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1124 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1128 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1129 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1134 pmap_invalidate_all(pmap_t pmap)
1137 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1142 pmap_invalidate_cache(void)
1149 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1152 pde_store(pde, newpde);
1153 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1154 pmap_update_pde_invalidate(va, newpde);
1158 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1161 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1164 KASSERT((sva & PAGE_MASK) == 0,
1165 ("pmap_invalidate_cache_range: sva not page-aligned"));
1166 KASSERT((eva & PAGE_MASK) == 0,
1167 ("pmap_invalidate_cache_range: eva not page-aligned"));
1169 if (cpu_feature & CPUID_SS)
1170 ; /* If "Self Snoop" is supported, do nothing. */
1171 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1172 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1175 * XXX: Some CPUs fault, hang, or trash the local APIC
1176 * registers if we use CLFLUSH on the local APIC
1177 * range. The local APIC is always uncached, so we
1178 * don't need to flush for that range anyway.
1180 if (pmap_kextract(sva) == lapic_paddr)
1184 * Otherwise, do per-cache line flush. Use the mfence
1185 * instruction to insure that previous stores are
1186 * included in the write-back. The processor
1187 * propagates flush to other processors in the cache
1191 for (; sva < eva; sva += cpu_clflush_line_size)
1197 * No targeted cache flush methods are supported by CPU,
1198 * or the supplied range is bigger than 2MB.
1199 * Globally invalidate cache.
1201 pmap_invalidate_cache();
1206 * Remove the specified set of pages from the data and instruction caches.
1208 * In contrast to pmap_invalidate_cache_range(), this function does not
1209 * rely on the CPU's self-snoop feature, because it is intended for use
1210 * when moving pages into a different cache domain.
1213 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1215 vm_offset_t daddr, eva;
1218 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1219 (cpu_feature & CPUID_CLFSH) == 0)
1220 pmap_invalidate_cache();
1223 for (i = 0; i < count; i++) {
1224 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1225 eva = daddr + PAGE_SIZE;
1226 for (; daddr < eva; daddr += cpu_clflush_line_size)
1234 * Routine: pmap_extract
1236 * Extract the physical page address associated
1237 * with the given map/virtual_address pair.
1240 pmap_extract(pmap_t pmap, vm_offset_t va)
1249 pdpe = pmap_pdpe(pmap, va);
1250 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1251 if ((*pdpe & PG_PS) != 0)
1252 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1254 pde = pmap_pdpe_to_pde(pdpe, va);
1255 if ((*pde & PG_V) != 0) {
1256 if ((*pde & PG_PS) != 0) {
1257 pa = (*pde & PG_PS_FRAME) |
1260 pte = pmap_pde_to_pte(pde, va);
1261 pa = (*pte & PG_FRAME) |
1272 * Routine: pmap_extract_and_hold
1274 * Atomically extract and hold the physical page
1275 * with the given pmap and virtual address pair
1276 * if that mapping permits the given protection.
1279 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1281 pd_entry_t pde, *pdep;
1290 pdep = pmap_pde(pmap, va);
1291 if (pdep != NULL && (pde = *pdep)) {
1293 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1294 if (vm_page_pa_tryrelock(pmap, (pde &
1295 PG_PS_FRAME) | (va & PDRMASK), &pa))
1297 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1302 pte = *pmap_pde_to_pte(pdep, va);
1304 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1305 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1308 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1319 pmap_kextract(vm_offset_t va)
1324 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1325 pa = DMAP_TO_PHYS(va);
1329 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1332 * Beware of a concurrent promotion that changes the
1333 * PDE at this point! For example, vtopte() must not
1334 * be used to access the PTE because it would use the
1335 * new PDE. It is, however, safe to use the old PDE
1336 * because the page table page is preserved by the
1339 pa = *pmap_pde_to_pte(&pde, va);
1340 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1346 /***************************************************
1347 * Low level mapping routines.....
1348 ***************************************************/
1351 * Add a wired page to the kva.
1352 * Note: not SMP coherent.
1355 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1360 pte_store(pte, pa | PG_RW | PG_V | PG_G);
1363 static __inline void
1364 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1369 pte_store(pte, pa | PG_RW | PG_V | PG_G | pmap_cache_bits(mode, 0));
1373 * Remove a page from the kernel pagetables.
1374 * Note: not SMP coherent.
1377 pmap_kremove(vm_offset_t va)
1386 * Used to map a range of physical addresses into kernel
1387 * virtual address space.
1389 * The value passed in '*virt' is a suggested virtual address for
1390 * the mapping. Architectures which can support a direct-mapped
1391 * physical to virtual region can return the appropriate address
1392 * within that region, leaving '*virt' unchanged. Other
1393 * architectures should map the pages starting at '*virt' and
1394 * update '*virt' with the first usable address after the mapped
1398 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1400 return PHYS_TO_DMAP(start);
1405 * Add a list of wired pages to the kva
1406 * this routine is only used for temporary
1407 * kernel mappings that do not need to have
1408 * page modification or references recorded.
1409 * Note that old mappings are simply written
1410 * over. The page *must* be wired.
1411 * Note: SMP coherent. Uses a ranged shootdown IPI.
1414 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1416 pt_entry_t *endpte, oldpte, pa, *pte;
1421 endpte = pte + count;
1422 while (pte < endpte) {
1424 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1425 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1427 pte_store(pte, pa | PG_G | PG_RW | PG_V);
1431 if (__predict_false((oldpte & PG_V) != 0))
1432 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1437 * This routine tears out page mappings from the
1438 * kernel -- it is meant only for temporary mappings.
1439 * Note: SMP coherent. Uses a ranged shootdown IPI.
1442 pmap_qremove(vm_offset_t sva, int count)
1447 while (count-- > 0) {
1448 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
1452 pmap_invalidate_range(kernel_pmap, sva, va);
1455 /***************************************************
1456 * Page table page management routines.....
1457 ***************************************************/
1458 static __inline void
1459 pmap_free_zero_pages(vm_page_t free)
1463 while (free != NULL) {
1466 /* Preserve the page's PG_ZERO setting. */
1467 vm_page_free_toq(m);
1472 * Schedule the specified unused page table page to be freed. Specifically,
1473 * add the page to the specified list of pages that will be released to the
1474 * physical memory manager after the TLB has been updated.
1476 static __inline void
1477 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1481 m->flags |= PG_ZERO;
1483 m->flags &= ~PG_ZERO;
1489 * Inserts the specified page table page into the specified pmap's collection
1490 * of idle page table pages. Each of a pmap's page table pages is responsible
1491 * for mapping a distinct range of virtual addresses. The pmap's collection is
1492 * ordered by this virtual address range.
1495 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1500 root = pmap->pm_root;
1505 root = vm_page_splay(mpte->pindex, root);
1506 if (mpte->pindex < root->pindex) {
1507 mpte->left = root->left;
1510 } else if (mpte->pindex == root->pindex)
1511 panic("pmap_insert_pt_page: pindex already inserted");
1513 mpte->right = root->right;
1518 pmap->pm_root = mpte;
1522 * Looks for a page table page mapping the specified virtual address in the
1523 * specified pmap's collection of idle page table pages. Returns NULL if there
1524 * is no page table page corresponding to the specified virtual address.
1527 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1530 vm_pindex_t pindex = pmap_pde_pindex(va);
1532 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1533 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1534 mpte = vm_page_splay(pindex, mpte);
1535 if ((pmap->pm_root = mpte)->pindex != pindex)
1542 * Removes the specified page table page from the specified pmap's collection
1543 * of idle page table pages. The specified page table page must be a member of
1544 * the pmap's collection.
1547 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1551 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1552 if (mpte != pmap->pm_root) {
1553 root = vm_page_splay(mpte->pindex, pmap->pm_root);
1554 KASSERT(mpte == root,
1555 ("pmap_remove_pt_page: mpte %p is missing from pmap %p",
1558 if (mpte->left == NULL)
1561 root = vm_page_splay(mpte->pindex, mpte->left);
1562 root->right = mpte->right;
1564 pmap->pm_root = root;
1568 * Decrements a page table page's wire count, which is used to record the
1569 * number of valid page table entries within the page. If the wire count
1570 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1571 * page table page was unmapped and FALSE otherwise.
1573 static inline boolean_t
1574 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t *free)
1578 if (m->wire_count == 0) {
1579 _pmap_unwire_ptp(pmap, va, m, free);
1586 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t *free)
1589 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1591 * unmap the page table page
1593 if (m->pindex >= (NUPDE + NUPDPE)) {
1596 pml4 = pmap_pml4e(pmap, va);
1598 } else if (m->pindex >= NUPDE) {
1601 pdp = pmap_pdpe(pmap, va);
1606 pd = pmap_pde(pmap, va);
1609 pmap_resident_count_dec(pmap, 1);
1610 if (m->pindex < NUPDE) {
1611 /* We just released a PT, unhold the matching PD */
1614 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
1615 pmap_unwire_ptp(pmap, va, pdpg, free);
1617 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
1618 /* We just released a PD, unhold the matching PDP */
1621 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
1622 pmap_unwire_ptp(pmap, va, pdppg, free);
1626 * This is a release store so that the ordinary store unmapping
1627 * the page table page is globally performed before TLB shoot-
1630 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1633 * Put page on a list so that it is released after
1634 * *ALL* TLB shootdown is done
1636 pmap_add_delayed_free_list(m, free, TRUE);
1640 * After removing a page table entry, this routine is used to
1641 * conditionally free the page, and manage the hold/wire counts.
1644 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, vm_page_t *free)
1648 if (va >= VM_MAXUSER_ADDRESS)
1650 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1651 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1652 return (pmap_unwire_ptp(pmap, va, mpte, free));
1656 pmap_pinit0(pmap_t pmap)
1659 PMAP_LOCK_INIT(pmap);
1660 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1661 pmap->pm_root = NULL;
1662 CPU_ZERO(&pmap->pm_active);
1663 PCPU_SET(curpmap, pmap);
1664 TAILQ_INIT(&pmap->pm_pvchunk);
1665 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1669 * Initialize a preallocated and zeroed pmap structure,
1670 * such as one in a vmspace structure.
1673 pmap_pinit(pmap_t pmap)
1678 PMAP_LOCK_INIT(pmap);
1681 * allocate the page directory page
1683 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1684 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1687 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
1689 if ((pml4pg->flags & PG_ZERO) == 0)
1690 pagezero(pmap->pm_pml4);
1692 /* Wire in kernel global address entries. */
1693 pmap->pm_pml4[KPML4I] = KPDPphys | PG_RW | PG_V | PG_U;
1694 for (i = 0; i < NDMPML4E; i++) {
1695 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + (i << PAGE_SHIFT)) |
1696 PG_RW | PG_V | PG_U;
1699 /* install self-referential address mapping entry(s) */
1700 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | PG_V | PG_RW | PG_A | PG_M;
1702 pmap->pm_root = NULL;
1703 CPU_ZERO(&pmap->pm_active);
1704 TAILQ_INIT(&pmap->pm_pvchunk);
1705 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1711 * This routine is called if the desired page table page does not exist.
1713 * If page table page allocation fails, this routine may sleep before
1714 * returning NULL. It sleeps only if a lock pointer was given.
1716 * Note: If a page allocation fails at page table level two or three,
1717 * one or two pages may be held during the wait, only to be released
1718 * afterwards. This conservative approach is easily argued to avoid
1722 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1724 vm_page_t m, pdppg, pdpg;
1726 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1729 * Allocate a page table page.
1731 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1732 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1733 if (lockp != NULL) {
1734 RELEASE_PV_LIST_LOCK(lockp);
1736 rw_runlock(&pvh_global_lock);
1738 rw_rlock(&pvh_global_lock);
1743 * Indicate the need to retry. While waiting, the page table
1744 * page may have been allocated.
1748 if ((m->flags & PG_ZERO) == 0)
1752 * Map the pagetable page into the process address space, if
1753 * it isn't already there.
1756 if (ptepindex >= (NUPDE + NUPDPE)) {
1758 vm_pindex_t pml4index;
1760 /* Wire up a new PDPE page */
1761 pml4index = ptepindex - (NUPDE + NUPDPE);
1762 pml4 = &pmap->pm_pml4[pml4index];
1763 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1765 } else if (ptepindex >= NUPDE) {
1766 vm_pindex_t pml4index;
1767 vm_pindex_t pdpindex;
1771 /* Wire up a new PDE page */
1772 pdpindex = ptepindex - NUPDE;
1773 pml4index = pdpindex >> NPML4EPGSHIFT;
1775 pml4 = &pmap->pm_pml4[pml4index];
1776 if ((*pml4 & PG_V) == 0) {
1777 /* Have to allocate a new pdp, recurse */
1778 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
1781 atomic_subtract_int(&cnt.v_wire_count, 1);
1782 vm_page_free_zero(m);
1786 /* Add reference to pdp page */
1787 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
1788 pdppg->wire_count++;
1790 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1792 /* Now find the pdp page */
1793 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1794 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1797 vm_pindex_t pml4index;
1798 vm_pindex_t pdpindex;
1803 /* Wire up a new PTE page */
1804 pdpindex = ptepindex >> NPDPEPGSHIFT;
1805 pml4index = pdpindex >> NPML4EPGSHIFT;
1807 /* First, find the pdp and check that its valid. */
1808 pml4 = &pmap->pm_pml4[pml4index];
1809 if ((*pml4 & PG_V) == 0) {
1810 /* Have to allocate a new pd, recurse */
1811 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1814 atomic_subtract_int(&cnt.v_wire_count, 1);
1815 vm_page_free_zero(m);
1818 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1819 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1821 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1822 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1823 if ((*pdp & PG_V) == 0) {
1824 /* Have to allocate a new pd, recurse */
1825 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1828 atomic_subtract_int(&cnt.v_wire_count,
1830 vm_page_free_zero(m);
1834 /* Add reference to the pd page */
1835 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
1839 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
1841 /* Now we know where the page directory page is */
1842 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
1843 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1846 pmap_resident_count_inc(pmap, 1);
1852 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1854 vm_pindex_t pdpindex, ptepindex;
1859 pdpe = pmap_pdpe(pmap, va);
1860 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1861 /* Add a reference to the pd page. */
1862 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
1865 /* Allocate a pd page. */
1866 ptepindex = pmap_pde_pindex(va);
1867 pdpindex = ptepindex >> NPDPEPGSHIFT;
1868 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
1869 if (pdpg == NULL && lockp != NULL)
1876 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1878 vm_pindex_t ptepindex;
1883 * Calculate pagetable page index
1885 ptepindex = pmap_pde_pindex(va);
1888 * Get the page directory entry
1890 pd = pmap_pde(pmap, va);
1893 * This supports switching from a 2MB page to a
1896 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
1897 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
1899 * Invalidation of the 2MB page mapping may have caused
1900 * the deallocation of the underlying PD page.
1907 * If the page table page is mapped, we just increment the
1908 * hold count, and activate it.
1910 if (pd != NULL && (*pd & PG_V) != 0) {
1911 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
1915 * Here if the pte page isn't mapped, or if it has been
1918 m = _pmap_allocpte(pmap, ptepindex, lockp);
1919 if (m == NULL && lockp != NULL)
1926 /***************************************************
1927 * Pmap allocation/deallocation routines.
1928 ***************************************************/
1931 * Release any resources held by the given physical map.
1932 * Called when a pmap initialized by pmap_pinit is being released.
1933 * Should only be called if the map contains no valid mappings.
1936 pmap_release(pmap_t pmap)
1941 KASSERT(pmap->pm_stats.resident_count == 0,
1942 ("pmap_release: pmap resident count %ld != 0",
1943 pmap->pm_stats.resident_count));
1944 KASSERT(pmap->pm_root == NULL,
1945 ("pmap_release: pmap has reserved page table page(s)"));
1947 m = PHYS_TO_VM_PAGE(pmap->pm_pml4[PML4PML4I] & PG_FRAME);
1949 pmap->pm_pml4[KPML4I] = 0; /* KVA */
1950 for (i = 0; i < NDMPML4E; i++) /* Direct Map */
1951 pmap->pm_pml4[DMPML4I + i] = 0;
1952 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
1955 atomic_subtract_int(&cnt.v_wire_count, 1);
1956 vm_page_free_zero(m);
1957 PMAP_LOCK_DESTROY(pmap);
1961 kvm_size(SYSCTL_HANDLER_ARGS)
1963 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1965 return sysctl_handle_long(oidp, &ksize, 0, req);
1967 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1968 0, 0, kvm_size, "LU", "Size of KVM");
1971 kvm_free(SYSCTL_HANDLER_ARGS)
1973 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1975 return sysctl_handle_long(oidp, &kfree, 0, req);
1977 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1978 0, 0, kvm_free, "LU", "Amount of KVM free");
1981 * grow the number of kernel page table entries, if needed
1984 pmap_growkernel(vm_offset_t addr)
1988 pd_entry_t *pde, newpdir;
1991 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1994 * Return if "addr" is within the range of kernel page table pages
1995 * that were preallocated during pmap bootstrap. Moreover, leave
1996 * "kernel_vm_end" and the kernel page table as they were.
1998 * The correctness of this action is based on the following
1999 * argument: vm_map_findspace() allocates contiguous ranges of the
2000 * kernel virtual address space. It calls this function if a range
2001 * ends after "kernel_vm_end". If the kernel is mapped between
2002 * "kernel_vm_end" and "addr", then the range cannot begin at
2003 * "kernel_vm_end". In fact, its beginning address cannot be less
2004 * than the kernel. Thus, there is no immediate need to allocate
2005 * any new kernel page table pages between "kernel_vm_end" and
2008 if (KERNBASE < addr && addr <= KERNBASE + NKPT * NBPDR)
2011 addr = roundup2(addr, NBPDR);
2012 if (addr - 1 >= kernel_map->max_offset)
2013 addr = kernel_map->max_offset;
2014 while (kernel_vm_end < addr) {
2015 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2016 if ((*pdpe & PG_V) == 0) {
2017 /* We need a new PDP entry */
2018 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2019 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2020 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2022 panic("pmap_growkernel: no memory to grow kernel");
2023 if ((nkpg->flags & PG_ZERO) == 0)
2024 pmap_zero_page(nkpg);
2025 paddr = VM_PAGE_TO_PHYS(nkpg);
2026 *pdpe = (pdp_entry_t)
2027 (paddr | PG_V | PG_RW | PG_A | PG_M);
2028 continue; /* try again */
2030 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2031 if ((*pde & PG_V) != 0) {
2032 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2033 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2034 kernel_vm_end = kernel_map->max_offset;
2040 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2041 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2044 panic("pmap_growkernel: no memory to grow kernel");
2045 if ((nkpg->flags & PG_ZERO) == 0)
2046 pmap_zero_page(nkpg);
2047 paddr = VM_PAGE_TO_PHYS(nkpg);
2048 newpdir = (pd_entry_t) (paddr | PG_V | PG_RW | PG_A | PG_M);
2049 pde_store(pde, newpdir);
2051 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2052 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2053 kernel_vm_end = kernel_map->max_offset;
2060 /***************************************************
2061 * page management routines.
2062 ***************************************************/
2064 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2065 CTASSERT(_NPCM == 3);
2066 CTASSERT(_NPCPV == 168);
2068 static __inline struct pv_chunk *
2069 pv_to_chunk(pv_entry_t pv)
2072 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2075 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2077 #define PC_FREE0 0xfffffffffffffffful
2078 #define PC_FREE1 0xfffffffffffffffful
2079 #define PC_FREE2 0x000000fffffffffful
2081 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2084 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2086 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2087 "Current number of pv entry chunks");
2088 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2089 "Current number of pv entry chunks allocated");
2090 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2091 "Current number of pv entry chunks frees");
2092 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2093 "Number of times tried to get a chunk page but failed.");
2095 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2096 static int pv_entry_spare;
2098 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2099 "Current number of pv entry frees");
2100 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2101 "Current number of pv entry allocs");
2102 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2103 "Current number of pv entries");
2104 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2105 "Current number of spare pv entries");
2109 * We are in a serious low memory condition. Resort to
2110 * drastic measures to free some pages so we can allocate
2111 * another pv entry chunk.
2113 * Returns NULL if PV entries were reclaimed from the specified pmap.
2115 * We do not, however, unmap 2mpages because subsequent accesses will
2116 * allocate per-page pv entries until repromotion occurs, thereby
2117 * exacerbating the shortage of free pv entries.
2120 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2122 struct pch new_tail;
2123 struct pv_chunk *pc;
2124 struct md_page *pvh;
2127 pt_entry_t *pte, tpte;
2130 vm_page_t free, m, m_pc;
2132 int bit, field, freed;
2134 rw_assert(&pvh_global_lock, RA_LOCKED);
2135 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2136 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2139 TAILQ_INIT(&new_tail);
2140 mtx_lock(&pv_chunks_mutex);
2141 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && free == NULL) {
2142 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2143 mtx_unlock(&pv_chunks_mutex);
2144 if (pmap != pc->pc_pmap) {
2146 pmap_invalidate_all(pmap);
2147 if (pmap != locked_pmap)
2151 /* Avoid deadlock and lock recursion. */
2152 if (pmap > locked_pmap) {
2153 RELEASE_PV_LIST_LOCK(lockp);
2155 } else if (pmap != locked_pmap &&
2156 !PMAP_TRYLOCK(pmap)) {
2158 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2159 mtx_lock(&pv_chunks_mutex);
2165 * Destroy every non-wired, 4 KB page mapping in the chunk.
2168 for (field = 0; field < _NPCM; field++) {
2169 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2170 inuse != 0; inuse &= ~(1UL << bit)) {
2172 pv = &pc->pc_pventry[field * 64 + bit];
2174 pde = pmap_pde(pmap, va);
2175 if ((*pde & PG_PS) != 0)
2177 pte = pmap_pde_to_pte(pde, va);
2178 if ((*pte & PG_W) != 0)
2180 tpte = pte_load_clear(pte);
2181 if ((tpte & PG_G) != 0)
2182 pmap_invalidate_page(pmap, va);
2183 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2184 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2186 if ((tpte & PG_A) != 0)
2187 vm_page_aflag_set(m, PGA_REFERENCED);
2188 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2189 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2190 if (TAILQ_EMPTY(&m->md.pv_list) &&
2191 (m->flags & PG_FICTITIOUS) == 0) {
2192 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2193 if (TAILQ_EMPTY(&pvh->pv_list)) {
2194 vm_page_aflag_clear(m,
2198 pc->pc_map[field] |= 1UL << bit;
2199 pmap_unuse_pt(pmap, va, *pde, &free);
2204 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2205 mtx_lock(&pv_chunks_mutex);
2208 /* Every freed mapping is for a 4 KB page. */
2209 pmap_resident_count_dec(pmap, freed);
2210 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2211 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2212 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2213 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2214 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2215 pc->pc_map[2] == PC_FREE2) {
2216 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2217 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2218 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2219 /* Entire chunk is free; return it. */
2220 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2221 dump_drop_page(m_pc->phys_addr);
2222 mtx_lock(&pv_chunks_mutex);
2225 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2226 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2227 mtx_lock(&pv_chunks_mutex);
2228 /* One freed pv entry in locked_pmap is sufficient. */
2229 if (pmap == locked_pmap)
2232 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2233 mtx_unlock(&pv_chunks_mutex);
2235 pmap_invalidate_all(pmap);
2236 if (pmap != locked_pmap)
2239 if (m_pc == NULL && free != NULL) {
2242 /* Recycle a freed page table page. */
2243 m_pc->wire_count = 1;
2244 atomic_add_int(&cnt.v_wire_count, 1);
2246 pmap_free_zero_pages(free);
2251 * free the pv_entry back to the free list
2254 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2256 struct pv_chunk *pc;
2257 int idx, field, bit;
2259 rw_assert(&pvh_global_lock, RA_LOCKED);
2260 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2261 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2262 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2263 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2264 pc = pv_to_chunk(pv);
2265 idx = pv - &pc->pc_pventry[0];
2268 pc->pc_map[field] |= 1ul << bit;
2269 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2270 pc->pc_map[2] != PC_FREE2) {
2271 /* 98% of the time, pc is already at the head of the list. */
2272 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2273 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2274 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2278 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2283 free_pv_chunk(struct pv_chunk *pc)
2287 mtx_lock(&pv_chunks_mutex);
2288 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2289 mtx_unlock(&pv_chunks_mutex);
2290 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2291 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2292 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2293 /* entire chunk is free, return it */
2294 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2295 dump_drop_page(m->phys_addr);
2296 vm_page_unwire(m, 0);
2301 * Returns a new PV entry, allocating a new PV chunk from the system when
2302 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2303 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2306 * The given PV list lock may be released.
2309 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2313 struct pv_chunk *pc;
2316 rw_assert(&pvh_global_lock, RA_LOCKED);
2317 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2318 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2320 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2322 for (field = 0; field < _NPCM; field++) {
2323 if (pc->pc_map[field]) {
2324 bit = bsfq(pc->pc_map[field]);
2328 if (field < _NPCM) {
2329 pv = &pc->pc_pventry[field * 64 + bit];
2330 pc->pc_map[field] &= ~(1ul << bit);
2331 /* If this was the last item, move it to tail */
2332 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2333 pc->pc_map[2] == 0) {
2334 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2335 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2338 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2339 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2343 /* No free items, allocate another chunk */
2344 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2347 if (lockp == NULL) {
2348 PV_STAT(pc_chunk_tryfail++);
2351 m = reclaim_pv_chunk(pmap, lockp);
2355 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2356 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2357 dump_add_page(m->phys_addr);
2358 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2360 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2361 pc->pc_map[1] = PC_FREE1;
2362 pc->pc_map[2] = PC_FREE2;
2363 mtx_lock(&pv_chunks_mutex);
2364 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2365 mtx_unlock(&pv_chunks_mutex);
2366 pv = &pc->pc_pventry[0];
2367 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2368 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2369 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2374 * Returns the number of one bits within the given PV chunk map element.
2377 popcnt_pc_map_elem(uint64_t elem)
2382 * This simple method of counting the one bits performs well because
2383 * the given element typically contains more zero bits than one bits.
2386 for (; elem != 0; elem &= elem - 1)
2392 * Ensure that the number of spare PV entries in the specified pmap meets or
2393 * exceeds the given count, "needed".
2395 * The given PV list lock may be released.
2398 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2400 struct pch new_tail;
2401 struct pv_chunk *pc;
2405 rw_assert(&pvh_global_lock, RA_LOCKED);
2406 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2407 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2410 * Newly allocated PV chunks must be stored in a private list until
2411 * the required number of PV chunks have been allocated. Otherwise,
2412 * reclaim_pv_chunk() could recycle one of these chunks. In
2413 * contrast, these chunks must be added to the pmap upon allocation.
2415 TAILQ_INIT(&new_tail);
2418 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2419 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
2420 free = popcnt_pc_map_elem(pc->pc_map[0]);
2421 free += popcnt_pc_map_elem(pc->pc_map[1]);
2422 free += popcnt_pc_map_elem(pc->pc_map[2]);
2424 free = popcntq(pc->pc_map[0]);
2425 free += popcntq(pc->pc_map[1]);
2426 free += popcntq(pc->pc_map[2]);
2431 if (avail >= needed)
2434 for (; avail < needed; avail += _NPCPV) {
2435 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2438 m = reclaim_pv_chunk(pmap, lockp);
2442 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2443 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2444 dump_add_page(m->phys_addr);
2445 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2447 pc->pc_map[0] = PC_FREE0;
2448 pc->pc_map[1] = PC_FREE1;
2449 pc->pc_map[2] = PC_FREE2;
2450 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2451 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2452 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2454 if (!TAILQ_EMPTY(&new_tail)) {
2455 mtx_lock(&pv_chunks_mutex);
2456 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2457 mtx_unlock(&pv_chunks_mutex);
2462 * First find and then remove the pv entry for the specified pmap and virtual
2463 * address from the specified pv list. Returns the pv entry if found and NULL
2464 * otherwise. This operation can be performed on pv lists for either 4KB or
2465 * 2MB page mappings.
2467 static __inline pv_entry_t
2468 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2472 rw_assert(&pvh_global_lock, RA_LOCKED);
2473 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2474 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2475 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2483 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2484 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2485 * entries for each of the 4KB page mappings.
2488 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2489 struct rwlock **lockp)
2491 struct md_page *pvh;
2492 struct pv_chunk *pc;
2494 vm_offset_t va_last;
2498 rw_assert(&pvh_global_lock, RA_LOCKED);
2499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2500 KASSERT((pa & PDRMASK) == 0,
2501 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
2502 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2505 * Transfer the 2mpage's pv entry for this mapping to the first
2506 * page's pv list. Once this transfer begins, the pv list lock
2507 * must not be released until the last pv entry is reinstantiated.
2509 pvh = pa_to_pvh(pa);
2510 va = trunc_2mpage(va);
2511 pv = pmap_pvh_remove(pvh, pmap, va);
2512 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2513 m = PHYS_TO_VM_PAGE(pa);
2514 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2515 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2516 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
2517 va_last = va + NBPDR - PAGE_SIZE;
2519 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2520 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2521 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
2522 for (field = 0; field < _NPCM; field++) {
2523 while (pc->pc_map[field]) {
2524 bit = bsfq(pc->pc_map[field]);
2525 pc->pc_map[field] &= ~(1ul << bit);
2526 pv = &pc->pc_pventry[field * 64 + bit];
2530 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2531 ("pmap_pv_demote_pde: page %p is not managed", m));
2532 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2537 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2538 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2541 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2542 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2543 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2545 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
2546 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
2550 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2551 * replace the many pv entries for the 4KB page mappings by a single pv entry
2552 * for the 2MB page mapping.
2555 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2556 struct rwlock **lockp)
2558 struct md_page *pvh;
2560 vm_offset_t va_last;
2563 rw_assert(&pvh_global_lock, RA_LOCKED);
2564 KASSERT((pa & PDRMASK) == 0,
2565 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
2566 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2569 * Transfer the first page's pv entry for this mapping to the 2mpage's
2570 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2571 * a transfer avoids the possibility that get_pv_entry() calls
2572 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2573 * mappings that is being promoted.
2575 m = PHYS_TO_VM_PAGE(pa);
2576 va = trunc_2mpage(va);
2577 pv = pmap_pvh_remove(&m->md, pmap, va);
2578 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2579 pvh = pa_to_pvh(pa);
2580 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2581 /* Free the remaining NPTEPG - 1 pv entries. */
2582 va_last = va + NBPDR - PAGE_SIZE;
2586 pmap_pvh_free(&m->md, pmap, va);
2587 } while (va < va_last);
2591 * First find and then destroy the pv entry for the specified pmap and virtual
2592 * address. This operation can be performed on pv lists for either 4KB or 2MB
2596 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2600 pv = pmap_pvh_remove(pvh, pmap, va);
2601 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2602 free_pv_entry(pmap, pv);
2606 * Conditionally create the PV entry for a 4KB page mapping if the required
2607 * memory can be allocated without resorting to reclamation.
2610 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2611 struct rwlock **lockp)
2615 rw_assert(&pvh_global_lock, RA_LOCKED);
2616 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2617 /* Pass NULL instead of the lock pointer to disable reclamation. */
2618 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2620 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2621 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2628 * Conditionally create the PV entry for a 2MB page mapping if the required
2629 * memory can be allocated without resorting to reclamation.
2632 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2633 struct rwlock **lockp)
2635 struct md_page *pvh;
2638 rw_assert(&pvh_global_lock, RA_LOCKED);
2639 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2640 /* Pass NULL instead of the lock pointer to disable reclamation. */
2641 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2643 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2644 pvh = pa_to_pvh(pa);
2645 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2652 * Fills a page table page with mappings to consecutive physical pages.
2655 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2659 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2661 newpte += PAGE_SIZE;
2666 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
2667 * mapping is invalidated.
2670 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2672 struct rwlock *lock;
2676 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
2683 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
2684 struct rwlock **lockp)
2686 pd_entry_t newpde, oldpde;
2687 pt_entry_t *firstpte, newpte;
2689 vm_page_t free, mpte;
2691 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2693 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2694 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2695 mpte = pmap_lookup_pt_page(pmap, va);
2697 pmap_remove_pt_page(pmap, mpte);
2699 KASSERT((oldpde & PG_W) == 0,
2700 ("pmap_demote_pde: page table page for a wired mapping"
2704 * Invalidate the 2MB page mapping and return "failure" if the
2705 * mapping was never accessed or the allocation of the new
2706 * page table page fails. If the 2MB page mapping belongs to
2707 * the direct map region of the kernel's address space, then
2708 * the page allocation request specifies the highest possible
2709 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
2710 * normal. Page table pages are preallocated for every other
2711 * part of the kernel address space, so the direct map region
2712 * is the only part of the kernel address space that must be
2715 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2716 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
2717 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
2718 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2720 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
2722 pmap_invalidate_page(pmap, trunc_2mpage(va));
2723 pmap_free_zero_pages(free);
2724 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
2725 " in pmap %p", va, pmap);
2728 if (va < VM_MAXUSER_ADDRESS)
2729 pmap_resident_count_inc(pmap, 1);
2731 mptepa = VM_PAGE_TO_PHYS(mpte);
2732 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
2733 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2734 KASSERT((oldpde & PG_A) != 0,
2735 ("pmap_demote_pde: oldpde is missing PG_A"));
2736 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2737 ("pmap_demote_pde: oldpde is missing PG_M"));
2738 newpte = oldpde & ~PG_PS;
2739 if ((newpte & PG_PDE_PAT) != 0)
2740 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2743 * If the page table page is new, initialize it.
2745 if (mpte->wire_count == 1) {
2746 mpte->wire_count = NPTEPG;
2747 pmap_fill_ptp(firstpte, newpte);
2749 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2750 ("pmap_demote_pde: firstpte and newpte map different physical"
2754 * If the mapping has changed attributes, update the page table
2757 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2758 pmap_fill_ptp(firstpte, newpte);
2761 * The spare PV entries must be reserved prior to demoting the
2762 * mapping, that is, prior to changing the PDE. Otherwise, the state
2763 * of the PDE and the PV lists will be inconsistent, which can result
2764 * in reclaim_pv_chunk() attempting to remove a PV entry from the
2765 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
2766 * PV entry for the 2MB page mapping that is being demoted.
2768 if ((oldpde & PG_MANAGED) != 0)
2769 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
2772 * Demote the mapping. This pmap is locked. The old PDE has
2773 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2774 * set. Thus, there is no danger of a race with another
2775 * processor changing the setting of PG_A and/or PG_M between
2776 * the read above and the store below.
2778 if (workaround_erratum383)
2779 pmap_update_pde(pmap, va, pde, newpde);
2781 pde_store(pde, newpde);
2784 * Invalidate a stale recursive mapping of the page table page.
2786 if (va >= VM_MAXUSER_ADDRESS)
2787 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2790 * Demote the PV entry.
2792 if ((oldpde & PG_MANAGED) != 0)
2793 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
2795 atomic_add_long(&pmap_pde_demotions, 1);
2796 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
2797 " in pmap %p", va, pmap);
2802 * pmap_remove_pde: do the things to unmap a superpage in a process
2805 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2806 vm_page_t *free, struct rwlock **lockp)
2808 struct md_page *pvh;
2810 vm_offset_t eva, va;
2813 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2814 KASSERT((sva & PDRMASK) == 0,
2815 ("pmap_remove_pde: sva is not 2mpage aligned"));
2816 oldpde = pte_load_clear(pdq);
2818 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2821 * Machines that don't support invlpg, also don't support
2825 pmap_invalidate_page(kernel_pmap, sva);
2826 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
2827 if (oldpde & PG_MANAGED) {
2828 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
2829 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2830 pmap_pvh_free(pvh, pmap, sva);
2832 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2833 va < eva; va += PAGE_SIZE, m++) {
2834 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2837 vm_page_aflag_set(m, PGA_REFERENCED);
2838 if (TAILQ_EMPTY(&m->md.pv_list) &&
2839 TAILQ_EMPTY(&pvh->pv_list))
2840 vm_page_aflag_clear(m, PGA_WRITEABLE);
2843 if (pmap == kernel_pmap) {
2844 if (!pmap_demote_pde_locked(pmap, pdq, sva, lockp))
2845 panic("pmap_remove_pde: failed demotion");
2847 mpte = pmap_lookup_pt_page(pmap, sva);
2849 pmap_remove_pt_page(pmap, mpte);
2850 pmap_resident_count_dec(pmap, 1);
2851 KASSERT(mpte->wire_count == NPTEPG,
2852 ("pmap_remove_pde: pte page wire count error"));
2853 mpte->wire_count = 0;
2854 pmap_add_delayed_free_list(mpte, free, FALSE);
2855 atomic_subtract_int(&cnt.v_wire_count, 1);
2858 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
2862 * pmap_remove_pte: do the things to unmap a page in a process
2865 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2866 pd_entry_t ptepde, vm_page_t *free, struct rwlock **lockp)
2868 struct md_page *pvh;
2872 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2873 oldpte = pte_load_clear(ptq);
2875 pmap->pm_stats.wired_count -= 1;
2876 pmap_resident_count_dec(pmap, 1);
2877 if (oldpte & PG_MANAGED) {
2878 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2879 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2882 vm_page_aflag_set(m, PGA_REFERENCED);
2883 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2884 pmap_pvh_free(&m->md, pmap, va);
2885 if (TAILQ_EMPTY(&m->md.pv_list) &&
2886 (m->flags & PG_FICTITIOUS) == 0) {
2887 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2888 if (TAILQ_EMPTY(&pvh->pv_list))
2889 vm_page_aflag_clear(m, PGA_WRITEABLE);
2892 return (pmap_unuse_pt(pmap, va, ptepde, free));
2896 * Remove a single page from a process address space
2899 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, vm_page_t *free)
2901 struct rwlock *lock;
2904 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2905 if ((*pde & PG_V) == 0)
2907 pte = pmap_pde_to_pte(pde, va);
2908 if ((*pte & PG_V) == 0)
2911 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
2914 pmap_invalidate_page(pmap, va);
2918 * Remove the given range of addresses from the specified map.
2920 * It is assumed that the start and end are properly
2921 * rounded to the page size.
2924 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2926 struct rwlock *lock;
2927 vm_offset_t va, va_next;
2928 pml4_entry_t *pml4e;
2930 pd_entry_t ptpaddr, *pde;
2932 vm_page_t free = NULL;
2936 * Perform an unsynchronized read. This is, however, safe.
2938 if (pmap->pm_stats.resident_count == 0)
2943 rw_rlock(&pvh_global_lock);
2947 * special handling of removing one page. a very
2948 * common operation and easy to short circuit some
2951 if (sva + PAGE_SIZE == eva) {
2952 pde = pmap_pde(pmap, sva);
2953 if (pde && (*pde & PG_PS) == 0) {
2954 pmap_remove_page(pmap, sva, pde, &free);
2960 for (; sva < eva; sva = va_next) {
2962 if (pmap->pm_stats.resident_count == 0)
2965 pml4e = pmap_pml4e(pmap, sva);
2966 if ((*pml4e & PG_V) == 0) {
2967 va_next = (sva + NBPML4) & ~PML4MASK;
2973 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
2974 if ((*pdpe & PG_V) == 0) {
2975 va_next = (sva + NBPDP) & ~PDPMASK;
2982 * Calculate index for next page table.
2984 va_next = (sva + NBPDR) & ~PDRMASK;
2988 pde = pmap_pdpe_to_pde(pdpe, sva);
2992 * Weed out invalid mappings.
2998 * Check for large page.
3000 if ((ptpaddr & PG_PS) != 0) {
3002 * Are we removing the entire large page? If not,
3003 * demote the mapping and fall through.
3005 if (sva + NBPDR == va_next && eva >= va_next) {
3007 * The TLB entry for a PG_G mapping is
3008 * invalidated by pmap_remove_pde().
3010 if ((ptpaddr & PG_G) == 0)
3012 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3014 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3016 /* The large page mapping was destroyed. */
3023 * Limit our scan to either the end of the va represented
3024 * by the current page table page, or to the end of the
3025 * range being removed.
3031 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3034 if (va != va_next) {
3035 pmap_invalidate_range(pmap, va, sva);
3040 if ((*pte & PG_G) == 0)
3042 else if (va == va_next)
3044 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3051 pmap_invalidate_range(pmap, va, sva);
3057 pmap_invalidate_all(pmap);
3058 rw_runlock(&pvh_global_lock);
3060 pmap_free_zero_pages(free);
3064 * Routine: pmap_remove_all
3066 * Removes this physical page from
3067 * all physical maps in which it resides.
3068 * Reflects back modify bits to the pager.
3071 * Original versions of this routine were very
3072 * inefficient because they iteratively called
3073 * pmap_remove (slow...)
3077 pmap_remove_all(vm_page_t m)
3079 struct md_page *pvh;
3082 pt_entry_t *pte, tpte;
3087 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3088 ("pmap_remove_all: page %p is not managed", m));
3090 rw_wlock(&pvh_global_lock);
3091 if ((m->flags & PG_FICTITIOUS) != 0)
3092 goto small_mappings;
3093 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3094 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3098 pde = pmap_pde(pmap, va);
3099 (void)pmap_demote_pde(pmap, pde, va);
3103 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3106 pmap_resident_count_dec(pmap, 1);
3107 pde = pmap_pde(pmap, pv->pv_va);
3108 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3109 " a 2mpage in page %p's pv list", m));
3110 pte = pmap_pde_to_pte(pde, pv->pv_va);
3111 tpte = pte_load_clear(pte);
3113 pmap->pm_stats.wired_count--;
3115 vm_page_aflag_set(m, PGA_REFERENCED);
3118 * Update the vm_page_t clean and reference bits.
3120 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3122 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3123 pmap_invalidate_page(pmap, pv->pv_va);
3124 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3125 free_pv_entry(pmap, pv);
3128 vm_page_aflag_clear(m, PGA_WRITEABLE);
3129 rw_wunlock(&pvh_global_lock);
3130 pmap_free_zero_pages(free);
3134 * pmap_protect_pde: do the things to protect a 2mpage in a process
3137 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3139 pd_entry_t newpde, oldpde;
3140 vm_offset_t eva, va;
3142 boolean_t anychanged;
3144 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3145 KASSERT((sva & PDRMASK) == 0,
3146 ("pmap_protect_pde: sva is not 2mpage aligned"));
3149 oldpde = newpde = *pde;
3150 if (oldpde & PG_MANAGED) {
3152 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3153 va < eva; va += PAGE_SIZE, m++)
3154 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3157 if ((prot & VM_PROT_WRITE) == 0)
3158 newpde &= ~(PG_RW | PG_M);
3159 if ((prot & VM_PROT_EXECUTE) == 0)
3161 if (newpde != oldpde) {
3162 if (!atomic_cmpset_long(pde, oldpde, newpde))
3165 pmap_invalidate_page(pmap, sva);
3169 return (anychanged);
3173 * Set the physical protection on the
3174 * specified range of this map as requested.
3177 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3179 vm_offset_t va_next;
3180 pml4_entry_t *pml4e;
3182 pd_entry_t ptpaddr, *pde;
3184 boolean_t anychanged, pv_lists_locked;
3186 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3187 pmap_remove(pmap, sva, eva);
3191 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3192 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3195 pv_lists_locked = FALSE;
3200 for (; sva < eva; sva = va_next) {
3202 pml4e = pmap_pml4e(pmap, sva);
3203 if ((*pml4e & PG_V) == 0) {
3204 va_next = (sva + NBPML4) & ~PML4MASK;
3210 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3211 if ((*pdpe & PG_V) == 0) {
3212 va_next = (sva + NBPDP) & ~PDPMASK;
3218 va_next = (sva + NBPDR) & ~PDRMASK;
3222 pde = pmap_pdpe_to_pde(pdpe, sva);
3226 * Weed out invalid mappings.
3232 * Check for large page.
3234 if ((ptpaddr & PG_PS) != 0) {
3236 * Are we protecting the entire large page? If not,
3237 * demote the mapping and fall through.
3239 if (sva + NBPDR == va_next && eva >= va_next) {
3241 * The TLB entry for a PG_G mapping is
3242 * invalidated by pmap_protect_pde().
3244 if (pmap_protect_pde(pmap, pde, sva, prot))
3248 if (!pv_lists_locked) {
3249 pv_lists_locked = TRUE;
3250 if (!rw_try_rlock(&pvh_global_lock)) {
3252 pmap_invalidate_all(
3255 rw_rlock(&pvh_global_lock);
3259 if (!pmap_demote_pde(pmap, pde, sva)) {
3261 * The large page mapping was
3272 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3274 pt_entry_t obits, pbits;
3278 obits = pbits = *pte;
3279 if ((pbits & PG_V) == 0)
3282 if ((prot & VM_PROT_WRITE) == 0) {
3283 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3284 (PG_MANAGED | PG_M | PG_RW)) {
3285 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3288 pbits &= ~(PG_RW | PG_M);
3290 if ((prot & VM_PROT_EXECUTE) == 0)
3293 if (pbits != obits) {
3294 if (!atomic_cmpset_long(pte, obits, pbits))
3297 pmap_invalidate_page(pmap, sva);
3304 pmap_invalidate_all(pmap);
3305 if (pv_lists_locked)
3306 rw_runlock(&pvh_global_lock);
3311 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3312 * single page table page (PTP) to a single 2MB page mapping. For promotion
3313 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3314 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3315 * identical characteristics.
3318 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3319 struct rwlock **lockp)
3322 pt_entry_t *firstpte, oldpte, pa, *pte;
3323 vm_offset_t oldpteva;
3326 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3329 * Examine the first PTE in the specified PTP. Abort if this PTE is
3330 * either invalid, unused, or does not map the first 4KB physical page
3331 * within a 2MB page.
3333 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
3336 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3337 atomic_add_long(&pmap_pde_p_failures, 1);
3338 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3339 " in pmap %p", va, pmap);
3342 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3344 * When PG_M is already clear, PG_RW can be cleared without
3345 * a TLB invalidation.
3347 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
3353 * Examine each of the other PTEs in the specified PTP. Abort if this
3354 * PTE maps an unexpected 4KB physical page or does not have identical
3355 * characteristics to the first PTE.
3357 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3358 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3361 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3362 atomic_add_long(&pmap_pde_p_failures, 1);
3363 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3364 " in pmap %p", va, pmap);
3367 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3369 * When PG_M is already clear, PG_RW can be cleared
3370 * without a TLB invalidation.
3372 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
3375 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3377 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
3378 " in pmap %p", oldpteva, pmap);
3380 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3381 atomic_add_long(&pmap_pde_p_failures, 1);
3382 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3383 " in pmap %p", va, pmap);
3390 * Save the page table page in its current state until the PDE
3391 * mapping the superpage is demoted by pmap_demote_pde() or
3392 * destroyed by pmap_remove_pde().
3394 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3395 KASSERT(mpte >= vm_page_array &&
3396 mpte < &vm_page_array[vm_page_array_size],
3397 ("pmap_promote_pde: page table page is out of range"));
3398 KASSERT(mpte->pindex == pmap_pde_pindex(va),
3399 ("pmap_promote_pde: page table page's pindex is wrong"));
3400 pmap_insert_pt_page(pmap, mpte);
3403 * Promote the pv entries.
3405 if ((newpde & PG_MANAGED) != 0)
3406 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
3409 * Propagate the PAT index to its proper position.
3411 if ((newpde & PG_PTE_PAT) != 0)
3412 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3415 * Map the superpage.
3417 if (workaround_erratum383)
3418 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3420 pde_store(pde, PG_PS | newpde);
3422 atomic_add_long(&pmap_pde_promotions, 1);
3423 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
3424 " in pmap %p", va, pmap);
3428 * Insert the given physical page (p) at
3429 * the specified virtual address (v) in the
3430 * target physical map with the protection requested.
3432 * If specified, the page will be wired down, meaning
3433 * that the related pte can not be reclaimed.
3435 * NB: This is the only routine which MAY NOT lazy-evaluate
3436 * or lose information. That is, this routine must actually
3437 * insert this page into the given map NOW.
3440 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3441 vm_prot_t prot, boolean_t wired)
3443 struct rwlock *lock;
3446 pt_entry_t newpte, origpte;
3451 va = trunc_page(va);
3452 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3453 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3454 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
3456 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
3457 va >= kmi.clean_eva,
3458 ("pmap_enter: managed mapping within the clean submap"));
3459 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3460 VM_OBJECT_LOCKED(m->object),
3461 ("pmap_enter: page %p is not busy", m));
3462 pa = VM_PAGE_TO_PHYS(m);
3463 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3464 if ((access & VM_PROT_WRITE) != 0)
3466 if ((prot & VM_PROT_WRITE) != 0)
3468 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3469 ("pmap_enter: access includes VM_PROT_WRITE but prot doesn't"));
3470 if ((prot & VM_PROT_EXECUTE) == 0)
3474 if (va < VM_MAXUSER_ADDRESS)
3476 if (pmap == kernel_pmap)
3478 newpte |= pmap_cache_bits(m->md.pat_mode, 0);
3483 rw_rlock(&pvh_global_lock);
3487 * In the case that a page table page is not
3488 * resident, we are creating it here.
3491 pde = pmap_pde(pmap, va);
3492 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
3493 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
3494 pte = pmap_pde_to_pte(pde, va);
3495 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3496 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3499 } else if (va < VM_MAXUSER_ADDRESS) {
3501 * Here if the pte page isn't mapped, or if it has been
3504 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va), &lock);
3507 panic("pmap_enter: invalid page directory va=%#lx", va);
3512 * Is the specified virtual address already mapped?
3514 if ((origpte & PG_V) != 0) {
3516 * Wiring change, just update stats. We don't worry about
3517 * wiring PT pages as they remain resident as long as there
3518 * are valid mappings in them. Hence, if a user page is wired,
3519 * the PT page will be also.
3521 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3522 pmap->pm_stats.wired_count++;
3523 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3524 pmap->pm_stats.wired_count--;
3527 * Remove the extra PT page reference.
3531 KASSERT(mpte->wire_count > 0,
3532 ("pmap_enter: missing reference to page table page,"
3537 * Has the physical page changed?
3539 opa = origpte & PG_FRAME;
3542 * No, might be a protection or wiring change.
3544 if ((origpte & PG_MANAGED) != 0) {
3545 newpte |= PG_MANAGED;
3546 if ((newpte & PG_RW) != 0)
3547 vm_page_aflag_set(m, PGA_WRITEABLE);
3549 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3555 * Increment the counters.
3557 if ((newpte & PG_W) != 0)
3558 pmap->pm_stats.wired_count++;
3559 pmap_resident_count_inc(pmap, 1);
3563 * Enter on the PV list if part of our managed memory.
3565 if ((m->oflags & VPO_UNMANAGED) == 0) {
3566 newpte |= PG_MANAGED;
3567 pv = get_pv_entry(pmap, &lock);
3569 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3570 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3571 if ((newpte & PG_RW) != 0)
3572 vm_page_aflag_set(m, PGA_WRITEABLE);
3578 if ((origpte & PG_V) != 0) {
3580 origpte = pte_load_store(pte, newpte);
3581 opa = origpte & PG_FRAME;
3583 if ((origpte & PG_MANAGED) != 0) {
3584 om = PHYS_TO_VM_PAGE(opa);
3585 if ((origpte & (PG_M | PG_RW)) == (PG_M |
3588 if ((origpte & PG_A) != 0)
3589 vm_page_aflag_set(om, PGA_REFERENCED);
3590 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3591 pmap_pvh_free(&om->md, pmap, va);
3592 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3593 TAILQ_EMPTY(&om->md.pv_list) &&
3594 ((om->flags & PG_FICTITIOUS) != 0 ||
3595 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3596 vm_page_aflag_clear(om, PGA_WRITEABLE);
3598 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
3599 PG_RW)) == (PG_M | PG_RW)) {
3600 if ((origpte & PG_MANAGED) != 0)
3604 * Although the PTE may still have PG_RW set, TLB
3605 * invalidation may nonetheless be required because
3606 * the PTE no longer has PG_M set.
3608 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3610 * This PTE change does not require TLB invalidation.
3614 if ((origpte & PG_A) != 0)
3615 pmap_invalidate_page(pmap, va);
3617 pte_store(pte, newpte);
3622 * If both the page table page and the reservation are fully
3623 * populated, then attempt promotion.
3625 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3626 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3627 vm_reserv_level_iffullpop(m) == 0)
3628 pmap_promote_pde(pmap, pde, va, &lock);
3632 rw_runlock(&pvh_global_lock);
3637 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
3638 * otherwise. Fails if (1) a page table page cannot be allocated without
3639 * blocking, (2) a mapping already exists at the specified virtual address, or
3640 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3643 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3644 struct rwlock **lockp)
3646 pd_entry_t *pde, newpde;
3647 vm_page_t free, mpde;
3649 rw_assert(&pvh_global_lock, RA_LOCKED);
3650 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3651 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
3652 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3653 " in pmap %p", va, pmap);
3656 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
3657 pde = &pde[pmap_pde_index(va)];
3658 if ((*pde & PG_V) != 0) {
3659 KASSERT(mpde->wire_count > 1,
3660 ("pmap_enter_pde: mpde's wire count is too low"));
3662 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3663 " in pmap %p", va, pmap);
3666 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3668 if ((m->oflags & VPO_UNMANAGED) == 0) {
3669 newpde |= PG_MANAGED;
3672 * Abort this mapping if its PV entry could not be created.
3674 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
3677 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
3678 pmap_invalidate_page(pmap, va);
3679 pmap_free_zero_pages(free);
3681 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3682 " in pmap %p", va, pmap);
3686 if ((prot & VM_PROT_EXECUTE) == 0)
3688 if (va < VM_MAXUSER_ADDRESS)
3692 * Increment counters.
3694 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3697 * Map the superpage.
3699 pde_store(pde, newpde);
3701 atomic_add_long(&pmap_pde_mappings, 1);
3702 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3703 " in pmap %p", va, pmap);
3708 * Maps a sequence of resident pages belonging to the same object.
3709 * The sequence begins with the given page m_start. This page is
3710 * mapped at the given virtual address start. Each subsequent page is
3711 * mapped at a virtual address that is offset from start by the same
3712 * amount as the page is offset from m_start within the object. The
3713 * last page in the sequence is the page with the largest offset from
3714 * m_start that can be mapped at a virtual address less than the given
3715 * virtual address end. Not every virtual page between start and end
3716 * is mapped; only those for which a resident page exists with the
3717 * corresponding offset from m_start are mapped.
3720 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3721 vm_page_t m_start, vm_prot_t prot)
3723 struct rwlock *lock;
3726 vm_pindex_t diff, psize;
3728 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3729 psize = atop(end - start);
3733 rw_rlock(&pvh_global_lock);
3735 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3736 va = start + ptoa(diff);
3737 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3738 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3739 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3740 pmap_enter_pde(pmap, va, m, prot, &lock))
3741 m = &m[NBPDR / PAGE_SIZE - 1];
3743 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3745 m = TAILQ_NEXT(m, listq);
3749 rw_runlock(&pvh_global_lock);
3754 * this code makes some *MAJOR* assumptions:
3755 * 1. Current pmap & pmap exists.
3758 * 4. No page table pages.
3759 * but is *MUCH* faster than pmap_enter...
3763 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3765 struct rwlock *lock;
3768 rw_rlock(&pvh_global_lock);
3770 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3773 rw_runlock(&pvh_global_lock);
3778 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3779 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3785 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3786 (m->oflags & VPO_UNMANAGED) != 0,
3787 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3788 rw_assert(&pvh_global_lock, RA_LOCKED);
3789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3792 * In the case that a page table page is not
3793 * resident, we are creating it here.
3795 if (va < VM_MAXUSER_ADDRESS) {
3796 vm_pindex_t ptepindex;
3800 * Calculate pagetable page index
3802 ptepindex = pmap_pde_pindex(va);
3803 if (mpte && (mpte->pindex == ptepindex)) {
3807 * Get the page directory entry
3809 ptepa = pmap_pde(pmap, va);
3812 * If the page table page is mapped, we just increment
3813 * the hold count, and activate it. Otherwise, we
3814 * attempt to allocate a page table page. If this
3815 * attempt fails, we don't retry. Instead, we give up.
3817 if (ptepa && (*ptepa & PG_V) != 0) {
3820 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
3824 * Pass NULL instead of the PV list lock
3825 * pointer, because we don't intend to sleep.
3827 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
3832 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3833 pte = &pte[pmap_pte_index(va)];
3847 * Enter on the PV list if part of our managed memory.
3849 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3850 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3853 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3854 pmap_invalidate_page(pmap, va);
3855 pmap_free_zero_pages(free);
3863 * Increment counters
3865 pmap_resident_count_inc(pmap, 1);
3867 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3868 if ((prot & VM_PROT_EXECUTE) == 0)
3872 * Now validate mapping with RO protection
3874 if ((m->oflags & VPO_UNMANAGED) != 0)
3875 pte_store(pte, pa | PG_V | PG_U);
3877 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3882 * Make a temporary mapping for a physical address. This is only intended
3883 * to be used for panic dumps.
3886 pmap_kenter_temporary(vm_paddr_t pa, int i)
3890 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3891 pmap_kenter(va, pa);
3893 return ((void *)crashdumpmap);
3897 * This code maps large physical mmap regions into the
3898 * processor address space. Note that some shortcuts
3899 * are taken, but the code works.
3902 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3903 vm_pindex_t pindex, vm_size_t size)
3906 vm_paddr_t pa, ptepa;
3910 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3911 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3912 ("pmap_object_init_pt: non-device object"));
3913 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3914 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3916 p = vm_page_lookup(object, pindex);
3917 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3918 ("pmap_object_init_pt: invalid page %p", p));
3919 pat_mode = p->md.pat_mode;
3922 * Abort the mapping if the first page is not physically
3923 * aligned to a 2MB page boundary.
3925 ptepa = VM_PAGE_TO_PHYS(p);
3926 if (ptepa & (NBPDR - 1))
3930 * Skip the first page. Abort the mapping if the rest of
3931 * the pages are not physically contiguous or have differing
3932 * memory attributes.
3934 p = TAILQ_NEXT(p, listq);
3935 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3937 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3938 ("pmap_object_init_pt: invalid page %p", p));
3939 if (pa != VM_PAGE_TO_PHYS(p) ||
3940 pat_mode != p->md.pat_mode)
3942 p = TAILQ_NEXT(p, listq);
3946 * Map using 2MB pages. Since "ptepa" is 2M aligned and
3947 * "size" is a multiple of 2M, adding the PAT setting to "pa"
3948 * will not affect the termination of this loop.
3951 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3952 size; pa += NBPDR) {
3953 pdpg = pmap_allocpde(pmap, addr, NULL);
3956 * The creation of mappings below is only an
3957 * optimization. If a page directory page
3958 * cannot be allocated without blocking,
3959 * continue on to the next mapping rather than
3965 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
3966 pde = &pde[pmap_pde_index(addr)];
3967 if ((*pde & PG_V) == 0) {
3968 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3969 PG_U | PG_RW | PG_V);
3970 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3971 atomic_add_long(&pmap_pde_mappings, 1);
3973 /* Continue on if the PDE is already valid. */
3975 KASSERT(pdpg->wire_count > 0,
3976 ("pmap_object_init_pt: missing reference "
3977 "to page directory page, va: 0x%lx", addr));
3986 * Routine: pmap_change_wiring
3987 * Function: Change the wiring attribute for a map/virtual-address
3989 * In/out conditions:
3990 * The mapping must already exist in the pmap.
3993 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3997 boolean_t pv_lists_locked;
3999 pv_lists_locked = FALSE;
4002 * Wiring is not a hardware characteristic so there is no need to
4007 pde = pmap_pde(pmap, va);
4008 if ((*pde & PG_PS) != 0) {
4009 if (!wired != ((*pde & PG_W) == 0)) {
4010 if (!pv_lists_locked) {
4011 pv_lists_locked = TRUE;
4012 if (!rw_try_rlock(&pvh_global_lock)) {
4014 rw_rlock(&pvh_global_lock);
4018 if (!pmap_demote_pde(pmap, pde, va))
4019 panic("pmap_change_wiring: demotion failed");
4023 pte = pmap_pde_to_pte(pde, va);
4024 if (wired && (*pte & PG_W) == 0) {
4025 pmap->pm_stats.wired_count++;
4026 atomic_set_long(pte, PG_W);
4027 } else if (!wired && (*pte & PG_W) != 0) {
4028 pmap->pm_stats.wired_count--;
4029 atomic_clear_long(pte, PG_W);
4032 if (pv_lists_locked)
4033 rw_runlock(&pvh_global_lock);
4038 * Copy the range specified by src_addr/len
4039 * from the source map to the range dst_addr/len
4040 * in the destination map.
4042 * This routine is only advisory and need not do anything.
4046 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4047 vm_offset_t src_addr)
4049 struct rwlock *lock;
4052 vm_offset_t end_addr = src_addr + len;
4053 vm_offset_t va_next;
4055 if (dst_addr != src_addr)
4059 rw_rlock(&pvh_global_lock);
4060 if (dst_pmap < src_pmap) {
4061 PMAP_LOCK(dst_pmap);
4062 PMAP_LOCK(src_pmap);
4064 PMAP_LOCK(src_pmap);
4065 PMAP_LOCK(dst_pmap);
4067 for (addr = src_addr; addr < end_addr; addr = va_next) {
4068 pt_entry_t *src_pte, *dst_pte;
4069 vm_page_t dstmpde, dstmpte, srcmpte;
4070 pml4_entry_t *pml4e;
4072 pd_entry_t srcptepaddr, *pde;
4074 KASSERT(addr < UPT_MIN_ADDRESS,
4075 ("pmap_copy: invalid to pmap_copy page tables"));
4077 pml4e = pmap_pml4e(src_pmap, addr);
4078 if ((*pml4e & PG_V) == 0) {
4079 va_next = (addr + NBPML4) & ~PML4MASK;
4085 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4086 if ((*pdpe & PG_V) == 0) {
4087 va_next = (addr + NBPDP) & ~PDPMASK;
4093 va_next = (addr + NBPDR) & ~PDRMASK;
4097 pde = pmap_pdpe_to_pde(pdpe, addr);
4099 if (srcptepaddr == 0)
4102 if (srcptepaddr & PG_PS) {
4103 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4105 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4106 if (dstmpde == NULL)
4108 pde = (pd_entry_t *)
4109 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4110 pde = &pde[pmap_pde_index(addr)];
4111 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4112 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4113 PG_PS_FRAME, &lock))) {
4114 *pde = srcptepaddr & ~PG_W;
4115 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4117 dstmpde->wire_count--;
4121 srcptepaddr &= PG_FRAME;
4122 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4123 KASSERT(srcmpte->wire_count > 0,
4124 ("pmap_copy: source page table page is unused"));
4126 if (va_next > end_addr)
4129 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4130 src_pte = &src_pte[pmap_pte_index(addr)];
4132 while (addr < va_next) {
4136 * we only virtual copy managed pages
4138 if ((ptetemp & PG_MANAGED) != 0) {
4139 if (dstmpte != NULL &&
4140 dstmpte->pindex == pmap_pde_pindex(addr))
4141 dstmpte->wire_count++;
4142 else if ((dstmpte = pmap_allocpte(dst_pmap,
4143 addr, NULL)) == NULL)
4145 dst_pte = (pt_entry_t *)
4146 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4147 dst_pte = &dst_pte[pmap_pte_index(addr)];
4148 if (*dst_pte == 0 &&
4149 pmap_try_insert_pv_entry(dst_pmap, addr,
4150 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4153 * Clear the wired, modified, and
4154 * accessed (referenced) bits
4157 *dst_pte = ptetemp & ~(PG_W | PG_M |
4159 pmap_resident_count_inc(dst_pmap, 1);
4162 if (pmap_unwire_ptp(dst_pmap, addr,
4164 pmap_invalidate_page(dst_pmap,
4166 pmap_free_zero_pages(free);
4170 if (dstmpte->wire_count >= srcmpte->wire_count)
4180 rw_runlock(&pvh_global_lock);
4181 PMAP_UNLOCK(src_pmap);
4182 PMAP_UNLOCK(dst_pmap);
4186 * pmap_zero_page zeros the specified hardware page by mapping
4187 * the page into KVM and using bzero to clear its contents.
4190 pmap_zero_page(vm_page_t m)
4192 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4194 pagezero((void *)va);
4198 * pmap_zero_page_area zeros the specified hardware page by mapping
4199 * the page into KVM and using bzero to clear its contents.
4201 * off and size may not cover an area beyond a single hardware page.
4204 pmap_zero_page_area(vm_page_t m, int off, int size)
4206 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4208 if (off == 0 && size == PAGE_SIZE)
4209 pagezero((void *)va);
4211 bzero((char *)va + off, size);
4215 * pmap_zero_page_idle zeros the specified hardware page by mapping
4216 * the page into KVM and using bzero to clear its contents. This
4217 * is intended to be called from the vm_pagezero process only and
4221 pmap_zero_page_idle(vm_page_t m)
4223 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4225 pagezero((void *)va);
4229 * pmap_copy_page copies the specified (machine independent)
4230 * page by mapping the page into virtual memory and using
4231 * bcopy to copy the page, one machine dependent page at a
4235 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4237 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4238 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4240 pagecopy((void *)src, (void *)dst);
4243 int unmapped_buf_allowed = 1;
4246 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4247 vm_offset_t b_offset, int xfersize)
4250 vm_offset_t a_pg_offset, b_pg_offset;
4253 while (xfersize > 0) {
4254 a_pg_offset = a_offset & PAGE_MASK;
4255 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4256 a_cp = (char *)PHYS_TO_DMAP(ma[a_offset >> PAGE_SHIFT]->
4257 phys_addr) + a_pg_offset;
4258 b_pg_offset = b_offset & PAGE_MASK;
4259 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4260 b_cp = (char *)PHYS_TO_DMAP(mb[b_offset >> PAGE_SHIFT]->
4261 phys_addr) + b_pg_offset;
4262 bcopy(a_cp, b_cp, cnt);
4270 * Returns true if the pmap's pv is one of the first
4271 * 16 pvs linked to from this page. This count may
4272 * be changed upwards or downwards in the future; it
4273 * is only necessary that true be returned for a small
4274 * subset of pmaps for proper page aging.
4277 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4279 struct md_page *pvh;
4280 struct rwlock *lock;
4285 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4286 ("pmap_page_exists_quick: page %p is not managed", m));
4288 rw_rlock(&pvh_global_lock);
4289 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4291 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4292 if (PV_PMAP(pv) == pmap) {
4300 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4301 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4302 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4303 if (PV_PMAP(pv) == pmap) {
4313 rw_runlock(&pvh_global_lock);
4318 * pmap_page_wired_mappings:
4320 * Return the number of managed mappings to the given physical page
4324 pmap_page_wired_mappings(vm_page_t m)
4329 if ((m->oflags & VPO_UNMANAGED) != 0)
4331 rw_wlock(&pvh_global_lock);
4332 count = pmap_pvh_wired_mappings(&m->md, count);
4333 if ((m->flags & PG_FICTITIOUS) == 0) {
4334 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4337 rw_wunlock(&pvh_global_lock);
4342 * pmap_pvh_wired_mappings:
4344 * Return the updated number "count" of managed mappings that are wired.
4347 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4353 rw_assert(&pvh_global_lock, RA_WLOCKED);
4354 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4357 pte = pmap_pte(pmap, pv->pv_va);
4358 if ((*pte & PG_W) != 0)
4366 * Returns TRUE if the given page is mapped individually or as part of
4367 * a 2mpage. Otherwise, returns FALSE.
4370 pmap_page_is_mapped(vm_page_t m)
4372 struct rwlock *lock;
4375 if ((m->oflags & VPO_UNMANAGED) != 0)
4377 rw_rlock(&pvh_global_lock);
4378 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4380 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4381 ((m->flags & PG_FICTITIOUS) == 0 &&
4382 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4384 rw_runlock(&pvh_global_lock);
4389 * Destroy all managed, non-wired mappings in the given user-space
4390 * pmap. This pmap cannot be active on any processor besides the
4393 * This function cannot be applied to the kernel pmap. Moreover, it
4394 * is not intended for general use. It is only to be used during
4395 * process termination. Consequently, it can be implemented in ways
4396 * that make it faster than pmap_remove(). First, it can more quickly
4397 * destroy mappings by iterating over the pmap's collection of PV
4398 * entries, rather than searching the page table. Second, it doesn't
4399 * have to test and clear the page table entries atomically, because
4400 * no processor is currently accessing the user address space. In
4401 * particular, a page table entry's dirty bit won't change state once
4402 * this function starts.
4405 pmap_remove_pages(pmap_t pmap)
4408 pt_entry_t *pte, tpte;
4409 vm_page_t free = NULL;
4410 vm_page_t m, mpte, mt;
4412 struct md_page *pvh;
4413 struct pv_chunk *pc, *npc;
4414 struct rwlock *lock;
4416 uint64_t inuse, bitmask;
4417 int allfree, field, freed, idx;
4420 * Assert that the given pmap is only active on the current
4421 * CPU. Unfortunately, we cannot block another CPU from
4422 * activating the pmap while this function is executing.
4424 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4427 cpuset_t other_cpus;
4429 other_cpus = all_cpus;
4431 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4432 CPU_AND(&other_cpus, &pmap->pm_active);
4434 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
4439 rw_rlock(&pvh_global_lock);
4441 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4444 for (field = 0; field < _NPCM; field++) {
4445 inuse = ~pc->pc_map[field] & pc_freemask[field];
4446 while (inuse != 0) {
4448 bitmask = 1UL << bit;
4449 idx = field * 64 + bit;
4450 pv = &pc->pc_pventry[idx];
4453 pte = pmap_pdpe(pmap, pv->pv_va);
4455 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
4457 if ((tpte & (PG_PS | PG_V)) == PG_V) {
4459 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
4461 pte = &pte[pmap_pte_index(pv->pv_va)];
4462 tpte = *pte & ~PG_PTE_PAT;
4464 if ((tpte & PG_V) == 0) {
4465 panic("bad pte va %lx pte %lx",
4470 * We cannot remove wired pages from a process' mapping at this time
4477 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4478 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4479 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4480 m, (uintmax_t)m->phys_addr,
4483 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4484 m < &vm_page_array[vm_page_array_size],
4485 ("pmap_remove_pages: bad tpte %#jx",
4491 * Update the vm_page_t clean/reference bits.
4493 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4494 if ((tpte & PG_PS) != 0) {
4495 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4501 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4504 pc->pc_map[field] |= bitmask;
4505 if ((tpte & PG_PS) != 0) {
4506 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4507 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4508 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4509 if (TAILQ_EMPTY(&pvh->pv_list)) {
4510 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4511 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4512 TAILQ_EMPTY(&mt->md.pv_list))
4513 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4515 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4517 pmap_remove_pt_page(pmap, mpte);
4518 pmap_resident_count_dec(pmap, 1);
4519 KASSERT(mpte->wire_count == NPTEPG,
4520 ("pmap_remove_pages: pte page wire count error"));
4521 mpte->wire_count = 0;
4522 pmap_add_delayed_free_list(mpte, &free, FALSE);
4523 atomic_subtract_int(&cnt.v_wire_count, 1);
4526 pmap_resident_count_dec(pmap, 1);
4527 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4528 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4529 TAILQ_EMPTY(&m->md.pv_list) &&
4530 (m->flags & PG_FICTITIOUS) == 0) {
4531 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4532 if (TAILQ_EMPTY(&pvh->pv_list))
4533 vm_page_aflag_clear(m, PGA_WRITEABLE);
4536 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
4540 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4541 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4542 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4544 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4550 pmap_invalidate_all(pmap);
4551 rw_runlock(&pvh_global_lock);
4553 pmap_free_zero_pages(free);
4559 * Return whether or not the specified physical page was modified
4560 * in any physical maps.
4563 pmap_is_modified(vm_page_t m)
4567 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4568 ("pmap_is_modified: page %p is not managed", m));
4571 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4572 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4573 * is clear, no PTEs can have PG_M set.
4575 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4576 if ((m->oflags & VPO_BUSY) == 0 &&
4577 (m->aflags & PGA_WRITEABLE) == 0)
4579 rw_wlock(&pvh_global_lock);
4580 rv = pmap_is_modified_pvh(&m->md) ||
4581 ((m->flags & PG_FICTITIOUS) == 0 &&
4582 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4583 rw_wunlock(&pvh_global_lock);
4588 * Returns TRUE if any of the given mappings were used to modify
4589 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4590 * mappings are supported.
4593 pmap_is_modified_pvh(struct md_page *pvh)
4600 rw_assert(&pvh_global_lock, RA_WLOCKED);
4602 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4605 pte = pmap_pte(pmap, pv->pv_va);
4606 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4615 * pmap_is_prefaultable:
4617 * Return whether or not the specified virtual address is elgible
4621 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4629 pde = pmap_pde(pmap, addr);
4630 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
4631 pte = pmap_pde_to_pte(pde, addr);
4632 rv = (*pte & PG_V) == 0;
4639 * pmap_is_referenced:
4641 * Return whether or not the specified physical page was referenced
4642 * in any physical maps.
4645 pmap_is_referenced(vm_page_t m)
4649 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4650 ("pmap_is_referenced: page %p is not managed", m));
4651 rw_wlock(&pvh_global_lock);
4652 rv = pmap_is_referenced_pvh(&m->md) ||
4653 ((m->flags & PG_FICTITIOUS) == 0 &&
4654 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4655 rw_wunlock(&pvh_global_lock);
4660 * Returns TRUE if any of the given mappings were referenced and FALSE
4661 * otherwise. Both page and 2mpage mappings are supported.
4664 pmap_is_referenced_pvh(struct md_page *pvh)
4671 rw_assert(&pvh_global_lock, RA_WLOCKED);
4673 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4676 pte = pmap_pte(pmap, pv->pv_va);
4677 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4686 * Clear the write and modified bits in each of the given page's mappings.
4689 pmap_remove_write(vm_page_t m)
4691 struct md_page *pvh;
4693 pv_entry_t next_pv, pv;
4695 pt_entry_t oldpte, *pte;
4698 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4699 ("pmap_remove_write: page %p is not managed", m));
4702 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4703 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4704 * is clear, no page table entries need updating.
4706 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4707 if ((m->oflags & VPO_BUSY) == 0 &&
4708 (m->aflags & PGA_WRITEABLE) == 0)
4710 rw_wlock(&pvh_global_lock);
4711 if ((m->flags & PG_FICTITIOUS) != 0)
4712 goto small_mappings;
4713 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4714 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4718 pde = pmap_pde(pmap, va);
4719 if ((*pde & PG_RW) != 0)
4720 (void)pmap_demote_pde(pmap, pde, va);
4724 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4727 pde = pmap_pde(pmap, pv->pv_va);
4728 KASSERT((*pde & PG_PS) == 0,
4729 ("pmap_remove_write: found a 2mpage in page %p's pv list",
4731 pte = pmap_pde_to_pte(pde, pv->pv_va);
4734 if (oldpte & PG_RW) {
4735 if (!atomic_cmpset_long(pte, oldpte, oldpte &
4738 if ((oldpte & PG_M) != 0)
4740 pmap_invalidate_page(pmap, pv->pv_va);
4744 vm_page_aflag_clear(m, PGA_WRITEABLE);
4745 rw_wunlock(&pvh_global_lock);
4749 * pmap_ts_referenced:
4751 * Return a count of reference bits for a page, clearing those bits.
4752 * It is not necessary for every reference bit to be cleared, but it
4753 * is necessary that 0 only be returned when there are truly no
4754 * reference bits set.
4756 * XXX: The exact number of bits to check and clear is a matter that
4757 * should be tested and standardized at some point in the future for
4758 * optimal aging of shared pages.
4761 pmap_ts_referenced(vm_page_t m)
4763 struct md_page *pvh;
4764 pv_entry_t pv, pvf, pvn;
4766 pd_entry_t oldpde, *pde;
4771 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4772 ("pmap_ts_referenced: page %p is not managed", m));
4773 rw_wlock(&pvh_global_lock);
4774 if ((m->flags & PG_FICTITIOUS) != 0)
4775 goto small_mappings;
4776 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4777 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4781 pde = pmap_pde(pmap, va);
4783 if ((oldpde & PG_A) != 0) {
4784 if (pmap_demote_pde(pmap, pde, va)) {
4785 if ((oldpde & PG_W) == 0) {
4787 * Remove the mapping to a single page
4788 * so that a subsequent access may
4789 * repromote. Since the underlying
4790 * page table page is fully populated,
4791 * this removal never frees a page
4794 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4796 pmap_remove_page(pmap, va, pde, NULL);
4808 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4811 pvn = TAILQ_NEXT(pv, pv_list);
4812 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4813 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4816 pde = pmap_pde(pmap, pv->pv_va);
4817 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4818 " found a 2mpage in page %p's pv list", m));
4819 pte = pmap_pde_to_pte(pde, pv->pv_va);
4820 if ((*pte & PG_A) != 0) {
4821 atomic_clear_long(pte, PG_A);
4822 pmap_invalidate_page(pmap, pv->pv_va);
4828 } while ((pv = pvn) != NULL && pv != pvf);
4831 rw_wunlock(&pvh_global_lock);
4836 * Clear the modify bits on the specified physical page.
4839 pmap_clear_modify(vm_page_t m)
4841 struct md_page *pvh;
4843 pv_entry_t next_pv, pv;
4844 pd_entry_t oldpde, *pde;
4845 pt_entry_t oldpte, *pte;
4848 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4849 ("pmap_clear_modify: page %p is not managed", m));
4850 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4851 KASSERT((m->oflags & VPO_BUSY) == 0,
4852 ("pmap_clear_modify: page %p is busy", m));
4855 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4856 * If the object containing the page is locked and the page is not
4857 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4859 if ((m->aflags & PGA_WRITEABLE) == 0)
4861 rw_wlock(&pvh_global_lock);
4862 if ((m->flags & PG_FICTITIOUS) != 0)
4863 goto small_mappings;
4864 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4865 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4869 pde = pmap_pde(pmap, va);
4871 if ((oldpde & PG_RW) != 0) {
4872 if (pmap_demote_pde(pmap, pde, va)) {
4873 if ((oldpde & PG_W) == 0) {
4875 * Write protect the mapping to a
4876 * single page so that a subsequent
4877 * write access may repromote.
4879 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4881 pte = pmap_pde_to_pte(pde, va);
4883 if ((oldpte & PG_V) != 0) {
4884 while (!atomic_cmpset_long(pte,
4886 oldpte & ~(PG_M | PG_RW)))
4889 pmap_invalidate_page(pmap, va);
4897 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4900 pde = pmap_pde(pmap, pv->pv_va);
4901 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4902 " a 2mpage in page %p's pv list", m));
4903 pte = pmap_pde_to_pte(pde, pv->pv_va);
4904 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4905 atomic_clear_long(pte, PG_M);
4906 pmap_invalidate_page(pmap, pv->pv_va);
4910 rw_wunlock(&pvh_global_lock);
4914 * pmap_clear_reference:
4916 * Clear the reference bit on the specified physical page.
4919 pmap_clear_reference(vm_page_t m)
4921 struct md_page *pvh;
4923 pv_entry_t next_pv, pv;
4924 pd_entry_t oldpde, *pde;
4928 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4929 ("pmap_clear_reference: page %p is not managed", m));
4930 rw_wlock(&pvh_global_lock);
4931 if ((m->flags & PG_FICTITIOUS) != 0)
4932 goto small_mappings;
4933 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4934 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4938 pde = pmap_pde(pmap, va);
4940 if ((oldpde & PG_A) != 0) {
4941 if (pmap_demote_pde(pmap, pde, va)) {
4943 * Remove the mapping to a single page so
4944 * that a subsequent access may repromote.
4945 * Since the underlying page table page is
4946 * fully populated, this removal never frees
4947 * a page table page.
4949 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4951 pmap_remove_page(pmap, va, pde, NULL);
4957 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4960 pde = pmap_pde(pmap, pv->pv_va);
4961 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4962 " a 2mpage in page %p's pv list", m));
4963 pte = pmap_pde_to_pte(pde, pv->pv_va);
4965 atomic_clear_long(pte, PG_A);
4966 pmap_invalidate_page(pmap, pv->pv_va);
4970 rw_wunlock(&pvh_global_lock);
4974 * Miscellaneous support routines follow
4977 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4978 static __inline void
4979 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4984 * The cache mode bits are all in the low 32-bits of the
4985 * PTE, so we can just spin on updating the low 32-bits.
4988 opte = *(u_int *)pte;
4989 npte = opte & ~PG_PTE_CACHE;
4991 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4994 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
4995 static __inline void
4996 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5001 * The cache mode bits are all in the low 32-bits of the
5002 * PDE, so we can just spin on updating the low 32-bits.
5005 opde = *(u_int *)pde;
5006 npde = opde & ~PG_PDE_CACHE;
5008 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5012 * Map a set of physical memory pages into the kernel virtual
5013 * address space. Return a pointer to where it is mapped. This
5014 * routine is intended to be used for mapping device memory,
5018 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5020 vm_offset_t va, offset;
5024 * If the specified range of physical addresses fits within the direct
5025 * map window, use the direct map.
5027 if (pa < dmaplimit && pa + size < dmaplimit) {
5028 va = PHYS_TO_DMAP(pa);
5029 if (!pmap_change_attr(va, size, mode))
5030 return ((void *)va);
5032 offset = pa & PAGE_MASK;
5033 size = roundup(offset + size, PAGE_SIZE);
5034 va = kmem_alloc_nofault(kernel_map, size);
5036 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5037 pa = trunc_page(pa);
5038 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5039 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5040 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5041 pmap_invalidate_cache_range(va, va + tmpsize);
5042 return ((void *)(va + offset));
5046 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5049 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5053 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5056 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5060 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5062 vm_offset_t base, offset;
5064 /* If we gave a direct map region in pmap_mapdev, do nothing */
5065 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
5067 base = trunc_page(va);
5068 offset = va & PAGE_MASK;
5069 size = roundup(offset + size, PAGE_SIZE);
5070 kmem_free(kernel_map, base, size);
5074 * Tries to demote a 1GB page mapping.
5077 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
5079 pdp_entry_t newpdpe, oldpdpe;
5080 pd_entry_t *firstpde, newpde, *pde;
5084 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5086 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
5087 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
5088 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
5089 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5090 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
5091 " in pmap %p", va, pmap);
5094 mpdepa = VM_PAGE_TO_PHYS(mpde);
5095 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
5096 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
5097 KASSERT((oldpdpe & PG_A) != 0,
5098 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
5099 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
5100 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
5104 * Initialize the page directory page.
5106 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
5112 * Demote the mapping.
5117 * Invalidate a stale recursive mapping of the page directory page.
5119 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
5121 pmap_pdpe_demotions++;
5122 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
5123 " in pmap %p", va, pmap);
5128 * Sets the memory attribute for the specified page.
5131 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5134 m->md.pat_mode = ma;
5137 * If "m" is a normal page, update its direct mapping. This update
5138 * can be relied upon to perform any cache operations that are
5139 * required for data coherence.
5141 if ((m->flags & PG_FICTITIOUS) == 0 &&
5142 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5144 panic("memory attribute change on the direct map failed");
5148 * Changes the specified virtual address range's memory type to that given by
5149 * the parameter "mode". The specified virtual address range must be
5150 * completely contained within either the direct map or the kernel map. If
5151 * the virtual address range is contained within the kernel map, then the
5152 * memory type for each of the corresponding ranges of the direct map is also
5153 * changed. (The corresponding ranges of the direct map are those ranges that
5154 * map the same physical pages as the specified virtual address range.) These
5155 * changes to the direct map are necessary because Intel describes the
5156 * behavior of their processors as "undefined" if two or more mappings to the
5157 * same physical page have different memory types.
5159 * Returns zero if the change completed successfully, and either EINVAL or
5160 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5161 * of the virtual address range was not mapped, and ENOMEM is returned if
5162 * there was insufficient memory available to complete the change. In the
5163 * latter case, the memory type may have been changed on some part of the
5164 * virtual address range or the direct map.
5167 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5171 PMAP_LOCK(kernel_pmap);
5172 error = pmap_change_attr_locked(va, size, mode);
5173 PMAP_UNLOCK(kernel_pmap);
5178 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5180 vm_offset_t base, offset, tmpva;
5181 vm_paddr_t pa_start, pa_end;
5185 int cache_bits_pte, cache_bits_pde, error;
5188 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5189 base = trunc_page(va);
5190 offset = va & PAGE_MASK;
5191 size = roundup(offset + size, PAGE_SIZE);
5194 * Only supported on kernel virtual addresses, including the direct
5195 * map but excluding the recursive map.
5197 if (base < DMAP_MIN_ADDRESS)
5200 cache_bits_pde = pmap_cache_bits(mode, 1);
5201 cache_bits_pte = pmap_cache_bits(mode, 0);
5205 * Pages that aren't mapped aren't supported. Also break down 2MB pages
5206 * into 4KB pages if required.
5208 for (tmpva = base; tmpva < base + size; ) {
5209 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5212 if (*pdpe & PG_PS) {
5214 * If the current 1GB page already has the required
5215 * memory type, then we need not demote this page. Just
5216 * increment tmpva to the next 1GB page frame.
5218 if ((*pdpe & PG_PDE_CACHE) == cache_bits_pde) {
5219 tmpva = trunc_1gpage(tmpva) + NBPDP;
5224 * If the current offset aligns with a 1GB page frame
5225 * and there is at least 1GB left within the range, then
5226 * we need not break down this page into 2MB pages.
5228 if ((tmpva & PDPMASK) == 0 &&
5229 tmpva + PDPMASK < base + size) {
5233 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
5236 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5241 * If the current 2MB page already has the required
5242 * memory type, then we need not demote this page. Just
5243 * increment tmpva to the next 2MB page frame.
5245 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5246 tmpva = trunc_2mpage(tmpva) + NBPDR;
5251 * If the current offset aligns with a 2MB page frame
5252 * and there is at least 2MB left within the range, then
5253 * we need not break down this page into 4KB pages.
5255 if ((tmpva & PDRMASK) == 0 &&
5256 tmpva + PDRMASK < base + size) {
5260 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
5263 pte = pmap_pde_to_pte(pde, tmpva);
5271 * Ok, all the pages exist, so run through them updating their
5272 * cache mode if required.
5274 pa_start = pa_end = 0;
5275 for (tmpva = base; tmpva < base + size; ) {
5276 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5277 if (*pdpe & PG_PS) {
5278 if ((*pdpe & PG_PDE_CACHE) != cache_bits_pde) {
5279 pmap_pde_attr(pdpe, cache_bits_pde);
5282 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5283 if (pa_start == pa_end) {
5284 /* Start physical address run. */
5285 pa_start = *pdpe & PG_PS_FRAME;
5286 pa_end = pa_start + NBPDP;
5287 } else if (pa_end == (*pdpe & PG_PS_FRAME))
5290 /* Run ended, update direct map. */
5291 error = pmap_change_attr_locked(
5292 PHYS_TO_DMAP(pa_start),
5293 pa_end - pa_start, mode);
5296 /* Start physical address run. */
5297 pa_start = *pdpe & PG_PS_FRAME;
5298 pa_end = pa_start + NBPDP;
5301 tmpva = trunc_1gpage(tmpva) + NBPDP;
5304 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5306 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5307 pmap_pde_attr(pde, cache_bits_pde);
5310 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5311 if (pa_start == pa_end) {
5312 /* Start physical address run. */
5313 pa_start = *pde & PG_PS_FRAME;
5314 pa_end = pa_start + NBPDR;
5315 } else if (pa_end == (*pde & PG_PS_FRAME))
5318 /* Run ended, update direct map. */
5319 error = pmap_change_attr_locked(
5320 PHYS_TO_DMAP(pa_start),
5321 pa_end - pa_start, mode);
5324 /* Start physical address run. */
5325 pa_start = *pde & PG_PS_FRAME;
5326 pa_end = pa_start + NBPDR;
5329 tmpva = trunc_2mpage(tmpva) + NBPDR;
5331 pte = pmap_pde_to_pte(pde, tmpva);
5332 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5333 pmap_pte_attr(pte, cache_bits_pte);
5336 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5337 if (pa_start == pa_end) {
5338 /* Start physical address run. */
5339 pa_start = *pte & PG_FRAME;
5340 pa_end = pa_start + PAGE_SIZE;
5341 } else if (pa_end == (*pte & PG_FRAME))
5342 pa_end += PAGE_SIZE;
5344 /* Run ended, update direct map. */
5345 error = pmap_change_attr_locked(
5346 PHYS_TO_DMAP(pa_start),
5347 pa_end - pa_start, mode);
5350 /* Start physical address run. */
5351 pa_start = *pte & PG_FRAME;
5352 pa_end = pa_start + PAGE_SIZE;
5358 if (error == 0 && pa_start != pa_end)
5359 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
5360 pa_end - pa_start, mode);
5363 * Flush CPU caches if required to make sure any data isn't cached that
5364 * shouldn't be, etc.
5367 pmap_invalidate_range(kernel_pmap, base, tmpva);
5368 pmap_invalidate_cache_range(base, tmpva);
5374 * Demotes any mapping within the direct map region that covers more than the
5375 * specified range of physical addresses. This range's size must be a power
5376 * of two and its starting address must be a multiple of its size. Since the
5377 * demotion does not change any attributes of the mapping, a TLB invalidation
5378 * is not mandatory. The caller may, however, request a TLB invalidation.
5381 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
5390 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
5391 KASSERT((base & (len - 1)) == 0,
5392 ("pmap_demote_DMAP: base is not a multiple of len"));
5393 if (len < NBPDP && base < dmaplimit) {
5394 va = PHYS_TO_DMAP(base);
5396 PMAP_LOCK(kernel_pmap);
5397 pdpe = pmap_pdpe(kernel_pmap, va);
5398 if ((*pdpe & PG_V) == 0)
5399 panic("pmap_demote_DMAP: invalid PDPE");
5400 if ((*pdpe & PG_PS) != 0) {
5401 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
5402 panic("pmap_demote_DMAP: PDPE failed");
5406 pde = pmap_pdpe_to_pde(pdpe, va);
5407 if ((*pde & PG_V) == 0)
5408 panic("pmap_demote_DMAP: invalid PDE");
5409 if ((*pde & PG_PS) != 0) {
5410 if (!pmap_demote_pde(kernel_pmap, pde, va))
5411 panic("pmap_demote_DMAP: PDE failed");
5415 if (changed && invalidate)
5416 pmap_invalidate_page(kernel_pmap, va);
5417 PMAP_UNLOCK(kernel_pmap);
5422 * perform the pmap work for mincore
5425 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5434 pdep = pmap_pde(pmap, addr);
5435 if (pdep != NULL && (*pdep & PG_V)) {
5436 if (*pdep & PG_PS) {
5438 /* Compute the physical address of the 4KB page. */
5439 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5441 val = MINCORE_SUPER;
5443 pte = *pmap_pde_to_pte(pdep, addr);
5444 pa = pte & PG_FRAME;
5452 if ((pte & PG_V) != 0) {
5453 val |= MINCORE_INCORE;
5454 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5455 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5456 if ((pte & PG_A) != 0)
5457 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5459 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5460 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5461 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5462 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5463 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5466 PA_UNLOCK_COND(*locked_pa);
5472 pmap_activate(struct thread *td)
5474 pmap_t pmap, oldpmap;
5479 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5480 oldpmap = PCPU_GET(curpmap);
5481 cpuid = PCPU_GET(cpuid);
5483 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5484 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5486 CPU_CLR(cpuid, &oldpmap->pm_active);
5487 CPU_SET(cpuid, &pmap->pm_active);
5489 cr3 = DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4);
5490 td->td_pcb->pcb_cr3 = cr3;
5492 PCPU_SET(curpmap, pmap);
5497 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5502 * Increase the starting virtual address of the given mapping if a
5503 * different alignment might result in more superpage mappings.
5506 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5507 vm_offset_t *addr, vm_size_t size)
5509 vm_offset_t superpage_offset;
5513 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5514 offset += ptoa(object->pg_color);
5515 superpage_offset = offset & PDRMASK;
5516 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5517 (*addr & PDRMASK) == superpage_offset)
5519 if ((*addr & PDRMASK) < superpage_offset)
5520 *addr = (*addr & ~PDRMASK) + superpage_offset;
5522 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5525 #include "opt_ddb.h"
5527 #include <ddb/ddb.h>
5529 DB_SHOW_COMMAND(pte, pmap_print_pte)
5539 va = (vm_offset_t)addr;
5540 pmap = PCPU_GET(curpmap); /* XXX */
5542 db_printf("show pte addr\n");
5545 pml4 = pmap_pml4e(pmap, va);
5546 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
5547 if ((*pml4 & PG_V) == 0) {
5551 pdp = pmap_pml4e_to_pdpe(pml4, va);
5552 db_printf(" pdpe %#016lx", *pdp);
5553 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
5557 pde = pmap_pdpe_to_pde(pdp, va);
5558 db_printf(" pde %#016lx", *pde);
5559 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
5563 pte = pmap_pde_to_pte(pde, va);
5564 db_printf(" pte %#016lx\n", *pte);
5567 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
5572 a = (vm_paddr_t)addr;
5573 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
5575 db_printf("show phys2dmap addr\n");