2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * In addition to hardware address maps, this
86 * module is called upon to provide software-use-only
87 * maps which may or may not be stored in the same
88 * form as hardware maps. These pseudo-maps are
89 * used to store intermediate results from copy
90 * operations to and from address spaces.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include "opt_pmap.h"
111 #include <sys/param.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/rwlock.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
129 #include <sys/cpuset.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_reserv.h>
144 #include <machine/intr_machdep.h>
145 #include <machine/apicvar.h>
146 #include <machine/cpu.h>
147 #include <machine/cputypes.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
150 #include <machine/specialreg.h>
152 #include <machine/smp.h>
155 #if !defined(DIAGNOSTIC)
156 #ifdef __GNUC_GNU_INLINE__
157 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
159 #define PMAP_INLINE extern inline
166 #define PV_STAT(x) do { x ; } while (0)
168 #define PV_STAT(x) do { } while (0)
171 #define pa_index(pa) ((pa) >> PDRSHIFT)
172 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
174 #define NPV_LIST_LOCKS MAXCPU
176 #define PHYS_TO_PV_LIST_LOCK(pa) \
177 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
179 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
180 struct rwlock **_lockp = (lockp); \
181 struct rwlock *_new_lock; \
183 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
184 if (_new_lock != *_lockp) { \
185 if (*_lockp != NULL) \
186 rw_wunlock(*_lockp); \
187 *_lockp = _new_lock; \
192 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
193 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
195 #define RELEASE_PV_LIST_LOCK(lockp) do { \
196 struct rwlock **_lockp = (lockp); \
198 if (*_lockp != NULL) { \
199 rw_wunlock(*_lockp); \
204 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
205 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
207 struct pmap kernel_pmap_store;
209 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
210 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
213 vm_paddr_t dmaplimit;
214 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
217 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
219 static int pat_works = 1;
220 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
221 "Is page attribute table fully functional?");
223 static int pg_ps_enabled = 1;
224 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
225 "Are large page mappings enabled?");
227 #define PAT_INDEX_SIZE 8
228 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
231 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
232 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
233 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
235 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
236 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
239 * Isolate the global pv list lock from data and other locks to prevent false
240 * sharing within the cache.
244 char padding[CACHE_LINE_SIZE - sizeof(struct rwlock)];
245 } pvh_global __aligned(CACHE_LINE_SIZE);
247 #define pvh_global_lock pvh_global.lock
250 * Data for the pv entry allocation mechanism
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static struct mtx pv_chunks_mutex;
254 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
255 static struct md_page *pv_table;
258 * All those kernel PT submaps that BSD is so fond of
260 pt_entry_t *CMAP1 = 0;
266 static caddr_t crashdumpmap;
268 static void free_pv_chunk(struct pv_chunk *pc);
269 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
270 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
271 static int popcnt_pc_map_elem(uint64_t elem);
272 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
273 static void reserve_pv_entries(pmap_t pmap, int needed,
274 struct rwlock **lockp);
275 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
276 struct rwlock **lockp);
277 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
278 struct rwlock **lockp);
279 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
280 struct rwlock **lockp);
281 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
282 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
284 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
286 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
287 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
288 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
289 vm_offset_t va, struct rwlock **lockp);
290 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
292 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
293 vm_prot_t prot, struct rwlock **lockp);
294 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
295 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
296 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
297 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
298 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
299 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
300 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
301 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
302 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
303 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
304 struct rwlock **lockp);
305 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
307 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
308 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
309 vm_page_t *free, struct rwlock **lockp);
310 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq,
311 vm_offset_t sva, pd_entry_t ptepde, vm_page_t *free,
312 struct rwlock **lockp);
313 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
314 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
316 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
317 vm_page_t m, struct rwlock **lockp);
318 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
320 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
322 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
323 struct rwlock **lockp);
324 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
325 struct rwlock **lockp);
326 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
327 struct rwlock **lockp);
329 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
331 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, vm_page_t *);
332 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
334 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
335 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
338 * Move the kernel virtual free pointer to the next
339 * 2MB. This is used to help improve performance
340 * by using a large (2MB) page for much of the kernel
341 * (.text, .data, .bss)
344 pmap_kmem_choose(vm_offset_t addr)
346 vm_offset_t newaddr = addr;
348 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
352 /********************/
353 /* Inline functions */
354 /********************/
356 /* Return a non-clipped PD index for a given VA */
357 static __inline vm_pindex_t
358 pmap_pde_pindex(vm_offset_t va)
360 return (va >> PDRSHIFT);
364 /* Return various clipped indexes for a given VA */
365 static __inline vm_pindex_t
366 pmap_pte_index(vm_offset_t va)
369 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
372 static __inline vm_pindex_t
373 pmap_pde_index(vm_offset_t va)
376 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
379 static __inline vm_pindex_t
380 pmap_pdpe_index(vm_offset_t va)
383 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
386 static __inline vm_pindex_t
387 pmap_pml4e_index(vm_offset_t va)
390 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
393 /* Return a pointer to the PML4 slot that corresponds to a VA */
394 static __inline pml4_entry_t *
395 pmap_pml4e(pmap_t pmap, vm_offset_t va)
398 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
401 /* Return a pointer to the PDP slot that corresponds to a VA */
402 static __inline pdp_entry_t *
403 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
407 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
408 return (&pdpe[pmap_pdpe_index(va)]);
411 /* Return a pointer to the PDP slot that corresponds to a VA */
412 static __inline pdp_entry_t *
413 pmap_pdpe(pmap_t pmap, vm_offset_t va)
417 pml4e = pmap_pml4e(pmap, va);
418 if ((*pml4e & PG_V) == 0)
420 return (pmap_pml4e_to_pdpe(pml4e, va));
423 /* Return a pointer to the PD slot that corresponds to a VA */
424 static __inline pd_entry_t *
425 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
429 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
430 return (&pde[pmap_pde_index(va)]);
433 /* Return a pointer to the PD slot that corresponds to a VA */
434 static __inline pd_entry_t *
435 pmap_pde(pmap_t pmap, vm_offset_t va)
439 pdpe = pmap_pdpe(pmap, va);
440 if (pdpe == NULL || (*pdpe & PG_V) == 0)
442 return (pmap_pdpe_to_pde(pdpe, va));
445 /* Return a pointer to the PT slot that corresponds to a VA */
446 static __inline pt_entry_t *
447 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
451 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
452 return (&pte[pmap_pte_index(va)]);
455 /* Return a pointer to the PT slot that corresponds to a VA */
456 static __inline pt_entry_t *
457 pmap_pte(pmap_t pmap, vm_offset_t va)
461 pde = pmap_pde(pmap, va);
462 if (pde == NULL || (*pde & PG_V) == 0)
464 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
465 return ((pt_entry_t *)pde);
466 return (pmap_pde_to_pte(pde, va));
470 pmap_resident_count_inc(pmap_t pmap, int count)
473 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
474 pmap->pm_stats.resident_count += count;
478 pmap_resident_count_dec(pmap_t pmap, int count)
481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
482 KASSERT(pmap->pm_stats.resident_count >= count,
483 ("pmap %p resident count underflow %ld %d", pmap,
484 pmap->pm_stats.resident_count, count));
485 pmap->pm_stats.resident_count -= count;
488 PMAP_INLINE pt_entry_t *
489 vtopte(vm_offset_t va)
491 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
493 return (PTmap + ((va >> PAGE_SHIFT) & mask));
496 static __inline pd_entry_t *
497 vtopde(vm_offset_t va)
499 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
501 return (PDmap + ((va >> PDRSHIFT) & mask));
505 allocpages(vm_paddr_t *firstaddr, int n)
510 bzero((void *)ret, n * PAGE_SIZE);
511 *firstaddr += n * PAGE_SIZE;
515 CTASSERT(powerof2(NDMPML4E));
518 create_pagetables(vm_paddr_t *firstaddr)
523 KPTphys = allocpages(firstaddr, NKPT);
524 KPML4phys = allocpages(firstaddr, 1);
525 KPDPphys = allocpages(firstaddr, NKPML4E);
526 KPDphys = allocpages(firstaddr, NKPDPE);
528 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
529 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
531 DMPDPphys = allocpages(firstaddr, NDMPML4E);
533 if ((amd_feature & AMDID_PAGE1GB) != 0)
534 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
536 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
537 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
539 /* Fill in the underlying page table pages */
540 /* Read-only from zero to physfree */
541 /* XXX not fully used, underneath 2M pages */
542 for (i = 0; (i << PAGE_SHIFT) < *firstaddr; i++) {
543 ((pt_entry_t *)KPTphys)[i] = i << PAGE_SHIFT;
544 ((pt_entry_t *)KPTphys)[i] |= PG_RW | PG_V | PG_G;
547 /* Now map the page tables at their location within PTmap */
548 for (i = 0; i < NKPT; i++) {
549 ((pd_entry_t *)KPDphys)[i] = KPTphys + (i << PAGE_SHIFT);
550 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V;
553 /* Map from zero to end of allocations under 2M pages */
554 /* This replaces some of the KPTphys entries above */
555 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++) {
556 ((pd_entry_t *)KPDphys)[i] = i << PDRSHIFT;
557 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V | PG_PS | PG_G;
560 /* And connect up the PD to the PDP */
561 for (i = 0; i < NKPDPE; i++) {
562 ((pdp_entry_t *)KPDPphys)[i + KPDPI] = KPDphys +
564 ((pdp_entry_t *)KPDPphys)[i + KPDPI] |= PG_RW | PG_V | PG_U;
568 * Now, set up the direct map region using 2MB and/or 1GB pages. If
569 * the end of physical memory is not aligned to a 1GB page boundary,
570 * then the residual physical memory is mapped with 2MB pages. Later,
571 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
572 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
573 * that are partially used.
575 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
576 ((pd_entry_t *)DMPDphys)[j] = (vm_paddr_t)i << PDRSHIFT;
577 /* Preset PG_M and PG_A because demotion expects it. */
578 ((pd_entry_t *)DMPDphys)[j] |= PG_RW | PG_V | PG_PS | PG_G |
581 for (i = 0; i < ndm1g; i++) {
582 ((pdp_entry_t *)DMPDPphys)[i] = (vm_paddr_t)i << PDPSHIFT;
583 /* Preset PG_M and PG_A because demotion expects it. */
584 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_PS | PG_G |
587 for (j = 0; i < ndmpdp; i++, j++) {
588 ((pdp_entry_t *)DMPDPphys)[i] = DMPDphys + (j << PAGE_SHIFT);
589 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_U;
592 /* And recursively map PML4 to itself in order to get PTmap */
593 ((pdp_entry_t *)KPML4phys)[PML4PML4I] = KPML4phys;
594 ((pdp_entry_t *)KPML4phys)[PML4PML4I] |= PG_RW | PG_V | PG_U;
596 /* Connect the Direct Map slot(s) up to the PML4. */
597 for (i = 0; i < NDMPML4E; i++) {
598 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] = DMPDPphys +
600 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] |= PG_RW | PG_V | PG_U;
603 /* Connect the KVA slot up to the PML4 */
604 ((pdp_entry_t *)KPML4phys)[KPML4I] = KPDPphys;
605 ((pdp_entry_t *)KPML4phys)[KPML4I] |= PG_RW | PG_V | PG_U;
609 * Bootstrap the system enough to run with virtual memory.
611 * On amd64 this is called after mapping has already been enabled
612 * and just syncs the pmap module with what has already been done.
613 * [We can't call it easily with mapping off since the kernel is not
614 * mapped with PA == VA, hence we would have to relocate every address
615 * from the linked base (virtual) address "KERNBASE" to the actual
616 * (physical) address starting relative to 0]
619 pmap_bootstrap(vm_paddr_t *firstaddr)
622 pt_entry_t *pte, *unused;
625 * Create an initial set of page tables to run the kernel in.
627 create_pagetables(firstaddr);
629 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
630 virtual_avail = pmap_kmem_choose(virtual_avail);
632 virtual_end = VM_MAX_KERNEL_ADDRESS;
635 /* XXX do %cr0 as well */
636 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
638 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
639 load_cr4(rcr4() | CR4_SMEP);
642 * Initialize the kernel pmap (which is statically allocated).
644 PMAP_LOCK_INIT(kernel_pmap);
645 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
646 kernel_pmap->pm_root = NULL;
647 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
648 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
651 * Initialize the global pv list lock.
653 rw_init(&pvh_global_lock, "pmap pv global");
656 * Reserve some special page table entries/VA space for temporary
659 #define SYSMAP(c, p, v, n) \
660 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
666 * CMAP1 is only used for the memory test.
668 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
673 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
677 /* Initialize the PAT MSR. */
687 int pat_table[PAT_INDEX_SIZE];
692 /* Bail if this CPU doesn't implement PAT. */
693 if ((cpu_feature & CPUID_PAT) == 0)
696 /* Set default PAT index table. */
697 for (i = 0; i < PAT_INDEX_SIZE; i++)
699 pat_table[PAT_WRITE_BACK] = 0;
700 pat_table[PAT_WRITE_THROUGH] = 1;
701 pat_table[PAT_UNCACHEABLE] = 3;
702 pat_table[PAT_WRITE_COMBINING] = 3;
703 pat_table[PAT_WRITE_PROTECTED] = 3;
704 pat_table[PAT_UNCACHED] = 3;
706 /* Initialize default PAT entries. */
707 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
708 PAT_VALUE(1, PAT_WRITE_THROUGH) |
709 PAT_VALUE(2, PAT_UNCACHED) |
710 PAT_VALUE(3, PAT_UNCACHEABLE) |
711 PAT_VALUE(4, PAT_WRITE_BACK) |
712 PAT_VALUE(5, PAT_WRITE_THROUGH) |
713 PAT_VALUE(6, PAT_UNCACHED) |
714 PAT_VALUE(7, PAT_UNCACHEABLE);
718 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
719 * Program 5 and 6 as WP and WC.
720 * Leave 4 and 7 as WB and UC.
722 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
723 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
724 PAT_VALUE(6, PAT_WRITE_COMBINING);
725 pat_table[PAT_UNCACHED] = 2;
726 pat_table[PAT_WRITE_PROTECTED] = 5;
727 pat_table[PAT_WRITE_COMBINING] = 6;
730 * Just replace PAT Index 2 with WC instead of UC-.
732 pat_msr &= ~PAT_MASK(2);
733 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
734 pat_table[PAT_WRITE_COMBINING] = 2;
739 load_cr4(cr4 & ~CR4_PGE);
741 /* Disable caches (CD = 1, NW = 0). */
743 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
745 /* Flushes caches and TLBs. */
749 /* Update PAT and index table. */
750 wrmsr(MSR_PAT, pat_msr);
751 for (i = 0; i < PAT_INDEX_SIZE; i++)
752 pat_index[i] = pat_table[i];
754 /* Flush caches and TLBs again. */
758 /* Restore caches and PGE. */
764 * Initialize a vm_page's machine-dependent fields.
767 pmap_page_init(vm_page_t m)
770 TAILQ_INIT(&m->md.pv_list);
771 m->md.pat_mode = PAT_WRITE_BACK;
775 * Initialize the pmap module.
776 * Called by vm_init, to initialize any structures that the pmap
777 * system needs to map virtual memory.
787 * Initialize the vm page array entries for the kernel pmap's
790 for (i = 0; i < NKPT; i++) {
791 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
792 KASSERT(mpte >= vm_page_array &&
793 mpte < &vm_page_array[vm_page_array_size],
794 ("pmap_init: page table page is out of range"));
795 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
796 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
800 * If the kernel is running on a virtual machine, then it must assume
801 * that MCA is enabled by the hypervisor. Moreover, the kernel must
802 * be prepared for the hypervisor changing the vendor and family that
803 * are reported by CPUID. Consequently, the workaround for AMD Family
804 * 10h Erratum 383 is enabled if the processor's feature set does not
805 * include at least one feature that is only supported by older Intel
806 * or newer AMD processors.
808 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
809 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
810 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
812 workaround_erratum383 = 1;
815 * Are large page mappings enabled?
817 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
819 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
820 ("pmap_init: can't assign to pagesizes[1]"));
821 pagesizes[1] = NBPDR;
825 * Initialize the pv chunk list mutex.
827 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
830 * Initialize the pool of pv list locks.
832 for (i = 0; i < NPV_LIST_LOCKS; i++)
833 rw_init(&pv_list_locks[i], "pmap pv list");
836 * Calculate the size of the pv head table for superpages.
838 for (i = 0; phys_avail[i + 1]; i += 2);
839 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
842 * Allocate memory for the pv head table for superpages.
844 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
846 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
847 for (i = 0; i < pv_npg; i++)
848 TAILQ_INIT(&pv_table[i].pv_list);
851 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
852 "2MB page mapping counters");
854 static u_long pmap_pde_demotions;
855 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
856 &pmap_pde_demotions, 0, "2MB page demotions");
858 static u_long pmap_pde_mappings;
859 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
860 &pmap_pde_mappings, 0, "2MB page mappings");
862 static u_long pmap_pde_p_failures;
863 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
864 &pmap_pde_p_failures, 0, "2MB page promotion failures");
866 static u_long pmap_pde_promotions;
867 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
868 &pmap_pde_promotions, 0, "2MB page promotions");
870 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
871 "1GB page mapping counters");
873 static u_long pmap_pdpe_demotions;
874 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
875 &pmap_pdpe_demotions, 0, "1GB page demotions");
877 /***************************************************
878 * Low level helper routines.....
879 ***************************************************/
882 * Determine the appropriate bits to set in a PTE or PDE for a specified
886 pmap_cache_bits(int mode, boolean_t is_pde)
888 int cache_bits, pat_flag, pat_idx;
890 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
891 panic("Unknown caching mode %d\n", mode);
893 /* The PAT bit is different for PTE's and PDE's. */
894 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
896 /* Map the caching mode to a PAT index. */
897 pat_idx = pat_index[mode];
899 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
902 cache_bits |= pat_flag;
904 cache_bits |= PG_NC_PCD;
906 cache_bits |= PG_NC_PWT;
911 * After changing the page size for the specified virtual address in the page
912 * table, flush the corresponding entries from the processor's TLB. Only the
913 * calling processor's TLB is affected.
915 * The calling thread must be pinned to a processor.
918 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
922 if ((newpde & PG_PS) == 0)
923 /* Demotion: flush a specific 2MB page mapping. */
925 else if ((newpde & PG_G) == 0)
927 * Promotion: flush every 4KB page mapping from the TLB
928 * because there are too many to flush individually.
933 * Promotion: flush every 4KB page mapping from the TLB,
934 * including any global (PG_G) mappings.
937 load_cr4(cr4 & ~CR4_PGE);
939 * Although preemption at this point could be detrimental to
940 * performance, it would not lead to an error. PG_G is simply
941 * ignored if CR4.PGE is clear. Moreover, in case this block
942 * is re-entered, the load_cr4() either above or below will
943 * modify CR4.PGE flushing the TLB.
945 load_cr4(cr4 | CR4_PGE);
950 * For SMP, these functions have to use the IPI mechanism for coherence.
952 * N.B.: Before calling any of the following TLB invalidation functions,
953 * the calling processor must ensure that all stores updating a non-
954 * kernel page table are globally performed. Otherwise, another
955 * processor could cache an old, pre-update entry without being
956 * invalidated. This can happen one of two ways: (1) The pmap becomes
957 * active on another processor after its pm_active field is checked by
958 * one of the following functions but before a store updating the page
959 * table is globally performed. (2) The pmap becomes active on another
960 * processor before its pm_active field is checked but due to
961 * speculative loads one of the following functions stills reads the
962 * pmap as inactive on the other processor.
964 * The kernel page table is exempt because its pm_active field is
965 * immutable. The kernel page table is always active on every
969 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
975 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
979 cpuid = PCPU_GET(cpuid);
980 other_cpus = all_cpus;
981 CPU_CLR(cpuid, &other_cpus);
982 if (CPU_ISSET(cpuid, &pmap->pm_active))
984 CPU_AND(&other_cpus, &pmap->pm_active);
985 if (!CPU_EMPTY(&other_cpus))
986 smp_masked_invlpg(other_cpus, va);
992 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
999 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1000 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1002 smp_invlpg_range(sva, eva);
1004 cpuid = PCPU_GET(cpuid);
1005 other_cpus = all_cpus;
1006 CPU_CLR(cpuid, &other_cpus);
1007 if (CPU_ISSET(cpuid, &pmap->pm_active))
1008 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1010 CPU_AND(&other_cpus, &pmap->pm_active);
1011 if (!CPU_EMPTY(&other_cpus))
1012 smp_masked_invlpg_range(other_cpus, sva, eva);
1018 pmap_invalidate_all(pmap_t pmap)
1020 cpuset_t other_cpus;
1024 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1028 cpuid = PCPU_GET(cpuid);
1029 other_cpus = all_cpus;
1030 CPU_CLR(cpuid, &other_cpus);
1031 if (CPU_ISSET(cpuid, &pmap->pm_active))
1033 CPU_AND(&other_cpus, &pmap->pm_active);
1034 if (!CPU_EMPTY(&other_cpus))
1035 smp_masked_invltlb(other_cpus);
1041 pmap_invalidate_cache(void)
1051 cpuset_t invalidate; /* processors that invalidate their TLB */
1055 u_int store; /* processor that updates the PDE */
1059 pmap_update_pde_action(void *arg)
1061 struct pde_action *act = arg;
1063 if (act->store == PCPU_GET(cpuid))
1064 pde_store(act->pde, act->newpde);
1068 pmap_update_pde_teardown(void *arg)
1070 struct pde_action *act = arg;
1072 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1073 pmap_update_pde_invalidate(act->va, act->newpde);
1077 * Change the page size for the specified virtual address in a way that
1078 * prevents any possibility of the TLB ever having two entries that map the
1079 * same virtual address using different page sizes. This is the recommended
1080 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1081 * machine check exception for a TLB state that is improperly diagnosed as a
1085 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1087 struct pde_action act;
1088 cpuset_t active, other_cpus;
1092 cpuid = PCPU_GET(cpuid);
1093 other_cpus = all_cpus;
1094 CPU_CLR(cpuid, &other_cpus);
1095 if (pmap == kernel_pmap)
1098 active = pmap->pm_active;
1099 if (CPU_OVERLAP(&active, &other_cpus)) {
1101 act.invalidate = active;
1104 act.newpde = newpde;
1105 CPU_SET(cpuid, &active);
1106 smp_rendezvous_cpus(active,
1107 smp_no_rendevous_barrier, pmap_update_pde_action,
1108 pmap_update_pde_teardown, &act);
1110 pde_store(pde, newpde);
1111 if (CPU_ISSET(cpuid, &active))
1112 pmap_update_pde_invalidate(va, newpde);
1118 * Normal, non-SMP, invalidation functions.
1119 * We inline these within pmap.c for speed.
1122 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1125 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1130 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1134 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1135 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1140 pmap_invalidate_all(pmap_t pmap)
1143 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1148 pmap_invalidate_cache(void)
1155 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1158 pde_store(pde, newpde);
1159 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1160 pmap_update_pde_invalidate(va, newpde);
1164 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1167 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1170 KASSERT((sva & PAGE_MASK) == 0,
1171 ("pmap_invalidate_cache_range: sva not page-aligned"));
1172 KASSERT((eva & PAGE_MASK) == 0,
1173 ("pmap_invalidate_cache_range: eva not page-aligned"));
1175 if (cpu_feature & CPUID_SS)
1176 ; /* If "Self Snoop" is supported, do nothing. */
1177 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1178 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1181 * XXX: Some CPUs fault, hang, or trash the local APIC
1182 * registers if we use CLFLUSH on the local APIC
1183 * range. The local APIC is always uncached, so we
1184 * don't need to flush for that range anyway.
1186 if (pmap_kextract(sva) == lapic_paddr)
1190 * Otherwise, do per-cache line flush. Use the mfence
1191 * instruction to insure that previous stores are
1192 * included in the write-back. The processor
1193 * propagates flush to other processors in the cache
1197 for (; sva < eva; sva += cpu_clflush_line_size)
1203 * No targeted cache flush methods are supported by CPU,
1204 * or the supplied range is bigger than 2MB.
1205 * Globally invalidate cache.
1207 pmap_invalidate_cache();
1212 * Remove the specified set of pages from the data and instruction caches.
1214 * In contrast to pmap_invalidate_cache_range(), this function does not
1215 * rely on the CPU's self-snoop feature, because it is intended for use
1216 * when moving pages into a different cache domain.
1219 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1221 vm_offset_t daddr, eva;
1224 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1225 (cpu_feature & CPUID_CLFSH) == 0)
1226 pmap_invalidate_cache();
1229 for (i = 0; i < count; i++) {
1230 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1231 eva = daddr + PAGE_SIZE;
1232 for (; daddr < eva; daddr += cpu_clflush_line_size)
1240 * Routine: pmap_extract
1242 * Extract the physical page address associated
1243 * with the given map/virtual_address pair.
1246 pmap_extract(pmap_t pmap, vm_offset_t va)
1255 pdpe = pmap_pdpe(pmap, va);
1256 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1257 if ((*pdpe & PG_PS) != 0)
1258 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1260 pde = pmap_pdpe_to_pde(pdpe, va);
1261 if ((*pde & PG_V) != 0) {
1262 if ((*pde & PG_PS) != 0) {
1263 pa = (*pde & PG_PS_FRAME) |
1266 pte = pmap_pde_to_pte(pde, va);
1267 pa = (*pte & PG_FRAME) |
1278 * Routine: pmap_extract_and_hold
1280 * Atomically extract and hold the physical page
1281 * with the given pmap and virtual address pair
1282 * if that mapping permits the given protection.
1285 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1287 pd_entry_t pde, *pdep;
1296 pdep = pmap_pde(pmap, va);
1297 if (pdep != NULL && (pde = *pdep)) {
1299 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1300 if (vm_page_pa_tryrelock(pmap, (pde &
1301 PG_PS_FRAME) | (va & PDRMASK), &pa))
1303 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1308 pte = *pmap_pde_to_pte(pdep, va);
1310 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1311 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1314 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1325 pmap_kextract(vm_offset_t va)
1330 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1331 pa = DMAP_TO_PHYS(va);
1335 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1338 * Beware of a concurrent promotion that changes the
1339 * PDE at this point! For example, vtopte() must not
1340 * be used to access the PTE because it would use the
1341 * new PDE. It is, however, safe to use the old PDE
1342 * because the page table page is preserved by the
1345 pa = *pmap_pde_to_pte(&pde, va);
1346 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1352 /***************************************************
1353 * Low level mapping routines.....
1354 ***************************************************/
1357 * Add a wired page to the kva.
1358 * Note: not SMP coherent.
1361 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1366 pte_store(pte, pa | PG_RW | PG_V | PG_G);
1369 static __inline void
1370 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1375 pte_store(pte, pa | PG_RW | PG_V | PG_G | pmap_cache_bits(mode, 0));
1379 * Remove a page from the kernel pagetables.
1380 * Note: not SMP coherent.
1383 pmap_kremove(vm_offset_t va)
1392 * Used to map a range of physical addresses into kernel
1393 * virtual address space.
1395 * The value passed in '*virt' is a suggested virtual address for
1396 * the mapping. Architectures which can support a direct-mapped
1397 * physical to virtual region can return the appropriate address
1398 * within that region, leaving '*virt' unchanged. Other
1399 * architectures should map the pages starting at '*virt' and
1400 * update '*virt' with the first usable address after the mapped
1404 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1406 return PHYS_TO_DMAP(start);
1411 * Add a list of wired pages to the kva
1412 * this routine is only used for temporary
1413 * kernel mappings that do not need to have
1414 * page modification or references recorded.
1415 * Note that old mappings are simply written
1416 * over. The page *must* be wired.
1417 * Note: SMP coherent. Uses a ranged shootdown IPI.
1420 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1422 pt_entry_t *endpte, oldpte, pa, *pte;
1427 endpte = pte + count;
1428 while (pte < endpte) {
1430 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1431 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1433 pte_store(pte, pa | PG_G | PG_RW | PG_V);
1437 if (__predict_false((oldpte & PG_V) != 0))
1438 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1443 * This routine tears out page mappings from the
1444 * kernel -- it is meant only for temporary mappings.
1445 * Note: SMP coherent. Uses a ranged shootdown IPI.
1448 pmap_qremove(vm_offset_t sva, int count)
1453 while (count-- > 0) {
1454 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
1458 pmap_invalidate_range(kernel_pmap, sva, va);
1461 /***************************************************
1462 * Page table page management routines.....
1463 ***************************************************/
1464 static __inline void
1465 pmap_free_zero_pages(vm_page_t free)
1469 while (free != NULL) {
1472 /* Preserve the page's PG_ZERO setting. */
1473 vm_page_free_toq(m);
1478 * Schedule the specified unused page table page to be freed. Specifically,
1479 * add the page to the specified list of pages that will be released to the
1480 * physical memory manager after the TLB has been updated.
1482 static __inline void
1483 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1487 m->flags |= PG_ZERO;
1489 m->flags &= ~PG_ZERO;
1495 * Inserts the specified page table page into the specified pmap's collection
1496 * of idle page table pages. Each of a pmap's page table pages is responsible
1497 * for mapping a distinct range of virtual addresses. The pmap's collection is
1498 * ordered by this virtual address range.
1501 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1505 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1506 root = pmap->pm_root;
1511 root = vm_page_splay(mpte->pindex, root);
1512 if (mpte->pindex < root->pindex) {
1513 mpte->left = root->left;
1516 } else if (mpte->pindex == root->pindex)
1517 panic("pmap_insert_pt_page: pindex already inserted");
1519 mpte->right = root->right;
1524 pmap->pm_root = mpte;
1528 * Looks for a page table page mapping the specified virtual address in the
1529 * specified pmap's collection of idle page table pages. Returns NULL if there
1530 * is no page table page corresponding to the specified virtual address.
1533 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1536 vm_pindex_t pindex = pmap_pde_pindex(va);
1538 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1539 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1540 mpte = vm_page_splay(pindex, mpte);
1541 if ((pmap->pm_root = mpte)->pindex != pindex)
1548 * Removes the specified page table page from the specified pmap's collection
1549 * of idle page table pages. The specified page table page must be a member of
1550 * the pmap's collection.
1553 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1558 if (mpte != pmap->pm_root) {
1559 root = vm_page_splay(mpte->pindex, pmap->pm_root);
1560 KASSERT(mpte == root,
1561 ("pmap_remove_pt_page: mpte %p is missing from pmap %p",
1564 if (mpte->left == NULL)
1567 root = vm_page_splay(mpte->pindex, mpte->left);
1568 root->right = mpte->right;
1570 pmap->pm_root = root;
1574 * Decrements a page table page's wire count, which is used to record the
1575 * number of valid page table entries within the page. If the wire count
1576 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1577 * page table page was unmapped and FALSE otherwise.
1579 static inline boolean_t
1580 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t *free)
1584 if (m->wire_count == 0) {
1585 _pmap_unwire_ptp(pmap, va, m, free);
1592 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t *free)
1595 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1597 * unmap the page table page
1599 if (m->pindex >= (NUPDE + NUPDPE)) {
1602 pml4 = pmap_pml4e(pmap, va);
1604 } else if (m->pindex >= NUPDE) {
1607 pdp = pmap_pdpe(pmap, va);
1612 pd = pmap_pde(pmap, va);
1615 pmap_resident_count_dec(pmap, 1);
1616 if (m->pindex < NUPDE) {
1617 /* We just released a PT, unhold the matching PD */
1620 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
1621 pmap_unwire_ptp(pmap, va, pdpg, free);
1623 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
1624 /* We just released a PD, unhold the matching PDP */
1627 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
1628 pmap_unwire_ptp(pmap, va, pdppg, free);
1632 * This is a release store so that the ordinary store unmapping
1633 * the page table page is globally performed before TLB shoot-
1636 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1639 * Put page on a list so that it is released after
1640 * *ALL* TLB shootdown is done
1642 pmap_add_delayed_free_list(m, free, TRUE);
1646 * After removing a page table entry, this routine is used to
1647 * conditionally free the page, and manage the hold/wire counts.
1650 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, vm_page_t *free)
1654 if (va >= VM_MAXUSER_ADDRESS)
1656 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1657 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1658 return (pmap_unwire_ptp(pmap, va, mpte, free));
1662 pmap_pinit0(pmap_t pmap)
1665 PMAP_LOCK_INIT(pmap);
1666 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1667 pmap->pm_root = NULL;
1668 CPU_ZERO(&pmap->pm_active);
1669 PCPU_SET(curpmap, pmap);
1670 TAILQ_INIT(&pmap->pm_pvchunk);
1671 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1675 * Initialize a preallocated and zeroed pmap structure,
1676 * such as one in a vmspace structure.
1679 pmap_pinit(pmap_t pmap)
1684 PMAP_LOCK_INIT(pmap);
1687 * allocate the page directory page
1689 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1690 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1693 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
1695 if ((pml4pg->flags & PG_ZERO) == 0)
1696 pagezero(pmap->pm_pml4);
1698 /* Wire in kernel global address entries. */
1699 pmap->pm_pml4[KPML4I] = KPDPphys | PG_RW | PG_V | PG_U;
1700 for (i = 0; i < NDMPML4E; i++) {
1701 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + (i << PAGE_SHIFT)) |
1702 PG_RW | PG_V | PG_U;
1705 /* install self-referential address mapping entry(s) */
1706 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | PG_V | PG_RW | PG_A | PG_M;
1708 pmap->pm_root = NULL;
1709 CPU_ZERO(&pmap->pm_active);
1710 TAILQ_INIT(&pmap->pm_pvchunk);
1711 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1717 * This routine is called if the desired page table page does not exist.
1719 * If page table page allocation fails, this routine may sleep before
1720 * returning NULL. It sleeps only if a lock pointer was given.
1722 * Note: If a page allocation fails at page table level two or three,
1723 * one or two pages may be held during the wait, only to be released
1724 * afterwards. This conservative approach is easily argued to avoid
1728 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1730 vm_page_t m, pdppg, pdpg;
1732 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1735 * Allocate a page table page.
1737 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1738 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1739 if (lockp != NULL) {
1740 RELEASE_PV_LIST_LOCK(lockp);
1742 rw_runlock(&pvh_global_lock);
1744 rw_rlock(&pvh_global_lock);
1749 * Indicate the need to retry. While waiting, the page table
1750 * page may have been allocated.
1754 if ((m->flags & PG_ZERO) == 0)
1758 * Map the pagetable page into the process address space, if
1759 * it isn't already there.
1762 if (ptepindex >= (NUPDE + NUPDPE)) {
1764 vm_pindex_t pml4index;
1766 /* Wire up a new PDPE page */
1767 pml4index = ptepindex - (NUPDE + NUPDPE);
1768 pml4 = &pmap->pm_pml4[pml4index];
1769 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1771 } else if (ptepindex >= NUPDE) {
1772 vm_pindex_t pml4index;
1773 vm_pindex_t pdpindex;
1777 /* Wire up a new PDE page */
1778 pdpindex = ptepindex - NUPDE;
1779 pml4index = pdpindex >> NPML4EPGSHIFT;
1781 pml4 = &pmap->pm_pml4[pml4index];
1782 if ((*pml4 & PG_V) == 0) {
1783 /* Have to allocate a new pdp, recurse */
1784 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
1787 atomic_subtract_int(&cnt.v_wire_count, 1);
1788 vm_page_free_zero(m);
1792 /* Add reference to pdp page */
1793 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
1794 pdppg->wire_count++;
1796 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1798 /* Now find the pdp page */
1799 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1800 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1803 vm_pindex_t pml4index;
1804 vm_pindex_t pdpindex;
1809 /* Wire up a new PTE page */
1810 pdpindex = ptepindex >> NPDPEPGSHIFT;
1811 pml4index = pdpindex >> NPML4EPGSHIFT;
1813 /* First, find the pdp and check that its valid. */
1814 pml4 = &pmap->pm_pml4[pml4index];
1815 if ((*pml4 & PG_V) == 0) {
1816 /* Have to allocate a new pd, recurse */
1817 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1820 atomic_subtract_int(&cnt.v_wire_count, 1);
1821 vm_page_free_zero(m);
1824 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1825 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1827 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1828 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1829 if ((*pdp & PG_V) == 0) {
1830 /* Have to allocate a new pd, recurse */
1831 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1834 atomic_subtract_int(&cnt.v_wire_count,
1836 vm_page_free_zero(m);
1840 /* Add reference to the pd page */
1841 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
1845 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
1847 /* Now we know where the page directory page is */
1848 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
1849 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1852 pmap_resident_count_inc(pmap, 1);
1858 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1860 vm_pindex_t pdpindex, ptepindex;
1865 pdpe = pmap_pdpe(pmap, va);
1866 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1867 /* Add a reference to the pd page. */
1868 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
1871 /* Allocate a pd page. */
1872 ptepindex = pmap_pde_pindex(va);
1873 pdpindex = ptepindex >> NPDPEPGSHIFT;
1874 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
1875 if (pdpg == NULL && lockp != NULL)
1882 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1884 vm_pindex_t ptepindex;
1889 * Calculate pagetable page index
1891 ptepindex = pmap_pde_pindex(va);
1894 * Get the page directory entry
1896 pd = pmap_pde(pmap, va);
1899 * This supports switching from a 2MB page to a
1902 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
1903 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
1905 * Invalidation of the 2MB page mapping may have caused
1906 * the deallocation of the underlying PD page.
1913 * If the page table page is mapped, we just increment the
1914 * hold count, and activate it.
1916 if (pd != NULL && (*pd & PG_V) != 0) {
1917 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
1921 * Here if the pte page isn't mapped, or if it has been
1924 m = _pmap_allocpte(pmap, ptepindex, lockp);
1925 if (m == NULL && lockp != NULL)
1932 /***************************************************
1933 * Pmap allocation/deallocation routines.
1934 ***************************************************/
1937 * Release any resources held by the given physical map.
1938 * Called when a pmap initialized by pmap_pinit is being released.
1939 * Should only be called if the map contains no valid mappings.
1942 pmap_release(pmap_t pmap)
1947 KASSERT(pmap->pm_stats.resident_count == 0,
1948 ("pmap_release: pmap resident count %ld != 0",
1949 pmap->pm_stats.resident_count));
1950 KASSERT(pmap->pm_root == NULL,
1951 ("pmap_release: pmap has reserved page table page(s)"));
1953 m = PHYS_TO_VM_PAGE(pmap->pm_pml4[PML4PML4I] & PG_FRAME);
1955 pmap->pm_pml4[KPML4I] = 0; /* KVA */
1956 for (i = 0; i < NDMPML4E; i++) /* Direct Map */
1957 pmap->pm_pml4[DMPML4I + i] = 0;
1958 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
1961 atomic_subtract_int(&cnt.v_wire_count, 1);
1962 vm_page_free_zero(m);
1963 PMAP_LOCK_DESTROY(pmap);
1967 kvm_size(SYSCTL_HANDLER_ARGS)
1969 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1971 return sysctl_handle_long(oidp, &ksize, 0, req);
1973 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1974 0, 0, kvm_size, "LU", "Size of KVM");
1977 kvm_free(SYSCTL_HANDLER_ARGS)
1979 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1981 return sysctl_handle_long(oidp, &kfree, 0, req);
1983 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1984 0, 0, kvm_free, "LU", "Amount of KVM free");
1987 * grow the number of kernel page table entries, if needed
1990 pmap_growkernel(vm_offset_t addr)
1994 pd_entry_t *pde, newpdir;
1997 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2000 * Return if "addr" is within the range of kernel page table pages
2001 * that were preallocated during pmap bootstrap. Moreover, leave
2002 * "kernel_vm_end" and the kernel page table as they were.
2004 * The correctness of this action is based on the following
2005 * argument: vm_map_findspace() allocates contiguous ranges of the
2006 * kernel virtual address space. It calls this function if a range
2007 * ends after "kernel_vm_end". If the kernel is mapped between
2008 * "kernel_vm_end" and "addr", then the range cannot begin at
2009 * "kernel_vm_end". In fact, its beginning address cannot be less
2010 * than the kernel. Thus, there is no immediate need to allocate
2011 * any new kernel page table pages between "kernel_vm_end" and
2014 if (KERNBASE < addr && addr <= KERNBASE + NKPT * NBPDR)
2017 addr = roundup2(addr, NBPDR);
2018 if (addr - 1 >= kernel_map->max_offset)
2019 addr = kernel_map->max_offset;
2020 while (kernel_vm_end < addr) {
2021 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2022 if ((*pdpe & PG_V) == 0) {
2023 /* We need a new PDP entry */
2024 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2025 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2026 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2028 panic("pmap_growkernel: no memory to grow kernel");
2029 if ((nkpg->flags & PG_ZERO) == 0)
2030 pmap_zero_page(nkpg);
2031 paddr = VM_PAGE_TO_PHYS(nkpg);
2032 *pdpe = (pdp_entry_t)
2033 (paddr | PG_V | PG_RW | PG_A | PG_M);
2034 continue; /* try again */
2036 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2037 if ((*pde & PG_V) != 0) {
2038 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2039 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2040 kernel_vm_end = kernel_map->max_offset;
2046 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2047 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2050 panic("pmap_growkernel: no memory to grow kernel");
2051 if ((nkpg->flags & PG_ZERO) == 0)
2052 pmap_zero_page(nkpg);
2053 paddr = VM_PAGE_TO_PHYS(nkpg);
2054 newpdir = (pd_entry_t) (paddr | PG_V | PG_RW | PG_A | PG_M);
2055 pde_store(pde, newpdir);
2057 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2058 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2059 kernel_vm_end = kernel_map->max_offset;
2066 /***************************************************
2067 * page management routines.
2068 ***************************************************/
2070 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2071 CTASSERT(_NPCM == 3);
2072 CTASSERT(_NPCPV == 168);
2074 static __inline struct pv_chunk *
2075 pv_to_chunk(pv_entry_t pv)
2078 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2081 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2083 #define PC_FREE0 0xfffffffffffffffful
2084 #define PC_FREE1 0xfffffffffffffffful
2085 #define PC_FREE2 0x000000fffffffffful
2087 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2090 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2092 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2093 "Current number of pv entry chunks");
2094 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2095 "Current number of pv entry chunks allocated");
2096 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2097 "Current number of pv entry chunks frees");
2098 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2099 "Number of times tried to get a chunk page but failed.");
2101 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2102 static int pv_entry_spare;
2104 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2105 "Current number of pv entry frees");
2106 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2107 "Current number of pv entry allocs");
2108 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2109 "Current number of pv entries");
2110 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2111 "Current number of spare pv entries");
2115 * We are in a serious low memory condition. Resort to
2116 * drastic measures to free some pages so we can allocate
2117 * another pv entry chunk.
2119 * Returns NULL if PV entries were reclaimed from the specified pmap.
2121 * We do not, however, unmap 2mpages because subsequent accesses will
2122 * allocate per-page pv entries until repromotion occurs, thereby
2123 * exacerbating the shortage of free pv entries.
2126 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2128 struct pch new_tail;
2129 struct pv_chunk *pc;
2130 struct md_page *pvh;
2133 pt_entry_t *pte, tpte;
2136 vm_page_t free, m, m_pc;
2138 int bit, field, freed;
2140 rw_assert(&pvh_global_lock, RA_LOCKED);
2141 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2142 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2145 TAILQ_INIT(&new_tail);
2146 mtx_lock(&pv_chunks_mutex);
2147 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && free == NULL) {
2148 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2149 mtx_unlock(&pv_chunks_mutex);
2150 if (pmap != pc->pc_pmap) {
2152 pmap_invalidate_all(pmap);
2153 if (pmap != locked_pmap)
2157 /* Avoid deadlock and lock recursion. */
2158 if (pmap > locked_pmap) {
2159 RELEASE_PV_LIST_LOCK(lockp);
2161 } else if (pmap != locked_pmap &&
2162 !PMAP_TRYLOCK(pmap)) {
2164 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2165 mtx_lock(&pv_chunks_mutex);
2171 * Destroy every non-wired, 4 KB page mapping in the chunk.
2174 for (field = 0; field < _NPCM; field++) {
2175 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2176 inuse != 0; inuse &= ~(1UL << bit)) {
2178 pv = &pc->pc_pventry[field * 64 + bit];
2180 pde = pmap_pde(pmap, va);
2181 if ((*pde & PG_PS) != 0)
2183 pte = pmap_pde_to_pte(pde, va);
2184 if ((*pte & PG_W) != 0)
2186 tpte = pte_load_clear(pte);
2187 if ((tpte & PG_G) != 0)
2188 pmap_invalidate_page(pmap, va);
2189 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2190 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2192 if ((tpte & PG_A) != 0)
2193 vm_page_aflag_set(m, PGA_REFERENCED);
2194 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2195 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2196 if (TAILQ_EMPTY(&m->md.pv_list) &&
2197 (m->flags & PG_FICTITIOUS) == 0) {
2198 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2199 if (TAILQ_EMPTY(&pvh->pv_list)) {
2200 vm_page_aflag_clear(m,
2204 pc->pc_map[field] |= 1UL << bit;
2205 pmap_unuse_pt(pmap, va, *pde, &free);
2210 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2211 mtx_lock(&pv_chunks_mutex);
2214 /* Every freed mapping is for a 4 KB page. */
2215 pmap_resident_count_dec(pmap, freed);
2216 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2217 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2218 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2219 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2220 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2221 pc->pc_map[2] == PC_FREE2) {
2222 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2223 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2224 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2225 /* Entire chunk is free; return it. */
2226 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2227 dump_drop_page(m_pc->phys_addr);
2228 mtx_lock(&pv_chunks_mutex);
2231 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2232 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2233 mtx_lock(&pv_chunks_mutex);
2234 /* One freed pv entry in locked_pmap is sufficient. */
2235 if (pmap == locked_pmap)
2238 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2239 mtx_unlock(&pv_chunks_mutex);
2241 pmap_invalidate_all(pmap);
2242 if (pmap != locked_pmap)
2245 if (m_pc == NULL && free != NULL) {
2248 /* Recycle a freed page table page. */
2249 m_pc->wire_count = 1;
2250 atomic_add_int(&cnt.v_wire_count, 1);
2252 pmap_free_zero_pages(free);
2257 * free the pv_entry back to the free list
2260 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2262 struct pv_chunk *pc;
2263 int idx, field, bit;
2265 rw_assert(&pvh_global_lock, RA_LOCKED);
2266 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2267 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2268 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2269 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2270 pc = pv_to_chunk(pv);
2271 idx = pv - &pc->pc_pventry[0];
2274 pc->pc_map[field] |= 1ul << bit;
2275 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2276 pc->pc_map[2] != PC_FREE2) {
2277 /* 98% of the time, pc is already at the head of the list. */
2278 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2279 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2280 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2284 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2289 free_pv_chunk(struct pv_chunk *pc)
2293 mtx_lock(&pv_chunks_mutex);
2294 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2295 mtx_unlock(&pv_chunks_mutex);
2296 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2297 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2298 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2299 /* entire chunk is free, return it */
2300 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2301 dump_drop_page(m->phys_addr);
2302 vm_page_unwire(m, 0);
2307 * Returns a new PV entry, allocating a new PV chunk from the system when
2308 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2309 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2312 * The given PV list lock may be released.
2315 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2319 struct pv_chunk *pc;
2322 rw_assert(&pvh_global_lock, RA_LOCKED);
2323 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2324 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2326 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2328 for (field = 0; field < _NPCM; field++) {
2329 if (pc->pc_map[field]) {
2330 bit = bsfq(pc->pc_map[field]);
2334 if (field < _NPCM) {
2335 pv = &pc->pc_pventry[field * 64 + bit];
2336 pc->pc_map[field] &= ~(1ul << bit);
2337 /* If this was the last item, move it to tail */
2338 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2339 pc->pc_map[2] == 0) {
2340 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2341 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2344 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2345 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2349 /* No free items, allocate another chunk */
2350 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2353 if (lockp == NULL) {
2354 PV_STAT(pc_chunk_tryfail++);
2357 m = reclaim_pv_chunk(pmap, lockp);
2361 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2362 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2363 dump_add_page(m->phys_addr);
2364 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2366 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2367 pc->pc_map[1] = PC_FREE1;
2368 pc->pc_map[2] = PC_FREE2;
2369 mtx_lock(&pv_chunks_mutex);
2370 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2371 mtx_unlock(&pv_chunks_mutex);
2372 pv = &pc->pc_pventry[0];
2373 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2374 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2375 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2380 * Returns the number of one bits within the given PV chunk map element.
2383 popcnt_pc_map_elem(uint64_t elem)
2388 * This simple method of counting the one bits performs well because
2389 * the given element typically contains more zero bits than one bits.
2392 for (; elem != 0; elem &= elem - 1)
2398 * Ensure that the number of spare PV entries in the specified pmap meets or
2399 * exceeds the given count, "needed".
2401 * The given PV list lock may be released.
2404 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2406 struct pch new_tail;
2407 struct pv_chunk *pc;
2411 rw_assert(&pvh_global_lock, RA_LOCKED);
2412 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2413 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2416 * Newly allocated PV chunks must be stored in a private list until
2417 * the required number of PV chunks have been allocated. Otherwise,
2418 * reclaim_pv_chunk() could recycle one of these chunks. In
2419 * contrast, these chunks must be added to the pmap upon allocation.
2421 TAILQ_INIT(&new_tail);
2424 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2425 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
2426 free = popcnt_pc_map_elem(pc->pc_map[0]);
2427 free += popcnt_pc_map_elem(pc->pc_map[1]);
2428 free += popcnt_pc_map_elem(pc->pc_map[2]);
2430 free = popcntq(pc->pc_map[0]);
2431 free += popcntq(pc->pc_map[1]);
2432 free += popcntq(pc->pc_map[2]);
2437 if (avail >= needed)
2440 for (; avail < needed; avail += _NPCPV) {
2441 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2444 m = reclaim_pv_chunk(pmap, lockp);
2448 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2449 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2450 dump_add_page(m->phys_addr);
2451 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2453 pc->pc_map[0] = PC_FREE0;
2454 pc->pc_map[1] = PC_FREE1;
2455 pc->pc_map[2] = PC_FREE2;
2456 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2457 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2458 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2460 if (!TAILQ_EMPTY(&new_tail)) {
2461 mtx_lock(&pv_chunks_mutex);
2462 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2463 mtx_unlock(&pv_chunks_mutex);
2468 * First find and then remove the pv entry for the specified pmap and virtual
2469 * address from the specified pv list. Returns the pv entry if found and NULL
2470 * otherwise. This operation can be performed on pv lists for either 4KB or
2471 * 2MB page mappings.
2473 static __inline pv_entry_t
2474 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2478 rw_assert(&pvh_global_lock, RA_LOCKED);
2479 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2480 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2481 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2489 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2490 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2491 * entries for each of the 4KB page mappings.
2494 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2495 struct rwlock **lockp)
2497 struct md_page *pvh;
2498 struct pv_chunk *pc;
2500 vm_offset_t va_last;
2504 rw_assert(&pvh_global_lock, RA_LOCKED);
2505 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2506 KASSERT((pa & PDRMASK) == 0,
2507 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
2508 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2511 * Transfer the 2mpage's pv entry for this mapping to the first
2512 * page's pv list. Once this transfer begins, the pv list lock
2513 * must not be released until the last pv entry is reinstantiated.
2515 pvh = pa_to_pvh(pa);
2516 va = trunc_2mpage(va);
2517 pv = pmap_pvh_remove(pvh, pmap, va);
2518 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2519 m = PHYS_TO_VM_PAGE(pa);
2520 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2521 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2522 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
2523 va_last = va + NBPDR - PAGE_SIZE;
2525 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2526 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2527 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
2528 for (field = 0; field < _NPCM; field++) {
2529 while (pc->pc_map[field]) {
2530 bit = bsfq(pc->pc_map[field]);
2531 pc->pc_map[field] &= ~(1ul << bit);
2532 pv = &pc->pc_pventry[field * 64 + bit];
2536 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2537 ("pmap_pv_demote_pde: page %p is not managed", m));
2538 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2543 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2544 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2547 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2548 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2549 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2551 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
2552 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
2556 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2557 * replace the many pv entries for the 4KB page mappings by a single pv entry
2558 * for the 2MB page mapping.
2561 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2562 struct rwlock **lockp)
2564 struct md_page *pvh;
2566 vm_offset_t va_last;
2569 rw_assert(&pvh_global_lock, RA_LOCKED);
2570 KASSERT((pa & PDRMASK) == 0,
2571 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
2572 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2575 * Transfer the first page's pv entry for this mapping to the 2mpage's
2576 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2577 * a transfer avoids the possibility that get_pv_entry() calls
2578 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2579 * mappings that is being promoted.
2581 m = PHYS_TO_VM_PAGE(pa);
2582 va = trunc_2mpage(va);
2583 pv = pmap_pvh_remove(&m->md, pmap, va);
2584 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2585 pvh = pa_to_pvh(pa);
2586 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2587 /* Free the remaining NPTEPG - 1 pv entries. */
2588 va_last = va + NBPDR - PAGE_SIZE;
2592 pmap_pvh_free(&m->md, pmap, va);
2593 } while (va < va_last);
2597 * First find and then destroy the pv entry for the specified pmap and virtual
2598 * address. This operation can be performed on pv lists for either 4KB or 2MB
2602 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2606 pv = pmap_pvh_remove(pvh, pmap, va);
2607 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2608 free_pv_entry(pmap, pv);
2612 * Conditionally create the PV entry for a 4KB page mapping if the required
2613 * memory can be allocated without resorting to reclamation.
2616 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2617 struct rwlock **lockp)
2621 rw_assert(&pvh_global_lock, RA_LOCKED);
2622 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2623 /* Pass NULL instead of the lock pointer to disable reclamation. */
2624 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2626 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2627 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2634 * Conditionally create the PV entry for a 2MB page mapping if the required
2635 * memory can be allocated without resorting to reclamation.
2638 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2639 struct rwlock **lockp)
2641 struct md_page *pvh;
2644 rw_assert(&pvh_global_lock, RA_LOCKED);
2645 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2646 /* Pass NULL instead of the lock pointer to disable reclamation. */
2647 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2649 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2650 pvh = pa_to_pvh(pa);
2651 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2658 * Fills a page table page with mappings to consecutive physical pages.
2661 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2665 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2667 newpte += PAGE_SIZE;
2672 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
2673 * mapping is invalidated.
2676 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2678 struct rwlock *lock;
2682 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
2689 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
2690 struct rwlock **lockp)
2692 pd_entry_t newpde, oldpde;
2693 pt_entry_t *firstpte, newpte;
2695 vm_page_t free, mpte;
2697 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2699 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2700 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2701 mpte = pmap_lookup_pt_page(pmap, va);
2703 pmap_remove_pt_page(pmap, mpte);
2705 KASSERT((oldpde & PG_W) == 0,
2706 ("pmap_demote_pde: page table page for a wired mapping"
2710 * Invalidate the 2MB page mapping and return "failure" if the
2711 * mapping was never accessed or the allocation of the new
2712 * page table page fails. If the 2MB page mapping belongs to
2713 * the direct map region of the kernel's address space, then
2714 * the page allocation request specifies the highest possible
2715 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
2716 * normal. Page table pages are preallocated for every other
2717 * part of the kernel address space, so the direct map region
2718 * is the only part of the kernel address space that must be
2721 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2722 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
2723 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
2724 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2726 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
2728 pmap_invalidate_page(pmap, trunc_2mpage(va));
2729 pmap_free_zero_pages(free);
2730 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
2731 " in pmap %p", va, pmap);
2734 if (va < VM_MAXUSER_ADDRESS)
2735 pmap_resident_count_inc(pmap, 1);
2737 mptepa = VM_PAGE_TO_PHYS(mpte);
2738 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
2739 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2740 KASSERT((oldpde & PG_A) != 0,
2741 ("pmap_demote_pde: oldpde is missing PG_A"));
2742 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2743 ("pmap_demote_pde: oldpde is missing PG_M"));
2744 newpte = oldpde & ~PG_PS;
2745 if ((newpte & PG_PDE_PAT) != 0)
2746 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2749 * If the page table page is new, initialize it.
2751 if (mpte->wire_count == 1) {
2752 mpte->wire_count = NPTEPG;
2753 pmap_fill_ptp(firstpte, newpte);
2755 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2756 ("pmap_demote_pde: firstpte and newpte map different physical"
2760 * If the mapping has changed attributes, update the page table
2763 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2764 pmap_fill_ptp(firstpte, newpte);
2767 * The spare PV entries must be reserved prior to demoting the
2768 * mapping, that is, prior to changing the PDE. Otherwise, the state
2769 * of the PDE and the PV lists will be inconsistent, which can result
2770 * in reclaim_pv_chunk() attempting to remove a PV entry from the
2771 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
2772 * PV entry for the 2MB page mapping that is being demoted.
2774 if ((oldpde & PG_MANAGED) != 0)
2775 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
2778 * Demote the mapping. This pmap is locked. The old PDE has
2779 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2780 * set. Thus, there is no danger of a race with another
2781 * processor changing the setting of PG_A and/or PG_M between
2782 * the read above and the store below.
2784 if (workaround_erratum383)
2785 pmap_update_pde(pmap, va, pde, newpde);
2787 pde_store(pde, newpde);
2790 * Invalidate a stale recursive mapping of the page table page.
2792 if (va >= VM_MAXUSER_ADDRESS)
2793 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2796 * Demote the PV entry.
2798 if ((oldpde & PG_MANAGED) != 0)
2799 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
2801 atomic_add_long(&pmap_pde_demotions, 1);
2802 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
2803 " in pmap %p", va, pmap);
2808 * pmap_remove_pde: do the things to unmap a superpage in a process
2811 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2812 vm_page_t *free, struct rwlock **lockp)
2814 struct md_page *pvh;
2816 vm_offset_t eva, va;
2819 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2820 KASSERT((sva & PDRMASK) == 0,
2821 ("pmap_remove_pde: sva is not 2mpage aligned"));
2822 oldpde = pte_load_clear(pdq);
2824 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2827 * Machines that don't support invlpg, also don't support
2831 pmap_invalidate_page(kernel_pmap, sva);
2832 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
2833 if (oldpde & PG_MANAGED) {
2834 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
2835 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2836 pmap_pvh_free(pvh, pmap, sva);
2838 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2839 va < eva; va += PAGE_SIZE, m++) {
2840 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2843 vm_page_aflag_set(m, PGA_REFERENCED);
2844 if (TAILQ_EMPTY(&m->md.pv_list) &&
2845 TAILQ_EMPTY(&pvh->pv_list))
2846 vm_page_aflag_clear(m, PGA_WRITEABLE);
2849 if (pmap == kernel_pmap) {
2850 if (!pmap_demote_pde_locked(pmap, pdq, sva, lockp))
2851 panic("pmap_remove_pde: failed demotion");
2853 mpte = pmap_lookup_pt_page(pmap, sva);
2855 pmap_remove_pt_page(pmap, mpte);
2856 pmap_resident_count_dec(pmap, 1);
2857 KASSERT(mpte->wire_count == NPTEPG,
2858 ("pmap_remove_pde: pte page wire count error"));
2859 mpte->wire_count = 0;
2860 pmap_add_delayed_free_list(mpte, free, FALSE);
2861 atomic_subtract_int(&cnt.v_wire_count, 1);
2864 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
2868 * pmap_remove_pte: do the things to unmap a page in a process
2871 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2872 pd_entry_t ptepde, vm_page_t *free, struct rwlock **lockp)
2874 struct md_page *pvh;
2878 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2879 oldpte = pte_load_clear(ptq);
2881 pmap->pm_stats.wired_count -= 1;
2882 pmap_resident_count_dec(pmap, 1);
2883 if (oldpte & PG_MANAGED) {
2884 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2885 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2888 vm_page_aflag_set(m, PGA_REFERENCED);
2889 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2890 pmap_pvh_free(&m->md, pmap, va);
2891 if (TAILQ_EMPTY(&m->md.pv_list) &&
2892 (m->flags & PG_FICTITIOUS) == 0) {
2893 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2894 if (TAILQ_EMPTY(&pvh->pv_list))
2895 vm_page_aflag_clear(m, PGA_WRITEABLE);
2898 return (pmap_unuse_pt(pmap, va, ptepde, free));
2902 * Remove a single page from a process address space
2905 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, vm_page_t *free)
2907 struct rwlock *lock;
2910 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2911 if ((*pde & PG_V) == 0)
2913 pte = pmap_pde_to_pte(pde, va);
2914 if ((*pte & PG_V) == 0)
2917 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
2920 pmap_invalidate_page(pmap, va);
2924 * Remove the given range of addresses from the specified map.
2926 * It is assumed that the start and end are properly
2927 * rounded to the page size.
2930 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2932 struct rwlock *lock;
2933 vm_offset_t va, va_next;
2934 pml4_entry_t *pml4e;
2936 pd_entry_t ptpaddr, *pde;
2938 vm_page_t free = NULL;
2942 * Perform an unsynchronized read. This is, however, safe.
2944 if (pmap->pm_stats.resident_count == 0)
2949 rw_rlock(&pvh_global_lock);
2953 * special handling of removing one page. a very
2954 * common operation and easy to short circuit some
2957 if (sva + PAGE_SIZE == eva) {
2958 pde = pmap_pde(pmap, sva);
2959 if (pde && (*pde & PG_PS) == 0) {
2960 pmap_remove_page(pmap, sva, pde, &free);
2966 for (; sva < eva; sva = va_next) {
2968 if (pmap->pm_stats.resident_count == 0)
2971 pml4e = pmap_pml4e(pmap, sva);
2972 if ((*pml4e & PG_V) == 0) {
2973 va_next = (sva + NBPML4) & ~PML4MASK;
2979 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
2980 if ((*pdpe & PG_V) == 0) {
2981 va_next = (sva + NBPDP) & ~PDPMASK;
2988 * Calculate index for next page table.
2990 va_next = (sva + NBPDR) & ~PDRMASK;
2994 pde = pmap_pdpe_to_pde(pdpe, sva);
2998 * Weed out invalid mappings.
3004 * Check for large page.
3006 if ((ptpaddr & PG_PS) != 0) {
3008 * Are we removing the entire large page? If not,
3009 * demote the mapping and fall through.
3011 if (sva + NBPDR == va_next && eva >= va_next) {
3013 * The TLB entry for a PG_G mapping is
3014 * invalidated by pmap_remove_pde().
3016 if ((ptpaddr & PG_G) == 0)
3018 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3020 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3022 /* The large page mapping was destroyed. */
3029 * Limit our scan to either the end of the va represented
3030 * by the current page table page, or to the end of the
3031 * range being removed.
3037 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3040 if (va != va_next) {
3041 pmap_invalidate_range(pmap, va, sva);
3046 if ((*pte & PG_G) == 0)
3048 else if (va == va_next)
3050 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3057 pmap_invalidate_range(pmap, va, sva);
3063 pmap_invalidate_all(pmap);
3064 rw_runlock(&pvh_global_lock);
3066 pmap_free_zero_pages(free);
3070 * Routine: pmap_remove_all
3072 * Removes this physical page from
3073 * all physical maps in which it resides.
3074 * Reflects back modify bits to the pager.
3077 * Original versions of this routine were very
3078 * inefficient because they iteratively called
3079 * pmap_remove (slow...)
3083 pmap_remove_all(vm_page_t m)
3085 struct md_page *pvh;
3088 pt_entry_t *pte, tpte;
3093 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3094 ("pmap_remove_all: page %p is not managed", m));
3096 rw_wlock(&pvh_global_lock);
3097 if ((m->flags & PG_FICTITIOUS) != 0)
3098 goto small_mappings;
3099 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3100 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3104 pde = pmap_pde(pmap, va);
3105 (void)pmap_demote_pde(pmap, pde, va);
3109 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3112 pmap_resident_count_dec(pmap, 1);
3113 pde = pmap_pde(pmap, pv->pv_va);
3114 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3115 " a 2mpage in page %p's pv list", m));
3116 pte = pmap_pde_to_pte(pde, pv->pv_va);
3117 tpte = pte_load_clear(pte);
3119 pmap->pm_stats.wired_count--;
3121 vm_page_aflag_set(m, PGA_REFERENCED);
3124 * Update the vm_page_t clean and reference bits.
3126 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3128 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3129 pmap_invalidate_page(pmap, pv->pv_va);
3130 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3131 free_pv_entry(pmap, pv);
3134 vm_page_aflag_clear(m, PGA_WRITEABLE);
3135 rw_wunlock(&pvh_global_lock);
3136 pmap_free_zero_pages(free);
3140 * pmap_protect_pde: do the things to protect a 2mpage in a process
3143 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3145 pd_entry_t newpde, oldpde;
3146 vm_offset_t eva, va;
3148 boolean_t anychanged;
3150 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3151 KASSERT((sva & PDRMASK) == 0,
3152 ("pmap_protect_pde: sva is not 2mpage aligned"));
3155 oldpde = newpde = *pde;
3156 if (oldpde & PG_MANAGED) {
3158 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3159 va < eva; va += PAGE_SIZE, m++)
3160 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3163 if ((prot & VM_PROT_WRITE) == 0)
3164 newpde &= ~(PG_RW | PG_M);
3165 if ((prot & VM_PROT_EXECUTE) == 0)
3167 if (newpde != oldpde) {
3168 if (!atomic_cmpset_long(pde, oldpde, newpde))
3171 pmap_invalidate_page(pmap, sva);
3175 return (anychanged);
3179 * Set the physical protection on the
3180 * specified range of this map as requested.
3183 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3185 vm_offset_t va_next;
3186 pml4_entry_t *pml4e;
3188 pd_entry_t ptpaddr, *pde;
3190 boolean_t anychanged, pv_lists_locked;
3192 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3193 pmap_remove(pmap, sva, eva);
3197 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3198 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3201 pv_lists_locked = FALSE;
3206 for (; sva < eva; sva = va_next) {
3208 pml4e = pmap_pml4e(pmap, sva);
3209 if ((*pml4e & PG_V) == 0) {
3210 va_next = (sva + NBPML4) & ~PML4MASK;
3216 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3217 if ((*pdpe & PG_V) == 0) {
3218 va_next = (sva + NBPDP) & ~PDPMASK;
3224 va_next = (sva + NBPDR) & ~PDRMASK;
3228 pde = pmap_pdpe_to_pde(pdpe, sva);
3232 * Weed out invalid mappings.
3238 * Check for large page.
3240 if ((ptpaddr & PG_PS) != 0) {
3242 * Are we protecting the entire large page? If not,
3243 * demote the mapping and fall through.
3245 if (sva + NBPDR == va_next && eva >= va_next) {
3247 * The TLB entry for a PG_G mapping is
3248 * invalidated by pmap_protect_pde().
3250 if (pmap_protect_pde(pmap, pde, sva, prot))
3254 if (!pv_lists_locked) {
3255 pv_lists_locked = TRUE;
3256 if (!rw_try_rlock(&pvh_global_lock)) {
3258 pmap_invalidate_all(
3261 rw_rlock(&pvh_global_lock);
3265 if (!pmap_demote_pde(pmap, pde, sva)) {
3267 * The large page mapping was
3278 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3280 pt_entry_t obits, pbits;
3284 obits = pbits = *pte;
3285 if ((pbits & PG_V) == 0)
3288 if ((prot & VM_PROT_WRITE) == 0) {
3289 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3290 (PG_MANAGED | PG_M | PG_RW)) {
3291 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3294 pbits &= ~(PG_RW | PG_M);
3296 if ((prot & VM_PROT_EXECUTE) == 0)
3299 if (pbits != obits) {
3300 if (!atomic_cmpset_long(pte, obits, pbits))
3303 pmap_invalidate_page(pmap, sva);
3310 pmap_invalidate_all(pmap);
3311 if (pv_lists_locked)
3312 rw_runlock(&pvh_global_lock);
3317 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3318 * single page table page (PTP) to a single 2MB page mapping. For promotion
3319 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3320 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3321 * identical characteristics.
3324 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3325 struct rwlock **lockp)
3328 pt_entry_t *firstpte, oldpte, pa, *pte;
3329 vm_offset_t oldpteva;
3332 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3335 * Examine the first PTE in the specified PTP. Abort if this PTE is
3336 * either invalid, unused, or does not map the first 4KB physical page
3337 * within a 2MB page.
3339 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
3342 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3343 atomic_add_long(&pmap_pde_p_failures, 1);
3344 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3345 " in pmap %p", va, pmap);
3348 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3350 * When PG_M is already clear, PG_RW can be cleared without
3351 * a TLB invalidation.
3353 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
3359 * Examine each of the other PTEs in the specified PTP. Abort if this
3360 * PTE maps an unexpected 4KB physical page or does not have identical
3361 * characteristics to the first PTE.
3363 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3364 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3367 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3368 atomic_add_long(&pmap_pde_p_failures, 1);
3369 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3370 " in pmap %p", va, pmap);
3373 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3375 * When PG_M is already clear, PG_RW can be cleared
3376 * without a TLB invalidation.
3378 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
3381 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3383 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
3384 " in pmap %p", oldpteva, pmap);
3386 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3387 atomic_add_long(&pmap_pde_p_failures, 1);
3388 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3389 " in pmap %p", va, pmap);
3396 * Save the page table page in its current state until the PDE
3397 * mapping the superpage is demoted by pmap_demote_pde() or
3398 * destroyed by pmap_remove_pde().
3400 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3401 KASSERT(mpte >= vm_page_array &&
3402 mpte < &vm_page_array[vm_page_array_size],
3403 ("pmap_promote_pde: page table page is out of range"));
3404 KASSERT(mpte->pindex == pmap_pde_pindex(va),
3405 ("pmap_promote_pde: page table page's pindex is wrong"));
3406 pmap_insert_pt_page(pmap, mpte);
3409 * Promote the pv entries.
3411 if ((newpde & PG_MANAGED) != 0)
3412 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
3415 * Propagate the PAT index to its proper position.
3417 if ((newpde & PG_PTE_PAT) != 0)
3418 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3421 * Map the superpage.
3423 if (workaround_erratum383)
3424 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3426 pde_store(pde, PG_PS | newpde);
3428 atomic_add_long(&pmap_pde_promotions, 1);
3429 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
3430 " in pmap %p", va, pmap);
3434 * Insert the given physical page (p) at
3435 * the specified virtual address (v) in the
3436 * target physical map with the protection requested.
3438 * If specified, the page will be wired down, meaning
3439 * that the related pte can not be reclaimed.
3441 * NB: This is the only routine which MAY NOT lazy-evaluate
3442 * or lose information. That is, this routine must actually
3443 * insert this page into the given map NOW.
3446 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3447 vm_prot_t prot, boolean_t wired)
3449 struct rwlock *lock;
3452 pt_entry_t newpte, origpte;
3457 va = trunc_page(va);
3458 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3459 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3460 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
3462 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
3463 va >= kmi.clean_eva,
3464 ("pmap_enter: managed mapping within the clean submap"));
3465 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3466 VM_OBJECT_LOCKED(m->object),
3467 ("pmap_enter: page %p is not busy", m));
3468 pa = VM_PAGE_TO_PHYS(m);
3469 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3470 if ((access & VM_PROT_WRITE) != 0)
3472 if ((prot & VM_PROT_WRITE) != 0)
3474 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3475 ("pmap_enter: access includes VM_PROT_WRITE but prot doesn't"));
3476 if ((prot & VM_PROT_EXECUTE) == 0)
3480 if (va < VM_MAXUSER_ADDRESS)
3482 if (pmap == kernel_pmap)
3484 newpte |= pmap_cache_bits(m->md.pat_mode, 0);
3489 rw_rlock(&pvh_global_lock);
3493 * In the case that a page table page is not
3494 * resident, we are creating it here.
3497 pde = pmap_pde(pmap, va);
3498 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
3499 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
3500 pte = pmap_pde_to_pte(pde, va);
3501 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3502 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3505 } else if (va < VM_MAXUSER_ADDRESS) {
3507 * Here if the pte page isn't mapped, or if it has been
3510 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va), &lock);
3513 panic("pmap_enter: invalid page directory va=%#lx", va);
3518 * Is the specified virtual address already mapped?
3520 if ((origpte & PG_V) != 0) {
3522 * Wiring change, just update stats. We don't worry about
3523 * wiring PT pages as they remain resident as long as there
3524 * are valid mappings in them. Hence, if a user page is wired,
3525 * the PT page will be also.
3527 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3528 pmap->pm_stats.wired_count++;
3529 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3530 pmap->pm_stats.wired_count--;
3533 * Remove the extra PT page reference.
3537 KASSERT(mpte->wire_count > 0,
3538 ("pmap_enter: missing reference to page table page,"
3543 * Has the physical page changed?
3545 opa = origpte & PG_FRAME;
3548 * No, might be a protection or wiring change.
3550 if ((origpte & PG_MANAGED) != 0) {
3551 newpte |= PG_MANAGED;
3552 if ((newpte & PG_RW) != 0)
3553 vm_page_aflag_set(m, PGA_WRITEABLE);
3555 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3561 * Increment the counters.
3563 if ((newpte & PG_W) != 0)
3564 pmap->pm_stats.wired_count++;
3565 pmap_resident_count_inc(pmap, 1);
3569 * Enter on the PV list if part of our managed memory.
3571 if ((m->oflags & VPO_UNMANAGED) == 0) {
3572 newpte |= PG_MANAGED;
3573 pv = get_pv_entry(pmap, &lock);
3575 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3576 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3577 if ((newpte & PG_RW) != 0)
3578 vm_page_aflag_set(m, PGA_WRITEABLE);
3584 if ((origpte & PG_V) != 0) {
3586 origpte = pte_load_store(pte, newpte);
3587 opa = origpte & PG_FRAME;
3589 if ((origpte & PG_MANAGED) != 0) {
3590 om = PHYS_TO_VM_PAGE(opa);
3591 if ((origpte & (PG_M | PG_RW)) == (PG_M |
3594 if ((origpte & PG_A) != 0)
3595 vm_page_aflag_set(om, PGA_REFERENCED);
3596 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3597 pmap_pvh_free(&om->md, pmap, va);
3598 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3599 TAILQ_EMPTY(&om->md.pv_list) &&
3600 ((om->flags & PG_FICTITIOUS) != 0 ||
3601 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3602 vm_page_aflag_clear(om, PGA_WRITEABLE);
3604 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
3605 PG_RW)) == (PG_M | PG_RW)) {
3606 if ((origpte & PG_MANAGED) != 0)
3610 * Although the PTE may still have PG_RW set, TLB
3611 * invalidation may nonetheless be required because
3612 * the PTE no longer has PG_M set.
3614 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3616 * This PTE change does not require TLB invalidation.
3620 if ((origpte & PG_A) != 0)
3621 pmap_invalidate_page(pmap, va);
3623 pte_store(pte, newpte);
3628 * If both the page table page and the reservation are fully
3629 * populated, then attempt promotion.
3631 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3632 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3633 vm_reserv_level_iffullpop(m) == 0)
3634 pmap_promote_pde(pmap, pde, va, &lock);
3638 rw_runlock(&pvh_global_lock);
3643 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
3644 * otherwise. Fails if (1) a page table page cannot be allocated without
3645 * blocking, (2) a mapping already exists at the specified virtual address, or
3646 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3649 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3650 struct rwlock **lockp)
3652 pd_entry_t *pde, newpde;
3653 vm_page_t free, mpde;
3655 rw_assert(&pvh_global_lock, RA_LOCKED);
3656 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3657 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
3658 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3659 " in pmap %p", va, pmap);
3662 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
3663 pde = &pde[pmap_pde_index(va)];
3664 if ((*pde & PG_V) != 0) {
3665 KASSERT(mpde->wire_count > 1,
3666 ("pmap_enter_pde: mpde's wire count is too low"));
3668 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3669 " in pmap %p", va, pmap);
3672 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3674 if ((m->oflags & VPO_UNMANAGED) == 0) {
3675 newpde |= PG_MANAGED;
3678 * Abort this mapping if its PV entry could not be created.
3680 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
3683 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
3684 pmap_invalidate_page(pmap, va);
3685 pmap_free_zero_pages(free);
3687 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3688 " in pmap %p", va, pmap);
3692 if ((prot & VM_PROT_EXECUTE) == 0)
3694 if (va < VM_MAXUSER_ADDRESS)
3698 * Increment counters.
3700 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3703 * Map the superpage.
3705 pde_store(pde, newpde);
3707 atomic_add_long(&pmap_pde_mappings, 1);
3708 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3709 " in pmap %p", va, pmap);
3714 * Maps a sequence of resident pages belonging to the same object.
3715 * The sequence begins with the given page m_start. This page is
3716 * mapped at the given virtual address start. Each subsequent page is
3717 * mapped at a virtual address that is offset from start by the same
3718 * amount as the page is offset from m_start within the object. The
3719 * last page in the sequence is the page with the largest offset from
3720 * m_start that can be mapped at a virtual address less than the given
3721 * virtual address end. Not every virtual page between start and end
3722 * is mapped; only those for which a resident page exists with the
3723 * corresponding offset from m_start are mapped.
3726 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3727 vm_page_t m_start, vm_prot_t prot)
3729 struct rwlock *lock;
3732 vm_pindex_t diff, psize;
3734 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3735 psize = atop(end - start);
3739 rw_rlock(&pvh_global_lock);
3741 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3742 va = start + ptoa(diff);
3743 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3744 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3745 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3746 pmap_enter_pde(pmap, va, m, prot, &lock))
3747 m = &m[NBPDR / PAGE_SIZE - 1];
3749 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3751 m = TAILQ_NEXT(m, listq);
3755 rw_runlock(&pvh_global_lock);
3760 * this code makes some *MAJOR* assumptions:
3761 * 1. Current pmap & pmap exists.
3764 * 4. No page table pages.
3765 * but is *MUCH* faster than pmap_enter...
3769 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3771 struct rwlock *lock;
3774 rw_rlock(&pvh_global_lock);
3776 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3779 rw_runlock(&pvh_global_lock);
3784 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3785 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3791 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3792 (m->oflags & VPO_UNMANAGED) != 0,
3793 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3794 rw_assert(&pvh_global_lock, RA_LOCKED);
3795 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3798 * In the case that a page table page is not
3799 * resident, we are creating it here.
3801 if (va < VM_MAXUSER_ADDRESS) {
3802 vm_pindex_t ptepindex;
3806 * Calculate pagetable page index
3808 ptepindex = pmap_pde_pindex(va);
3809 if (mpte && (mpte->pindex == ptepindex)) {
3813 * Get the page directory entry
3815 ptepa = pmap_pde(pmap, va);
3818 * If the page table page is mapped, we just increment
3819 * the hold count, and activate it. Otherwise, we
3820 * attempt to allocate a page table page. If this
3821 * attempt fails, we don't retry. Instead, we give up.
3823 if (ptepa && (*ptepa & PG_V) != 0) {
3826 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
3830 * Pass NULL instead of the PV list lock
3831 * pointer, because we don't intend to sleep.
3833 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
3838 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3839 pte = &pte[pmap_pte_index(va)];
3853 * Enter on the PV list if part of our managed memory.
3855 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3856 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3859 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3860 pmap_invalidate_page(pmap, va);
3861 pmap_free_zero_pages(free);
3869 * Increment counters
3871 pmap_resident_count_inc(pmap, 1);
3873 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3874 if ((prot & VM_PROT_EXECUTE) == 0)
3878 * Now validate mapping with RO protection
3880 if ((m->oflags & VPO_UNMANAGED) != 0)
3881 pte_store(pte, pa | PG_V | PG_U);
3883 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3888 * Make a temporary mapping for a physical address. This is only intended
3889 * to be used for panic dumps.
3892 pmap_kenter_temporary(vm_paddr_t pa, int i)
3896 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3897 pmap_kenter(va, pa);
3899 return ((void *)crashdumpmap);
3903 * This code maps large physical mmap regions into the
3904 * processor address space. Note that some shortcuts
3905 * are taken, but the code works.
3908 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3909 vm_pindex_t pindex, vm_size_t size)
3912 vm_paddr_t pa, ptepa;
3916 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3917 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3918 ("pmap_object_init_pt: non-device object"));
3919 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3920 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3922 p = vm_page_lookup(object, pindex);
3923 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3924 ("pmap_object_init_pt: invalid page %p", p));
3925 pat_mode = p->md.pat_mode;
3928 * Abort the mapping if the first page is not physically
3929 * aligned to a 2MB page boundary.
3931 ptepa = VM_PAGE_TO_PHYS(p);
3932 if (ptepa & (NBPDR - 1))
3936 * Skip the first page. Abort the mapping if the rest of
3937 * the pages are not physically contiguous or have differing
3938 * memory attributes.
3940 p = TAILQ_NEXT(p, listq);
3941 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3943 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3944 ("pmap_object_init_pt: invalid page %p", p));
3945 if (pa != VM_PAGE_TO_PHYS(p) ||
3946 pat_mode != p->md.pat_mode)
3948 p = TAILQ_NEXT(p, listq);
3952 * Map using 2MB pages. Since "ptepa" is 2M aligned and
3953 * "size" is a multiple of 2M, adding the PAT setting to "pa"
3954 * will not affect the termination of this loop.
3957 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3958 size; pa += NBPDR) {
3959 pdpg = pmap_allocpde(pmap, addr, NULL);
3962 * The creation of mappings below is only an
3963 * optimization. If a page directory page
3964 * cannot be allocated without blocking,
3965 * continue on to the next mapping rather than
3971 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
3972 pde = &pde[pmap_pde_index(addr)];
3973 if ((*pde & PG_V) == 0) {
3974 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3975 PG_U | PG_RW | PG_V);
3976 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3977 atomic_add_long(&pmap_pde_mappings, 1);
3979 /* Continue on if the PDE is already valid. */
3981 KASSERT(pdpg->wire_count > 0,
3982 ("pmap_object_init_pt: missing reference "
3983 "to page directory page, va: 0x%lx", addr));
3992 * Routine: pmap_change_wiring
3993 * Function: Change the wiring attribute for a map/virtual-address
3995 * In/out conditions:
3996 * The mapping must already exist in the pmap.
3999 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
4003 boolean_t pv_lists_locked;
4005 pv_lists_locked = FALSE;
4008 * Wiring is not a hardware characteristic so there is no need to
4013 pde = pmap_pde(pmap, va);
4014 if ((*pde & PG_PS) != 0) {
4015 if (!wired != ((*pde & PG_W) == 0)) {
4016 if (!pv_lists_locked) {
4017 pv_lists_locked = TRUE;
4018 if (!rw_try_rlock(&pvh_global_lock)) {
4020 rw_rlock(&pvh_global_lock);
4024 if (!pmap_demote_pde(pmap, pde, va))
4025 panic("pmap_change_wiring: demotion failed");
4029 pte = pmap_pde_to_pte(pde, va);
4030 if (wired && (*pte & PG_W) == 0) {
4031 pmap->pm_stats.wired_count++;
4032 atomic_set_long(pte, PG_W);
4033 } else if (!wired && (*pte & PG_W) != 0) {
4034 pmap->pm_stats.wired_count--;
4035 atomic_clear_long(pte, PG_W);
4038 if (pv_lists_locked)
4039 rw_runlock(&pvh_global_lock);
4044 * Copy the range specified by src_addr/len
4045 * from the source map to the range dst_addr/len
4046 * in the destination map.
4048 * This routine is only advisory and need not do anything.
4052 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4053 vm_offset_t src_addr)
4055 struct rwlock *lock;
4058 vm_offset_t end_addr = src_addr + len;
4059 vm_offset_t va_next;
4061 if (dst_addr != src_addr)
4065 rw_rlock(&pvh_global_lock);
4066 if (dst_pmap < src_pmap) {
4067 PMAP_LOCK(dst_pmap);
4068 PMAP_LOCK(src_pmap);
4070 PMAP_LOCK(src_pmap);
4071 PMAP_LOCK(dst_pmap);
4073 for (addr = src_addr; addr < end_addr; addr = va_next) {
4074 pt_entry_t *src_pte, *dst_pte;
4075 vm_page_t dstmpde, dstmpte, srcmpte;
4076 pml4_entry_t *pml4e;
4078 pd_entry_t srcptepaddr, *pde;
4080 KASSERT(addr < UPT_MIN_ADDRESS,
4081 ("pmap_copy: invalid to pmap_copy page tables"));
4083 pml4e = pmap_pml4e(src_pmap, addr);
4084 if ((*pml4e & PG_V) == 0) {
4085 va_next = (addr + NBPML4) & ~PML4MASK;
4091 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4092 if ((*pdpe & PG_V) == 0) {
4093 va_next = (addr + NBPDP) & ~PDPMASK;
4099 va_next = (addr + NBPDR) & ~PDRMASK;
4103 pde = pmap_pdpe_to_pde(pdpe, addr);
4105 if (srcptepaddr == 0)
4108 if (srcptepaddr & PG_PS) {
4109 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4111 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4112 if (dstmpde == NULL)
4114 pde = (pd_entry_t *)
4115 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4116 pde = &pde[pmap_pde_index(addr)];
4117 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4118 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4119 PG_PS_FRAME, &lock))) {
4120 *pde = srcptepaddr & ~PG_W;
4121 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4123 dstmpde->wire_count--;
4127 srcptepaddr &= PG_FRAME;
4128 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4129 KASSERT(srcmpte->wire_count > 0,
4130 ("pmap_copy: source page table page is unused"));
4132 if (va_next > end_addr)
4135 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4136 src_pte = &src_pte[pmap_pte_index(addr)];
4138 while (addr < va_next) {
4142 * we only virtual copy managed pages
4144 if ((ptetemp & PG_MANAGED) != 0) {
4145 if (dstmpte != NULL &&
4146 dstmpte->pindex == pmap_pde_pindex(addr))
4147 dstmpte->wire_count++;
4148 else if ((dstmpte = pmap_allocpte(dst_pmap,
4149 addr, NULL)) == NULL)
4151 dst_pte = (pt_entry_t *)
4152 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4153 dst_pte = &dst_pte[pmap_pte_index(addr)];
4154 if (*dst_pte == 0 &&
4155 pmap_try_insert_pv_entry(dst_pmap, addr,
4156 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4159 * Clear the wired, modified, and
4160 * accessed (referenced) bits
4163 *dst_pte = ptetemp & ~(PG_W | PG_M |
4165 pmap_resident_count_inc(dst_pmap, 1);
4168 if (pmap_unwire_ptp(dst_pmap, addr,
4170 pmap_invalidate_page(dst_pmap,
4172 pmap_free_zero_pages(free);
4176 if (dstmpte->wire_count >= srcmpte->wire_count)
4186 rw_runlock(&pvh_global_lock);
4187 PMAP_UNLOCK(src_pmap);
4188 PMAP_UNLOCK(dst_pmap);
4192 * pmap_zero_page zeros the specified hardware page by mapping
4193 * the page into KVM and using bzero to clear its contents.
4196 pmap_zero_page(vm_page_t m)
4198 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4200 pagezero((void *)va);
4204 * pmap_zero_page_area zeros the specified hardware page by mapping
4205 * the page into KVM and using bzero to clear its contents.
4207 * off and size may not cover an area beyond a single hardware page.
4210 pmap_zero_page_area(vm_page_t m, int off, int size)
4212 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4214 if (off == 0 && size == PAGE_SIZE)
4215 pagezero((void *)va);
4217 bzero((char *)va + off, size);
4221 * pmap_zero_page_idle zeros the specified hardware page by mapping
4222 * the page into KVM and using bzero to clear its contents. This
4223 * is intended to be called from the vm_pagezero process only and
4227 pmap_zero_page_idle(vm_page_t m)
4229 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4231 pagezero((void *)va);
4235 * pmap_copy_page copies the specified (machine independent)
4236 * page by mapping the page into virtual memory and using
4237 * bcopy to copy the page, one machine dependent page at a
4241 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4243 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4244 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4246 pagecopy((void *)src, (void *)dst);
4249 int unmapped_buf_allowed = 1;
4252 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4253 vm_offset_t b_offset, int xfersize)
4256 vm_offset_t a_pg_offset, b_pg_offset;
4259 while (xfersize > 0) {
4260 a_pg_offset = a_offset & PAGE_MASK;
4261 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4262 a_cp = (char *)PHYS_TO_DMAP(ma[a_offset >> PAGE_SHIFT]->
4263 phys_addr) + a_pg_offset;
4264 b_pg_offset = b_offset & PAGE_MASK;
4265 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4266 b_cp = (char *)PHYS_TO_DMAP(mb[b_offset >> PAGE_SHIFT]->
4267 phys_addr) + b_pg_offset;
4268 bcopy(a_cp, b_cp, cnt);
4276 * Returns true if the pmap's pv is one of the first
4277 * 16 pvs linked to from this page. This count may
4278 * be changed upwards or downwards in the future; it
4279 * is only necessary that true be returned for a small
4280 * subset of pmaps for proper page aging.
4283 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4285 struct md_page *pvh;
4286 struct rwlock *lock;
4291 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4292 ("pmap_page_exists_quick: page %p is not managed", m));
4294 rw_rlock(&pvh_global_lock);
4295 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4297 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4298 if (PV_PMAP(pv) == pmap) {
4306 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4307 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4308 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4309 if (PV_PMAP(pv) == pmap) {
4319 rw_runlock(&pvh_global_lock);
4324 * pmap_page_wired_mappings:
4326 * Return the number of managed mappings to the given physical page
4330 pmap_page_wired_mappings(vm_page_t m)
4335 if ((m->oflags & VPO_UNMANAGED) != 0)
4337 rw_wlock(&pvh_global_lock);
4338 count = pmap_pvh_wired_mappings(&m->md, count);
4339 if ((m->flags & PG_FICTITIOUS) == 0) {
4340 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4343 rw_wunlock(&pvh_global_lock);
4348 * pmap_pvh_wired_mappings:
4350 * Return the updated number "count" of managed mappings that are wired.
4353 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4359 rw_assert(&pvh_global_lock, RA_WLOCKED);
4360 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4363 pte = pmap_pte(pmap, pv->pv_va);
4364 if ((*pte & PG_W) != 0)
4372 * Returns TRUE if the given page is mapped individually or as part of
4373 * a 2mpage. Otherwise, returns FALSE.
4376 pmap_page_is_mapped(vm_page_t m)
4378 struct rwlock *lock;
4381 if ((m->oflags & VPO_UNMANAGED) != 0)
4383 rw_rlock(&pvh_global_lock);
4384 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4386 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4387 ((m->flags & PG_FICTITIOUS) == 0 &&
4388 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4390 rw_runlock(&pvh_global_lock);
4395 * Destroy all managed, non-wired mappings in the given user-space
4396 * pmap. This pmap cannot be active on any processor besides the
4399 * This function cannot be applied to the kernel pmap. Moreover, it
4400 * is not intended for general use. It is only to be used during
4401 * process termination. Consequently, it can be implemented in ways
4402 * that make it faster than pmap_remove(). First, it can more quickly
4403 * destroy mappings by iterating over the pmap's collection of PV
4404 * entries, rather than searching the page table. Second, it doesn't
4405 * have to test and clear the page table entries atomically, because
4406 * no processor is currently accessing the user address space. In
4407 * particular, a page table entry's dirty bit won't change state once
4408 * this function starts.
4411 pmap_remove_pages(pmap_t pmap)
4414 pt_entry_t *pte, tpte;
4415 vm_page_t free = NULL;
4416 vm_page_t m, mpte, mt;
4418 struct md_page *pvh;
4419 struct pv_chunk *pc, *npc;
4420 struct rwlock *lock;
4422 uint64_t inuse, bitmask;
4423 int allfree, field, freed, idx;
4426 * Assert that the given pmap is only active on the current
4427 * CPU. Unfortunately, we cannot block another CPU from
4428 * activating the pmap while this function is executing.
4430 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4433 cpuset_t other_cpus;
4435 other_cpus = all_cpus;
4437 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
4438 CPU_AND(&other_cpus, &pmap->pm_active);
4440 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
4445 rw_rlock(&pvh_global_lock);
4447 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4450 for (field = 0; field < _NPCM; field++) {
4451 inuse = ~pc->pc_map[field] & pc_freemask[field];
4452 while (inuse != 0) {
4454 bitmask = 1UL << bit;
4455 idx = field * 64 + bit;
4456 pv = &pc->pc_pventry[idx];
4459 pte = pmap_pdpe(pmap, pv->pv_va);
4461 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
4463 if ((tpte & (PG_PS | PG_V)) == PG_V) {
4465 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
4467 pte = &pte[pmap_pte_index(pv->pv_va)];
4468 tpte = *pte & ~PG_PTE_PAT;
4470 if ((tpte & PG_V) == 0) {
4471 panic("bad pte va %lx pte %lx",
4476 * We cannot remove wired pages from a process' mapping at this time
4483 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4484 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4485 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4486 m, (uintmax_t)m->phys_addr,
4489 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4490 m < &vm_page_array[vm_page_array_size],
4491 ("pmap_remove_pages: bad tpte %#jx",
4497 * Update the vm_page_t clean/reference bits.
4499 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4500 if ((tpte & PG_PS) != 0) {
4501 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4507 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4510 pc->pc_map[field] |= bitmask;
4511 if ((tpte & PG_PS) != 0) {
4512 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4513 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4514 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4515 if (TAILQ_EMPTY(&pvh->pv_list)) {
4516 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4517 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4518 TAILQ_EMPTY(&mt->md.pv_list))
4519 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4521 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4523 pmap_remove_pt_page(pmap, mpte);
4524 pmap_resident_count_dec(pmap, 1);
4525 KASSERT(mpte->wire_count == NPTEPG,
4526 ("pmap_remove_pages: pte page wire count error"));
4527 mpte->wire_count = 0;
4528 pmap_add_delayed_free_list(mpte, &free, FALSE);
4529 atomic_subtract_int(&cnt.v_wire_count, 1);
4532 pmap_resident_count_dec(pmap, 1);
4533 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4534 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4535 TAILQ_EMPTY(&m->md.pv_list) &&
4536 (m->flags & PG_FICTITIOUS) == 0) {
4537 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4538 if (TAILQ_EMPTY(&pvh->pv_list))
4539 vm_page_aflag_clear(m, PGA_WRITEABLE);
4542 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
4546 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4547 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4548 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4550 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4556 pmap_invalidate_all(pmap);
4557 rw_runlock(&pvh_global_lock);
4559 pmap_free_zero_pages(free);
4565 * Return whether or not the specified physical page was modified
4566 * in any physical maps.
4569 pmap_is_modified(vm_page_t m)
4573 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4574 ("pmap_is_modified: page %p is not managed", m));
4577 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4578 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4579 * is clear, no PTEs can have PG_M set.
4581 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4582 if ((m->oflags & VPO_BUSY) == 0 &&
4583 (m->aflags & PGA_WRITEABLE) == 0)
4585 rw_wlock(&pvh_global_lock);
4586 rv = pmap_is_modified_pvh(&m->md) ||
4587 ((m->flags & PG_FICTITIOUS) == 0 &&
4588 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4589 rw_wunlock(&pvh_global_lock);
4594 * Returns TRUE if any of the given mappings were used to modify
4595 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4596 * mappings are supported.
4599 pmap_is_modified_pvh(struct md_page *pvh)
4606 rw_assert(&pvh_global_lock, RA_WLOCKED);
4608 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4611 pte = pmap_pte(pmap, pv->pv_va);
4612 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4621 * pmap_is_prefaultable:
4623 * Return whether or not the specified virtual address is elgible
4627 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4635 pde = pmap_pde(pmap, addr);
4636 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
4637 pte = pmap_pde_to_pte(pde, addr);
4638 rv = (*pte & PG_V) == 0;
4645 * pmap_is_referenced:
4647 * Return whether or not the specified physical page was referenced
4648 * in any physical maps.
4651 pmap_is_referenced(vm_page_t m)
4655 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4656 ("pmap_is_referenced: page %p is not managed", m));
4657 rw_wlock(&pvh_global_lock);
4658 rv = pmap_is_referenced_pvh(&m->md) ||
4659 ((m->flags & PG_FICTITIOUS) == 0 &&
4660 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4661 rw_wunlock(&pvh_global_lock);
4666 * Returns TRUE if any of the given mappings were referenced and FALSE
4667 * otherwise. Both page and 2mpage mappings are supported.
4670 pmap_is_referenced_pvh(struct md_page *pvh)
4677 rw_assert(&pvh_global_lock, RA_WLOCKED);
4679 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4682 pte = pmap_pte(pmap, pv->pv_va);
4683 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4692 * Clear the write and modified bits in each of the given page's mappings.
4695 pmap_remove_write(vm_page_t m)
4697 struct md_page *pvh;
4699 pv_entry_t next_pv, pv;
4701 pt_entry_t oldpte, *pte;
4704 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4705 ("pmap_remove_write: page %p is not managed", m));
4708 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4709 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4710 * is clear, no page table entries need updating.
4712 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4713 if ((m->oflags & VPO_BUSY) == 0 &&
4714 (m->aflags & PGA_WRITEABLE) == 0)
4716 rw_wlock(&pvh_global_lock);
4717 if ((m->flags & PG_FICTITIOUS) != 0)
4718 goto small_mappings;
4719 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4720 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4724 pde = pmap_pde(pmap, va);
4725 if ((*pde & PG_RW) != 0)
4726 (void)pmap_demote_pde(pmap, pde, va);
4730 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4733 pde = pmap_pde(pmap, pv->pv_va);
4734 KASSERT((*pde & PG_PS) == 0,
4735 ("pmap_remove_write: found a 2mpage in page %p's pv list",
4737 pte = pmap_pde_to_pte(pde, pv->pv_va);
4740 if (oldpte & PG_RW) {
4741 if (!atomic_cmpset_long(pte, oldpte, oldpte &
4744 if ((oldpte & PG_M) != 0)
4746 pmap_invalidate_page(pmap, pv->pv_va);
4750 vm_page_aflag_clear(m, PGA_WRITEABLE);
4751 rw_wunlock(&pvh_global_lock);
4755 * pmap_ts_referenced:
4757 * Return a count of reference bits for a page, clearing those bits.
4758 * It is not necessary for every reference bit to be cleared, but it
4759 * is necessary that 0 only be returned when there are truly no
4760 * reference bits set.
4762 * XXX: The exact number of bits to check and clear is a matter that
4763 * should be tested and standardized at some point in the future for
4764 * optimal aging of shared pages.
4767 pmap_ts_referenced(vm_page_t m)
4769 struct md_page *pvh;
4770 pv_entry_t pv, pvf, pvn;
4772 pd_entry_t oldpde, *pde;
4777 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4778 ("pmap_ts_referenced: page %p is not managed", m));
4779 rw_wlock(&pvh_global_lock);
4780 if ((m->flags & PG_FICTITIOUS) != 0)
4781 goto small_mappings;
4782 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4783 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4787 pde = pmap_pde(pmap, va);
4789 if ((oldpde & PG_A) != 0) {
4790 if (pmap_demote_pde(pmap, pde, va)) {
4791 if ((oldpde & PG_W) == 0) {
4793 * Remove the mapping to a single page
4794 * so that a subsequent access may
4795 * repromote. Since the underlying
4796 * page table page is fully populated,
4797 * this removal never frees a page
4800 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4802 pmap_remove_page(pmap, va, pde, NULL);
4814 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4817 pvn = TAILQ_NEXT(pv, pv_list);
4818 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4819 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4822 pde = pmap_pde(pmap, pv->pv_va);
4823 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4824 " found a 2mpage in page %p's pv list", m));
4825 pte = pmap_pde_to_pte(pde, pv->pv_va);
4826 if ((*pte & PG_A) != 0) {
4827 atomic_clear_long(pte, PG_A);
4828 pmap_invalidate_page(pmap, pv->pv_va);
4834 } while ((pv = pvn) != NULL && pv != pvf);
4837 rw_wunlock(&pvh_global_lock);
4842 * Clear the modify bits on the specified physical page.
4845 pmap_clear_modify(vm_page_t m)
4847 struct md_page *pvh;
4849 pv_entry_t next_pv, pv;
4850 pd_entry_t oldpde, *pde;
4851 pt_entry_t oldpte, *pte;
4854 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4855 ("pmap_clear_modify: page %p is not managed", m));
4856 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4857 KASSERT((m->oflags & VPO_BUSY) == 0,
4858 ("pmap_clear_modify: page %p is busy", m));
4861 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4862 * If the object containing the page is locked and the page is not
4863 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4865 if ((m->aflags & PGA_WRITEABLE) == 0)
4867 rw_wlock(&pvh_global_lock);
4868 if ((m->flags & PG_FICTITIOUS) != 0)
4869 goto small_mappings;
4870 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4871 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4875 pde = pmap_pde(pmap, va);
4877 if ((oldpde & PG_RW) != 0) {
4878 if (pmap_demote_pde(pmap, pde, va)) {
4879 if ((oldpde & PG_W) == 0) {
4881 * Write protect the mapping to a
4882 * single page so that a subsequent
4883 * write access may repromote.
4885 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4887 pte = pmap_pde_to_pte(pde, va);
4889 if ((oldpte & PG_V) != 0) {
4890 while (!atomic_cmpset_long(pte,
4892 oldpte & ~(PG_M | PG_RW)))
4895 pmap_invalidate_page(pmap, va);
4903 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4906 pde = pmap_pde(pmap, pv->pv_va);
4907 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4908 " a 2mpage in page %p's pv list", m));
4909 pte = pmap_pde_to_pte(pde, pv->pv_va);
4910 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4911 atomic_clear_long(pte, PG_M);
4912 pmap_invalidate_page(pmap, pv->pv_va);
4916 rw_wunlock(&pvh_global_lock);
4920 * pmap_clear_reference:
4922 * Clear the reference bit on the specified physical page.
4925 pmap_clear_reference(vm_page_t m)
4927 struct md_page *pvh;
4929 pv_entry_t next_pv, pv;
4930 pd_entry_t oldpde, *pde;
4934 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4935 ("pmap_clear_reference: page %p is not managed", m));
4936 rw_wlock(&pvh_global_lock);
4937 if ((m->flags & PG_FICTITIOUS) != 0)
4938 goto small_mappings;
4939 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4940 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4944 pde = pmap_pde(pmap, va);
4946 if ((oldpde & PG_A) != 0) {
4947 if (pmap_demote_pde(pmap, pde, va)) {
4949 * Remove the mapping to a single page so
4950 * that a subsequent access may repromote.
4951 * Since the underlying page table page is
4952 * fully populated, this removal never frees
4953 * a page table page.
4955 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4957 pmap_remove_page(pmap, va, pde, NULL);
4963 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4966 pde = pmap_pde(pmap, pv->pv_va);
4967 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4968 " a 2mpage in page %p's pv list", m));
4969 pte = pmap_pde_to_pte(pde, pv->pv_va);
4971 atomic_clear_long(pte, PG_A);
4972 pmap_invalidate_page(pmap, pv->pv_va);
4976 rw_wunlock(&pvh_global_lock);
4980 * Miscellaneous support routines follow
4983 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4984 static __inline void
4985 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4990 * The cache mode bits are all in the low 32-bits of the
4991 * PTE, so we can just spin on updating the low 32-bits.
4994 opte = *(u_int *)pte;
4995 npte = opte & ~PG_PTE_CACHE;
4997 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5000 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
5001 static __inline void
5002 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5007 * The cache mode bits are all in the low 32-bits of the
5008 * PDE, so we can just spin on updating the low 32-bits.
5011 opde = *(u_int *)pde;
5012 npde = opde & ~PG_PDE_CACHE;
5014 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5018 * Map a set of physical memory pages into the kernel virtual
5019 * address space. Return a pointer to where it is mapped. This
5020 * routine is intended to be used for mapping device memory,
5024 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5026 vm_offset_t va, offset;
5030 * If the specified range of physical addresses fits within the direct
5031 * map window, use the direct map.
5033 if (pa < dmaplimit && pa + size < dmaplimit) {
5034 va = PHYS_TO_DMAP(pa);
5035 if (!pmap_change_attr(va, size, mode))
5036 return ((void *)va);
5038 offset = pa & PAGE_MASK;
5039 size = roundup(offset + size, PAGE_SIZE);
5040 va = kmem_alloc_nofault(kernel_map, size);
5042 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5043 pa = trunc_page(pa);
5044 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5045 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5046 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5047 pmap_invalidate_cache_range(va, va + tmpsize);
5048 return ((void *)(va + offset));
5052 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5055 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5059 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5062 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5066 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5068 vm_offset_t base, offset;
5070 /* If we gave a direct map region in pmap_mapdev, do nothing */
5071 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
5073 base = trunc_page(va);
5074 offset = va & PAGE_MASK;
5075 size = roundup(offset + size, PAGE_SIZE);
5076 kmem_free(kernel_map, base, size);
5080 * Tries to demote a 1GB page mapping.
5083 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
5085 pdp_entry_t newpdpe, oldpdpe;
5086 pd_entry_t *firstpde, newpde, *pde;
5090 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5092 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
5093 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
5094 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
5095 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5096 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
5097 " in pmap %p", va, pmap);
5100 mpdepa = VM_PAGE_TO_PHYS(mpde);
5101 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
5102 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
5103 KASSERT((oldpdpe & PG_A) != 0,
5104 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
5105 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
5106 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
5110 * Initialize the page directory page.
5112 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
5118 * Demote the mapping.
5123 * Invalidate a stale recursive mapping of the page directory page.
5125 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
5127 pmap_pdpe_demotions++;
5128 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
5129 " in pmap %p", va, pmap);
5134 * Sets the memory attribute for the specified page.
5137 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5140 m->md.pat_mode = ma;
5143 * If "m" is a normal page, update its direct mapping. This update
5144 * can be relied upon to perform any cache operations that are
5145 * required for data coherence.
5147 if ((m->flags & PG_FICTITIOUS) == 0 &&
5148 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5150 panic("memory attribute change on the direct map failed");
5154 * Changes the specified virtual address range's memory type to that given by
5155 * the parameter "mode". The specified virtual address range must be
5156 * completely contained within either the direct map or the kernel map. If
5157 * the virtual address range is contained within the kernel map, then the
5158 * memory type for each of the corresponding ranges of the direct map is also
5159 * changed. (The corresponding ranges of the direct map are those ranges that
5160 * map the same physical pages as the specified virtual address range.) These
5161 * changes to the direct map are necessary because Intel describes the
5162 * behavior of their processors as "undefined" if two or more mappings to the
5163 * same physical page have different memory types.
5165 * Returns zero if the change completed successfully, and either EINVAL or
5166 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5167 * of the virtual address range was not mapped, and ENOMEM is returned if
5168 * there was insufficient memory available to complete the change. In the
5169 * latter case, the memory type may have been changed on some part of the
5170 * virtual address range or the direct map.
5173 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5177 PMAP_LOCK(kernel_pmap);
5178 error = pmap_change_attr_locked(va, size, mode);
5179 PMAP_UNLOCK(kernel_pmap);
5184 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5186 vm_offset_t base, offset, tmpva;
5187 vm_paddr_t pa_start, pa_end;
5191 int cache_bits_pte, cache_bits_pde, error;
5194 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5195 base = trunc_page(va);
5196 offset = va & PAGE_MASK;
5197 size = roundup(offset + size, PAGE_SIZE);
5200 * Only supported on kernel virtual addresses, including the direct
5201 * map but excluding the recursive map.
5203 if (base < DMAP_MIN_ADDRESS)
5206 cache_bits_pde = pmap_cache_bits(mode, 1);
5207 cache_bits_pte = pmap_cache_bits(mode, 0);
5211 * Pages that aren't mapped aren't supported. Also break down 2MB pages
5212 * into 4KB pages if required.
5214 for (tmpva = base; tmpva < base + size; ) {
5215 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5218 if (*pdpe & PG_PS) {
5220 * If the current 1GB page already has the required
5221 * memory type, then we need not demote this page. Just
5222 * increment tmpva to the next 1GB page frame.
5224 if ((*pdpe & PG_PDE_CACHE) == cache_bits_pde) {
5225 tmpva = trunc_1gpage(tmpva) + NBPDP;
5230 * If the current offset aligns with a 1GB page frame
5231 * and there is at least 1GB left within the range, then
5232 * we need not break down this page into 2MB pages.
5234 if ((tmpva & PDPMASK) == 0 &&
5235 tmpva + PDPMASK < base + size) {
5239 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
5242 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5247 * If the current 2MB page already has the required
5248 * memory type, then we need not demote this page. Just
5249 * increment tmpva to the next 2MB page frame.
5251 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5252 tmpva = trunc_2mpage(tmpva) + NBPDR;
5257 * If the current offset aligns with a 2MB page frame
5258 * and there is at least 2MB left within the range, then
5259 * we need not break down this page into 4KB pages.
5261 if ((tmpva & PDRMASK) == 0 &&
5262 tmpva + PDRMASK < base + size) {
5266 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
5269 pte = pmap_pde_to_pte(pde, tmpva);
5277 * Ok, all the pages exist, so run through them updating their
5278 * cache mode if required.
5280 pa_start = pa_end = 0;
5281 for (tmpva = base; tmpva < base + size; ) {
5282 pdpe = pmap_pdpe(kernel_pmap, tmpva);
5283 if (*pdpe & PG_PS) {
5284 if ((*pdpe & PG_PDE_CACHE) != cache_bits_pde) {
5285 pmap_pde_attr(pdpe, cache_bits_pde);
5288 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5289 if (pa_start == pa_end) {
5290 /* Start physical address run. */
5291 pa_start = *pdpe & PG_PS_FRAME;
5292 pa_end = pa_start + NBPDP;
5293 } else if (pa_end == (*pdpe & PG_PS_FRAME))
5296 /* Run ended, update direct map. */
5297 error = pmap_change_attr_locked(
5298 PHYS_TO_DMAP(pa_start),
5299 pa_end - pa_start, mode);
5302 /* Start physical address run. */
5303 pa_start = *pdpe & PG_PS_FRAME;
5304 pa_end = pa_start + NBPDP;
5307 tmpva = trunc_1gpage(tmpva) + NBPDP;
5310 pde = pmap_pdpe_to_pde(pdpe, tmpva);
5312 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5313 pmap_pde_attr(pde, cache_bits_pde);
5316 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5317 if (pa_start == pa_end) {
5318 /* Start physical address run. */
5319 pa_start = *pde & PG_PS_FRAME;
5320 pa_end = pa_start + NBPDR;
5321 } else if (pa_end == (*pde & PG_PS_FRAME))
5324 /* Run ended, update direct map. */
5325 error = pmap_change_attr_locked(
5326 PHYS_TO_DMAP(pa_start),
5327 pa_end - pa_start, mode);
5330 /* Start physical address run. */
5331 pa_start = *pde & PG_PS_FRAME;
5332 pa_end = pa_start + NBPDR;
5335 tmpva = trunc_2mpage(tmpva) + NBPDR;
5337 pte = pmap_pde_to_pte(pde, tmpva);
5338 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5339 pmap_pte_attr(pte, cache_bits_pte);
5342 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
5343 if (pa_start == pa_end) {
5344 /* Start physical address run. */
5345 pa_start = *pte & PG_FRAME;
5346 pa_end = pa_start + PAGE_SIZE;
5347 } else if (pa_end == (*pte & PG_FRAME))
5348 pa_end += PAGE_SIZE;
5350 /* Run ended, update direct map. */
5351 error = pmap_change_attr_locked(
5352 PHYS_TO_DMAP(pa_start),
5353 pa_end - pa_start, mode);
5356 /* Start physical address run. */
5357 pa_start = *pte & PG_FRAME;
5358 pa_end = pa_start + PAGE_SIZE;
5364 if (error == 0 && pa_start != pa_end)
5365 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
5366 pa_end - pa_start, mode);
5369 * Flush CPU caches if required to make sure any data isn't cached that
5370 * shouldn't be, etc.
5373 pmap_invalidate_range(kernel_pmap, base, tmpva);
5374 pmap_invalidate_cache_range(base, tmpva);
5380 * Demotes any mapping within the direct map region that covers more than the
5381 * specified range of physical addresses. This range's size must be a power
5382 * of two and its starting address must be a multiple of its size. Since the
5383 * demotion does not change any attributes of the mapping, a TLB invalidation
5384 * is not mandatory. The caller may, however, request a TLB invalidation.
5387 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
5396 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
5397 KASSERT((base & (len - 1)) == 0,
5398 ("pmap_demote_DMAP: base is not a multiple of len"));
5399 if (len < NBPDP && base < dmaplimit) {
5400 va = PHYS_TO_DMAP(base);
5402 PMAP_LOCK(kernel_pmap);
5403 pdpe = pmap_pdpe(kernel_pmap, va);
5404 if ((*pdpe & PG_V) == 0)
5405 panic("pmap_demote_DMAP: invalid PDPE");
5406 if ((*pdpe & PG_PS) != 0) {
5407 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
5408 panic("pmap_demote_DMAP: PDPE failed");
5412 pde = pmap_pdpe_to_pde(pdpe, va);
5413 if ((*pde & PG_V) == 0)
5414 panic("pmap_demote_DMAP: invalid PDE");
5415 if ((*pde & PG_PS) != 0) {
5416 if (!pmap_demote_pde(kernel_pmap, pde, va))
5417 panic("pmap_demote_DMAP: PDE failed");
5421 if (changed && invalidate)
5422 pmap_invalidate_page(kernel_pmap, va);
5423 PMAP_UNLOCK(kernel_pmap);
5428 * perform the pmap work for mincore
5431 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5440 pdep = pmap_pde(pmap, addr);
5441 if (pdep != NULL && (*pdep & PG_V)) {
5442 if (*pdep & PG_PS) {
5444 /* Compute the physical address of the 4KB page. */
5445 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5447 val = MINCORE_SUPER;
5449 pte = *pmap_pde_to_pte(pdep, addr);
5450 pa = pte & PG_FRAME;
5458 if ((pte & PG_V) != 0) {
5459 val |= MINCORE_INCORE;
5460 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5461 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5462 if ((pte & PG_A) != 0)
5463 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5465 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5466 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5467 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5468 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5469 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5472 PA_UNLOCK_COND(*locked_pa);
5478 pmap_activate(struct thread *td)
5480 pmap_t pmap, oldpmap;
5485 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5486 oldpmap = PCPU_GET(curpmap);
5487 cpuid = PCPU_GET(cpuid);
5489 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5490 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5492 CPU_CLR(cpuid, &oldpmap->pm_active);
5493 CPU_SET(cpuid, &pmap->pm_active);
5495 cr3 = DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4);
5496 td->td_pcb->pcb_cr3 = cr3;
5498 PCPU_SET(curpmap, pmap);
5503 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5508 * Increase the starting virtual address of the given mapping if a
5509 * different alignment might result in more superpage mappings.
5512 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5513 vm_offset_t *addr, vm_size_t size)
5515 vm_offset_t superpage_offset;
5519 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5520 offset += ptoa(object->pg_color);
5521 superpage_offset = offset & PDRMASK;
5522 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5523 (*addr & PDRMASK) == superpage_offset)
5525 if ((*addr & PDRMASK) < superpage_offset)
5526 *addr = (*addr & ~PDRMASK) + superpage_offset;
5528 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5531 #include "opt_ddb.h"
5533 #include <ddb/ddb.h>
5535 DB_SHOW_COMMAND(pte, pmap_print_pte)
5545 va = (vm_offset_t)addr;
5546 pmap = PCPU_GET(curpmap); /* XXX */
5548 db_printf("show pte addr\n");
5551 pml4 = pmap_pml4e(pmap, va);
5552 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
5553 if ((*pml4 & PG_V) == 0) {
5557 pdp = pmap_pml4e_to_pdpe(pml4, va);
5558 db_printf(" pdpe %#016lx", *pdp);
5559 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
5563 pde = pmap_pdpe_to_pde(pdp, va);
5564 db_printf(" pde %#016lx", *pde);
5565 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
5569 pte = pmap_pde_to_pte(pde, va);
5570 db_printf(" pte %#016lx\n", *pte);
5573 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
5578 a = (vm_paddr_t)addr;
5579 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
5581 db_printf("show phys2dmap addr\n");